KR0143167B1 - Pip display circuit of wide screen television receiver - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a multi-screen display circuit in a wide screen television receiver, and more particularly to a wide screen television receiver in which a wide screen television having a 16: 9 aspect ratio displays a double-sided image of the same size from side to side. And a circuit.

2. The technical problem the invention is trying to solve:

The present invention provides a method and a circuit for displaying different video nodes with the same image quality as one TV.

3. Summary of the solution of the invention:

And a second step of displaying two screens on a single image display device, the first step of equalizing the size and image quality of two different images, and the two different types of image signals The control signal generated in accordance with the synchronization signal is wide in field units. When reading the stored value, the image signal at the same position is continuously read left and right by the control signal generated in accordance with the synchronization signal of one screen. Is to match two different types of image synchronization.

4. Important uses of the invention:

Widescreen two-screen video display.

Description

Two-Screen Display Circuit in Widescreen TV Receivers

1 is a diagram for explaining the PIP function of a conventional television receiver.

2 is a diagram for explaining the PIP and POP functions of a conventional wide television receiver.

3 is an exemplary screen display of the wide television receiver according to the present invention.

4 is a circuit diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen display circuit in a wide screen television receiver, and more particularly to a wide screen television receiver displaying two moving images of the same size from side to side on a wide television receiver having a 16: 9 aspect ratio. It relates to a two screen display circuit.

In general, there is a picture-in-picture method as a method of displaying a plurality of main and sub-screen images on one screen at the same time in a television receiver as shown in FIG. This discloses a specific example of the method and processing in US Patent Nos. 5,025,721 and Korean Patent Application Nos. 1988-16514, 1988-5803, and 1988-9677 filed by the same applicant. The PIP screen of the small screen is always digitally processed to be inserted into a selected window on the main screen in synchronization with the main screen. Recently, a lot of products with a 16: 9 aspect ratio have been sold as wide TVs. Here, as shown in FIG. 2 (a), a main screen is displayed with a 4: 3 aspect ratio of a conventional television receiver as a source using a POP function on a wide TV, and a sub screen is displayed on the remaining portion after the main screen is displayed. It has been processed in the same manner as the PIP or as shown in Figure 2 (b). However, most of the PIP functions in the past are merely a function of reviewing reference screens such as channel search, and are not generally easy to view PIP screens.

Accordingly, an object of the present invention is to provide a circuit for displaying different video screens with the same image quality as one TV.

The present invention provides a first chroma processing circuit for separating the first composite video signal from the luminance signal, the color difference signals (R-Y, B-Y), and the synchronization signal, and generating a locked control signal.

A second chroma processing circuit for separating the second composite video signal into luminance myths and color difference signals (R-Y, B-Y) and a synchronization signal and generating a locked control signal;

First and second A / D converters for digitizing respective luminance signals and color difference signals among the outputs of the first and second chroma processing circuits;

First and second vertical filters for low-pass filtering the outputs of the first and second A / D converters to prevent an aliasing error due to a decrease in the number of lines;

First and second memory controllers for generating a control signal for controlling read / write of a vertical / horizontal synchronization signal passed through the first and second vertical filters during the output of the first and second chroma processing circuits;

First and second field memories for storing data in which the outputs of the first and second vertical filters are recorded or reproduced in units of fields according to the read / write control signals generated by the first and second memory controllers;

And a D / A converter which reads the outputs of the first and second field memories at a faster frequency of the write clock, converts them into analog signals, and restores the original signals.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram according to the present invention,

A first chroma processing circuit 405 for separating the first composite video signal into a luminance signal, a color difference signal (RY, BY), and a synchronization signal, and generating a locked control signal; The second chroma processing circuit 407 which separates the color difference signals RY and BY and the synchronization signal and generates the locked control signal, and the luminance of each of the outputs of the first and second chroma processing circuits 405 and 407. The first and second A / D converters 408 and 409 for digitizing the signal and the color difference signal and the output of the first and second A / D converters 408 and 409 are prevented from generating an aliasing error due to the decrease in the number of lines. The first and second vertical filters 412 and 413 for low pass filtering, and the vertical and horizontal synchronizing signals of the outputs of the first and second chroma processing circuits 412 and 413 through the first and second vertical filters 412 and 413. First and second memory controllers 410 and 411 for generating a control signal for controlling read / write of the first and second memories; First and second field memories 415 and 416 which store data in which the outputs of the first and second vertical filters 412 and 413 are recorded or reproduced in units of fields according to the read / write control signals generated by the fisherman 410 and 411, and The D / A converter 419 reads the outputs of the first and second field memories 415 and 416 at a faster frequency of the write clock, converts them into analog signals, and restores the original signals.

The present invention relates to a two-screen wide screen TV displaying two different moving images having the same size left and right on one screen and a function thereof in a wide screen TV having a 16: 9 aspect ratio as shown in FIG. . As shown in Fig. 3, when two images with a 4: 3 aspect ratio are placed side by side on a wide screen having a 16: 9 aspect ratio, both A and B screens must have a 2: 1 hour compression in the horizontal direction. In the direction there should be 3: 2 line compression. That is, in a typical video signal, an image of one horizontal period is displayed on one line from the left end to the right end of the screen. In order to display one horizontal period image of two screens on one line, the two images are sampled at regular intervals. Write to the field memory, and read each at twice the write time. This is a 2: 1 hour compression in the horizontal direction. In addition, as shown in FIG. 3, when two images of 4: 3 ratio are displayed at the same time, a blank space is generated at the top and bottom of the screen, and the size of the space is 1/3 of the vertical height of the screen. (Calculation; 4X2: 3 = 16: X → X = 6 where X is the area in which the effective picture is displayed), that is, the effective picture is 2/3 of the vertical height.

However, since the screen vertically has a scanning line structure of about 240 lines per field, a circuit for downsampling 240 lines to 160 lines is required in this case. This is usually performed by sampling down from 160 samples to 160 samples, but the technique is applied in a vertical direction, which can be easily designed, and thus detailed description thereof will be omitted.

In order to display two images on one screen as described above, special processing must be performed in the horizontal or vertical direction of the image. A configuration diagram of a two-screen TV including an arranging circuit is shown in FIG.

The two different first and second composite video signals are decomposed into luminance signals and chrominance signals RY and BY by the first and second chroma processing circuits 405 and 407, respectively, and the respective synchronization signals (H sync, V). Synchronously). The synchronization signals generate high frequency clocks locked to the synchronization signals through a conventional PLL circuit to generate control signals required by each unit. In addition, the color difference signals of the luminance signals of the respective paths are converted by the first and second A / D converters 408 and 409 by sampling clocks fs locked to their synchronization signals, and in aliasing due to the decrease in the number of vertical lines. error) to pass through the first and second vertical low pass filters 412 and 416. These signals are not all written to the first and second field memories 415 and 416, but only two of the three lines are written. When the first and second field memories 415 and 416 are read out after (240 lines / field to 160 lines / field), they are locked to a selected synchronization signal (complex video signal A in FIG. 4) among the two images. It uses a clock with a frequency of 2fs that is twice as fast as the clock (this clock is the same as the clock (fs) supplied to the A / D converter). When one line of data is read from the first and second field memories 415 and 416 and input to the D / A converter 417, respectively, in the order of the image to be displayed by the clock, an image as shown in FIG. 3 can be obtained. The reason why the first and second field memories 415 and 416 use a clock locked to one of the read synchronization signals is that the two images are mostly images derived from completely independent nodes, so that the starting points of the images cannot be the same. This is for displaying at the same position as the display position of the signal.

As described above, wide-screen TVs are generally released or developed in 32-36 size, but the present invention has the advantage of having the same effect as having two ordinary TVs of 17-19 size at the same time. have.

Claims (1)

First and second chroma processing circuits 405 and 407, first and second A / D converters 408 and 409, D / A converter 418, first and second field memories 415 and 416, and first and second memory controllers. In a two-screen display circuit of a television receiver having (410, 411), In order to prevent the occurrence of an aliasing error due to the reduction of the number of lines from the outputs of the first and second A / D converters 408 and 409, the low pass filtering is performed vertically, respectively, according to the control of the first and second memory controllers 410 and 411. And said first and second field memories (415,416) comprise first and second vertical filters (412, 413) for input.