JPH10285191A - Information processing system, picture processing system/ method, information processor and computer readable memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable information processing system which has high accuracy by constituting the system supplementing a non-normal part with data which are repetitively and synchronously transferred from a data supply means if the non-normal part exists in received data when data stored in a storage medium is asynchronously transferred by a serial bus. SOLUTION: A picture processing system where a personal computer 103, a printer 102 and a DSC(digital still camera) 101 are connected by using an IEEE 1394 interface is provided. The outputs of the DSC 101 are accumulated in the storage device of the personal computer 103 and they are synchronously transferred to the printer 102, absent data are fetched in at a second frame if there is data absence in receiving the data in the first frame. The same data are repetitively and synchronously transferred until the reception of data in a reception node completes and the lack of transfer data is supplemented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an information processing system,
Image processing systems and their methods, and information processing apparatus and computer-readable memory, for example,
The present invention relates to an information processing system including a plurality of devices interconnected by a serial bus capable of synchronous transfer, an image processing system and a method thereof, an information processing device, and a computer-readable memory.

[0002]

2. Description of the Related Art A digital computer such as an image scanner, a digital still camera (DSC), or a digital video camera (DSV) is connected to a personal computer (PC), and images captured by each digital device are temporarily stored on a hard disk on the PC. There is a system in which an image is converted into print data by an application program running on a PC and then printed by a printer after storing the image in a PC or the like.

In such a system, drivers, which are programs for controlling devices such as digital devices and printers, operate independently on a PC, and images input from the digital devices by the drivers are processed on the PC. After being converted into video data in a format that is easy to display and easy to display, it is stored on a hard disk or the like. When printing the stored video, the video data is subjected to image processing such that an optimum processing result is obtained between input / output devices of the video, and printing is performed.

[0004]

However, at present, many peripheral devices such as the above-described image scanner, DSC, DSV, and printer are connected to the PC. In the future, the types of peripheral devices will further increase, and the number of peripheral devices connected to the PC is expected to increase. Furthermore, due to improvements in interfaces, not only peripheral devices for PCs but also many audiovisual (AV) devices and the like may be connected in large numbers on one network. The development of such peripheral devices
While providing many benefits to PC users, it also increases the amount of data communication between the devices, which may cause a problem of congesting the network.

[0005] For example, data communication between a PC and a printer when printing an image continuously or promptly affects the entire network or a server, so that a desired image can be printed normally. It may be missed or delayed. In other words, there is a problem that traffic congestion on the network hinders processing by the PC and lowers the data communication speed. Particularly, in a network such as an asynchronous transfer mode (ATM) in which priority can be set, if traffic on the network is congested, there is a disadvantage that the communication speed of data communication with low priority is extremely deteriorated.

On the other hand, synchronous (isochronous) transfer, in which a required amount of data can be transmitted within a predetermined time, is performed when an abnormal portion of a data packet occurs on a network due to the structure used for real-time data transfer. However, there is a problem with the data retry method because only the data with the missing data packet reaches the other party.

An object of the present invention is to solve the above-mentioned problems, and an information processing system, an image processing system, a method thereof, and an information processing system comprising a plurality of devices interconnected by a serial bus capable of synchronous transfer. Information processing system and image processing system capable of performing high-speed data transfer by synchronous transfer in an information processing device and a computer-readable memory, and compensating for data when an abnormal part such as a missing part occurs in the synchronously transferred data It is an object of the present invention to provide an information processing apparatus and a computer-readable memory.

[0008]

However, the above technique has the following problems.

[0009] An information processing system according to the present invention is an information processing system comprising a plurality of devices connected by a serial bus capable of synchronous transfer, comprising: data supply means for synchronously transferring data stored in a storage medium; Having data receiving means for receiving the synchronously transferred data,
When the received data includes an abnormal part, the data receiving means supplements the abnormal part with data repeatedly and synchronously transferred by the data supply means.

[0010] An image processing system according to the present invention is an image processing system comprising a plurality of devices interconnected by a serial bus capable of synchronous transfer, wherein data for synchronously transferring image data stored in a storage medium is provided. Supply means, data receiving means for receiving the synchronously transferred image data, and forming means for forming a visible image on a recording medium based on the image data received by the receiving means,
When the received data includes an abnormal part, the data receiving means supplements the abnormal part with data repeatedly and synchronously transferred by the data supply means.

[0011] An information processing method according to the present invention is an information processing method for an information processing system comprising a plurality of devices connected by a serial bus capable of synchronous transfer, wherein data stored in a storage medium is repeatedly synchronously transferred. The synchronously transferred data is received, and when the received data includes an abnormal part, the abnormal part is supplemented by data synchronously and repeatedly transmitted.

An image processing method according to the present invention is an image processing method for an image processing system including a plurality of devices interconnected by a serial bus capable of synchronous transfer,
Repeatedly synchronously transfer the image data stored in the storage medium, receive the synchronously transferred image data, if there is an abnormal part in the received data, supplement the abnormal part with data repeatedly synchronously transferred, A visible image is formed on a recording medium based on the received image data.

An information processing apparatus according to the present invention is an information processing apparatus connected to another device via a serial bus capable of synchronous transfer, a receiving means for repeatedly receiving synchronously transferred data, When there is an abnormal part in the data received by the receiving means, a supplementing means for supplementing the abnormal part with the repeatedly received data is provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an information processing system according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a general configuration example of a system to which the present invention is applied, wherein a PC 103, a printer 102 and a DSC 101
Are connected using an IEEE1394 interface. Therefore, an outline of the IEEE1394 interface will be described in advance.

[0016]

[Overview of IEEE1394] With the advent of home digital VTRs and digital video discs (DVDs), video data and audio data (hereinafter collectively referred to as "AV data")
For example, there is a need to transfer data with a large amount of information in real time. To transfer AV data to a PC or other digital devices in real time, an interface having a high-speed data transfer capability is required. IEEE1394-1995 (High Perfo
rmance Serial Bus) (hereafter "1394 serial bus") was developed.

FIG. 2 is a diagram showing an example of a network system configured using a 1394 serial bus. This system is equipped with devices A, B, C, D, E, F, G and H, AB, B
13 between D and DE, and between AC, CF, CG and CH
Connected with a twisted pair cable for 94 serial bus. Examples of these devices A to H are PC, digital VT
There are storage devices using media such as R, DVD, DSC, DVC, hard disk and MO, CRT and LCD monitors, image scanners, film scanners, and printers. The connection between the devices can be a mixture of the daisy chain method and the node branch method, and a highly flexible connection can be performed. Also, each device has its own unique ID,
By recognizing the ID, one network is configured in a range of devices connected by the 1394 serial bus.
For example, simply by daisy-chaining each device with one 1394 serial bus cable, each device plays a role of relay, and a single network can be configured as a whole.

Further, the 1394 serial bus has a function corresponding to a plug-and-play function and automatically recognizing a device simply by connecting a cable to the device and recognizing a connection state. In a system as shown in FIG. 2,
When a certain device is removed from the network or added to the network, the bus is automatically reset (the configuration information of the existing network is reset), and the configuration information of the new network is reconstructed. With this function, it is possible to always set and recognize the configuration of the network at that time.

The data transfer speed of the 1394 serial bus is defined as 100/200/400 Mbps, and compatibility is maintained by the device having the higher transfer speed supporting the lower transfer speed. The data transfer mode includes an ATM for transferring asynchronous data such as a control signal and a synchronous transfer mode for transferring synchronous data such as AV data. This asynchronous data and synchronous data are mixed in each cycle (usually 125 μs / cycle), following the transfer of the cycle start packet (CSP) that indicates the start of the cycle, and prioritizing the transfer of synchronous data. And transferred.

FIG. 3 is a diagram showing the configuration of the 1394 serial bus. The configuration of the 1394 serial bus has a layer (hierarchical) structure. The configuration closest to the hardware is a 1394 serial bus cable 813, and there is a connector port 810 to which a connector at the end of the cable is connected. Connector port 8
Above 10 are a physical layer 811 and a link layer 812 that are configured by the hardware unit 800. The hardware unit 800 is configured with an interface chip, the physical layer 811 performs coding and control related to connection, and the link layer 812 performs packet transfer and cycle time control.

A transaction layer 814 of the firmware unit 801 manages data to be transferred (transacted) and issues commands such as read and write. The management layer 815 of the firmware unit 801 is 1394
It manages the connection status and ID of each device connected to the serial bus, and manages the network configuration. The above hardware and firmware are the substantial configuration of the 1394 serial bus.

The application layer 816 of the software unit 802 differs depending on the software used, and how data is transferred on the interface is defined by a protocol such as an AV protocol.

FIG. 4 is a diagram showing an address space in the 1394 serial bus. Each device (node) connected to the 1394 serial bus must have a unique 64-bit address for the node. This address is stored in the memory of the device, and by constantly recognizing the node address of itself or the other party, it is possible to perform data communication specifying the other party.

The addressing of the 1394 serial bus is based on the IE
The address is set according to the EE1212 standard. The first 10 bits are used to specify the bus, and the next 6 bits are used to specify the node ID.
Used to specify. 48 set in each device
The bit address is also divided into 20 bits and 28 bits, and is used with a structure of 256 Mbytes. 20
0 to 0xFFFFD of the bit address space is the memory space,
0xFFFFE is called a private space, and 0xFFFFF is called a register space. The private space is an address that can be used freely within the device, and the register space stores information common to devices connected to the bus and is used for communication between the devices. First 51 of register space
Two bytes contain the CSR architecture core register (CSR core), the next 512 bytes contain the serial bus registers, and the next 1024 bytes contain the configuration
ROM, the rest are unit-specific registers in unit space,
Each is placed.

In general, to simplify the design of heterogeneous bus systems, nodes should use only the first 2048 bytes of the initial unit space, which results in the CSR core, serial bus registers, configuration ROM and It is desirable that the first 2048 bytes of the unit space be composed of 4096 bytes.

The above is the outline of the 1394 serial bus.
Next, the features of the 1394 serial bus will be described in more detail.

[0027]

[Details of 1394 Serial Bus] [Electrical Specifications of 1394 Serial Bus] FIG. 5 is a diagram showing a cross section of a cable for a 1394 serial bus. The 1394 serial bus cable has a power line in addition to the two twisted pair signal lines, so that power can be supplied to a device having no power source or a device whose voltage has been reduced due to a failure or the like. The voltage of the DC power supplied from the power supply line is regulated to 8 to 40 V, and the current is regulated to a maximum current of 1.5 A.

[DS-Link Method] FIG. 6 shows a data transfer method of DS-Link (Data / Strob) adopted in the 1394 serial bus.
FIG. 3 is a diagram for explaining an (e Link) method.

The DS-Link system is suitable for high-speed serial data communication and requires two sets of signal lines. That is, one of the two twisted pairs transmits a data signal, and the other transmits a strobe signal. On the receiving side, there is a feature that a clock signal can be generated by taking the exclusive OR of the data signal and the strobe signal. For this reason, when using the DS-Link method, there is no need to mix a clock signal into the data signal, so transfer efficiency is higher than other serial data transfer methods, and a clock signal can be generated, so a phase locked loop (PLL) This eliminates the need for a circuit, thereby reducing the circuit size of the controller LSI.In addition, when there is no data to be transferred, there is no need to send information indicating that the device is in an idle state, so the transceiver circuits of each device are put into a sleep state. And power consumption can be reduced.

[Bus Reset Sequence] Each device (node) connected to the 1394 serial bus has a node ID.
Are given, and are recognized as nodes constituting the network. For example, when the number of nodes increases / decreases due to node disconnection or power on / off, that is, the network configuration changes, and it is necessary to recognize a new network configuration, each node that detects the change sends a bus to the bus. A reset signal is transmitted to enter a mode for recognizing a new network configuration. This change in the network configuration is detected by detecting a change in the bias voltage at the connector port.

When a bus reset signal is transmitted from a certain node, the physical layer of each node transmits the bus reset signal to the link layer at the same time as receiving the bus reset signal, and transmits the bus reset signal to another node. Transmit. After all the nodes finally receive the bus reset signal, the bus reset sequence is started. Note that the bus reset sequence is started when a cable is unplugged or inserted, or when a network error or the like is detected by hardware, and is also started by directly giving an instruction to the physical layer such as host control using a protocol. You. Further, when the bus reset sequence is started, the data transfer is temporarily suspended, the data transfer is suspended during the bus reset, and resumed under the new network configuration after the bus reset is completed.

[Node ID Determination Sequence] After the bus reset, each node starts an operation of giving each node a node ID in order to construct a new network configuration. The general sequence from the bus reset to the determination of the node ID at this time will be described with reference to the flowcharts shown in FIGS.

FIG. 7 is a flowchart showing a series of sequences from the generation of the bus reset signal until the node ID is determined and data transfer can be performed. Steps
In step S101, the occurrence of the bus reset signal is constantly monitored, and when the bus reset signal is generated, the process proceeds to step S102. In order to obtain a new network configuration when the network configuration is reset, the parent-child relationship between the nodes directly connected to each other is obtained. Is declared. Steps are taken until the parent-child relationship is determined between all nodes by the determination in step S103.
S102 is repeated.

When the parent-child relationship is determined, the process proceeds to step S104, where a root is determined.
Setting of the node ID that gives Node IDs are set in the order of predetermined nodes from the root, and step S106
Step S105 is repeated until all nodes have been given node IDs.

When the setting of the node ID is completed, the new network configuration is recognized by all the nodes, so that data transfer between the nodes can be performed.
The data transfer is started in step S107, and the sequence returns to step S101, and the occurrence of the bus reset signal is monitored again.

FIG. 8 is a flowchart showing details from monitoring of the bus reset (S101) to the determination of the route (S104), and FIG. 9 is a flowchart showing details of the node ID setting (S105, 106).

In FIG. 8, the generation of a bus reset signal is monitored in step S201. When the bus reset signal is generated, the network configuration is reset once. Next, in step S202, as a first step of re-recognizing the reset network configuration, each device resets the flag FL with data indicating that it is a leaf. In step S203, each device checks the number of ports, that is, the number of other nodes connected to itself, and in step S204,
According to the result of S203, the number of undefined (undetermined parent-child) ports is examined to start the declaration of the parent-child relationship. Here, the number of undefined ports is equal to the number of ports immediately after the bus reset, but as the parent-child relationship is determined, the number of undefined ports detected in step S204 decreases.

The declaration of the parent-child relationship immediately after the bus reset is limited to actual leaves. Whether it is a leaf or not can be known from the result of checking the number of ports in step S203. That is, if the number of ports is "1", it is a leaf. In step S205, the leaf declares a parent-child relationship “I am a child and the other is a parent” with respect to the connection partner node, and ends the operation.

On the other hand, the node, the branch of which the result of the confirmation of the number of ports in step S203 is “2 or more”, that is, the number of undefined ports> 1 immediately after the bus reset, proceeds to step S206 and sets the flag FL. The data indicating the branch is set, and the process waits for the declaration of the parent-child relationship from another node in step S207. A parent-child relationship is declared from another node, and the branch that has received the declaration returns to step S204 to check the number of undefined ports, but if the number of undefined ports is "1", the branch connected to the remaining port For the node, a parent-child relationship of "I am a child and the other is a parent" can be declared in step S205. Further, the branch having the undefined port number “2 or more” waits for the declaration of the parent-child relationship from another node again in step S207.

Any one branch (or exceptionally,
If the number of undefined ports on a leaf that did not operate quickly despite the child declaration being made becomes “0”, the declaration of the parent-child relationship for the entire network has ended, and the number of undefined ports is “0”. Is the only node that has become the parent of all the nodes, that is, the data indicating the route is set in the flag FL in step S208, and the process proceeds to step S209.
Is recognized as a root.

Thus, the procedure from the bus reset to the declaration of the parent-child relationship between all the nodes in the network is completed.

Next, the procedure for assigning an ID to each node will be described. First, it is the leaf that can set the ID. Then, an ID is set in the order of leaf → branch → root in ascending order (node number: 0).

In step S301 of FIG. 9, the process branches to processing according to the type of node, that is, leaf, branch, and route, based on the data set in the flag FL.

First, in the case of leaves, in step S302, the number of leaves (natural number) existing in the network is set as a variable N, and in step S303, each leaf
Request a node number. If there are multiple requests, the route performs arbitration (operation of arbitrating one) in step S304, assigns a node number to one node in step S305, and indicates that the other nodes have failed to acquire the node number. Notify.

The leaf from which the node number could not be obtained by the determination in step S306 repeats the request for the node number again in step S303. On the other hand, in step S307, the leaf from which the node number has been acquired notifies all nodes by broadcasting ID information including the acquired node number.
When the broadcast of the ID information ends, in step S308,
The variable N representing the number of leaves is decremented. And
The procedure from steps S303 to S308 is repeated until the variable N becomes “0” as determined in step S309, and after the ID information of all the leaves has been broadcast, the process proceeds to step S310 to shift to the branch ID setting.

The setting of the branch ID is performed in substantially the same manner as the leaf. First, in step S310, the number of branches (natural number) existing in the network is set as a variable M, and then in step S311, each branch requests a node number from the root. In response to this request, the root performs arbitration in step S312, gives a node number of a small number following the leaf to one branch in step S313, and notifies another branch of a result indicating that acquisition of the node number has failed.

According to the determination in step S314, the branch from which the node number could not be obtained repeats the request for the node number again in step S311. On the other hand, in step S315, the branch from which the node number has been acquired is notified to all nodes by broadcasting the acquired node number. When the broadcast of the ID information ends, in step S316, the variable M representing the number of branches is decremented. Then, step S3 is performed until the variable M becomes “0” as determined in step S317.
The procedure from 11 to S316 is repeated, and after the ID information of all the leaves is broadcast, the process proceeds to step S318 to shift to the root ID setting.

At this point, since the root node is the only node that has not finally obtained an ID, in step S318, the lowest node number that has not been given to another node is set as its own node number. Broadcast ID information.

Thus, the procedure up to setting the IDs of all the nodes is completed. Next, a specific procedure of a sequence for determining a node ID will be described using the network example shown in FIG.

In the network shown in FIG. 10, a node A and a node C are directly connected below a node B which is a root, a node D is directly connected below a node C, and a node E and a node below the node D. F has a directly connected hierarchical structure. The procedure for determining the hierarchical structure, the root node, and the node ID is as follows.

After the occurrence of the bus reset, a parent-child relationship is declared between ports to which the nodes are directly connected in order to recognize the connection status of each node. Here, the parent and child means that the upper level of the hierarchical structure is “parent” and the lower level is “child”. In FIG. 10, it is the node A that first declared the parent-child relationship after the bus reset. As described above, the declaration of the parent-child relationship can be started from a node (leaf) to which only one port is connected. If the number of ports is “1”, the end of the network tree, that is, the leaf is recognized, and the parent-child relationship is determined from the node that operates first among the leaves. Thus, the port of the node that has declared the parent-child relationship is set as the child of the two nodes connected to each other, and the port of the partner node is set as the parent. In this way, a child-parent relationship is set between nodes AB, ED, and FD.

Further, a parent-child relationship is declared to a higher-order node sequentially from a node having a plurality of ports up the hierarchy, that is, a node that has received a declaration of a parent-child relationship from another node among branches. In FIG. 10, after the parent-child relationship between the nodes DE and DF is determined, the node D declares the parent-child relationship to the node C. As a result, the node D
A child-parent relationship is set between -C. Node C receiving the parent-child relationship declaration from node D declares a parent-child relationship for node B connected to another port, and as a result, a child-parent relationship is set between nodes CB. .

In this manner, a hierarchical structure as shown in FIG. 10 is formed, and the parent node B in all finally connected ports is determined as the root node. Note that there is only one route in one network configuration. Further, when the node B, which has been declared the parent-child relationship from the node A, immediately declares the parent-child relationship to another node, for example, there is a possibility that another node such as the node C becomes a root. . That is, depending on the timing at which the declaration of the parent-child relationship is transmitted, there is a possibility that any node may become the root, and even if the network configuration is the same, a specific node does not always become the root.

When the route is determined, the process enters a mode for determining each node ID. All nodes have a broadcast function of notifying the determined ID information to all other nodes. The ID information includes a node number, information on a connected position, the number of ports having the number, the number of connected ports, information on a parent-child relationship of each port, and the like.
Broadcast as ID information.

As described above, the assignment of the node numbers starts from the leaf, and the node numbers = 0, 1, 2,... Are assigned in order. Then, by broadcasting the ID information, it is recognized that the node number has been assigned.

When all the leaves have acquired the node numbers, the process proceeds to the branch and the node numbers following the leaves are assigned. Like the leaf, the ID information is broadcast in order from the branch to which the node number is assigned, and finally the root broadcasts its own ID information. Thus, the root always owns the highest node number in the network.

As described above, the ID setting of the entire hierarchical structure is completed, the network configuration is constructed, and the bus initialization operation is completed.

[Control Information for Node Management] As a basic function of the CSR architecture for performing node management, a CSR core shown in FIG. 4 exists on a register. The locations and functions of these registers are shown in FIG. 11, where the offsets are relative to 0xFFFFF0000000.

In the CSR architecture, 0xFFFFF0000200
And registers related to the serial bus.
FIG. 12 shows the locations and functions of these registers.

In the place starting from 0xFFFFF0000800, information on the node resources of the serial bus is arranged. FIG. 13 shows the positions and functions of these registers.

The CSR architecture has a configuration ROM to represent the function of each node.
This ROM has a minimum format and a general format, xFFFFF0000400
It is arranged from. In the minimum format, the vendor
It only represents the ID, and this vendor ID is a globally unique value represented by 24 bits.

The general format has information on nodes in a format as shown in FIG. 15. In this case, the vendor ID can be stored in a root directory (root_directory). Also, a bus info block
And the root leaf have a 64-bit globally unique device number, including the vendor ID. This device number is used for continuously recognizing a node after a reconfiguration such as a bus reset.

[Serial Bus Management] As shown in FIG. 3, the protocol of the 1394 serial bus is composed of a physical layer, a link layer, and a transaction layer. Among them, bus management provides basic functions for node control and bus resource management based on the CSR architecture.

A node that performs bus management (hereinafter, referred to as a “bus management node”) exists solely on the same bus and provides a management function to other nodes on the serial bus. Control, performance optimization, power management, transmission speed management, configuration management, etc.

The bus management function is roughly divided into three functions: a bus manager, a synchronous (isochronous) resource manager, and a node control. Node control is CS
R is a management function that enables communication between nodes in the physical layer, link layer, transaction layer, and application. The synchronous (isochronous) resource manager is a management function necessary for performing synchronous data transfer on the serial bus, and manages the transfer bandwidth of synchronous data and the assignment of channel numbers. To perform this management, the bus management node
After the bus is initialized, it is dynamically selected from nodes having a synchronous (isochronous) resource manager function.

In a configuration in which a bus management node does not exist on a bus, a node having a synchronous (isochronous) resource manager function performs a part of the bus management function such as power management and cycle master control. Further, the bus management is a management function of providing a service for providing a bus control interface to an application, and a serial bus control request (SB_CONTROL.
request), serial bus event control confirmation (SB_CONTROL.
confirmation), serial bus event notification (SB_EVENT.i
ndication).

The serial bus control request is used when an application requests the bus management node for bus reset, bus initialization, bus status information, and the like. The serial bus event control confirmation is notified to the application from the bus management node as a result of the serial bus control request. The serial bus event notification is for notifying an event generated asynchronously from the bus management node to the application.

[Data Transfer Protocol] In the data transfer of the 1394 serial bus, synchronous data (synchronous packets) that need to be transmitted periodically and asynchronous data (asynchronous packets) that can be transmitted and received at arbitrary timing are simultaneously transmitted. It exists and guarantees the real-time property of synchronous data. In data transfer, bus arbitration is performed in order to request a bus use right and obtain use consent prior to transfer.

In the asynchronous transfer, the transmitting node ID and the receiving node ID are sent together with the transfer data as packet data. When the receiving node confirms its own ID and receives the packet, it returns an acknowledge signal to the transmitting node, thereby completing one transaction.

In synchronous transfer, the transmitting node requests a synchronous channel together with the transmission rate, and the channel ID is sent as packet data together with the transfer data. The receiving node confirms the desired channel ID and receives the data packet. The required number of channels and transmission speed are determined by the application layer.

These data transfer protocols are defined by three layers: a physical layer, a link layer, and a transaction layer. The physical layer performs a physical / electrical interface with a bus, automatic recognition of node connection, arbitration of bus use right between nodes (bus arbitration), and the like. The link layer performs cycle control for addressing, data check, packet transmission / reception, and synchronous transfer. The transaction layer performs processing related to asynchronous data. Less than,
The processing in each layer will be described.

[Physical Layer] Next, bus arbitration in the physical layer will be described.
16 is a diagram for explaining a request for a bus use right, and FIG. 17 is a diagram for explaining permission for a bus use.

When the bus arbitration starts, one or a plurality of nodes respectively request the bus use right toward the parent node. For example, when the nodes C and F shown in FIG. 16 request the bus use right, the parent node A that has received the request from the node F further requests the bus use right toward the parent node, that is, relays the request. Therefore, the request for the right to use the bus is finally delivered to the arbitrating route.

The route receiving the request for the right to use the bus determines to which node the right to use the bus is given. This arbitration work can be performed only by the route, and the node that wins the arbitration is permitted to use the bus. FIG. 17 shows an example in which the node C is permitted to use the bus and the node F is rejected from using the bus. The route uses DP (datap
refix) packet to signal that bus use was denied. The request for the right to use the bus of the node whose use of the bus is rejected is kept waiting until the next arbitration.

As described above, the node that has won the arbitration and obtained the permission to use the bus can start data transfer thereafter. FIG. 18 is a flowchart showing a series of bus arbitration flows.

In order for a node to start data transfer,
The bus must be idle. In order to recognize that the data transfer that has been started earlier is completed and the bus is currently in an idle state, a predetermined idle time gap length (for example, a subaction gap) that is individually set in each transfer mode is used. When the progress is detected and the gap length has elapsed, each node determines that the bus is in an idle state. That is, in step S401, it is determined whether a predetermined gap length according to data to be transferred, such as asynchronous data and synchronous data, has elapsed. Unless a predetermined gap length has elapsed, it is not possible to request the right to use the bus necessary to start the transfer.

When the predetermined gap length has elapsed, step S4
In 02, it is determined whether or not there is data to be transferred, and if so, a bus use right is requested in step S403. At this time,
The transmission of the signal indicating the request for the right to use the bus is relayed to each node in the network and finally delivered to the route, as shown in FIG. If there is no data to be transferred, the process returns to step S401, and waits for a predetermined gap length to elapse.

Next, the route that has received the request for the right to use the bus in step S404 checks the number of nodes that have requested the right to use the bus in step S405.
At 408, the node is granted bus use. If the number of nodes requesting the right to use the bus is “2 or more”, an arbitration operation is performed in step S406 to reduce the number of nodes permitted to use the bus to one. This arbitration work is fair so that the same node is not always given permission. Then, in step S407, the procedure branches to the node that permits the use of the bus and the other nodes, and sends a signal indicating permission of the use of the bus in step S408 to the node that permits the use of the bus. Immediately starts transfer of data (packet) to be transferred. Further, in step S409, a DP (data prefix) packet indicating rejection of bus use is sent to the other nodes, and the node receiving the packet transmits the DP (data prefix) packet in step S4 to request the bus use right again.
Return to 01, and wait for a predetermined gap length to elapse.

[Transaction Layer] There are three types of transactions: read transactions, write transactions, and lock transactions. In a read transaction, an initiator (request node) reads data from a specific address in a memory of a target (response node). In a write transaction, an initiator writes data to a specific address of a target memory.

In the lock transaction, reference data and update data are transferred from the initiator to the target. The reference data is combined with the data of the target address to become a designated address indicating a specific address of the target. Then, the data at the specified address is updated with the update data.

FIG. 19 shows CS in the transaction layer.
FIG. 4 is a diagram showing a request / response protocol for each of read, write, and lock commands based on the R architecture. Request, notification, response, and confirmation shown in the figure are service units in a transaction layer. Transaction request (TR_
DATA.request) is the transfer of the packet to the responding node,
The transaction notification (TR_DATA.indication) is a notification that the request has arrived at the responding node, and the transaction response (T
(R_DATA.response) is transmission of an acknowledgment, and transaction confirmation (TR_DATA.confirmation) is reception of an acknowledgment.

[Link Layer] FIG. 20 is a diagram showing services in the link layer. A link request (LK_DATA.request) for requesting packet transfer to the responding node, and a link notification (LK_DATA.i) for notifying the responding node of packet reception.
ndication), an acknowledgment transmission link response from the response node (LK_DATA.response), and an acknowledgment transmission link confirmation (LK_DATA.confirmation) of the requesting node. One packet transfer process is called a subaction, and there are two types of asynchronous subactions and synchronous subactions. Hereinafter, the operation of each sub-action will be described.

[Asynchronous Subaction] The asynchronous subaction is an asynchronous data transfer. FIG. 21 is a diagram showing a temporal transition state in asynchronous transfer. The first sub-action gap shown in FIG. 21 indicates the idle state of the bus. When the idle time reaches a predetermined value, a node desiring data transfer requests a bus use right, and bus arbitration is executed.

When the use of the bus is permitted by the bus arbitration, the data is then transferred to a packet, and the node that has received the data returns a response code ACK for a reception confirmation after a short gap called an ACK gap. Alternatively, the data transfer is completed by returning the response packet. The ACK is composed of 4-bit information and a 4-bit checksum, and includes information indicating success, busy state, or pending state, and is immediately returned to the data transmission node.

FIG. 22 is a diagram showing a format example of an asynchronous transfer packet. The packet has a header part in addition to the data part and the data CRC for error correction, and the destination part ID, the source node ID, the transfer data length and various codes are written in the header part.

The asynchronous transfer is one-to-one communication from the own node to the partner node. The packet sent from the transfer source node is distributed to each node in the network, but since each node ignores packets other than its own, only the node designated as the destination reads the packet.

[Synchronization Subaction] The synchronization subaction is a synchronous data transfer. This synchronous transfer, which can be said to be the greatest feature of the 1394 serial bus, is particularly suitable for transferring data that requires real-time transfer, such as AV data. In contrast to the asynchronous transfer, which is a one-to-one transfer, the asynchronous transfer can uniformly transfer data from one transfer source node to all other nodes by a broadcast function.

FIG. 23 is a diagram showing a temporal transition state in the synchronous transfer. Synchronous transfer is performed on the bus at regular intervals, and this time interval is called a synchronous cycle, and the synchronous cycle time is 125 μS. A cycle start packet 2000 indicates the start of a synchronization cycle and plays a role of adjusting the time of each node. The node transmitting the cycle start packet 2000 is a node called a cycle master. After a transfer in the immediately preceding cycle is completed, after a predetermined idle period (subaction gap 2001),
Cycle start packet 20 to signal the start of this cycle
Send 00. In other words, this cycle start packet
The time interval for transmitting 2000 is 125 μS.

FIG. 23 shows channel A, channel B, and channel C.
As shown in FIG. 7, by giving a channel ID to each of a plurality of types of packets in one synchronization cycle, the packets can be distinguished and transferred. As a result, real-time transfer can be performed substantially simultaneously between a plurality of nodes, and the receiving node only needs to receive the data of the channel ID desired by itself. This channel ID does not represent the address of the receiving node or the like, but is merely a logical number for data. Therefore, a certain transmitted packet is distributed from one source node to all other nodes, that is, broadcasted.

Prior to packet transmission by synchronous transfer, bus arbitration is performed as in asynchronous transfer. However, there is no ACK in synchronous transfer because it is not one-to-one communication as in asynchronous transfer.

The iso gap (synchronization gap) shown in FIG. 23 represents an idle period necessary for confirming that the bus is in an idle state before performing synchronous transfer. After the predetermined idle period has elapsed, the node that wishes to perform synchronous transfer determines that the bus is in an idle state, and performs bus arbitration.

FIG. 24 is a diagram showing a format example of a synchronous transfer packet. Each packet divided into each channel has a data part and data CR for error correction, respectively.
In addition to C, there is a header portion, in which a transfer data length, a channel number, various codes, a header CRC for error correction, and the like are written. The details of the packet field are shown in FIG.

[Bus Cycle] In the 1394 serial bus, synchronous transfer and asynchronous transfer can be mixed, and FIG. 26 shows an example of a temporal transition of the transfer state on the bus at that time.

Here, the synchronous transfer is executed prior to the asynchronous transfer. The reason is that after the cycle start packet, synchronous transfer can be started with a gap length (synchronous gap) shorter than the gap length (subaction gap) of the idle period necessary to start asynchronous transfer. Therefore, synchronous transfer is performed with priority over asynchronous transfer.

In the general bus cycle shown in FIG. 26, at the start of cycle #m, a cycle start packet is transferred from the cycle master to each node. Thus, each node performs time adjustment, waits for a predetermined idle period (synchronization gap), and then performs a synchronous transfer. The node participates in bus arbitration and starts packet transfer. In FIG. 26, channel e, channel s, and channel k
Are sequentially transferred synchronously. After the operations from the arbitration to the packet transfer are repeated for the given channel, and all the synchronous transfers in the cycle #m are completed, the asynchronous transfer can be performed.

When the idle time reaches a subaction gap where asynchronous transfer is possible, a node that wants to perform asynchronous transfer participates in arbitration. However, asynchronous transfer can be performed only after the end of synchronous transfer, the time to transfer the next cycle start packet (cycle synchronizing).
Until ch), only when a sub-action gap to activate asynchronous transfer is obtained.

In cycle #m shown in FIG. 26, after synchronous transfer for three channels, two packets (packet 1 and packet 2) including ACK are transferred by asynchronous transfer. After the asynchronous transfer packet 2, it is time to start the cycle m + 1 (cycle synch), and the transfer in the cycle #m ends here. However, during asynchronous or synchronous transfer operations,
Time to send the next cycle start packet (cycle
When (synch) is reached, the transfer is not forcibly interrupted, and after the transfer is completed, a cycle start packet of the next cycle is transmitted after an idle period. That is, when one cycle lasts for 125 μs or more, the next cycle is shortened from the reference 125 μs by the extension. As described above, the synchronization cycle can be exceeded or shortened on the basis of 125 μs.

However, synchronous transfer is performed every cycle if necessary to maintain real-time transfer, and asynchronous transfer may be postponed to the next and subsequent cycles due to the shortened cycle time.

[FCP] In the AV / C protocol, a function control protocol (F) is used to control devices on the 1394 serial bus.
unctional Control Protocol (FCP) is provided.
Asynchronous packets defined by IEEE1394 are used for transmission and response of FCP control commands. In FCP, the controlling node is called a controller, the controlled node is called a target, and the FCP packet frame sent from the controller to the target is an AV / C command frame.
Conversely, an FCP packet frame returned from the target to the controller is called an AV / C response frame.

FIG. 27 shows that node A is a controller and node B
Indicates the case of the target, of which the 512 bytes from the address 0000B00 are the command register and the 512 bytes from the address 0000D00 are the response registers. , Data is written to the register at the specified address. The relationship between the transmission of the AV / C command frame by the controller and the response of the AV / C response frame by the target at this time is called an AV / C transaction. In a typical AV / C transaction, the target receives 10
It is necessary to send a response frame to the controller within 0 ms.

FIG. 28 is a diagram showing a packet format of an asynchronous transfer including an FCP packet frame. A command frame or a response frame is inserted into the data area of the asynchronous data packet shown in FIG. Be executed.

FIG. 29 is a diagram showing the structure of an AV / C command frame, and FIG. 30 is a diagram showing the structure of an AV / C response frame.
Ctype and response of header as FCP packet frame
The structure is such that the data part of FCP is connected after e, subunit_type, and subunit_ID.

Ctype indicates the command type in the command frame, and includes CONTROL, STATUS, INQUIRY, NOTIFY
Each state is shown.

[0104] response indicates a response code in the response frame, and is ACCEPTED, REJECTED, IN_TRA
Each state such as NSITION, IMPLEMENTED, CHANGED, INTERIM is shown.

Further, subunit_type is the classification of the device, su
bunit_ID indicates an instance number.

The data portion of the FCP has an operation code + operand configuration, and can control a target using various AV / C commands and can respond to an AV / C response.

[CIP] A common synchronization packet is used as a real-time data transfer protocol in the AV / C protocol.
(Common Isochronous Packet: CIP)
As shown in FIG. 31, the CIP and the real-time data are stored in the data portion of the synchronization packet.

The length of the source packet of the AV / C protocol is fixed for each device. As shown in FIG. 32, the source packet on the transmitting side is divided into 1, 2, 4, and 8 data blocks. And transmitted as a plurality of synchronization packets. The node receiving the packet assembles these packets,
Since the original packet has to be restored, the source packet header with the timestamp field needed to restore the real-time data, as shown in FIG.
A CIP header is provided.

When the apparatus is started, packets are transferred every period of the bus, but empty packets of only a packet header and a CIP header are sent even if there is no data to be sent. The CIP header contains a block count value DB for detecting data block loss during packet transfer.
Information such as C and FMT indicating the type of data code is included.

[0110]

First Embodiment Next, as one embodiment of the present invention, a system in which digital devices are connected by a 1394 serial bus as shown in FIG. 1 will be described.

[Configuration] The system shown in FIG.
394 Data transfer based on serial bus specifications can be performed. Note that the DSC 101 is a device for recording and reproducing moving images or still images, and may be a DSC (digital still camera) or a DV.
Any recording / reproducing device 101 such as C (digital video camera) may be used. Then, if the video (image) data output from the recording / reproducing apparatus 101 is directly transferred to the printer 102, direct printing is possible.

The connection method of the 1394 serial bus is shown in FIG.
The connection is not limited to the connection shown in FIG. 1, and the devices may be connected in any order. In addition to the devices shown in FIG. 1, input / output devices that support a 1394 serial bus, data communication devices, and the like can be connected, such as a hard disk, MO, CD-R, CD-RW, and DVD-ROM. Such storage device may be used.

FIG. 34 is a block diagram showing a detailed configuration of each digital device shown in FIG.

In the recording / reproducing apparatus 101, reference numeral 4 denotes a lens or a CC.
Imaging system consisting of D, 5 is A / D converter, 6 is video (image)
A signal processing circuit, 7 is a compression / expansion circuit for compressing / expanding video (image) data by a predetermined algorithm, and 8 is a recording / reproducing system including a magnetic tape or magnetic disk and its recording / reproducing head, a PC card and its driver / connector, etc. , 9 is a system controller, 10 is an operation unit for inputting instructions, 11 is a D / A converter, 12 is an EVF as a display unit, 13 is a frame memory for storing video (image) data to be transferred without compression, 14 is a memory control unit for controlling the reading of the memory 13, 15 is a frame memory for storing video (image) data to be compressed and transferred, 16 is a memory control unit for controlling the reading of the memory 15, etc., 17 is Data selector, 18 is 13
This is the 94 serial bus interface.

In the printer 102, 19 is an interface section of a 1394 serial bus, 20 is a data selector,
21 is a decoding circuit for decoding (expanding) video (image) data compressed by a predetermined algorithm, 22 is an image processing circuit for performing image processing on an image to be printed, 23 is a memory for forming an image to be printed, 24, a printer head; 25, a driver for scanning the printer head and paper feeding; 26, a printer controller as a control unit of the printer 102; and 27, an operation unit for inputting instructions.

In the PC 103, 61 is an interface section of a 1394 serial bus, and 62 is a PCI (Peripheral Component Int.).
erconnect) bus, 63 is an MPU, 64 is a decoding circuit for decoding (decompressing) video (image) data compressed by a predetermined algorithm, 65 is a display with a built-in D / A converter and video memory, 66 is a hard disk, 67 is a memory such as a RAM or a ROM, and 68 is an operation unit including a keyboard and a mouse.

[Operation of Recording Apparatus 101] First, the operation of the recording / reproducing apparatus 101 will be described. When recording video (image) data, the video (image) signal output from the imaging system 4 is digitized by the A / D converter 5 and then processed by the video (image) signal processing circuit 6 for video (image) processing. Is done. One of the outputs of the video (image) signal processing circuit 6 is converted back to an analog signal by the D / A converter 11 as a video (image) during shooting, and is displayed on the EVF 12. Other outputs are subjected to compression processing by a compression algorithm by a predetermined algorithm, and are recorded on a recording medium by a recording / reproducing system 8. Here, the compression processing of the predetermined algorithm is a compression method based on the JPEG method typical of DSC and the DCT (discrete cosine transform) and VLC (variable length coding) which are typical band compression methods for home digital video. And the MPEG method are used.

When reproducing video (image) data, the recording / reproducing system 8 reproduces a desired video (image) from a recording medium. At this time, under the control of the system controller 9, a video (image) desired by the user is selected and reproduced based on the instruction input from the operation unit 10. Of the video (image) data reproduced from the recording medium, data that is transferred while being compressed is output to the frame memory 15. Also,
When the reproduction data is expanded to transfer the uncompressed data, the video (image) data expanded by the expansion circuit 7 is output to the frame memory 13. When the reproduced video (image) data is displayed on the EVF 12, the video (image) data expanded by the expansion circuit 7 is converted into an analog signal by the D / A converter 11 and displayed on the EVF 12.

The frame memories 13 and 15 are memory control units 14 controlled by the system controller 9, respectively.
The read / write is controlled by the and, and the read video data is output to the data selector 17. Of course, the outputs of the frame memories 13 and 15 are controlled so as not to be input to the data selector 17 at the same timing.

The system controller 9 includes the recording / reproducing device 1
01 controls the operation of each part in the printer 10
Control command data for an external device such as the PC 2 or the PC 103 can be transmitted from the data selector 17 to the external device via the 1394 serial bus. The transmission and reception of the command at this time uses the FCP data packet by the asynchronous transfer.

Various command data transferred from the printer 102 or the PC 103 are input from the data selector 17 to the system controller 9, so that the recording / reproducing device 1
By sending command data to 01, the recording and playback device 10
Operation of each part of 1 can be instructed. Among these, command data indicating the presence or absence of a decoder for video data or the type of the decoder, which is transferred from the printer 102 or the PC 103, is transmitted as a request command to the system controller 9.
After that, it is used for selecting compression / non-compression of the video data sent from the recording / reproducing apparatus 101. That is, the system controller 9 transmits the command to the memory control unit 14 or 15 in response to the request command, and
Control is performed so that video data corresponding to the request command is read from 13 or 15 and transferred.

More specifically, the system controller 9 determines whether to transfer the compressed or uncompressed data based on the information of the decoder included in each device transferred as a command from the printer 102 or the PC 103. That is, when it is determined that the compression method of the recording / reproducing apparatus 101 is decodable, the compressed video data is transferred, and when it is determined that the decoding is impossible, non-compressed video data is transferred.

The video (image) data and command data input to the data selector 17 are transferred by the 1394 interface unit 18 based on the specification of the 1394 serial bus, and received by the printer 102 or the PC 103. Command data is also appropriately transferred to the target node.

Regarding the data transfer method, mainly data such as moving images, still images and audio are transferred as synchronous data using a CIP header as real-time data, and command data is transferred as asynchronous data as FCP frame data. You. However, the still image data can be sent by asynchronous transfer according to the transfer situation such as network traffic when real-time guarantee is not required.

[Operation of Printer 102] Next, the printer 102
Will be described. The data input to the 1394 interface unit 19 is classified by the data selector 20 according to the type of data, and data to be printed such as video (image) data is decompressed by the decoding circuit 21 if compressed. Thereafter, it is output to the image processing circuit 22. At this time, since the data compression method and compression / non-compression are set in the recording / reproducing apparatus 101 based on information such as the presence or absence or type of the decoder instructed to the recording / reproducing apparatus 101 in advance, the compressed data In the case of (1), the data can be expanded by the decoding circuit 21 provided in the printer 102. Of course, the uncompressed data passes through the decoding circuit 21 and is directly input to the image processing circuit 22.

The data inputted to the image processing circuit 22 is subjected to image processing suitable for printing here, and read / write is controlled by a printer controller 26 in a memory 23.
Is developed as print image data. The print image data in the memory 23 is sent to the printer head 24, and a visible image based on the print image data is printed on recording paper. The operation of the driver 25 that performs drive scanning and paper feeding of the printer head 24, the operation of the printer head 24, and the operations of other units are controlled by the printer controller 23.

The operation unit 27 is for inputting instructions such as paper feeding, reset, ink check, and standby / start / stop of the printer operation. In response to the instruction input, the printer controller 26 controls the operation of each unit. Control behavior.

Next, if the data input to the 1394 interface section 19 is command data for the printer 102, the data is transmitted from the data selector 20 to the printer controller 26 as a control command, and the printer controller 26 The operation of each unit is controlled according to the command.

The decoding circuit 21 is described as an example of an encoding method supported by a decoder provided in the printer.
The EG method is conceivable. Decoding of JPEG-encoded data can be performed by hardware or software. Therefore, the JPEG decoding program file is stored in the ROM in the decoding circuit 21 or the decoding program is transferred from another node.
A decoder that decodes EG-encoded data may be used.

If the JPEG encoded image data is transferred from the recording / reproducing apparatus 101 to the printer 102 and is decoded in the printer 102, the transfer efficiency is higher than the transfer after returning to the uncompressed data. Needless to say. Also,
If the decoding is performed by software, the cost of the decoding circuit 21 of the printer 102 can be advantageously reduced.

As described above, the operation in which image data is transferred from the recording / reproducing apparatus 101 to the printer 102 and printed is so-called direct printing, and printing can be performed without requiring processing by the PC 103.

[Process of PC 103] Next, the process of PC 103 will be described. Video (image) data transferred from the recording / reproducing device 101 to the 1394 interface unit 61 of the PC 103 is transferred to each unit in the PC 103 via the PCI bus 62.

The MPU 63 performs various processes using the memory 67 as a work memory in accordance with an instruction input from the operation unit 68, an operating system (OS) or application software, and transfers the transferred video (image) data to a hard disk.
Record to 66. Here, since the data compression method and compression / non-compression are set in the recording / reproducing apparatus 101 based on information such as the presence or absence or type of the decoder instructed in advance to the recording / reproducing apparatus 101, the compressed data In case of PC10
It can be expanded by the decoding circuit 64 provided in 3. Therefore, when displaying video (image) data on the display 65, the compressed video (image) data is decoded (decompressed) by the decoding circuit 64.
Is input to the display 65 and uncompressed video (image)
The data is directly input to the display 65, D / A converted and displayed. As the decoding circuit 64, a decoder card of JPEG or MPEG system or the like incorporated in a motherboard, decoder software stored in a ROM or the like, or the like is used.

In this manner, the transferred video (image)
The data is input to the PC 103 and subjected to processing such as recording, display, and editing, and is further transferred from the PC 103 to another device.

[Data Transfer Procedure] FIG. 35 is a flowchart showing an example of a data transfer procedure in the device configuration shown in FIG.

In the recording / reproducing apparatus 101, video (image)
When transferring data to another device connected to the 1394 serial bus, the system controller 9 performs transfer setting based on the transfer destination specified by the user in step S1,
In step S2, a command including predetermined information notifying that data is to be transferred and information prompting to return information such as the presence / absence and type of a decoder included in the transfer destination device are transmitted to the transfer destination device. I do. The transfer destination device receiving this command returns predetermined transfer confirmation command data including the decoder information to the recording / reproducing device 101.

The system controller 9 of the recording / reproducing apparatus 101
After confirming the reception of the decoder information in step S3, the presence of the decoder at the transmission destination and the type of the decoder are determined, and in step S4, it is determined whether or not decoding is possible when the compressed data is transmitted, and the decoding is performed. If it is determined that it is possible, “decoder present” is set in step S5. If it is determined that decoding is impossible, or if the received transfer confirmation command data does not include decoder information, "no decoder" is set in step S6.

Here, the decoder information included in the transfer confirmation command data is data for the transmission source device that determines whether to transfer compressed data or uncompressed data. From the point of view of the equipment,
It also has a role as data requesting whether to transfer compressed data or uncompressed data.

If the transmission destination device can know the compression method used by the transmission source device in advance, the transmission destination device returns the command data in step S2.
It is also possible to request the transfer of compressed data or the transfer of uncompressed data directly.

Next, in step S7, the system controller 9 stores data corresponding to the video (image) to be transferred to the printer 102 or the PC 103 selected by the user from the video (image) recorded on the recording medium. The transfer of the video (image) data read from the medium and read from the storage medium in step S8 is started. Next, the system controller
In step S9, the set "presence / absence of a decoder" is determined, and in the case of "presence of a decoder", in step S10, the data is read from the frame memory 15 in which the compressed data read from the recording medium is directly stored. The memory control unit 16, the data selector 17, and the 1394 interface unit 18 are controlled so as to be transferred. In the case of "no decoder", in step S11, the memory control unit 14 and the data selector 17 are controlled to read and transfer data from the frame memory 13 in which the uncompressed data expanded by the expansion circuit 7 is stored. And the 1394 interface unit 18.

The transfer of the video data is performed by using the synchronous transfer of the 1394 serial interface.
The video data is transferred by receiving a transfer start command from 2 and repeatedly transmitting, for example, a frame of the video data to be transferred.

The system controller 9 proceeds to step S12
When the transfer completion command indicating that the reception of the video (image) data for one screen or a predetermined frame has been completed is received from the PC 103 or the printer 102, the transfer of the video (image) data ends.

Next, in step S13, the system controller 9 determines whether or not the transfer of another video (image) is instructed by the user, and when the transfer of another video (image) is instructed. Returns to step S7, and repeats steps S7 to S13.

If transfer of another video (image) has not been instructed, the process proceeds to step S14, where it is determined whether or not transfer of video (image) to another device has been instructed by the user. Step when transfer to device is instructed
Returning to S1, steps S1 to S14 are repeated. If transfer to another device has not been instructed, the process ends.

[Data Structure] First, the data structure of uncompressed image data transferred to the printer will be described.

FIG. 36 is a diagram showing a matrix of xy coordinates of uncompressed image data in a 525-60 system in accordance with NTSC which is one of video standards used in home digital video. The 525-60 system is a 525 scan line
This is video data that can be displayed interlaced at 60 frames per second, in which the effective display area is 720 × 480 pixels, the upper left coordinate is (0, 0), the lower right coordinate is (719, 479) Then, it is defined as a matrix space as shown in FIG. For example, the image data at the position of x = 716, y = 479 is the 47th image data.
Indicates the 716th dot pixel of 9 lines.

FIG. 37 is a diagram showing the structure of image data for one frame in an uncompressed format represented by YUV (4: 2: 2). Y represents luminance, U and V represent color differences, and YUV (4: 2: 2) represents 8-bit luminance data Y per pixel and 4-bit color difference data.
Expressed in U and V. The data blocks in line units are arranged in the order of U, Y, V, Y from left to right.
Since it is composed of byte data, 720 pixels per line is 14
It will consist of 40 bytes. Data blocks for each line are arranged in order from top to bottom of the image, and within one frame, line 0, line 1, ..., line 4
The order is 79.

FIG. 38 is a diagram showing the data structure of one frame in the uncompressed format represented by RGB. The RGB shown here represents the gradation of 8 bits for each color per pixel. In addition, the data blocks in line units are arranged from left to right in the order of R, G, B, and R, and each pixel is composed of 3 bytes of RGB data.
It will be composed of bytes. As data blocks for each line, they are arranged in order from top to bottom of the image,
In one frame, the order is line 0, line 1, ..., line 479.

FIG. 39 is a diagram showing a source packet for synchronous transfer including a line-by-line data block configured in an uncompressed format. The source packet is a data block unit in the synchronous transfer using the CIP shown in FIG. Here, a source packet is created by adding a 4-byte source packet header to a data block in units of one line. Therefore, by checking the line number portion of the source packet header of the synchronously transferred data,
You can check which line data. For example,
By re-capturing the source packet data that could not be captured in the first frame in the second frame, it is possible to perform a retry operation by synchronous transfer.

[Synchronous Transfer of Print Image Data] FIG. 40 is a diagram showing a data structure when the printer 102 receives the synchronous transfer data. Reference numeral 102 denotes a mechanism for receiving the minimum data required for printing.

First, the data retry will be described. When an image data transfer command command is issued from the printer 102 to the recording / reproducing device 101, the recording / reproducing device 10
1 repeatedly outputs still image data. The image data is output in order from the data of line 0.

It is assumed that the printer 102 receives the image data of the first frame, but an error has occurred in the data packet, and the printer 102 cannot capture the data of the fourth line. Then, the printer 102 fetches only the source packet of the fourth line from the image data of the next second frame and replenishes the missing image data. Printer 102
When it is confirmed that all the data has been collected, a transfer end command is returned to the recording / reproducing device 101, whereby the data transfer sequence is completed.

Next, a mechanism for constructing a printer system for configuring a printer buffer with a minimum necessary buffer capacity will be described.

In the case of an ink jet printer or the like, unlike the page printer, it is not necessary to start printing after receiving all the data for one frame. When data for a line required for one scan of the print head, that is, data for a line determined by the number of vertical dots of the print head is received, it is more efficient to print the data. In general, the printing time of the printer is longer than the transfer time of the image data by the recording / reproducing device 101, so that it is more efficient to sequentially print while receiving the image data.

Here, assuming an ink jet printer having a print head of 48 dots, the image data required for one scan is 48 lines × 720 pixels. The source packets to be received to perform the first scan of the print head may be 48 packets from line 0 to line 47, and when the necessary data is obtained, the printer head is scanned to print an image for 48 lines. Meanwhile, the recording and playback device 101
Since the transfer end command is not issued, the output of the still image data is repeated. The printer 102 arbitrarily fetches 48 packets from the line 48 to the line 95 at a timing when data for performing the second scan is required, and prints an image for 48 lines when the necessary data is completed.

By repeating the above operation, the printer 102 issues a transfer end command when data for performing the tenth scan from the last line 432 to the line 479 has been fetched.

That is, the recording / reproducing apparatus 101 is connected to the printer 102
While printing is in progress, the printer 102 repeatedly outputs still image data by synchronous transfer, so that the printer 102 captures and prints data of a size corresponding to the buffer capacity of the buffer memory and the number of dots of the print head. It can be performed.

Next, the case where the image data transferred to the printer is compressed in the DV format used for digital video will be briefly described.

FIG. 41 shows the 525-bit used in digital video.
FIG. 3 is a diagram showing the structure of DCT-compressed video data of 60 systems. The basic structure is to divide the vertical 480 lines into 10 in 48 lines, divide it into 5 and create a super block, divide one super block into 27 more macro blocks, It compresses video data in block units. Incidentally, it can be seen that the super block (S9, 3) in the figure indicates the fourth block from the left at the bottom.

Here, DCT compression used in DVC, DV
I won't go into detail about the format data,
As video information, data divided into 50 in super block units is distributed to source packets, and video data is transmitted and received by synchronous transfer. Also, since one source packet includes not only video data but also audio data and control data, etc., when capturing still image data continuously output from the recording / reproducing device 101 by the printer 102, the source packet header is described in the source packet header. Check the number of the super block that has been added, and if, for example, data is missing when the first frame is received, take in the missing data in the second frame and decompress the compressed data. Can perform a retry operation.

As described above, according to the present embodiment, the PC and the peripheral devices such as the printer, the DSC and the DVC are connected to the IEEE 13
94 In a configuration connected to a network using a general-purpose interface such as a serial interface, the same data is repeatedly and synchronously transferred until data reception at the receiving node is completed. .

When the printer is to perform printing based on data transferred from a recording / reproducing device such as DSC or DVC, the printer repeatedly performs synchronous transfer of still image data, so that the printer can control the buffer size of the reception buffer and the print head size. Since the data packet corresponding to the data size according to the specification can be captured and printed, the data transfer can be easily performed even when the receiving buffer of the printer is small.

[0163]

Second Embodiment Hereinafter, an information processing system according to a second embodiment of the present invention will be described. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[Structure] As a second embodiment, a system in which a recording / reproducing device 201 and a printer 202 shown in FIG. 42 are directly connected by a 1394 serial bus will be described. In this case, a direct print in which the printer 202 directly prints the video (image) data output from the recording / reproducing device 201 is realized.

FIG. 43 is a block diagram showing the configuration of the system according to the second embodiment. Basically, the recording and reproducing apparatus 201 and the printer 202 are connected by a 1394 serial bus except for the PC 103 from the configuration of the first embodiment shown in FIG.

The difference from the configuration of the first embodiment is that the recording / reproducing device 201 performs MPEG, JPEG, DV
The ROM 74 stores at least one type of decoding program for decompressing at least one type of video (image) data in accordance with the method and other types of video (image) data compression. Also, the recording / reproducing apparatus 201 shown in FIG. 43 does not have the frame memory 13 and the memory control unit 14, which are components for transferring uncompressed data.

The decoding program may be executed as required.
The data is read from the ROM 74 under the control of the read controller 73 by the system controller 9 and transferred from the data selector 17 to the printer 102 via the 1394 interface 18.
The decoding program is mainly transferred asynchronously, and is transferred before the transfer of the video (image) data or in parallel with the transfer of the video (image) data packet in the gap.

The printer 202, as a circuit for decoding video (image) data, stores the received decoding program in the rewritable memory 71 in whole or in part, and stores the decoding program stored in the memory 71. The received video (image) data is decoded by the decoding processing circuit 72 operating according to the program.

The memory 71 can store a decoding program corresponding to a device to which compressed data is transferred, and when used together with the decoding processing circuit 72, functions as a plurality of types of decoders. However, the configuration may be such that the memory 71 does not function at all unless the decoding program is stored in the memory 71. However, only a predetermined decoding program may be stored in the memory 71 in advance.

[Operation] As an operation of the second embodiment, when the compressed video (image) data is transferred from the recording / reproduction device 201 to the printer 202, the recording / reproduction device is transferred prior to the video (image) data transfer. A decoding program corresponding to the video (image) data compression method used in 201
An example will be described in which the data is read from the printer 202, transferred to the printer 202, stored in the memory 71, and used to decode the transferred compressed video (image) data. In this way, the video (image) data as compressed can always be transferred, so that the transfer efficiency is higher than when uncompressed video (image) data is transferred, and the printer 202 transmits the decoder information. It can be dealt with without it.

The recording / reproducing apparatus 201 may use one compression / expansion method for all video (image) data to be recorded, or may use a plurality of compression methods in which the compression method changes depending on the data amount or the recording time. They may be mixed.

FIG. 44 is a flowchart showing the operation in the second embodiment. The system controller 9 performs transfer settings based on the transfer destination specified by the user in step S21, in this case, the printer 202, and in step S22, selects the printer selected by the user from the video (image) recorded on the recording medium. Data corresponding to the video (image) to be transferred to 102 is read from the storage medium, and transfer of the video (image) data read from the storage medium is started in step S23.

Next, the system controller 9 determines in step 24 that the printer 202 to which video (image) data is to be transferred.
It is determined whether or not the decoding program needs to be transferred to the printer 202. If necessary, the decoding program is read from the ROM 74 and transferred to the printer 202 in step S25. When the transfer is unnecessary, that is, when the printer 9 has a function of decoding the compressed video (image) data to be transferred, or when the decoding program has already been transferred, the decoding program is not transferred.

Subsequently, in step S26, the system controller 9 sends the data to the memory controller 16 so that the data is read from the frame memory 15 in which the compressed video (image) data read from the storage medium is stored and transferred. The selector 17 and the 1394 interface 18 are controlled. The printer 202 decodes the compressed video (image) data according to a predetermined operation procedure, and starts a printing process of the obtained video (image) data.

When the transfer of the video (image) data is completed in step S27, the system controller 9 proceeds to step S28.
Then, it is determined whether or not transfer of another video (image) is instructed by the user, and if transfer of another video (image) is instructed, the process returns to step S22, and steps S22 to S2 are performed.
Repeat 8.

In the second embodiment having such a configuration, the compressed video (image) data is transferred as a repetition of the still image data by asynchronous transfer similarly to the data format of the first embodiment shown in FIG. This allows the printer 202 to perform a data retry operation when receiving video (image) data, and perform printing by taking in data of a size corresponding to the buffer capacity of the buffer memory and the number of dots of the print head. Can be.

There is no problem if video (image) data to be printed is sent from the recording / reproducing apparatus 201 to the printer 202 as uncompressed image data as shown in FIG.

As described above, according to the present embodiment, direct printing in which image data is directly transferred from a recording / reproducing apparatus to a printer without using a PC or the like for printing is also described.
The same effect as in the first embodiment can be obtained.

The term "abnormal" in the present invention mainly refers to a state in which data is missing. However, not only when data is missing, but when data is abnormal, for example, the received data is incorrect due to an error check code. This may be the case.

[0180]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or a CPU or MPU) of the system or the apparatus.
Needless to say, this can also be achieved by the PU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Examples of the storage medium for supplying the program code include a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM,
CD-R, magnetic tape, non-volatile memory card, ROM, etc. can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0184]

As described above, according to the present invention,
High-speed data transfer by synchronous transfer in an information processing system, an image processing system and a method thereof, and an information processing device and a computer-readable memory including a plurality of devices interconnected by a serial bus capable of synchronous transfer In addition, it is possible to provide an information processing system, an image processing system, a method thereof, an information processing apparatus, and a computer-readable memory for supplementing data when an abnormal part such as a missing part occurs in synchronously transferred data. Thus, the information obtained is very accurate and reliable. This effect is particularly effective when printing out a still image.

[Brief description of the drawings]

FIG. 1 is a diagram showing a general configuration example of a system to which the present invention is applied;

FIG. 2 is a diagram showing an example of a network system configured using a 1394 serial bus;

FIG. 3 is a diagram showing a configuration of a 1394 serial bus.

FIG. 4 is a diagram showing an address space in a 1394 serial bus;

FIG. 5 is a diagram showing a cross section of a 1394 serial bus cable;

FIG. 6 is a diagram for explaining a DS-Link (Data / StrobeLink) method of a data transfer method adopted in a 1394 serial bus;

FIG. 7 is a flowchart showing a series of sequences from generation of a bus reset signal to determination of a node ID to enable data transfer;

FIG. 8 is a flowchart showing details from monitoring a bus reset to determining a route;

FIG. 9 is a flowchart showing details of node ID setting;

FIG. 10 is a diagram showing an example of a network;

FIG. 11 is a diagram showing the locations and functions of registers by a CSR core;

FIG. 12 is a diagram showing the positions and functions of registers related to the serial bus in the CSR architecture;

FIG. 13 is a diagram showing the position and function of a register in which information on serial bus node resources is arranged in the CSR architecture;

FIG. 14 is a diagram showing an example of a configuration ROM in a minimum format;

FIG. 15 is a diagram showing an example of a general format configuration ROM.

FIG. 16 is a diagram for explaining a request for a bus use right;

FIG. 17 is a diagram illustrating permission to use a bus.

FIG. 18 is a flowchart showing a series of bus arbitration flows;

FIG. 19 is a diagram showing a request / response protocol for each of read, write, and lock commands based on the CSR architecture in the transaction layer;

FIG. 20 is a diagram showing a service in a link layer;

FIG. 21 is a diagram showing a temporal transition state in asynchronous transfer;

FIG. 22 is a diagram illustrating a format example of an asynchronous transfer packet.

FIG. 23 is a diagram showing a temporal transition state in synchronous transfer;

FIG. 24 is a diagram showing a format example of a packet for synchronous transfer;

FIG. 25 is a diagram showing details of a packet field;

FIG. 26 is a diagram showing an example of a temporal transition of a transfer state on a 1394 serial bus when synchronous transfer and asynchronous transfer are mixed;

FIG. 27 illustrates a relationship between a controller and a target.

FIG. 28 is a diagram showing a packet format of an asynchronous transfer including an FCP packet frame;

FIG. 29 is a diagram showing a structure of an AV / C command frame.

FIG. 30 is a diagram showing the structure of an AV / C response frame.

FIG. 31 is a view for explaining that CIP and real-time data are stored in a data portion of a synchronization packet;

FIG. 32 is a view for explaining that a source packet on the transmission side is divided into 1, 2, 4, and 8 data blocks and transmitted as a plurality of synchronization packets;

FIG. 33 shows a CIP header.

FIG. 34 is a block diagram showing a detailed configuration of each digital device shown in FIG. 1;

FIG. 35 is a flowchart showing an example of a data transfer procedure in the device configuration shown in FIG. 34;

FIG. 36 is a diagram showing a matrix of xy coordinates of uncompressed image data in a 525-60 system in accordance with NTSC which is one of video standards used in home digital video;

FIG. 37 shows an uncompressed format represented by YUV (4: 2: 2).
Diagram showing the image data configuration for one frame,

FIG. 38: 1 in an uncompressed format represented by RGB
A diagram showing a data structure of a frame,

FIG. 39 is a diagram showing a source packet for synchronous transfer including a data block in a line unit configured in an uncompressed format;

FIG. 40 is a diagram showing a data structure when a printer receives synchronous transfer data.

FIG. 41 is a diagram showing the structure of 525-60 system DCT-compressed video data used in digital video.

FIG. 42 is a diagram showing a second example of a system to which the present invention is applied;

FIG. 43 is a block diagram showing a configuration of a system according to a second embodiment;

FIG. 44 is a flowchart showing an operation in the second embodiment.

Claims (27)

[Claims] 1. An information processing system comprising a plurality of devices connected by a serial bus capable of synchronous transfer, a data supply means for synchronously transferring data stored in a storage medium, and the synchronously transferred data. And a data receiving unit for receiving, when there is an abnormal portion in the received data, the data receiving unit supplements the abnormal portion with data repeatedly and synchronously transferred by the data supply unit. Information processing system. 2. When the encoded data is synchronously transferred, the data supply means includes:
2. The information processing system according to claim 1, wherein a decoding program corresponding to the encoding is transferred. 3. The method according to claim 1, wherein the data supply unit asynchronously transfers a decoding program corresponding to the encoding when synchronously transmitting the encoded data. Information processing system. 4. The information processing system according to claim 1, wherein said serial bus is a bus conforming to the IEEE 1394 standard. 5. The information processing system according to claim 4, wherein the synchronous transfer is an isochronous transfer defined in the IEEE1394 standard. 6. The information processing system according to claim 3, wherein the asynchronous transfer is an asynchronous transfer defined in the IEEE1394 standard. 7. The information processing system according to claim 1, further comprising output means for outputting data received by said data receiving means to a printer. 8. The information processing system according to claim 7, wherein the printer is an ink jet printer. 9. An image processing system comprising a plurality of devices interconnected by a serial bus capable of synchronous transfer, a data supply unit for synchronously transferring image data stored in a storage medium, and the synchronous transfer. Data receiving means for receiving the received image data, and forming means for forming a visible image on a recording medium based on the image data received by the receiving means, wherein the data receiving means When there is a normal part, the abnormal part is supplemented by data repeatedly and synchronously transferred by the data supply means. 10. The data supply means synchronously transfers the image data as packets of a predetermined unit, and the data reception means converts the received image data each time a packet having a size corresponding to a reception buffer size is received. 10. The image processing system according to claim 9, wherein the image processing system supplies the image processing means to a forming unit. 11. The data supply unit synchronously transfers image data as a packet in a predetermined unit, and the data reception unit receives the image data every time a packet having a size corresponding to an image formation unit of the formation unit is received. 10. The image processing system according to claim 9, wherein image data is supplied to the forming unit. 12. The method according to claim 9, wherein said data supply means transfers a decoding program corresponding to said encoding, prior to transfer of said image data, when synchronously transferring encoded image data. An image processing system according to any one of claims 1 to 11. 13. The data supply means according to claim 9, wherein, when the encoded image data is synchronously transferred, a decoding program corresponding to the encoding is asynchronously transferred. An image processing system according to claim 1. 14. The system according to claim 9, wherein said serial bus is a bus conforming to the IEEE1394 standard.
3. The information processing system according to any one of 3. 15. The information processing system according to claim 14, wherein the synchronous transfer is an isochronous transfer specified in the IEEE1394 standard. 16. The information processing system according to claim 13, wherein the asynchronous transfer is an asynchronous transfer defined in the IEEE1394 standard. 17. The information processing system according to claim 9, wherein said image data is color image data. 18. An information processing method for an information processing system including a plurality of devices connected by a serial bus capable of synchronous transfer, wherein the data stored in a storage medium is repeatedly synchronously transferred, and the synchronous transfer is performed. An information processing method comprising: receiving data; if the received data includes an abnormal part, the abnormal part is supplemented with data that is repeatedly synchronously transferred. 19. An image processing method for an image processing system comprising a plurality of devices connected to each other by a serial bus capable of synchronous transfer, wherein the image data stored in a storage medium is repeatedly and synchronously transferred. When the transferred image data is received and the received data has an abnormal part, the abnormal part is supplemented with the data repeatedly and synchronously transferred, and a visible image is formed on a recording medium based on the received image data. An image processing method comprising: 20. A computer-readable memory storing a program code of an information processing method of an information processing system including a plurality of devices connected by a serial bus capable of synchronous transfer, wherein data stored in a storage medium is stored. A code of a step of repeatedly performing synchronous transfer, a code of a step of receiving the synchronously transferred data, and a code of a step of supplementing the abnormal part with data that is repeatedly synchronously transferred when the received data has an abnormal part. A computer readable memory comprising: 21. A computer readable memory storing a program code of an image processing method of an image processing system including a plurality of devices interconnected by a serial bus capable of synchronous transfer, the program code being stored in a storage medium. A code for repeatedly transmitting synchronously the image data, a code for receiving the synchronously transmitted image data, and if the received data includes an abnormal part, the abnormal part is repetitively transmitted by the synchronously transmitted data. A computer readable memory, comprising: a code of a supplementing step; and a code of a step of forming a visible image on a recording medium based on received image data. 22. The transfer step, wherein the image data is synchronously transferred as packets of a predetermined unit, and the receiving step includes the step of forming the received image data each time a packet having a size corresponding to a receiving buffer size is received. 22. The computer readable memory of claim 21, wherein the computer readable memory is provided. 23. An information processing apparatus connected to another device via a serial bus capable of synchronous transfer, a receiving unit for repeatedly receiving data to be synchronously transferred, and data received by the receiving unit. And a replenishing means for supplementing the abnormal part with the repeatedly received data when there is an abnormal part. 24. The information processing apparatus according to claim 23, wherein said serial bus is a bus conforming to the IEEE1394 standard. 25. The information processing apparatus according to claim 24, wherein the synchronous transfer is an isochronous transfer defined in the IEEE1394 standard. 26. The information processing apparatus according to claim 23, further comprising output means for outputting data received by said receiving means to a printer. 27. The information processing apparatus according to claim 26, wherein said printer comprises an ink jet printer.