JPH0578232B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image enlarging device that enlarges and displays a single screen image using a plurality of screens.

BACKGROUND ART There is an image enlarging device that writes an input video signal for one screen to a video memory, reads out the input video signal written to the video memory as a plurality of video signals, and displays them on a plurality of screens to enlarge the image. . In recent years, more and more devices of this type are configured with multiple screens using multiple projection televisions, and for this reason, the connections between the top and bottom and left and right pictures have become important.

Figure 5 shows a schematic configuration of an image enlargement device that uses, for example, four projection TVs and combines these four screens to form an image for one screen to realize enlarged display. The input video signal is written by the write address generator 2 into the regular field memory 1 according to the address specified for each pixel based on the vertical synchronizing pulse V _syoc , the horizontal synchronizing pulse H _syoc and the system clock. . The pixel data written in the field memory 1 is read out by a read address generator 4 in accordance with read addresses given in time series corresponding to each screen. Since this read data has pixels for each screen multiplexed, it is distributed in an operation completely opposite to the multiplexing of read addresses, and becomes output image data for four screens.

A timing chart of the above-mentioned operation is shown in FIG. 6, where b is the input image data, data in the upper half of the screen is represented by U (pper), and data in the lower half is represented by L (ower). . Here, the address given to the field memory 1 is reset at the same timing for both writing c and reading d. As a result, output image data e and (f) for the upper screen and lower screen are obtained. Note that for convenience of explanation, only the upper and lower image data have been described, but in reality, each of the upper and lower image data is further divided into left and right image data.

In such a configuration, as shown in FIG. 7b, even if the joint between the upper and lower screens is adjusted smoothly in the case of a still image, a discrepancy occurs at the joint between the upper and lower screens in the case of a moving image. There is a problem.
Here, it is assumed that the lighthouse is stationary and the yacht is moving to the left. This phenomenon in which discrepancies occur between the upper and lower screens is due to the fact that the display by scanning with a single beam is expanded using multiple beams (in this example,
This is an inconvenience caused by scanning with four beams), and is caused by the fact that the points (point A) that should originally be displayed almost simultaneously in FIG. 7 are displayed at different timings. The display time difference is the 6th
From figures b, e, and f, it is approximately one vertical synchronization period. The magnitude of the discrepancy between the upper and lower screens increases as the speed of the moving object increases. Note that a similar phenomenon occurs on the left and right screens, but since the time difference is as small as about one horizontal scanning period, it does not pose a visual problem.

Summary of the invention The present invention has been made in view of the above points, and
To provide an image enlarging device capable of smoothing the joint between upper and lower screens even when there is movement in the image.

The image enlarging device according to the present invention divides an input video signal for one screen into a plurality of parts for each screen display position, and enlarges each of the divided video signals in the vertical and horizontal directions. An image enlarging device that performs a display operation by supplying a plurality of images to a plurality of image display devices arranged in the vertical and horizontal directions, the image display devices being arranged adjacent to each other in the vertical scanning direction among the image display devices. The configuration includes time shifting means for relatively time-shifting the video signal supplied to the video signal by one vertical synchronization period.

Embodiments Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a luminance signal or color signal separated from a video signal and digitized becomes input image data to a field memory 1, which is a video memory. This field memory 1 can store image data for one field, which is 1/2 frame. Writing of data to field memory 1 is performed according to a write address designated by write address generator 2. Readout of data from field memory 1 is performed by readout control circuit 3
It is carried out by. This readout control circuit 3 receives the magnification information of the vertical and horizontal screens as input, and controls the process from reading out the data in the field memory 1 to final output. Further, four read address generators 4a to 4d are provided corresponding to the four screens, and these read address generators 4a to 4d vertically synchronize the read addresses for reading data for each screen from the field memory 1. Pulse V _syoc ,
Generated based on the horizontal synchronization pulse _Hsyoc and the system clock. The read addresses for each screen are multiplexed by an address multiplexer 5 and supplied to the field memory 1. Data read from the field memory 1 is distributed by a distribution switch 6 to H memories 7a to 7d corresponding to the respective screens of four image display devices such as projection televisions. The H memories 7a to 7d can store data for a maximum of 1H (horizontal scanning period).

Next, the operation of this configuration will be explained with reference to FIGS. 2 and 3.

The input image data is input by the write address generator 2 into a vertical synchronizing pulse V _syoc and a horizontal synchronizing pulse.
Data is regularly written into the field memory 1 according to the address specified for each pixel based on H _syoc and the system clock. Here, set the output to 4
In the case of a screen, it is assumed that the field memory 1 stores pixel data A to X (actually a very large number of pixels) as shown in FIG. 2a.
For this stored data, the image is enlarged by obtaining data as shown in FIG. 2b as output. Therefore, a third
The read addresses shown in Figure a are given in chronological order. This is the read address generator 4 corresponding to each screen.
Addresses output from each of a to 4d are multiplexed by an address multiplexer 5,
For the sake of explanation, in FIG. 3A, pixel data names are shown instead of real addresses, so this can also be seen as pixel data read out from the field memory 1.

Next, the distribution switch 6 performs an operation completely opposite to that in the case where the read addresses are multiplexed by the address multiplexer 5. That is, since the data read out from the field memory 1 is multiplexed with pixel data for each screen, these data are distributed to the H memories 7a to 7d corresponding to each screen.
This is shown in FIGS. 3b to 3e, where the distribution switch 6 is
Alternately outputs to H memory 7a, 7b in 1H, and the next
Alternately outputs to H memories 7c and 7d in 1H, and alternately outputs to H memories 7a and 7b in the next 1H,
Repeat this action.

Subsequently, the pixel data distributed to the H memories 7a to 7d are divided into 1/2 as shown in FIG. 3 f to i.
By reading out the data twice for 1H at a clock speed of The H memories 7a to 7d used here are FIFOs with a maximum capacity of 1H.
(First-In-First-Out) type memory, where the write and read clocks are input independently, and the third
Writing and reading resets are also possible, as indicated by the ↑ marks in Figures b to i. Furthermore, the distribution switch 6 can actually be replaced by supplying a switching signal to the write enable terminals of the H memories 7a to 7d.

In the present invention, the write address generator 2 further provides a reset signal generated from the reset pulse generator 8 in synchronization with the vertical synchronization pulse V _syoc and delayed by a delay circuit 9 having a delay time of approximately 1/2 the vertical synchronization period. Each read address generator 4a-4d is reset by the reset pulse directly supplied from the reset pulse generator 8. As a result, as shown in FIGS. 4c and 4d, the reset timing of the write address is time-shifted by about 1/2 vertical synchronization period with respect to the reset timing of the read address. According to this, as can be seen from FIG. 4 e and f showing each output image data of the upper screen and the lower screen, the reading of the output image data e of the upper screen is advanced by one vertical synchronization period, so that the output image data of the upper screen and the lower screen are Since point A located at the joint with the lower screen will be displayed almost simultaneously, even if there is movement in the image, the joint between the upper and lower screens will be smooth. In addition, the point at which the write address is reset is shifted by about 1/2 vertical synchronization period, so it corresponds to the point where the input image is just divided into the upper and lower screens, so it is moved in units of one scanning line for adjustment. It's becoming possible.

In FIG. 4, for convenience of explanation, only the upper and lower image data have been described, but in reality, each of the upper and lower image data is further divided into left and right image data. Furthermore, in this embodiment, since only one field memory 1 is used,
Judging from the timings shown in FIG. 4c and d, there seems to be a conflict between writing and reading, but for example, the first point of U2 (point B in FIG. 4b) is read out immediately after being written to field memory 1. Also, the last point of L1 (point C in Figure 4 f) is the last point of L2 (point D in Figure 4 b) which is the next screen immediately after being read out.
Since it will be rewritten to , no problem will occur.

From the explanation of the image enlargement process above, it is clear that the operation is performed in cases other than 4 screens, but for example, 3×3=
The operation in the case of 9 screens will be briefly explained. First, data is read from field memory 1 repeatedly in the following order: the top three screens in the first 1H, the middle three screens in the next 1H, and the bottom three screens in the next 1H. , H memory is read out three times at 1/3 clock speed. Here, compared to the case of 4 screens,
The only circuits added are a read address generator and H memory corresponding to each screen. Furthermore, how many times the screen is to be enlarged is determined by the vertical and horizontal magnification information given to the readout control circuit 3 in FIG. They can be set independently of each other, and can be set regardless of the number of read address generators and H memories. This means that, for example, you can easily perform enlargement using only 4 out of 9 screens, increase the enlargement rate to greatly enlarge just one part of the input image, or enlarge it vertically or horizontally. It shows.

Further, in the above embodiment, a case was explained in which one field memory was used, but in the present invention, two field memories are used, and while input image data is being written to one memory, input image data is input from the other memory. It is also applicable to a structure in which the operation of reading data to an output screen is repeated alternately every vertical synchronization period. Note that similar operations can be performed using a frame memory, and the use of a frame memory is extremely advantageous in reducing the cost of the device and enlarging the image by 9 times, 25 times, etc.

Furthermore, although Fig. 1 shows an example in which each luminance signal or chrominance signal of a color video signal is divided into four parts, it is sufficient to increase the field memory and H memory by the amount of each signal, and the control circuit other than the memory can be shared. can.

Effects of the Invention As explained above, according to the image enlarging device according to the present invention, among the plurality of image display devices arranged in the vertical and horizontal directions, one image display device arranged in the vertical direction is Since it is configured to supply a video signal time-shifted by the synchronization period, even if there is movement in the image, the seam between the upper and lower screens can be made smooth.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a diagram showing the correspondence of pixel data between 1 screen a and 4 enlarged screens b, Fig. 3 is a timing chart to explain the operation in units of 1H in Fig. 1, and Fig. 4 is the same as in Fig. 1. 5 is a block diagram showing a conventional example. FIG. 6 is a timing chart for explaining the operation of 1 field in FIG. 5. FIG. 7 is a timing chart for explaining the operation in 1 field units. Input image a when there is movement in the image
and an enlarged image b. Explanation of symbols of main parts, 1...Field memory, 2...Write address generator, 4a to 4d...
...Read address generator, 6...Distribution switch,
7a to 7d...H memory, 8...Reset pulse generator.

Claims (1)

[Claims] 1. An input video signal for one screen is divided into a plurality of parts for each screen display position, each of the divided video signals is expanded in the vertical and horizontal directions, and each of the expanded video signals is An image enlarging device that performs a display operation by supplying power to a plurality of image display devices arranged in the vertical and horizontal directions, the image display devices arranged adjacent to each other in the vertical scanning direction. An image enlarging device comprising time shifting means for relatively time shifting a supplied video signal by one vertical synchronization period. 2. The time shift means adjusts the reset timing of the write address for the video memory.
1/2 of the read address reset timing synchronized with the vertical synchronization pulse of the input video signal.
2. The image enlarging device according to claim 1, wherein the image enlarging device performs a time shift by a vertical synchronization period.