JPH01185074A - Image magnifying device - Google Patents

Abstract

PURPOSE:To cause the joint of upper and lower screens smooth even when an image is moved by providing a means to relatively time-shift a video signal displayed on screens arranged in a vertical scanning direction among plural screens only for 1 vertical synchronizing period. CONSTITUTION:A writing address generator 2 is reset by a resetting pulse to be generated synchronizing to a vertical synchronizing pulse Vsync from a resetting pulse generator 8 and, simultaneously, to be delayed by a delaying circuit 9 having the delay time of approximately 1/2 vertical synchronizing period, and respective reading address generators 4a-4d are reset by the resetting pulses to be directly supplied from the resetting pulse generator 8. Consequently, the resetting timing of the writing address is time-shifted by the approximately 1/2 vertical synchronizing period to the timing of the resetting of the reading address, and the reading of output image data (e) on the upper screen is made earlier by 1 vertical synchronizing period. Thus, A points located at the joint of the upper screen and lower screen are approximately simultaneously displayed, and the joint of the upper and lower screens can be made smooth even when the image is moved.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image enlarging device that enlarges and displays a single screen image using a plurality of screens.

BACKGROUND ART There is an image enlarging device that writes an input video signal for one screen to a video memory, reads out the input video signal written to the video memory as a plurality of video signals, and displays them on a plurality of screens to enlarge the image. . In recent years, more and more devices of this type have multiple screens configured using multiple projection televisions, and for this reason, the connections between the top and bottom and left and right pictures have become important.

FIG. 5 shows a schematic configuration of an image enlarging device for enlarging and displaying images on four screens, for example, in which a digitized input video signal is generated by a write address generator 2 into a vertical synchronizing pulse V5ync, a horizontal synchronizing pulse H5ync, and a system The data is regularly written into the field memory 1 according to the address specified for each pixel based on the clock.

The pixel data written in the field memory 1 is read out by a read address generator 4 according to read addresses given in time series corresponding to each screen.

Since this read data has pixels for each screen multiplexed, it is distributed in an operation completely opposite to the multiplexing of read addresses, and becomes output image data for four screens.

A timing chart of the above-mentioned operation is shown in FIG. 6, and (b) is the input image data, where the data in the upper half of the screen is U (pper) and the data in the lower half is L (
over). Here, field memory 1
The timing for resetting the address given to is the same for both writing (C) and reading (d). This results in
Output image data (e) and (
f) is obtained. Note that for convenience of explanation, only the upper and lower image data have been described, but in reality, each of the upper and lower image data is further divided into left and right image data.

In such a configuration, as shown in FIG. 7(b), even if the joint between the upper and lower screens is adjusted smoothly in the case of a still image, a discrepancy occurs in the joint between the upper and lower screens in the case of a moving image. There is a problem with this.

Here, it is assumed that the lighthouse is stationary and the yacht is moving to the left. This phenomenon of discrepancy between the upper and lower screens is an inconvenience caused by scanning the display by scanning one beam with multiple beams (four beams in this example) for magnification, as shown in Figure 7. This is because the points (point A) that should originally be displayed at almost the same time are displayed at different timings. The display time difference is about one vertical synchronization period from FIGS. 6(b), (e), and (f). The magnitude of the discrepancy between the upper and lower screens increases as the speed of the moving object increases. Note that a similar phenomenon occurs on the left and right screens, but since the time difference is as small as about one horizontal scanning period, it does not pose a visual problem.

Summary of the Invention The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an image enlarging device that can smooth the connection between the upper and lower screens even when there is movement in the image. .

The image enlarging device according to the present invention writes an input video signal for one screen into a video memory, and when reading out the manually input video signal stored in the video memory as a plurality of video signals and displaying them on a plurality of screens, The configuration is such that the video signals displayed on the screens arranged in the vertical scanning direction of the multiple screens, that is, the top and bottom screens, are relatively time-shifted by one vertical synchronization period (period equivalent to one field). .

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a luminance signal or color signal separated from a video signal and digitized becomes input image data to a field memory 1, which is a video memory. This field memory 1 can store image data for one field, which is 1/2 frame. Writing of data to field memory 1 is performed according to a write address designated by write address generator 2. Reading of data from field memory 1 is performed by read control circuit 3. This readout control circuit 3 receives the magnification information of the horizontal and vertical screens as input, and controls the process from reading out the data in the field memory 1 to final output. Additionally, four read address generators 4a to 4d are provided corresponding to the four screens, and these read address generators 4a to 4d vertically synchronize read addresses for reading data for each screen from the field memory 1. pulse v 5 sync.

It is generated based on the horizontal synchronization pulse H5ynC and the system clock. The read addresses for each screen are multiplexed by an address multiplexer 5 and supplied to the field memory 1. The data read from the field memory 1 is transferred to the H memory 7 corresponding to each screen by the distribution switch 6.
Distributed from a to 7d. H memories 7a to 7d have maximum IH
It is possible to store data for (horizontal scanning period).

Next, the operation of this configuration will be explained with reference to FIGS. 2 and 3.

Manual image data is written by write address generator 2 by vertical synchronization pulse V5yncs horizontal synchronization pulse H5ync
The data is written into the field memory 1 regularly in accordance with the address specified for each pixel based on the system clock and the system clock. Here, if the output is 4 screens, the field memory 1 contains pixel data A as shown in FIG. 2(a).
-X (which is actually a very large number of pixels) is stored. For this stored data, the second
The image is enlarged by obtaining data as shown in Figure (b). Therefore, the read addresses shown in FIG. 3(a) are given to the field memory 1 in chronological order. This converts the addresses output from each of the read address generators 4a to 4d corresponding to each screen to the address multiplexer 5.
For the sake of explanation, in FIG. 3(a), pixel data names are shown instead of real addresses, so this can also be seen as pixel data read out from the field memory 1.

Next, the distribution switch 6 performs an operation completely opposite to that in the case where the read addresses are multiplexed by the address multiplexer 5. That is, since the data read out from the field memory 1 is multiplexed with pixel data for each screen, these data are distributed to the H memories 7a to 7d corresponding to each screen.

This is shown in FIGS. 3(b) to (e), and the distribution switch 6
is output alternately to H memories 7a and 7b by IH, and the next IH
The operation of alternately outputting to the H memories 7c and 7d at the next IH and alternately outputting to the H memories 7a and 7b at the next IH is repeated.

Subsequently, as shown in FIG. 3(f) to (i), the pixel data distributed to the H memories 7a to 7d are read out twice for the IH with a 1/2 speed clock, so that the pixel data distributed to the H memories 7a to 7d are Image data for a screen enlarged twice in height and twice in height will be obtained. The H memories 7a to 7d used here have a maximum capacity of F I F O (Plrst-In
-Plrst-Out) format memory, the write and read clocks are input independently, and
), it is also possible to reset writing and reading as indicated by the ↑ mark.

In addition, the distribution switch 6 is also actually the H memory 7a to 7d.
This can be replaced by supplying a switching signal to the write enable terminal.

In the present invention, the write address generator 2 further receives a vertical synchronization pulse V S)'n from the reset pulse generator 8.
Each read address generator 4a to 4 is reset by a reset pulse generated in synchronization with e and delayed by a delay circuit 9 having a delay time of approximately 1/2 vertical synchronization period.
d is reset by the above reset pulse directly supplied from the reset pulse generator 8. As a result, as shown in FIGS. 4C and 4D, the reset timing of the write address is time-shifted by about 1/2 vertical synchronization period with respect to the reset timing of the read address. According to this, FIG. 4(e) shows each output image data of the upper side and the lower side.

As shown in (f), the output image data of the upper side (e
) is read out one vertical synchronization period earlier, point A located at the joint between the upper and lower surfaces will be displayed almost simultaneously, so even if there is movement in the image, the joint between the upper and lower screens will be displayed at the same time. becomes smooth. In addition, the point at which the write address is reset is shifted by about 1/2 vertical synchronization period, so it corresponds to the point where the input image is divided into upper and lower screens, so it is moved by about 1 scanning line pattern for adjustment.
It has become J Noh.

In FIG. 4, for convenience of explanation, only the upper and lower image data have been described, but in reality, each of the upper and lower image data is further divided into left and right image data. In addition, in this embodiment, the field memory 1 used
Since there is only one piece, writing and reading are likely to conflict based on the timings in Figures 4(C) and (d), but for example, the first point of U2 (point B in Figure 4(b)) Immediately after being written to field memory 1, it is read out, and the last point of Ll (point 0 in FIG. Since it is rewritten to point D in Figure (b), no problem occurs.

From the above description of the image enlargement process, it is clear that the operation in cases other than 4 screens is also possible, but the operation in the case of 3×3=9 screens, for example, will be briefly explained. First, to read data from field memory 1, read the top 31 screens to the first IH, the middle 3 screens to the next IH, and the bottom 3 screens to the next IH.
This is repeated for each screen, and reading from the H memory is repeated three times at a clock speed of 1/3. Here, compared to the case of four screens, the only additional circuits are the read address generator and H memory corresponding to each screen. Furthermore, how many times the screen is to be enlarged is determined by the vertical and horizontal magnification information given to the readout control circuit 3 shown in FIG. , - can be set independently from each other and can be set regardless of the number of read address generators and H memories. This means that, for example, you can easily enlarge using only 4 out of 9 screens, increase the magnification rate to greatly enlarge just one part of an image, or enlarge it vertically or horizontally. ing.

Furthermore, in the above embodiment, a case was explained in which one field memory was used, but in the present invention, two field memories are used, and while input image data is being written to one memory, input image data is transferred from the other memory. It is also applicable to a structure in which the operation of reading data to an output screen is repeated alternately every vertical synchronization period. Note that similar operations can be performed using a frame memory, and using a frame memory is extremely advantageous in reducing the cost of the device and enlarging the image by 9 times, 25 times, etc.

Furthermore, although Fig. 1 shows an example in which each luminance signal or chrominance signal of a color video signal is divided into four parts, it is sufficient to increase the field memory and H memory by the amount of each signal, and the control circuit other than the memory can be shared. can.

As described in detail, the image enlarging device according to the present invention writes a human video signal for one screen into a video memory,
When reading out the input video signal written to this video memory as multiple video signals and displaying them on multiple screens,
Since each video signal of the upper and lower screens is time-shifted relatively by one vertical synchronization period, even if there is movement in the image, the joint between the upper and lower screens can be made smooth.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the correspondence of pixel data between one screen (a) and four enlarged screens (b), and FIG. FIG. 4 is a timing chart for explaining the IH small unit operation, FIG. 4 is a timing chart for explaining the operation for one field unit in FIG. 1, FIG. 5 is a block diagram showing the conventional example, and FIG. FIG. 5 is a timing chart for explaining the operation of the first field li, and FIG. 7 is a diagram showing an input image (a) and an enlarged image (b) when there is movement in the image. Explanation of symbols of main parts 1...Field memory 2...Write address generators 4a to 4d...Read address generator 6...
...Distribution switches 7a to 7d...H memory 8...Reset pulse generator Applicant: Pioneer Corporation

Claims (2)

[Claims] (1) An image enlarging device that writes an input video signal for one screen into a video memory, reads out the input video signal written into the video memory as a plurality of video signals, and displays the plurality of video signals on a plurality of screens. An image enlarging device comprising time shifting means for relatively time-shifting video signals displayed on each of the screens arranged in the vertical scanning direction by one vertical synchronization period. (2) The time shifting means time-shifts the reset timing of the write address for the video memory by 1/2 vertical synchronization period with respect to the reset timing of the read address synchronized with the vertical synchronization pulse of the input video signal. The image enlarging device according to claim 1, characterized in that: