JPH0512892B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiplex data transmission system, and more particularly to a communication processing circuit for use in a multiplex transmission system in an automobile or the like.

[Background of the invention]

For example, automobiles are equipped with a large number of electrical components such as various lamps and motors, as well as electrical devices such as various sensors and actuators for controlling the automobile, and the number of these devices continues to increase as automobiles become more electronic. It's on.

For this reason, if each of these many electrical devices was wired independently as in the past, the wiring would be extremely complex and large-scale, resulting in increased costs, weight, and space. This causes serious problems such as an increase in the amount of energy used or mutual interference.

Therefore, as one method to solve these problems, it has been proposed to simplify the wiring by using a multiplex transmission method that can transmit a large number of signals with a small number of wiring lines. It can be seen in the publication No.

FIG. 1 shows an example of an in-vehicle integrated wiring system using such a multiplex transmission method.

The system shown in Figure 1 uses an optical fiber cable OF as a signal transmission path, and the central control unit CCU
(Hereafter, simply referred to as CCU. Note that this is Central
Control Unit) and multiple terminal processing units LCU
(Hereafter, simply referred to as LCU. Note that this is Local
(abbreviation for Control Unit) is commonly connected by an optical signal channel, and is an optical fiber cable.
An optical branch connector OC is provided at the branch point of OF.

The CCU is installed in a suitable location, such as near the car's dash board, and controls the entire system.

A predetermined number of LCUs are distributed in the vicinity of a large number of electrical devices installed in the automobile, such as various operation switches SW, indicators such as meters M, lamps L, and sensors S.

A photoelectric conversion module O/E that bidirectionally converts optical signals and electrical signals is provided at the portion where the CCU and each LCU are connected to the optical fiber cable OF.

The CCU is equipped with a microcomputer and has a data communication function using serial data.
It's called CIM. Please note that this is a Communication
Interface Adapter) is provided, and the CCU is
By sequentially selecting one of the LCUs and transmitting and receiving data to and from that LCU, multiplex transmission via one channel of optical fiber cable OF is possible, which is complicated and requires large amounts of data. It is possible to simplify the large-scale wiring inside a car.

Next, an example of such a data transmission system will be described in more detail.

Figure 2 is an overall block configuration diagram showing an example of this transmission system, and 10 is a central processing unit (in Figure 1).
20 is a signal transmission path (corresponds to the optical fiber cable OF in Figure 1), 30 to 32 are terminal processing units (corresponds to LCU in Figure 1), 40 is A/D,
51 to 58 are external loads. Note that this embodiment shows a case where an electrical signal transmission line is used as the signal transmission line 20, and therefore, a photoelectric conversion module is not required for the central processing unit 10 and the terminal processing units 30 to 32. , terminal processing device 3
The contents of 0 to 32 are essentially only CIM.

A central processing unit 10 including a computer (microcomputer) is connected to each terminal processing unit 30 to 32 via a transmission path 20, and data is transmitted to external loads 51 to 58 consisting of various sensors, lamps, actuators, motors, and other electrical devices. The transmission of data and the acquisition of data from these are performed using a multiplex transmission method. At this time, external loads 57 and 58 such as sensors that output analog data are
It is coupled to the terminal processing device 32 via the terminal 40, so that a digital data transmission operation can be performed.

The signal transmission line 20 may be of any type as long as it is bidirectional, and any type of signal transmission path such as not only an electrical signal transmission system but also an optical signal transmission system using an optical fiber may be used.
Duplex), in response to a call from the central processing unit 10 to one of the plurality of terminal processing units 30 to 32, data is exchanged between one of the terminal processing units and the central processing unit 10 via the transmission path 20. It is designed to be carried out alternately through

Because of this half-duplex multiplex transmission,
The data sent from the central processing unit 10 is attached with an address indicating its destination, and among the terminal processing units that recognize that the address attached to the data received from the transmission path 20 is its own address. only one of them is responding.

In this way, in response to data sent from the central processing unit 10 with an address attached, only one terminal processing unit that understands the address and determines that it is its own responds. By sending its own data to the central processing unit 10, the above-mentioned half-duplex data transmission operation can be achieved.

In addition, in this system example, each terminal processing device 3
The functions of terminal processing devices 30 to 32 are concentrated into specific ones, making it easy to implement LSI (large scale integrated circuit) of these terminal processing devices 30 to 32. The specific functions at this time include the above-mentioned data transmission function, that is, the function necessary for multiplex transmission using the half-duplex method, and controlling external equipment such as A/D 40 attached to each terminal processing device. There are two types of functions. As a result, it becomes possible to dedicate the data transmission function. For example, when applied to an integrated wiring system in a car, the above-mentioned half-duplex method is used, and the required transmission speed and number of address bits are adjusted. You can do things like decide accordingly.

Furthermore, this multiplex transmission method utilizes the functions of the LSI-based terminal processing device as described above and can be applied to the central processing unit 10. As a result, the central processing unit 10 can perform the data transmission function. Using a general-purpose computer (such as a microcomputer) that does not have
The central processing unit 10 can be configured simply by combining the LSI terminal processing units 33, and the software load required on the computer of the central processing unit 10 can be reduced, and the terminal processing unit can be used as a general-purpose terminal processing unit. You can increase your sexuality. In this case, some of the functions of the terminal processing device 33 combined with the central processing unit remain unused, but this is unavoidable.

Next, FIG. 3 shows a rough block diagram of the configuration of each terminal processing device 30 to 32.
The received signal RXD input from 0 is sent to the synchronization circuit 10.
2, synchronizes the clock from the clock generator 107, and sends the received signal to the control circuit 101.
A clock synchronized with the clock component of RXD is applied, whereby the control circuit 101 generates a control signal and serially reads the data portion of the received signal into the shift register 104.

On the other hand, the address comparison circuit 103 is given an address previously assigned to the terminal processing device, and this address and the shift register 104
The address comparison circuit 103 compares the data read into a predetermined bit position of the shift register 104, and only when the two match, the data in the shift register 104 is transferred to the I/O buffer 105 and provided to an external device.

Further, the control circuit 101 includes a counter that is incremented by a clock, generates a sequential control signal, and after giving the data according to the received signal RXD to the I/O buffer 105, the control circuit 101 subsequently outputs the data to the I/O buffer 105. to shift register 104
The data to be transmitted from the external device to the central processing unit 10 is prepared in the shift register 104 as serial data. Then, this data is transferred to the shift register 104.
The received signal TXD is read out serially and sent to the transmission line 20 as the received signal TXD. At this time, the received signal
Since the address attached to RXD is attached to the transmission signal TXD as it is and sent out, the central processing unit 10 takes in this transmission signal TXD because it matches the address sent by itself, and thereby half One cycle of data exchange using the duplex method is completed.

In this way, the central processing unit 10 sends data to the next terminal processing device, and by repeating this, data is periodically exchanged with each of the plurality of terminal processing devices 30 to 32, and multiplex transmission is performed. It becomes possible.

The A/D control circuit 106 is an A/D 4 necessary when used as the terminal processing device 32 in FIG.
0 control function, and provides the control function necessary to digitize data from external loads 57, 58 such as sensors that generate analog signals and input it into the shift register 104 by the A/D 40. do the work. Note that the details will be described later.

Next, FIG. 4 is a block diagram showing an example of the terminal processing devices 30 to 33, in which the same or equivalent parts as in FIG. 3 are given the same reference numerals. In this FIG. A synchronization circuit 302 is for generating a clock that is asynchronously synchronized with 2.
Counter for generating phase clocks φ _S and φ _M , 30
3 is a counter for sequential control; 304 is a sequence decoder that generates various control signals from the output of the counter 303; 305 is an abnormality detector;
306 is an address decoder for input/output switching selection of the I/O buffer 105, 307 is a 4-bit comparator for address comparison, 308 is an error detection circuit, and 310 is a composite gate consisting of two AND gates and one NOR gate. , 311 is an exclusive OR gate for error detection, 312 is an AND gate for data transmission, 313 and 314 are tri-state buffers, 320 is an 8-bit shift register, 321 is a 32-bit register, 322
32 is a gate for channel 32, 323 is an A/D control counter, 324 is an A/D control signal generation circuit, and 325 is a counter for A/D channel selection. Note that the shift register 104 is 25 bits (24 bits + 1 bit), and the I/O buffer 1
05 has 14 ports (14 bits).

These terminal processing devices 30 to 33 (hereinafter referred to as
CIM) is designed to operate by selecting one of multiple operating modes, and the CIM shown in Figure 2
When used as CIM 30 to 31, DIO mode is selected, when used as CIM 32 in FIG. 2, AD mode is selected, and when used as CIM 33 in FIG. 2, MPU mode is selected.
Note that this mode selection will be described later.

First, when DIO mode is selected, A/
The D control circuit 106 does not operate, and the data contents of the shift register 104 at this time become as shown in FIG. 14 bits up to .19 are allocated to data DIO of I/O buffer 1005. Four bits from No. 20 to No. 23 are allocated to address data ADDR, and No. 24 is allocated to the start bit. Note that the number of bits allocated to DIO data is 14 because it is
This is because the O buffer 105 is of 14 bits. Also, for this reason, in this CIM,
The maximum number of external loads that can be connected to the I/O buffer 105 is 14.

The data transmission method used by this system is called a start-stop synchronization, bidirectional, inverted dual transmission method, and digital data is transmitted in NRZ (nonreturn to
The transmission waveform is as shown in FIG. 6. In other words, the frame that transmits data from the CIM on the CCU side to the CIM on the LCU side is the receive frame, and vice versa.
If the frame transmitted from the LCU side to the CCU side is a transmission frame, both the reception frame and the transmission frame are 74 bits, so one frame is 148 bits. Both the receive frame and the transmit frame have the same frame structure, with 25 bits of “0” at the beginning, followed by a start bit consisting of 1 bit of “1” for start-stop synchronization, and then Then 24 bits of received data
RXD or transmit data TXD is transmitted in NRZ signal format, and the inverted data of these data is
RXD or is now being transmitted.
Note that this inverted data is transmitted for the purpose of checking transmission errors.

As already explained, in this system, multiplex transmission is performed using the half-duplex method, so the first 4 bits of the data RXD of the received frame are
The CCU will be the person to whom the call will be made at that time.
Address data ADDR of the LCU is attached as shown in FIG. 5, and in response to this, the same address data ADDR is attached to the first 4 bits of the data TXD of the transmission frame sent out from the LCU and transmitted. Furthermore, since the transmit frame is transmitted from the LCU side only to the LCU called by the CCU side, even if an address is not added to the transmit data TXD, the CCU side cannot tell which LCU the data is from. You can immediately determine whether there is one.
Therefore, it is not necessary to attach an address to the data TXD of the transmission frame, and the first 4 bits of the data TXD may be data such as (0000) that does not match any address of the LCU.

Now, returning to FIG. 4, the CIM address will be explained.

As already explained, this system
A different 4-bit address is assigned to each CIM on the LCU side, and data is multiplexed in a half-duplex system based on this address.

The inputs that serve to allocate this address to each CIM are the four inputs 2 ⁰ to 2 ³ connected to the comparator 307, and the address of the CIM is determined by the data ADDR to ADDR3 that should be given to these inputs. It is specified. for example,
To specify the address of the CIM as “10”, address data ADDR0=0, ADDR1=
1, ADDR2=0, ADDR3=1, input 2 ⁰
〜2 ³ (1010) should be input.
Note that in this system, data "0" is represented by the ground potential and data "1" is represented by the power supply voltage Vcc, so for address "10", input 2 is
⁰ and 2 ² are grounded, and inputs 2 ¹ and 2 ³ are connected to the power supply.

By the way, in this CIM, address input 2 ⁰ ~
2 ³ is also input to the address decoder 306, and the directionality of the I/O buffer 105 is controlled by its output. As a result, when an address is specified, it is determined which of the 14 terminals of I/O buffer 105 will serve as a data output port. In this system, the address directly corresponds to the number of output ports. Therefore, if the address is set to "10", 10 of the 14 terminals of the I/O buffer will become output ports, and the remaining 4 will become input ports.

Although omitted in FIG. 4, the output of this address decoder 306 is also given to the sequence decoder 304 of the control circuit 101, so that the operation mode of this CIM can be switched as shown in FIG. It's getting old. In other words, in this system, if the address is set to “0”,
CIM is in MPU mode, CIM with address set between “1” and “D” is in DIO mode,
The CIMs whose addresses are set to either "E" or "F" are operated in AD mode.

Next, the functions of the control circuit 101 and the synchronization circuit 102 will be explained.

As already explained in connection with FIG. 6, this system employs the start-stop synchronization method. Therefore, when data is transmitted in both the receive frame and the transmit frame, 25 bits of "0" are always set before the start of data transmission. is inserted, and then "1" data is inserted as a 1-bit start bit (FIG. 6).

Therefore, the synchronization circuit 301 detects the rising edge of the start bit following the first 25 bits of "0" in the transmission frame, and establishes bit synchronization of the internal clock. Therefore, until the next received frame appears, operations are performed using the internal clock that is bit synchronized with the timing at this time.

A counter 302 generates two-phase clocks φ _S and φ _M from an internal clock synchronized by a synchronization circuit 301 . As a result, the clocks φ _S and φ _M become phase-synchronized with the received data RXD that is subsequently input.

The sequence counter 303 receives a signal representing the rising edge detection timing of the start bit from the synchronization circuit 301, is set to a specific count value, for example, count 0, and is then counted by the clock _φS or _φM . Therefore, the control procedure for the entire CIM can be determined based on the count output, and by looking at the count value, it is possible to know which step the CIM is in at any given timing.

Therefore, the count output of this counter 303 is supplied to the sequence decoder 304, and this CIM
Control signals required for operation, e.g. RXMODO,
All internally required control signals such as TXMODE, READ, and SHIFT are sent to the sequence decoder 304.
I am trying to make it occur. In other words, this embodiment uses a sequence control method using clocks φ _S and φ _M , and therefore the counter 3
By decoding the output of 03, all necessary controls can be performed.

Next, the transmitted data RXD is
The operation of determining whether or not the data is directed to the CCU, that is, whether or not the call by transmission of the received frame from the CCU is directed to the CCU will be explained.

As already explained, one input of the comparator 307 is given the address data from the inputs 2 ⁰ to 2 ³ , and the other input is given the data from the Q ₂₀ bit to the Q ₂₃ bit of the shift register 104. is now being given. The comparator 307 outputs a match signal MYADDR only when both input data match. Therefore, the received data is stored in the shift register 104.
RXD is input, and the output signal of the comparator 307 is output at the timing when the address data (see Figure 5) attached to the beginning of the data RXD is stored in the part from _Q20 bit to _Q23 bit.
Examine MYADDR and then use this signal
If MYADDR is “1”, that data
I can see that RXD is for me, and the call from CCU is for me.

Therefore, a control signal is sent to the error detection circuit 308.
Supply COMPMODE, take in the signal MYADDR at the predetermined timing mentioned above, and when it is “0”, generate the output INITIAL,
As a result, the sequence counter 303 is set to count 0, and the operation of the entire CIM is restored to its original state in preparation for inputting the next data transmission. on the other hand,
When the signal MYADDR was “1”,
Since INITIAL is not generated by the error detection circuit 308, the operation of the CIM continues as it is according to the count value of the sequence counter 303 at that time.

Next, the transmission error detection operation will be explained.

In this system, as already explained with reference to FIG. 6, data transmission is performed using the inverted two-continuous transmission method, thereby making it possible to detect transmission errors. For this reason, data is given to the exclusive OR gate 311 from the first _Q0 bit and the last _Q24 bit of the shift register 104, and the output of this gate 311 is used as a signal.
It is designed to be given to the error detection circuit 308 as ERROR.

The sequence decoder 304 outputs the control signal RXMODE during the transmission period of the received signal RXD following the start bit (FIG. 6) and controls the composite gate 3.
Open the lower gate of 10, thereby opening the transmission line 2.
The data starting from 0 is input to the shift register 104 as a serial signal SI. At this time, composite gate 3
Since 10 includes a NOR gate, data supplied from transmission line 20 is inverted and input to shift register 104 .

Therefore, when the 24 bits of data following the start bit of the received frame (Fig. 6) are input to the shift register 104, the portion from bit _Q0 to bit _Q23 of this shift register 104 contains the received signal RXD. The inverted data will be written. Next, as is clear from Figure 6,
After the 24-bit received signal RXD is transmitted, a 24-bit inverted signal is subsequently transmitted, which is inverted at the composite gate 310 to become data RXD, which is input to the shift register 104 as the serial signal SI. begins to be As a result, at the timing when the first bit of the inverted signal of _Q0 is inverted and inputted to the shift register 104, the inverted data of the first bit of the received signal RXD written previously is input to the shift register 104.
At the timing when the data of the second bit of the inverted signal RXD is written to _{the Q24 bit} of the received signal RXD, the data of the second bit of the received signal RXD is transferred to the _Q24 bit. , inverted signal
At each bit timing when RXD is serially written to the shift register 104 one bit at a time, the _Q24 bit of the shift register 104 and the _Q0
The same bit data of the received signal RXD and the inverted signal are always written in correspondence to the bits.

By the way, as described above, the two inputs of the exclusive OR gate 311 are inputted with the data of the Q ₀ bit and the Q ₂₄ bit of the shift register 104. Therefore, the received signal RXD and the inverted signal
If no error occurs during the transmission of RXD, the output of the exclusive OR gate 311 should always be "1" during the transmission period of the inverted signal. This is because each corresponding bit of the received signal RXD and its inverted signal is always “1”.
and "0" should be inverted, and as a result, the input to the gate 311 always indicates a mismatch, and this only occurs when an error occurs in the transmission.

Therefore, the error detection circuit 308 uses an inverted signal
During the 24-bit period when RXD is being transmitted, the signal
If you monitor ERROR and generate the signal INITIAL when it reaches the "0" level,
Error detection behavior is obtained. In addition, as a method for handling transmission errors in such data transmission systems, there is also a known method in which when a transmission error is detected, it is repaired and correct data is obtained. At that point, the system cancels the data reception operation for that frame and prepares for data reception for the next frame, thereby simplifying the configuration.

Next, the overall operation of data transmission in the DIO mode of the CIM shown in FIG. 4 will be explained with reference to the timing chart shown in FIG.

φ _M and φ _S are two-phase clocks output from the counter 302, and are generated based on an internal clock from a clock oscillator included in the synchronous circuit 301.

On the other hand, is a signal supplied to this CIM from the outside, which is the same as a reset signal for a microcomputer, etc., and is used for all CIMs in Figure 2.
It is supplied from an external reset circuit when necessary, such as when the power is turned on, and initializes the entire transmission system.

After initialization, sequence counter 3
03, the count value is set to 0, and from there it is incremented by the clock _φM . No operation is performed until the count value reaches 25, and when the count value reaches 25, the IDLE signal is generated, the CIM enters the idle state, and sequential control based on the count value of the sequence counter 303 is stopped. , tri-state buffer 31
3 opens and becomes ready to receive signals. At this time, after initialization, sequence counter 3
The synchronization circuit 30 prevents the signal from being ready for signal reception until the count value of 03 reaches 25.
1 for start-stop synchronization, and the received signal RXD
This is because since the number of bits is 24 bits, it is necessary to provide a "0" period of at least 25 bits.

When entering the idle state, the sequence counter 302 continues to increment by counting the clocks φ _S and φ _M , but the sequence decoder 304 continues to generate the control signals IDLE and INITIAL and simply waits until the received signal is input. It will be in a waiting state. For this purpose, 25 bits of "0" are added to the beginning of each received frame and transmitted frame, as shown in FIG.

In this way, I entered an idle state, and now,
Assume that the received signal RXD is input at time _t0 . Then, a 1-bit start bit is attached to the beginning of this signal RXD. Therefore, the synchronization circuit 301 detects this start bit and performs bit synchronization of the internal clock. Therefore, from now on,
Data until transmission operation for one frame is completed
The synchronization between RXD, clocks _φM and _φS is maintained by the stability of the internal clock, and an astop synchronization function is obtained.

When the start bit is detected, the sequence counter 303 is set to a count output of 0 (hereinafter, the output data of this counter 303 will be denoted by S and, for example, S0 in this case), and the sequence decoder 304 will be controlled by this. Stop signal IDLE and generate control signal RXMODE. Further, in parallel with this, a shift pulse SHIFT is supplied to the shift register 104 in synchronization with the clock _φM .

As a result, the 48-bit received signal RXD following the start bit and the inverted signal (Fig. 6) are written as serial data from the transmission line 20 through the composite gate 310 to the shift register 104 while being shifted one bit at a time. go. At this time, the first 24-bit received signal RXD is sent to the composite gate 31.
Since the data is serially written into the shift register 104 as data inverted by 0, during the 24-bit period following the start bit, that is, when the sequence counter 303 reaches from S1 to S24, Q ₀ of the shift register 105 Data obtained by inverting the received signal RXD is written into the bits from bit to _Q23 . Here, a control signal is output at the next rising edge of the clock φ _M in S25, and the error detection circuit 3
08 works. Then, in this state, an inverted signal begins to be input, and as a result, data RXD, which is an inverted version of the inverted signal, is serially written from the _Q0 bit of the shift register 104. As a result, the data written to the shift register 104 from S1 to S24 passes from the first bit to the Q24 bit position of the shift register 104, and the sequence counter 303 starts at the _Q24 bit position of the shift register 104.
From then to S48, one bit is sequentially overflowed. Meanwhile, in parallel with this, data RXD based on the inverted signal is serially written through the _Q0 bit position of the shift register 104, starting from the first bit. Detection of transmission errors proceeds as described above.

Therefore, when the sequence counter 303 reaches S48, data RXD, which is the same as the received signal RXD, is written directly into bits _Q0 to _Q23 of the shift register 104.
Therefore, by checking the output signal MYADDR of the comparator 307 at the timing of S48, the above-mentioned address is confirmed, and it is possible to determine whether the data RXD just received is addressed to itself or not, that is, whether the data RXD received from the CCU at this time is A judgment is made as to whether or not the call is addressed to the user. In addition,
If a transmission error or address mismatch is detected while the sequence counter 303 is between S25 and S48, the error detection circuit 308 outputs a control signal at the time S48 is reached.
INITIAL is generated, and at this point the sequence counter 303 is set to S0 and returns to the state of 25 bits before idle, all reception operations for this received frame are canceled and preparations are made for inputting the next signal.

Now, when no transmission error is detected while the sequence counter 303 is from S25 to S48, and no address mismatch is detected, that is, when S48 is reached, the error detection circuit 308 is activated.
When the INITIAL signal is not generated, the sequence decoder 304
generates the control signal WRITESTB. As a result, at the time of S48, the INITIAL signal and
When one of the WRITESTB signals is generated, the latter is output when neither a transmission error nor an address mismatch occurs, and the former is output when either a transmission error or an address mismatch occurs.

Now, when the control signal WRITESTB is output at the time of S48, the shift register 104 at that time
data is written to the I/O buffer 105 in parallel, and as a result, the data brought from the CCU by the received data RXD is transferred from the output port of the I/O buffer 105 to any of the external loads 51 to 56. supplied to In addition, at this time,
Since it operates in DIO mode, a maximum of 14 bits from Q ₆ bits to Q ₁₉ bits can be transmitted as data RXD as explained in Figure 5, and how many bits of these can be transmitted as I/O As already explained, whether the output port of the buffer 105 is determined by the address is determined.

When the process reaches S48, all the processing of the received frame is completed, and the processing of the transmitted frame starts from the next step S49 (FIG. 6).

First, no processing is performed from S49 to S72. This is due to start-stop synchronization of the CIM on the CCU side, and is due to the start-stop synchronization of the CIM on the CCU side.
It is intended for the same purpose as the operation with the period set before IDLE.

When entering S73, the sequence decoder 304 outputs the control signal PS, which causes the shift register 104 to perform a parallel data reading operation, which is applied to the input port of the I/O buffer 105 from one of the external loads 51 to 56. Enter data in parallel. The number of bits of data read at this time is 14-bit I/O buffer 105.
This is the number of bits remaining after subtracting the bits used as output ports for processing the received frame. For example, as mentioned above, when the address of this CIM is set to 10, the number of output ports will be 10, so in this case the input port will be 4 bits.

To write parallel data to the shift register 104, the shift clock is used together with the signal PS.
Since 1 bit of SHIFT is required, after raising the signal SP by the clock _φS of S73,
Shift pulse SHIFT synchronized with clock φ _S of 4
is supplied before the rise of the control signal TXMODE.

Also, at this time, as is clear from Figure 6,
Add a start bit before the transmit data TXD,
Furthermore, an address must be added to the first 4 bits of data TXD. Therefore, although it is omitted in FIG. 4, only during the period when the signal PS is generated, the _Q24 bit of the shift register 104 receives a signal representing data "1", and the _Q20 to _{Q23 bits receive a signal representing data "1} ". Address data is supplied to the sections from inputs ²⁰ to ²³ , respectively.

In this way, after the 25-bit data "0" transmission period necessary for asynchronous synchronization is set by the DUMMY state from S49 to S73, the control signal TXMODE rises at S74, which causes the TX
(transmission) state. The generation of signal TXMODE activates the upper AND gate of composite gate 310, which in turn activates AND gate 312. As a result, Q ₂₄ of shift register 104
Bit data, ie, data "1" serving as a start bit, is sent to the transmission line 20 through the AND gate 312. And the following S75
The contents of the shift register 104 are shifted one bit at a time to the next stage by the shift clock SHIFT generated in synchronization with the subsequent clock _φM , and are sent to the transmission line 20 from the _Q24 bit through the AND gate 312, thereby forming the transmission frame ( A transmission signal TXD including the start bit shown in FIG. 6) is transmitted.

On the other hand, in parallel with data reading from the shift register 104, the data read from the _Q23- bit cell is inverted through the composite gate 310 and supplied to the serial input of the shift register 104. As a result, from S75 onward, the transmission data TXD written from bit _Q0 to bit _Q23 of the shift register 104 is transferred bit by bit to the transmission line 2 by the shift clock SHIFT.
At the same time, it is inverted and sequentially written from the _Q0 bit of the shift register 104 as serial data SI.

Therefore, when all the transmission data TXD written in the cells of the _Q0 bit to _Q23 bit of the shift register 104 during the period when the control signal PS is being generated has been read out, the transmission data TXD is written from the _Q0 bit to the _Q23 bit. In the cells up to the bit, inverted data is stored in place of the previous transmission data TXD.

Therefore, after the reading of the transmission data TXD is completed, the reading of the inverted data from the shift register 104 is subsequently started, and as shown in FIG. It will be sent out on the 20th.

In this way, when reaching S122, shift register 1
Since all the inverted data from the _Q23 bit to the _Q0 bit of 04 has been read out, the control signal TXMODE falls, the supply of the shift clock SHIFT is also stopped, and the transmission state ends. Then, the control signal INITIAL is generated by the next clock φ _M following S122, the sequence counter 303 is set to S0, and the CIM returns to the signal reception preparation state before IDLE.

Therefore, according to this system, half-duplex multiplex communication using start-stop synchronization, bidirectional, and inverted two-way transmission can be reliably performed between the CCU and LCU, and the transmission path can be consolidated and wired. be able to.

Next, the operation of CIM in AD mode in this system will be explained.

As mentioned above, external loads 57, 5 that output analog signals, such as various sensors, are electrical devices that should exchange data with the CCU via the CIM.
8 (FIG. 2), therefore, in the embodiment of the present invention, it includes an A/D control circuit 106 and also has a function of controlling the external A/D 40. The operating mode of CIM at this time is AD mode.

Now, as already explained, this CIM
In this case, the operation mode is set by the address data to be applied to inputs ²⁰ to ²³ , and the address data corresponding to AD mode is "E" and "F" as shown in FIG. ”.

Next, shift register 104 when this CIM is set to operate in AD mode.
The contents of the data stored in the A/D 40 are as shown in Figure 5, and the 8 bits from No. 0 to No. 7 are stored in the A/D 40.
taken in from external loads 57, 58, etc. via
For storing AD data, 2 bits No.8 and No.9 are
It is for storing AD channel data, which allows
For DIO data, there are 10 bits from No. 10 to No. 19. Note that the other details are the same as in DIO mode. In addition, the AD channel data at this time is data for specifying a channel when a multi-channel A/D is used, and since this system uses a 4-channel A/D 40, 2 bits are used. It is being assigned.

The shift register 320 is an 8-bit type that stores digital data (A/D converted analog data given from external loads 57, 58, etc.) serially taken in from an external A/D 40 and converts it into parallel data. In addition to enabling readout, A/
Counter 3 for specifying D40 channel
It functions to accept 2-bit channel selection data given from A/D 25 in parallel, read it serially, and supply it to A/D 40.

Register 321 is 32 bits, and A/D4
Since 0 is 8 bits and corresponds to 4 channels, it is used as an 8-bit 4-channel register, and stores data taken in from the A/D 40 in 8 bits for each channel.

The gate 322 also has 32 bits (8 bits, 4 channels) corresponding to the register 321, and AD channel data read from the _Q8 bit and _Q9 bit cells of the shift register 104 for data transmission (Fig. 5). controlled by register 32
It functions to select one of the channels of 1 and write the 8-bit data into the shift register _Q0 bit to _Q7 bit cells as AD data (FIG. 5).

The counter 323 is incremented by the count of the clock φ _M and serves to control the entire operation of the A/D control circuit 106 sequentially and cyclically.

The A/D control signal generation circuit 324 is the counter 3
The A/D control circuit 106 includes a decoder and a logic circuit for decoding the output of the A/D control circuit 106, and functions to generate various control signals necessary for the operation of the entire A/D control circuit 106.

Next, the overall operation of this A/D control circuit 106 will be explained.

In this CIM, control proceeds sequentially in response to each count output of the counter 323, and the number of steps is 27, and the count output is 0.
One cycle of control is completed from count output 26 (this is called S0) to count output 26 (this is called S26), and data for one channel of A/D 40 is taken into register 321.

First, when one cycle of control starts, the signal INC
The channel selection counter 325 is incremented by this, and the output data of the counter 325 is sequentially (0, 0) every cycle.
→(0,1)→(1,0)→(1,1)→(0,
0).

The output data of this counter 325 is written in parallel to the first two bit positions of the shift register 320, and then read out as serial data ADSI and supplied to the A/D 40.

In parallel, the output data of the counter 325 is also supplied to the register 321 via a decoder (not shown), and 8 bits of the corresponding channel of the register 321 are selected.

Next, the A/D 40 selects the corresponding analog input channel according to the channel selection data inputted as serial data ADSI, converts the analog data into digital data, and then outputs it to the shift register 320 as 8-bit serial data ADSO. is supplied to the serial input of the shift register 320 and stored in the shift register 320.

Thereafter, the 8-bit digitally converted data AD stored in this shift register 320
are read out in parallel at a predetermined timing and transferred to 8 bits of a predetermined channel of the register 321, which is preselected by the output data of the counter 325, completing one cycle of control operation.

In this way, for example, if the output data of the counter 325 is (0, 0), the A/D 40
After the analog data on channel 0 of is digitized and stored in the 8 bits of channel 0 of register 321, counter 323 is reset to S0 and proceeds to the next cycle of operation, and counter 325 is incremented to store its output data. becomes (0, 1), and the analog data of channel 1 is now digitized and stored in the 8 bits of channel 1 of register 321.

Therefore, according to this CIM, the data acquisition operation from the A/D 40 by the A/D control circuit 106 is performed timing-wise independently of the data transmission processing by the sequence counter 303 and the sequence decoder 304, and The data of each channel is refreshed once every 4 cycles of AD control operation, and the register 321 stores the analog data input to the 4 channels of the A/D 40 as 8-bit digital data for each channel. It will always be available as data.

Now, suppose that the received signal RXD is input from the transmission path and the address data attached to it is for this CIM. Note that the address data at this time is "E" or "F", as already explained.

Then, the format of the data written to the shift register 104 at the time when the input of the received frame is finished (S48 in FIG. 8) is the AD mode shown in FIG.
4 Q ₈ bits and Q ₉ bits consist of 2 bits.
AD channel data is stored. Therefore, this AD channel data is sent as a signal in S48.
It is read when WRITESTB occurs, which selects one of the four channels of gate 322.

As a result, in S73 (Fig. 8), the signal PS and
When SHIFT occurs, 4 of register 321
Of the two channels, the shift register 104
The channel selected by the two bits Q ₈ and Q ₉
Only AD data is read and written into the 8-bit portion of shift register 104 from _Q0 bit to _Q7 bit.

This is then included in the transmission signal TXD in the transmission state after S74 and transmitted to the CCU.

By the way, in this CIM, as mentioned above, the reception processing of the reception signal RXD and the subsequent transmission signal
Register 3 is always used regardless of TXD transmission processing.
AD data is prepared in 21.

Therefore, in this system, no matter what timing the received signal RXD destined for itself appears, the transmission signal TXD using AD data can be immediately transmitted, and the transmission processing is not affected by the operation of the A/D 40. There is no risk that the transmission speed will decrease due to the time required for the A/D conversion operation.

In addition, in this system, when converting the CIM into an LSI, the A/D 40 is attached externally, in order to reduce costs when making the CIM more general-purpose. In other words, as explained in Figure 2, this system uses one type of CIM by setting the mode.
As LCU30-31, as LCU32,
Alternatively, it can also be used as CIM 33 of CCU 10. However, in this case, if the A/D is built in, it will be useless when used as CIM30, 31, 33, and moreover, if it is generally applied to an automobile's integrated wiring system, it will be used as CIM32. the number is different
Since the number is smaller than that used for CIMs 30, 31, and 33, there is not much merit in having A/Ds built into all of the CIMs. Therefore,
The A/D is external.

However, as this A/D is externally connected, four connection terminals are required for the external A/D 40, as is clear from Figure 4, which reduces the number of terminal pins when converted to an LSI. There is a risk that this will lead to an increase.

Therefore, in this system, when the CIM is set to AD mode, the I/O buffer 105
Four of the fourteen ports can be switched as connection terminals for the A/D 40. That is, in this system, the I/O buffer 105
There are 14 ports, and as is clear from Figure 5, when CUM is set to DIO mode, all of them may be used as input/output ports, but when it is in AD mode, there are at most 10 ports.
Only ports are used, and 4 ports are left unused for input/output of DIO data. Therefore, I switched these remaining 4 ports to AD mode,
If used as a terminal pin for A/D40,
Even if the A/D is attached externally, there is no increase in the number of terminal pins, which increases versatility when integrated into LSI and reduces costs.

By the way, in the above system, a large number of
A CCU is provided to control data transmission between LCUs, and the microcontroller included in this CCU appropriately controls the entire system. For this reason, the CIM used in the CCU and each LCU is
When set to DIO mode, transmission of data TXD for each frame is started under control from the microcomputer, while when set to DIO mode on the LCU side, data TXD sent from the CCU side is received. It is input as data RXD, and when it is completely received, it becomes the own transmission data.
TXD transmission is now starting.

Therefore, in a transmission system using this CIM, a CCU equipped with a microcomputer etc. is essential in order to obtain the necessary data transmission function, and a transmission system cannot be configured using CIM alone. In other words, as shown in Figure 9, two CIM
CIM and MPU
mode and set the CIM to DIO mode, data transmission from none of the CIMs will start in this state, so the data transmission function will not work. This is the same whether both CIMs are set to MPU mode or DIO mode.

However, even with the configuration shown in Figure 9, if data is sent from any CIM using some means, the data transmission operation will start and the data transmission will continue alternately. You can make it happen.

However, even if transmission is started in this way, it is inevitable that data transmission errors will occur due to noise etc. in such a data transmission system, and as a result, once a transmission error occurs, the data will be lost at that point. The transmission operation will stop, and therefore stable data transmission operation cannot be expected.

On the other hand, wiring systems in automobiles are not limited to relatively large-scale data transmission systems that include many LCUs, but also relatively small-scale data transmission systems in which multiplex transmission between two LCUs is sufficient. Extensive data transmission systems may also be required.
An example of this is a wiring system between a switch panel on the side of a steering wheel column and a controlled device such as a headlamp or horn. Therefore, for such a system, it is desirable to use the small-scale data transmission system shown in FIG. 9, if possible.

However, even for such a small-scale data transmission system, if it is configured using the above-mentioned CIM, one CIM is equipped with a control device such as a microcomputer, and this CIM is given the function of a CCU. Or, it is necessary to provide a separate CCU for the two LCUs.
The drawback was that the system was relatively expensive compared to the overall scale.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the conventional CIM, and to immediately and stably perform multiplex data transmission simply by connecting two CIMs to each other via a transmission path and creating a one-to-one transmission system of LCUs. The purpose of the present invention is to provide an improved CIM that can reduce the cost of small-scale data transmission systems and is useful for concentrating wiring in automobiles.

[Summary of the invention]

To achieve this objective, the present invention provides CIM with:
Two operating modes, active mode and passive mode, are provided, and these can be switched by address input. Depending on whether the operating mode is active mode or passive mode, the input/output direction of the data port is reversed. The feature is that the number of output ports is the same as the number of input ports even when in passive mode.

[Embodiments of the invention]

Embodiments of a communication processing circuit (CIM) according to the present invention will be described below with reference to the drawings.

FIG. 10 shows an embodiment of the present invention.
The difference from CIM is that an automatic transmission circuit 330 is provided, and the rest is the same as seen from these figures. Note that the comparator 307 of the address comparison circuit 103 and the shift register 1
The configuration of the connecting portion with 04 is the same as that in FIG. 4, but is depicted in more detail in FIG. 10.

Now, as already explained, the CIM in Figure 4 is
Depending on the address setting, DIO mode, AD mode,
It is possible to operate by switching to three types of MPU modes.

On the other hand, in the embodiment of the present invention shown in FIG. 10, three types of modes can be set by address as in the conventional CIM.
Among the seed modes, other modes can be taken, and these other modes include two modes: an active mode and a passive mode.
In order to enable setting of this other mode, in this embodiment of the present invention, as shown in FIG. 11, two mode select input terminal pins MS ₀ are provided in addition to the four address input terminal pins. , MS ₁ are provided, and a predetermined mode can be set by a matrix of address inputs and mode select inputs.

Now, in order to configure a one-to-one transmission system as shown in Fig. 9 using CIMs according to the present invention, one CIM, for example, the CIM, must be placed in active mode, and the other CIM (CIM in this case) must be placed in passive mode. Set to . In addition, in this example,
To set the CIM to active mode, set the address to one from "1" to "D" (at this time, it is in DIO mode as shown in Figure 7), and then select the mode. Input MS ₁ = 1, MS ₀ = 0 or 1. To set the passive mode, similarly set the address to one from "1" to "D" and press the mode select button. Input MS ₁ =
I'm used to setting it to 0.

By the way, also in the embodiment shown in FIG.
The function of the address in the data transmission operation is the same as that of the CIM shown in FIG. On the other hand, in a one-to-one transmission system as shown in Figure 9, CIM
Data is exchanged between the CIM and the CIM.
Therefore, in order to enable data transmission at this time, the system must be configured by setting both CIM and CIM to the same address (limited to addresses 1 to D).

For this reason, in the active mode, it is necessary to invert the input port and output port of the I/O buffer for the same address, and such a configuration is used, but this point will be described later.

Next, the control circuit 10 including the automatic transmission circuit 330
An example of No. 1 is shown in FIG.

The automatic transmission circuit 330 according to this embodiment is composed of a gate circuit, an inverter, and a flip-flop, so that when the CIM is set to active mode, the sequence counter 303
When the count output reaches S254, it generates a signal LOAD49 at a predetermined timing and loads S49 into the sequence counter 303, and its operation is as shown in FIG. In addition, the signal STB3 in this FIG.
is a signal that has meaning when this CIM is set to MPU mode, and is not particularly relevant in active mode.

In this way, by using a CIM according to an embodiment of the present invention that can be set to active mode and passive mode in DIO mode, a one-to-one LCU transmission system as shown in FIG. 9 is constructed, as shown in FIG. 14. It becomes like this. Here, CIM34 is in DIO mode and CIM set in active mode,
CIM 35 each represents a CIM set in DIO mode and passive mode. Therefore,
The CIM 34 operates as a CIM in the DIO mode described in FIG. 4, etc., except that the automatic transmission circuit 330 shown in FIGS. 10 and 12 is activated. Therefore, DIO explained in Figure 4 etc.
It is designed to behave exactly the same as CIM in mode.

Next, according to the embodiment of the present invention shown in FIG.
1 constructed using CIM as shown in Figure 14.
The operation of the one-to-one transmission system will be explained. In addition, as mentioned above, CIM34 in FIG.
35, the basic operation is in the DIO mode (particularly, the CIM 35 is exactly the same as the DIO mode), so the following explanation will be made using FIG. 8.

First, when the transmission system is powered on by operating the engine key of a car, initialization is performed, and the sequence counter 303
The output of is set to S0. Subsequently, this counter 303 is incremented by the count of the clock _φM . In this way, the counter 303 starts incrementing and when its count output reaches S25, both the CIMs 34 and 35 go into an idle state, and after that, they are in a state where they are just waiting for the reception signal to be input. I end up.

By the way, in this system, as is clear from FIG. 14, only two CIMs 34 and 35 are coupled to the signal transmission path 20, and therefore,
Once all of these enter the idle state, no matter how long the data transmission operation is started, as explained in FIG. 9.

However, in this Fig. 14, CIM34,
35 is according to an embodiment of the present invention, whereby CIM 35 is set to active mode.

On the other hand, as explained in connection with FIG. 10, the basic operation of the CIM according to the present invention is the same as that of the CIM shown in FIG. continues counting the clock _φM .

Therefore, in the system shown in Figure 14, when CIMs 34 and 35 enter the idle state after initialization, the CIMs in passive mode
35 remains in the idle state, but since the CIM 34 is set to active mode, the automatic transmission circuit 330 is activated, and as a result, after the count output of the sequential counter 303 reaches S254, At a predetermined timing, a signal LODO49 is generated as shown in FIG. 13, and S49 is loaded into the output of the sequential counter 303.

As already explained, CIM34 according to the present invention,
35, the transmission operation is also controlled by the count data of the sequential counter 303, as explained in FIGS. 4 to 8. Therefore, when the output data of the sequence counter 303 of the CIM 34 is set to S49, the operation of the CIM 34 jumps from the idle state to the DUMMY state, as is clear from FIG.
Thereafter, by incrementing this sequential counter 303, 25-bit "0" is transmitted and the following S
The operation of transmitting data TXD from 74 will begin.

Thus, once the CIM 34 starts transmitting data, this data is received by the idle CIM 35, and as a result, the CIM
Data transmission between 34 and 35 is performed alternately in DIO mode, one frame at a time, and two CIM
Data transmission by the one-to-one transmission system between 34 and 35 begins.

Therefore, the state transition diagram of the CIM 34 and CIM 35 at this time is shown in FIG. 15.

On the other hand, if the data transmission operation between CIM34 and 35 is started in this way, and a transmission error occurs while data transmission is being carried out using the regular half-duplex method, then Both become idle and data transmission operations are stopped again.

However, at this time as well, since the CIM34 is in active mode, the sequence counter 3
When the count output of 03 reaches S254, S49 is loaded into the sequence counter 303 again, and data transmission is automatically started.

Therefore, according to the CIM according to the embodiment of the present invention, data can be transmitted stably at all times by simply selecting the active mode and passive mode as the operating mode and configuring a one-to-one transmission system as shown in FIG. This allows a small-scale data transmission system to be constructed at low cost.

Here, mode selection and switching of input/output ports of the I/O buffer 105 in one embodiment of the present invention will be explained.

As already explained, in the embodiment of the present invention shown in FIG. 10, active mode and passive mode can be selected in DIO mode, and automatic transmission circuit 330 is activated in active mode. However, the data transmission operation in DIO mode and other configurations are shown in Figure 4.
This is the same as CIM, and therefore, in the DIO mode, the directionality of the ports of the I/O buffer 105 is determined by the address, and the address directly becomes the number of output ports. For example, the 4-bit address “1” to “D” corresponds to the DIO mode, but if the address is set to “1”, the I/O
1 of the 14-bit ports of O buffer 105
Bits are output ports and 13 bits are input ports. At address "D", 13 bits are output ports and 1 bit is an input port.

On the other hand, as already explained, in a one-to-one transmission system as shown in Figure 14, both CIM3
If addresses 4 and 35 do not match,
Data transmission is not possible.

Therefore, in the system of FIG. 14, data transmitted from one CIM, for example CIM 34, is always received only by CIM 35, and the other
Since data sent by CIM35 is received only by CIM34, both CIM34 and CIM35
If the number of input ports and the number of output ports of the I/O buffer 105 are made the same, data transmission will be wasted and the number of bits that can be transmitted cannot be used effectively. In other words, due to the nature of data transmission, the data at the input port of one CIM in such a one-to-one transmission system is
Since data transmission must be received by an output port in a CIM, the number of input ports in one CIM is equal to the number of output ports in the other CIM, and vice versa. Most preferably, the number of ports is equal to the number of input ports on the other CIM.

Therefore, in this embodiment, I/O by address is
In the passive mode, the input/output ports of the O buffer 105 are switched in the same way as the CIM shown in Figure 4.
On the other hand, when the active mode is set, the number of addresses is made to correspond to the number of input ports, contrary to the passive mode. For example, if CIM34 and 35 in Figure 14 are set to address "1", CIM35
Of the 14 ports of the I/O buffer 105, 1 is an output port and 13 are input ports, whereas the CIM 34 in active mode
With this, there are 13 output ports and 1 input port, making it possible to fully utilize the data transfer function in one-to-one transmission.

As already explained, when the CIM of the present invention is set to the active mode, after the power is turned on or data reception is completed, the sequence counter 303 advances to S254 and then starts automatic transmission operation.

Therefore, if the data transmission rate by the clock φ _M is 250 Kbit/Sec, automatic transmission operation will start with a waiting time of approximately 1 mSec, but this time is determined by the maximum number of bits of the sequence counter 303 and the clock frequency. Needless to say, it can be set arbitrarily.

Further, in the embodiment shown in FIG. 10, since the sequence counter 303 is used to set the time until automatic transmission starts, the addition of the configuration required for operation in the active mode is small and costs can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, the CCU
Even if a one-to-one transmission system is configured with two LCUs that do not include It is possible to easily provide a communication processing circuit that is effective in reducing the cost of systems and the like.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing an example of an in-vehicle integrated wiring system, Fig. 2 is a block diagram showing an example of a data transmission system, Fig. 3 is a block diagram showing an example of each terminal processing device, and Fig. 4 is a block diagram showing an example of a data transmission system. 3 is a more detailed block diagram, FIG. 5 is an explanatory diagram showing an example of data content, FIG. 6 is an explanatory diagram showing an example of a transmission waveform, FIG. 7 is an explanatory diagram showing an example of mode selection, FIG. 8 is a timing chart for explaining the operation in DIO mode, FIG. 9 is a conceptual diagram of a small-scale data transmission system, FIG. 10 is a block diagram showing an embodiment of a communication processing circuit according to the present invention, and FIG. 12 is a block diagram showing an embodiment of the automatic transmission circuit, FIG. 13 is a timing chart for explaining its operation, and FIG. 14 is an illustration of a communication processing circuit according to the present invention. FIG. 15 is a block diagram showing one embodiment of the one-to-one transmission system, and is an explanatory diagram of its operation. 10...Central processing unit, 20...Signal transmission line,
30-32... terminal processing device, 33... communication control device, 40... A/D (analog-digital converter), 51-58... external load, 101... control circuit, 102... synchronous circuit, 103... Address comparison circuit, 104... Shift register, 105
... I/O buffer, 106 ... A/D control circuit, 107 ... Clock generator, 301 ... Synchronization circuit, 302 ... Counter, 303 ... Sequence counter, 304 ... Sequence decoder, 3
05...Abnormality detector, 306...Address decoder, 307...Comparator, 308...Error detection circuit, 310...Composite gate, 311...Exclusive OR gate, 312...And gate, 320...Shift register, 321...Register, 322...Gate, 323...Counter, 324...A/D control signal generation circuit, 32
5...Counter, 330...Automatic transmission circuit.

Claims (1)

[Scope of Claims] 1. A plurality of data ports that can be switched to either an input port for data acquisition or an output port for data transmission, and a call using input data in a predetermined format from a paired partner station. In response, a data reception operation is performed on an output port among the data ports, and subsequently, an operation of transmitting data taken in from an input port among the data ports to the other station is started. In the communication processing circuit, means for switching the operation mode of the communication processing circuit to either active mode or passive mode, and the number of output ports in the active mode and the number of output ports in the passive mode depending on the switching between the active mode and the passive mode. and means for switching the input/output direction of each of the plurality of data ports so that the number of input ports is the same, the active mode becomes an operation mode in which transmission is automatically started at a predetermined period, and the A communication processing circuit characterized in that the passive mode is configured to be an operation mode in which the passive mode is in a waiting state. 2. A plurality of data ports that can be switched to either an input port for data import or an output port for data transmission, and the data port A communication processing circuit configured to perform a data reception operation to an output port in a communication processing circuit, and then start a transmission operation of data taken in from an input port among the data ports to a partner station. , a means for switching the operation mode of the communication processing circuit to either active mode or passive mode, and a means for switching the operation mode of the communication processing circuit to either active mode or passive mode, and determining the number of output ports in active mode and the input port in passive mode according to the switching between active mode and passive mode. means for switching the input/output direction of each of the plurality of data ports so that the number of data ports is the same, the active mode becomes an operation mode in which transmission is automatically started at a predetermined period, and the passive mode becomes an operation mode in which transmission is automatically started at a predetermined period. Using two communication processing circuits configured to be in an operation mode of waiting in the receiving state,
1. A one-to-one transmission system, characterized in that one is set to the active mode and the other is set to the passive mode, and then connected to each other via a transmission system, and data is transmitted in the same direction.