JP2502491B2 - Communication processing circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a communication processing circuit used in a multiplex data transmission system, and more particularly to a communication processing circuit used in an automobile integrated wiring system.

[Background of the Invention]

For example, automobiles are equipped with various electrical components such as various lamps and motors, as well as various electrical devices such as various sensors and actuators for controlling automobiles, and the number of such electrical devices is increasing as the automobiles become more electronic. It is connected.

For this reason, as in the conventional case, wiring is performed independently for each of a large number of these electric devices, which leads to extremely complicated and large-scale wiring, which reduces cost, weight, and space. It causes a big problem such as increase or mutual interference.

Therefore, as one of the methods for solving such a problem, it has been proposed to simplify the wiring by a multiplex transmission method capable of transmitting a large number of signals with a small number of wirings. There is one disclosed in Japanese Patent No. 47752.

FIG. 1 shows an example of an integrated wiring system in a vehicle by such a multiplex transmission system.

The system of FIG. 1 uses an optical fiber cable OF as a signal transmission line, and has a central control unit CCU (hereinafter, simply referred to as CCU. This is an abbreviation for Central Control Unit) and a plurality of terminal processing units LCU (hereinafter, simply referred to as “CCU”). It is called LCU. Note that this is an abbreviation for Local Control Unit) and is commonly coupled with an optical signal channel between them, and an optical branch connector OC is provided at the branch point of the optical fiber cable OF.

The CCU is installed in an appropriate place such as near the dash board of a car and controls the entire system.

LCUs are arranged in a predetermined number in the vicinity of electric devices such as various operation switches SW, indicators such as meters M, lamps L, and sensors S installed in the automobile in a distributed manner.

A photoelectric conversion module O / E that bidirectionally converts an optical signal and an electric signal is provided in a portion where the CCU and each LCU are connected to the optical fiber cable OF.

The CCU has a microcomputer and has a data communication function by serial data, and in response to this, each LCU is provided with a communication processing circuit CIM (hereinafter simply referred to as CIM. This is an abbreviation of Communication Interface Adaptor), The CCU selects one of the LCUs in sequence, exchanges data with that LCU, and repeats this to make 1
Multiplex transmission is possible via the channel's optical fiber cable OF, and the complicated and large-scale in-vehicle wiring can be simplified.

FIG. 2 is a block diagram for explaining an example of such a transmission system in more detail. 10 is a central processing unit (corresponding to the CCU in FIG. 1), 20 is a signal transmission line (the optical fiber in FIG. 1). Cable OF), 30 to 32 are terminal processing units (corresponding to LCU in FIG. 1), 40 is A / D, and 51 to 58 are external loads. In addition, in this example, a case where an electric signal transmission line is used as the signal transmission line 20 is shown.Therefore, the central processing unit 10 and the terminal processing units 30 to 32 do not need a photoelectric conversion module, and therefore, The contents of the terminal processing devices 30 to 32 are substantially only CIM.

A central processing unit 10 including a computer (microcomputer) is connected to each of the terminal processing units 30 to 32 via a transmission line 20, and data for external loads 51 to 58 made of various electric devices such as sensors, lamps, actuators and motors. Is transmitted and data is taken in from them by a multiplex transmission system. At this time, external loads 57, 58 such as sensors that output analog data are output to the terminal output device via the A / D 40.
It is connected to 32 and can perform transmission operation by digital data.

The signal transmission path 20 may be bidirectional, and not limited to an electric signal transmission section, an arbitrary optical signal transmission system such as an optical fiber transmission system may be used. The communication system based on this is a so-called half duplex system. In response to a call from the central processing unit 10 to one of the plurality of terminal processing units 30 to 32, data is transferred between one of the terminal processing units and the central processing unit 10 via the transmission line 20. Are being held alternately.

Due to the multiplex transmission by such a half-duplex method, the data transmitted from the central processing unit 10 is provided with an address indicating its destination, and the address given to the data received from the transmission path 20 is its own. Only one of the terminal processing devices that recognizes the address responds.

In this way, only one of the terminal processing devices that understands the address according to the data sent with the address from the central processing unit 10 and judges that it is its own responds to it. By transmitting its own data to the central processing unit 10, the above-mentioned data transmission operation by the half-duplex method can be obtained.

Further, in this system, the central processing unit 10 is constituted by a microcomputer and a CIM33 having a data communication function by serial data, and the data transmission operation by the half-duplex system described above is performed through this CIM33. As a result, a general-purpose micro computer without a data transmission function can be used.

By the way, as is clear from the above description, for such a transmission system, CIMs having different functions are used.
Need. That is, the CIM 33 used for the central processing unit 10
And the CIM used for each terminal processing unit 30 to 32, of course, have different functions, and even for the terminal processing unit, the CIM of LCU30, 31 and the CIM of LCU32 have the interface function for A / D40. It has different functions, such as those with and without, and thus requires a CIM with different functions for each.

Therefore, in the conventional transmission system, due to the large number of types of CIMs, there is a significant cost increase in the specialization of these CIMs and in the LSI (large-scale integrated circuit), and it is difficult to reduce the system cost. I got it.

[Object of the Invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to configure the transmission system as described above with only one type of CIM, to make the CIM dedicated and to be LSI, and to reduce the cost of the transmission system. To provide useful CIM.

[Outline of Invention]

In order to achieve this object, the present invention is characterized in that it has a plurality of different functions, and the CIM is configured so that only the necessary functions can be selected by an external input.

Example of Invention

Hereinafter, the communication processing circuit according to the present invention will be described in detail with reference to the illustrated embodiment.

FIG. 3 is a schematic functional block diagram showing a basic configuration in one embodiment of the present invention. A start / stop system is provided by a control circuit 101 for sequentially controlling the entire operation and a reception signal RXD input from the transmission line 20. A synchronizing circuit 102 for synchronizing the clock by means of, an address comparing circuit 103 for selecting an operation mode by means of address data ADDR ₀ to ₃ given in advance as externally provided 4-bit data, and an address comparison of input data, and input data. Shift register 104 for serially taking in and sending out data, I / O buffer 105 for performing data input / output in parallel, and A for controlling external A / D 40 to enable analog data transmission. The / D control circuit 106 and a clock generator 107 for generating a clock necessary for the entire operation are shown in the state of being integrated into an LSI.

The address data input to the address comparison circuit 103 is 4 bits as described above, and by selecting the data ADDR to be given by these 4 bits, one of three operation modes of DIO mode, AD mode and MPU mode is selected. Switching of internal functions is performed so as to operate in one operation mode.

First, the DIO mode is an operation mode that gives a function required when this CIM is used as the terminal processing devices 30 to 31 described in FIG. 2. For this purpose, the address data ADDR is set to "1". You can set it to any address from "or" D ".

Next, the AD mode means the terminal processing device 32 in FIG.
This is an operation mode in which a required function can be given when used as the CIM. For this purpose, the address data ADDR may be set to either "E" or "F".

The MPU mode is an operation mode for giving a necessary function when used as the CIM 33 in FIG. 2, and at this time, the address data ADDA is set to "0".

The relationship between the address setting and the operation mode described above is shown in FIG.

Therefore, according to this embodiment, the transmission system as shown in FIG. 2 can be configured with only one type of CIM, and the CIM can be generalized. It will be possible to obtain the full advantage of LSI.

Next, the operation of the embodiment of the present invention in each of these operation modes will be sequentially described.

When the CIM according to the embodiment of the present invention shown in FIG. 3 is set to any of the addresses "1" to "D", the function block becomes the state shown in FIG. The input reception signal RXD is supplied to the synchronizing circuit 102, which synchronizes the clock from the clock generator 107 and controls the control circuit 101.
A clock that is start-stop synchronized with the clock component of the received signal RXD is given to the control circuit 101, which causes the control circuit 101 to generate a control signal and serially read the data portion of the received signal into the shift register 104.

On the other hand, the address comparison circuit 103 is given an address previously assigned to the terminal processing device from the addresses "1" to "D", and this address and the predetermined bit position of the shift register 104 are read. The address comparison circuit 103 compares the stored data with each other, and the data in the shift register 104 is transferred to the I / O buffer 105 and provided to an external device only when they match each other.

Further, the control circuit 101 includes a counter that advances in a clock, generates a sequential control signal, and receives a reception signal RX.
After the data by D is given to the I / O buffer 105, the data is transferred from the I / O buffer 105 to the shift register 10 subsequently.
The data is taken into 4 differently, and the data to be transmitted from the external device to the central processing unit 10 is prepared as serial data in the shift register 104. Then, this data is serially read from the shift register 104 and sent to the transmission line 20 as a transmission signal TXD. At this time, the address attached to the reception signal RXD remains the same as the transmission signal TXD.
Since the central processing unit 10 matches the address sent by itself, the central processing unit 10
TXD is fetched, which completes the transfer of data for one cycle in half-duplex mode.

In this way, the central processing unit 10 sends data to the next terminal processing unit, and by repeating this, data is periodically transferred between each of the plurality of terminal processing units 30 to 32, and multiplex transmission is performed. It will be possible.

Next, FIG. 6 is a block diagram showing in more detail one embodiment of the CIM in the DIO mode shown in FIG. 5, in which the same or equivalent parts as in FIG. In FIG. 6, 301 is a synchronizing circuit for generating a clock that is start-stop synchronized with the received signal RXD, 302 is a counter for generating two-phase clocks φ _S and φ _M , 303 is a counter for sequential control, and 304 is a counter. A sequence decoder that produces various control signals from the output of 303, 305 is an abnormality detector, 306 is an address decoder for selecting the input / output switching of the I / O buffer 105, 307 is a 4-bit comparator for address comparison, and 308 is Error detection circuit, 310 is a composite gate consisting of two AND gates and one NOR gate, 311 is an exclusive OR gate for error detection, 312 is an AND gate for sending data, and 313 and 314 are tristates. Is Tsufua. The shift register 104 has 25 bits (24 bits
Bit + 1 bit, I / O buffer 105 is for 14 ports (14 bits).

First, when the DIO mode is selected, the A / D control circuit
106 does not operate, and the data contents of the shift register 104 at this time are as shown in FIG. 7, and 6 from No. 0 to No. 5
Bits are not used, 14 bits from No. 6 to No. 19 are I
Allocated to the data DIO of the / O buffer 105. And No.2
Four bits from 0 to No. 23 are assigned to the address data ADDR, and No. 24 is assigned to the start bit.
The number of bits assigned to the DIO data is 14 because the I / O buffer 105 is 14 bits. Also for this reason, according to this embodiment
In CIM, the maximum number of external loads that can be connected to the I / O buffer 105 is 14.

The data transmission method according to this embodiment is called start-stop synchronization, bidirectional, two-way reverse transmission, and digital data is transmitted by the NRZ (nonreturn to zero) method. It is as shown in FIG. That is, a frame that transmits data from the CIM on the CCU side to the CIM on the LCU side is a reception frame, and conversely from the LCU side to C
If the frame to be transmitted to the CU side is the transmission frame, both the reception frame and the transmission frame are 74 bits, and accordingly, one frame is 148 bits. The received frame and the transmitted frame both have the same frame structure. First, there is a 25-bit "0", and then a start bit consisting of a 1-bit "1" is provided for start-stop synchronization. After that, 24-bit reception data RXD or transmission data TXD is transmitted in the NRZ signal format, and further inverted data ▲ ▼ or ▲ ▼ of these data is transmitted. This inverted data ▲ ▼
Or, the reason why ▲ ▼ is transmitted is because of a transmission error check.

As described above, in this embodiment, since the multiplex transmission is performed by the half-duplex method, the data of the received frame is
Address data ADDR of the LCU to which the CCU makes an interrogation at that time is attached to the first 4 bits of the RXD as shown in FIG. 7, and the data of the transmission frame transmitted from the LCU in response to this. The first 4 bits of TXD are transmitted with the same address data ADDR attached. Note that the transmission frame is transmitted from the LCU side only to the LCU called on the CCU side, so even if no address is added to the transmission data TXD, that data is from any LCU on the CCU side. You can immediately determine if there is. Therefore, it is not always necessary to add an address to the data TXD of the transmission frame, and the first 4 bits of the data TXD may be data that does not match any address of the LCU, such as (0000).

Now, returning to FIG. 6, the CIM address will be described.

As described above, in this embodiment, the CIM on the LCU side is assigned with a different 4-bit address, and the half-duplex data is multiplexed based on this address. I'm running.

Then, you should give this address a four input 2 ^{0 ~} 2 input that serves is connected to a comparator 307 to be assigned to each of the CIM, on these input data
The address of the CIM concerned is specified by ADDR _{0 to} ADDR ₁ .
For example, to specify the address of the CIM as "10", the address data ADDR ₀ = 0, ADDR ₁ = 1 and ADDR ₂ =
0, ADDR ₃ = 1 and then, it suffices to input 2 ^{0-2 3} (1010) are input. In this embodiment, since the data "0" is represented by the ground potential and the data "1" is represented by the power supply voltage V _cc , the inputs 2 ⁰ , 2 are input to the address "10".
Ground ² and connect inputs 2 ¹ and 2 ³ to the power supply.

Incidentally, in this embodiment, the address input 2 ^{0 ~} 2 are also input to the address decoder 306, the direction of the 1 / O buffer 105 is summer to be controlled by the output. As a result, when the address is designated, which of the 14 terminals of the I / O buffer 105 will be the data output port is determined. Then, in this embodiment, the address directly corresponds to the number of output ports. Therefore, if the address is set to "10" now, the I / O buffer
Of the 14 terminals, 10 are output ports, and the remaining 4 are input ports.

Although omitted in FIG. 6, the output of the address decoder 306 is the sequence decoder 304 of the control circuit 101.
, So that the operation mode of this CIM can be switched as already described in FIG. That is, in this embodiment, the CIM having the address set to "0" is in the MPU mode, the CIM having the address set from "1" to "D" is in the DIO mode, and the addresses are "E", " The CIMs set to either F "are made to operate in AD mode respectively.

Next, the functions of the control circuit 101 and the synchronization circuit 102 will be described.

In this embodiment, as described above with reference to FIG. 8, the start-stop synchronization method is adopted. Therefore, when data transmission is carried out for both the reception frame and the transmission frame, 25 bits of "0 "Is inserted, and then" 1 "data is inserted as a 1-bit start bit (Fig. 8).

Therefore, the synchronization circuit 301 exists at the beginning of the received frame.
The rising edge of the start bit following the 5-bit “0” is detected and the internal clock bit is synchronized. Therefore, until the next reception frame appears, the operation is performed by the internal clock bit-synchronized with the timing at this time.

The counter 302 produces two-phase clocks φ _S and φ _M from the internal clock synchronized by the synchronizing circuit 302. As a result, the clocks φ _S and φ _M are the received data that is input after that.
It will be phase-synchronized with RXD.

The sequence counter 303 receives a signal indicating the start bit rising detection timing from the synchronizing circuit 302 and is set to a specific count value, for example, a count 0 state,
After that, it is counted by the clock φ _S or φ _M.
Therefore, the control procedure of the entire CIM can be determined by the count output, and by observing the count value, it is possible to know in which step the operation of the CIM is at an arbitrary timing.

Therefore, the count output of the counter 303 is supplied to the sequence decoder 304, and the control signals necessary for the operation of this CIM, for example, all control signals internally required such as RXMODO, TXMODE, READ, and SHIFT are generated by the sequence decoder 304. I am trying to let you. That is, this embodiment is based on the sequence control method using the clocks φ _S and φ _M. Therefore, if the output of the counter 303 is decoded, all necessary control can be performed.

Next, the operation of determining whether or not the transmitted data RXD has data for that CIM, that is, whether or not the interrogation by the transmission of the received frame from the CCU is for itself will be described.

As already described, to one input of the comparator 307, is given the address data from the input 2 ^{0 ~} 2, and the other input from the Q _20-bit shift register 104
Data up to Q ₂₃ bit is being given. Then, the comparator 307 outputs the coincidence signal MYADDR only when both input data coincide. Therefore, the received data RXD is input to the shift register 104,
The output signal MYADD of the comparator 307 at the timing which has address data attached to the head (see FIG. 7) is stored in the Q ₂₀ data portions from bit to Q ₂₃ bit RXD
If you check R and the signal MYADDR becomes "1" at that time, you can see that the data RXD is for yourself and the call from CCU is for yourself.

Therefore, the control signal COMPMODE is supplied to the error detection circuit 308, the signal MYADDR is taken in at the above-mentioned predetermined timing, and when it is "0", the output INITIAL is generated, which causes the sequence counter 303 to count 0. Then, the operation of the entire CIM is restored and the next data transmission is prepared for input. On the other hand, the signal MYADDR is "1"
The error detection circuit 308
Since no AL is generated, the CIM operation continues as it is according to the count value of the sequence counter 303 at that time.

 Next, the transmission error detection operation will be described.

In this embodiment, the data transmission by the inversion double transmission system has already been adopted as described with reference to FIG. 8, whereby the transmission error can be detected. Therefore, data is given to the exclusive OR gate 311 from the first Q ₀ bit and the last Q ₂₄ bit of the shift register 104, and the output of this gate 311 is the signal ▲.
▼ is then applied to the error detection circuit 308.

The sequence decoder 304 outputs the control signal RXMODE to open the lower gate of the composite gate 310 during the transmission period of the reception signal RXD following the start bit and ▲ ▼ (FIG. 8), and thereby the data from the transmission line 20 is transmitted. The serial signal SI
Is input to the shift register 104. At this time, since the composite gate 310 includes the NOR gate, the transmission line 20
The data supplied from the
Entered in 104.

Therefore, at the time when 24 bits of data following the start bit of the received frame (FIG. 8) are input to the shift register 104, the Q ₀ bit to the Q bit of the shift register 104 are changed.
Inverted data of received signal RXD for up to ₂₃ bits ▲
▼ will be written. Next, as is apparent from FIG. 8, when the 24-bit reception signal RXD is transmitted and then the 24-bit inversion signal ▲ ▼ is transmitted, it is inverted by the composite gate 310. Becomes data RXD and starts to be input to the shift register 104 as a serial signal SI. As a result, the shift register 104
At the timing when the leading bit of the inverted signal ▲ ▼ is inverted and input to Q ₀ , the inverted data of the leading bit of the received signal RXD that was written before that is the shift register 104.
2 second bit of data Q ₂₄ are transferred to the bit inverted signal RXD is the received signal RXD at the timing written in the Q ₀ of
The data of the second bit will be moved to the bit of Q ₂₄ , and eventually, at each bit timing when the inverted signal RXD is serially written to the shift register 104 one bit at a time, Q _{24 of the} shift register 104 will be changed. The data of the same bit of the received signal RXD and the inverted signal ▲ ▼ are always written in the bit and the Q ₀ bit in correspondence with each other.

By the way, as mentioned above, exclusive agate
The two inputs of 311 are Q ₀ bit and Q _{0 of the} shift register 104.
_24- bit data has been entered. Therefore, the received signal
If no error occurs during the transmission of RXD and the inverted signal ▲ ▼, the output of the exclusive OR gate 311 should always be “1” during the transmission of the inverted signal ▲ ▼. Because the received signal RXD and its inverted signal ▲
In each bit corresponding to ▼, "1" and "0" must be inverted, and as a result, the input of the gate 311 always shows a mismatch, which is not possible only when there is an error in transmission. Because it will be.

Therefore, the error detection circuit 308 outputs the signal ▲ ▼ during the 24-bit period during which the inverted signal ▲ ▼ is transmitted.
Signal, and when it reaches the “0” level, signal INITIA
If L is generated, an error detecting operation can be obtained. As a transmission error processing method in such a data transmission system, there is also known a method of detecting a transmission error and correcting it to obtain correct data. However, in this embodiment, the transmission error is When it is detected, the data reception operation of the frame is canceled at that time to prepare for the data reception of the next frame, which simplifies the configuration.

Next, the overall operation of data transmission in the DIO mode of the embodiment of FIG. 6 will be described with reference to the timing chart of FIG.

φ _M and φ _S are two-phase clocks output from the counter 302 and are generated based on the internal clock generated by the clock oscillator included in the synchronizing circuit 301.

On the other hand, ▲ ▼ is the signal supplied from the outside to this CIM, which is the same as the reset signal of the micro computer, etc., and is supplied to every CIM in the system in FIG. It is supplied from an external reset circuit when necessary, such as when the transmission system is initialized.

When the initialization is finished, the count value of the sequence counter 303 is set to 0, and the clock φ _M advances from there. No operation is performed until the count value reaches 25. When the count value reaches 25, the IDLE signal and ▲ ▼ signal are generated, the CIM enters the idle state, and sequential control by the count value of the sequence counter 303 is not performed. Stopped, Tri-State Buffer 31
3 is opened and ready for signal reception. At this time,
After the initialization, the signal is not ready to be received until the count value of the sequence counter 303 reaches 25 because of the start-stop synchronization by the synchronizing circuit 301. Since the received signal RXD is 24 bits, the minimum 25 bits is required. This is because it is necessary to give the “0” period.

When entering the idle state in this way, the sequence counter 30
Although 2 continues to step by counting the clocks φ _S and φ _M , the sequence decoder 304 remains in the state of generating the control steps IDLE and INITIAL, and is in a state of simply waiting for the reception signal to be input.

Therefore, this signal IDLE is the transmission signal, as will be described later.
This is a signal for putting the CIM in the idle state as shown in FIG. 9 during the period in which the "0" transmission sent in the DUMMY period before TX is received and the start-stop synchronization is established. Therefore, as shown in FIG. 8, 25-bit "0" is added to the beginning of each received frame and transmitted frame.

In this way, the idle state is entered, at which time t ₀
It is assumed that the received signal RXD is input at. Then, the start bit of 1 bit is added to the head of the signal RXD. Therefore, the synchronizing circuit 301 detects this start bit and synchronizes the bits of the internal clock. Therefore, thereafter, the synchronization between the data RXD, ▲ ▼ and the clocks φ _M and φ _S until the transmission operation for one frame is completed is maintained by the stability of the internal clock, and the start-stop synchronization function is obtained. It will be.

Sequence counter 30 when a start bit is detected
3 is set to the count output 0 (hereinafter, the output data of this counter 303 is marked with S, for example, represented by S ₀ in this case), whereby the sequence decoder 304 causes the control signal I
Stop DLE and generate control signal RXMODE. Further, in parallel with this, the shift pulse SHIFT is supplied to the shift register 104 in synchronization with the clock φ _M.

As a result, the received signal of 48 bits following the start bit
RXD and the inverted signal ▲ ▼ (FIG. 8) are written from the transmission line 20 through the composite gate 310 to the shift register 104 as serial data while shifting one bit at a time. At this time, the first 24-bit reception signal RXD is serially written in the shift register 104 as the data ▲ ▼ inverted by the composite gate 310.
Period of 24 bits following the start bit, i.e. at the time when the sequence counter 303 reaches to S24 from S1, the received signal bit from Q ₀ bit of the shift register 105 to Q ₂₃ RX
Data ▲ ▼ with D inverted will be written. Here, at the next rise of the clock φ _M of S25, the control signal ▲
▼ is output and the error detection circuit 308 functions. Then, in this state, the inversion signal continues.
Begins to be input, and as a result, this time the inverted signal ▲ ▼
Inverted data RXD is serially written from the Q ₀ bit of the shift register 105. This allows S1 to S24
The data ▲ ▼ written in the shift register 104 passes through the Q ₂₄ bit position of the shift register 104 from the leading bit and is sequentially overflowed by 1 bit until the sequence counter 303 changes from S25 to S48. go. On the other hand, in parallel with this, the data RXD by the inversion signal ▲ ▼ is serially written from the first bit through the Q ₀ bit position of the shift register 104,
During this time, the transmission error detection by the exclusive OR gate 311 and the error detection circuit 308 is performed as described above.

Accordance connexion, in Natsuta time the sequence counter 303 S48, from Q ₀ of the shift register 104 bits to Q ₂₃ bits is in a state where the same data RXD and the received signal RXD is written as writing. Therefore, the address is confirmed by checking the output signal MYADDR of the comparator 307 at the timing of S48, and whether or not the data RXD just received is addressed to itself, that is, from the CCU at this time. A determination is made as to whether the call is for itself. If a transmission error is detected during the period when the sequence counter 303 is between S25 and S48, or if an address mismatch is detected, the error detection circuit 308 generates a control signal INITIAL at the time of reaching S48. At this time, the sequence counter 303 is set to S ₀ , returns to the 25-bit state before idle, and all the reception operations for this reception frame are canceled to prepare for the input of the next signal.

Now, when the transmission error is not detected while the sequence counter 303 is from S25 to S48, and the address mismatch is not detected, that is, the error detection circuit 308 does not generate the INITIAL signal at the time of reaching S48. Sometimes
At the time when this S48 is reached, the sequence decoder 304 generates the control signal WRITESTB. As a result, at the time of S48, either the INITIAL signal or the WRITESTB signal is generated, the former occurs when neither transmission error nor address mismatch occurs, and either the transmission error or address mismatch occurs. Sometimes the latter will be output respectively.

Now, when the control signal WRITESTB is output at the time of S48, the data of the shift register 104 at that time is written in parallel to the I / O buffer 105, and as a result, the received data RXD brings it from the CCU. The output data of the I / O buffer 105 is supplied to the external loads 51 to 56. Incidentally, at this time, since it is of operating in DIO mode, up to 14 bits from Q ₆ bits as described in FIG. 7 to Q ₁₉ bits are possible transmitted as data RXD, and, what of them Bit is I / O buffer 1
As described above, the output port of 05 is determined by the address.

In this way, when the processing reaches S48, the processing of the received frame is completed, and the processing of the received frame starts from the next S49 (8th processing).
Figure).

First, no processing is performed from S49 to S72. This is for the start-stop synchronization of the CIM on the CCU side, and has the same purpose as the operation in the period set before IDLE in the processing of the received frame described above.

Upon entering S73, the sequence decoder 304 outputs the control signal PS, which causes the shift register 104 to perform a parallel data read operation and is applied to the input port of the I / O buffer 105 from any of the external loads 51 to 56. Enter data in parallel. The number of data bits read at this time is the remaining number of the 14-bit I / O buffer 105 ports minus the bit used as the output port in the processing of the received frame. For example, as described above, when the address of this CIM is set to 10, the number of output ports becomes 10, and at this time, the number of input ports becomes 4 bits.

Since one bit of shift clock SHIFT is required together with the signal PS to write the pannel data to the shift register 104, the signal SP is raised by the clock φ _S of S73 and then the shift pulse SH synchronized with the clock φ _S of S74.
IFT is supplied before the rise of control signal TXMODE.

At this time, as is apparent from FIG. 8, a start bit is added before the transmission data TXD, and the data T
An address must be added to the first 4 bits of XD. For this reason, although omitted in FIG. 6, a signal representing data "1" is supplied to the Q ₂₄ bit of the shift register 104 only during the period when the signal PS is generated, and a signal representing the data "1" is output from the Q ₂₀ bit to the Q ₂₃ bit.
The portion of the bit address data from the input 2 ^{0 ~} 2 are summer as supplied.

In this way, the data "0" transmission period for 25 bits required for start-stop synchronization is set by the DUMMY state from S49 to S73. Therefore, as shown in FIG. 9, this DUMMY is a 25-bit data “0” necessary for start-stop synchronization on the receiving side,
This is the period of transmission prior to (transmission). After that, when S74 is entered, the control signal TXMODE rises, which causes T
Enters the X (transmission) state. The generation of this signal TXMODE activates the AND gate above the composite gate 310 and further activates the AND gate 312. As a result, the Q ₂₄ bit data of the shift register 104, that is, the data “1” that is the start bit passes through the AND gate 312 and is transmitted to the transmission line
Sent to 0. Then, the contents of the shift register 104 are shifted by one bit to the subsequent stage by the shift clock SHIFT generated in synchronization with the subsequent clock φ _M after S75, and sent from the Q ₂₄ bit to the transmission line 20 through the AND gate 312, As a result, the transmission signal TXD including the start bit of the transmission frame (FIG. 8) is transmitted.

On the other hand, in parallel with the data read from such a shift register 104, the Q ₂₃ data read from the cells of the bit is through connexion inverting the composite gate 310 is supplied to the serial input of the shift register 104. As a result, S
75 after the transmission data TXD that has been written to the Q ₀ of the shift register 104 bits to Q ₂₃ bits is Shifutokurotsuku S
The shift register is sent out to the transmission line 20 bit by bit by HIFT and is inverted and is serial data SI as a shift register.
It will be written sequentially from the Q ₀ bit of 104.

Therefore, during the period when the control signal PS is being generated, when all the transmission data TXD written in the cells of the shift register 104 from the Q ₀ bit to the Q ₂₃ bit are read out, this Q ₀ bit is completed.
The inverted data ▲ ▼ is stored in the cells from bit ₂₃ to Q ₂₃ instead of the transmitted data TXD up to that point.

Therefore, after the completion of the reading of the transmission data TXD, the inversion data ▲ ▼ is subsequently read from the shift register 104, and the inversion data ▲ ▼ becomes the transmission data TXD as shown in FIG. Then, it is sent to the transmission line 20.

Thus when reaching the S122, since the inverted data all read complete from Q ₂₃ bits of the shift register 104 to the Q ₀ bit control signal TXMODE is falling, ending the be stopped transmission state supply of Shifutokurotsuku SHIFT. Then, the control signal INITIAL is generated by the next clock φ _M following S122, the sequence counter 303 is set to S0, and CIM is idle (ID
LE) Return to the previous signal reception preparation state.

Therefore, according to this embodiment, in order to reliably perform half-duplex multiplex communication by start-stop synchronization, bidirectional, and inversion double transmission, the DIO required by the LCU side. It is possible to obtain a CIM having a function of operating in a mode.

Next, the operation of the CIM in the AD mode according to this embodiment will be described.

As described above, there are external loads 57 and 58 (Fig. 2) that output analog signals such as various sensors as an electric device that should exchange data with the CCU via the CIM. 1 includes the A / D control circuit 106 and also has a function of controlling the external A / D 40. The CIM operation mode at this time is the AD mode.

And, as also previously described, and summer as the setting of the I connexion operation mode to the address data to be supplied to the input 2 ^{0 ~} 2 is performed in this embodiment, the address data corresponding to the AD mode, As shown in FIG. 4, they are "E" and "F".

Now, the CIM according to this embodiment has the address "E" or "F".
When set to, the functional block status becomes as shown in FIG. Then, the contents of the data stored in the shift register 104 when set in this way are as shown in FIG. 7, and 8 bits from No. 0 to No. 7 are external loads via the A / DA 40. For storing AD data fetched from 57, 58, etc., 2 bits of No. 8 and No. 9 are for storing AD channel data, which makes it possible to store No. 10 to No. 1 for DIO data.
It is 9 bits and 10 bits. Others are the same as in DIO mode. Further, the AD channel data at this time is data for designating a channel when the A / D of the multi-channel is used, and in this embodiment, since the A / D 40 of the 4 channel is used, 2 bits are used. Is assigned.

Next, FIG. 11 is a block diagram showing the embodiment of FIG. 10 in more detail. In FIG. 11, 320 is a shift register, 321, a register, 322 is a gate, and 323 is for A / D control. A counter, 324 is an A / D control signal generation circuit, and 325 is an A / D channel selection counter. In addition, the others are the sixth
This is the same as described in the case of the figure.

The shift register 320 is an 8-bit type, and has an external A / D
Digital data captured serially from 40 (external load
A / D converted analog data given from 57, 58, etc.) is stored to enable parallel reading, and
It functions to receive in parallel the 2-bit channel selection data given from the counter 325 for designating the channel of the A / D 40, read it serially, and supply it to the A / D 40.

The register 321 is 32 bits, and the A / D 40 is 8 bits and 4 channels.
Used as a channel register, it stores the data acquired from the A / D40 at 8 bits for each channel.

The gate 322 also has 32 bits (8 bits and 4 channels) corresponding to the register 321, and A read from the Q ₈ bits and Q ₉ bits cells of the shift register 104 for data transmission.
Controlled by the D channel data (Fig. 7), one of the channels in register 321 is selected and its 8 bit data is transferred from the shift register Q ₀ bit to the Q ₇ bit cell.
Functions to write as AD data (Fig. 7).

The counter 323 advances by counting the clock φ _M ,
It functions to sequentially and cyclically control the operation of the entire A / D control circuit 106.

The A / D control signal generation circuit 324 includes a decoder for decoding the output of the counter 323 and a logic circuit.
It functions to generate various control signals necessary for the overall operation.

Next, the operation of the entire A / D control circuit 106 will be described.

In this embodiment, the control is sequentially advanced corresponding to each count output of the counter 323, the number of steps is 27, and the count output is 0 (this is called S0) to the count output 26 (this is called S26). The control for one cycle is completed, and the data for one channel of the A / D 40 is taken into the register 321.

First, when the control for one cycle is started, the signal INC increments the counter 325 for channel selection, whereby the output data of the counter 325 is sequentially (0,0) → (0,1) → (every cycle. 1,0) → (1,1) →
It changes with (0,0).

The output data of the counter 325 is written in parallel at the first two bit positions of the shift register 320, then read as serial data ADSI and supplied to the A / D 40.

In parallel with this, the output data of the counter 325 is also supplied to the register 321 via a decoder (not shown) to select the corresponding 8 bits of the channel of the register 321.

Subsequently, the A / D 40 selects the analog input channel corresponding to the channel selection data input as the serial data ADSI, converts the analog data into digital data, and then outputs the 8-bit serial data AD.
It is supplied to the serial input of the shift register 320 as SO,
It is stored in this shift register 320.

After that, the 8-bit digitally converted data AD stored in the shift register 320 is read in parallel at a predetermined timing, and the predetermined channel of the register 321 selected in advance by the output data of the counter 325 is transferred. The operation is moved to 8 bits, and the control operation for one cycle is completed.

Thus, for example, the output data of the counter 325 is (0,0)
If the analog data of channel 0 of A / D40 is digitalized and stored in 8 bits of channel 0 of register 321, the counter 323 is reset to S0 and the operation of the next cycle proceeds. , Counter 32
5 is incremented and its output data becomes (0,1). This time, the analog data of the channel 1 is digitalized and stored in the 8 bits of the channel 1 of the register 321.

Therefore, according to this embodiment, the A / D control circuit 106
Sequence counter 303 is used to capture data from the A / D40.
The data of each channel of the register 321 is refreshed once every four cycles of AD control operation, and the data of each channel of the register 321 is refreshed, and the register 321 has four bits of A / D40. The analog data input to one channel is always prepared as 8-bit digital data for each channel.

So, now, the received signal RXD is input from the transmission line,
It is assumed that the address data attached to it is for this CIM. The address data at this time is "E" or "F", as already described.

Then, when the reception frame is completely input (9th
Since the format of the data written to the shift register 104 in (S48) of the figure is the AD mode of FIG. 7, the AD channel data consisting of 2 bits is included in the Q ₈ bit and the Q ₉ bit of this shift register 104. It is stored. Therefore, this AD channel data is read at the time when the signal WRITESTB is generated in S48, and thus one of the four channels of the gate E322 is selected.

As a result, S73 (FIG. 9) at a point of time when the signal PS and SHIFT is generated, among the four channels of the register 321, AD data channel selected by the two bits of Q _8, Q ₉ of the shift register 104 only it is read, it is written to the 8 bits portion from Q ₀ bit of the shift register 104 to Q ₇ bits.

Then, this is included in the transmission signal TXD in the transmission state after S74 and transmitted to the CCU.

By the way, in this embodiment, as described above, the received signal
AD data is always prepared in the register 321 regardless of the RXD reception process and the subsequent transmission signal TXD transmission process.

Therefore, in this embodiment, even if the reception signal RXD addressed to itself appears at any timing, the transmission signal TXD can be immediately transmitted by the AD data, and the transmission processing is affected by the operation of the A / D 40. There is no fear that the transmission speed will decrease due to the time required for the A / D conversion operation.

In this embodiment, the A / D4 is used when converting the CIM into an LSI.
With 0 as an external component, the cost is reduced when the CIM is generalized. That is, as described in FIG. 2, in this embodiment, one type of CIM is set to L depending on the mode setting.
CIM for CU30-31, CIM for LCU32, or C
It can also be used as CIM33 of CU10. Then, at this time, if the A / D is built in, CIM30,31,33
It is useless when used as a CIM3
Since the number used as 2 is smaller than the number used as other CIMs 30, 31, 33, there is not much merit by incorporating A / D in all CIMs. Therefore, A / D
Is externally attached.

However, because this A / D is externally attached, as is apparent from FIG. 11, four connection terminals are required for the external A / D40. May increase.

Therefore, in one embodiment of the present invention, when the CIM is set to the AD mode, four of the 14 ports of the I / O buffer 105 can be switched as connection terminals for the A / D 40. That is, in the embodiment of the present invention, the I / O buffer 105 has 14 ports, which are all used as input / output ports when the CIM is set to the DIO mode, as is clear from FIG. However, in AD mode, only 10 ports are used at the maximum, and the 4 ports No. 11 to No. 14 shown in FIG. 11 are not used for input / output of DIO data and are left. Therefore, by switching the remaining 4 ports in AD mode and using them as terminal pins for the A / D 40, the number of terminal pins does not increase even if the A / D is externally attached, increasing versatility at the time of LSI implementation and reducing the cost. Down is possible.

Next, the operation of the CIM in the MPU mode according to this embodiment will be described.

As is clear from FIG. 4, the CIM according to this embodiment is
To switch to PU mode, set the address ADDR _{0 to} ADD.
The address setting by R ₃ "0", i.e. keep all the input 2 ^{0 ~} 2 ground potential, may be Shiteyare and (0000).

This MPU mode is a mode for giving necessary functions when used as the CIM33 shown in Fig. 2. Unlike the case used in the DIO mode and AD mode, the CCU10
When data is given from the microcomputer of
It transmits data to any of CIMs 30 to 31 of U, and when it receives the data returned in response to it, it performs the transmission interface operation of transferring the data to the microcomputer.

By the way, as described above with reference to FIG. 8, since the explanation has been mainly from the viewpoint of the CIM on the LCU side, a frame for transmitting data from the CIM on the CCU side to the CIM on the LCU side is a received frame, On the contrary, the frame transmitted from the LCU side to the CCU side has been used as the transmission frame, but after that, each
A frame for transmitting data as seen from the CIM will be described as a transmission frame, and a frame for accepting data by itself will be described as a reception frame. Therefore, thereafter, a transmission frame in a certain CIM, for example CIM33, becomes a reception frame in another CIM, for example, CIM30, while a transmission frame in CIM30 becomes a reception frame in CIM33.

Now, FIG. 12 is a schematic block diagram of the function when the address “0” is set in the CIM according to the embodiment of the present invention and the CIM is controlled to operate in the CPU mode.
It shows the state of M33. In addition, as described above, in this embodiment, the CI having the same configuration is set by setting the address.
M can have the function in any of the three modes, that is, the CPU mode, the DIP mode, and the AD mode. Therefore, the state in FIG. 12 is the function block in the CPU mode. However, this does not mean that the configuration of the CIM according to this embodiment is different from that shown in FIG.

As is apparent from FIG. 12, the functions of the I / O buffer 105 (FIG. 3) and the A / D 40 are stopped in the CPU mode, and the I / O buffer 105 and the microcomputer are connected by a 14-bit data bus. Needless to say, the terminal pins at this time are used in common with the input / output ports of the I / O buffer 105, and no increase or decrease in the number of terminal pins occurs.

Of the 14-bit (14) input / output, 8 bits are for data, and the remaining 6 bits are for control signals.

Now, in this CPU mode, the shift register 104
As shown in Fig.7, the data contents of 2 are from Q ₀ to Q _23.
All 4 bits are used as MPU data, and the microcomputer is adapted to access this shift register 104 via an 8 bit data bus.

On the other hand, the control circuit 101 receives the control signal from the microcomputer, the data from the microcomputer is stored in all the bits of Q _{0 to} Q ₂₃ of the shift register 104, and at the same time, the transmission operation starts, and this data is stored. Transmission of the transmission frame is started from time t _x as shown in FIG.

When the transmission frame is transmitted from the CIM33 in this way, one of the CIMs 30 to 32 on the LCU side responds accordingly, and the CIM subsequently transmits, so that the transmission time of one frame (148 bits) from the time t _x. When the time t _y
In the shift register 104, an interrogation was made from the CIM33.
The data transmitted from the CIM (one of CIMs 30 to 32) is stored and the processing ends.

Therefore, the control circuit 101 of the CIM 33 generates an interrupt request ▲ ▼ at this time t _y , and in response to this, the microcomputer reads the data of the shift register 104 and ends the data transmission for one cycle. Needless to say, the data transfer operation between the CIMs at this time is the same as that in the DIO mode described with reference to FIG.

Next, FIG. 14 is a functional block diagram showing one embodiment of the CIM 33, that is, the CIM when set in the MPU mode, and shows only the block corresponding to the function required in the MPU mode. Reference numerals 400 and 402 are 8-bit switches, 404 is an 8-bit data latch, and others are the same as those in the embodiment shown in FIG.

In this MPU mode, from the Q ₀ bit of shift register 104
Q ₂₃ until bits are connected to the data bus of the microcomputer through the input and output pins of the 8 bits, one another and summer to exchange data in, Therefore, the shift register 104 Q
Bits from _{0 to} Q ₂₃ are divided into three groups, Q _{0 to} Q ₇ (Reg 3), Q
It is treated as divided into _{8 to} Q ₁₅ (Reg 2) and Q _{16 to} Q ₂₃ (Reg 1), and is accessed sequentially in time division.

Therefore, for this reason, by using the 8-bit switches 400 and 402, the register select signal RS0,
Switch 400 control signals READ1 to 3 depending on the combination of RS1
Then, the control signals STB1 to 3 of the switch 402 are made, and the input / output terminal pins 7 to 14 are sequentially connected to Reg1, Reg2, and Reg3, and the access between the microcomputer and the shift register 104 is performed three times by 8 bits. It is designed to send and receive data in. In this case, when writing data from the microcomputer to the shift register 104, the data read time from the microcomputer and the shift register 10
In order to compensate for the difference with the data writing time for 4,
A latch 404 is provided, and data from the microcomputer is temporarily
It is designed to write after it is latched.

In this MPU mode, the address added to the beginning of the 24-bit data at the time of data reception is not collated in this CIM33. Accordance connexion, address applied to the input 2 ⁰ ~2 ³ (oooo) is used only for setting the CIM to Yotsute MPU mode to the address decoder 306, summer as comparator 307 in FIG. 6 does not operate ing.

Next, in this MPU mode, I / O terminal pin 1 of CIM33
6 to 6 serve as a transmission path of control signals to the microcomputer, whereby the microcomputer E supplies the clock E, the chip select signal ▲ ▼, the read / write signal RW, and the register select signal RS0, to the CIM control circuit 101. RS
1, while an interrupt request signal from this CIM
▼ is output to the microcomputer.

15 and 16 show an embodiment of a processing circuit for these signals, which is omitted in FIG. 14, but is included in a part of the control circuit 101. First, the clock E is shown in FIG. Is supplied to the circuit and is processed together with the internal clock CLOCK to generate a two-phase clock EH, EL. And these black EH,
Signals RW, ▲ ▼, RS0 and RS1 from the EL and the microcomputer are processed by the circuit shown in FIG. 16, and signals STB0 to 3 and READ0 to 1 are generated. Here, the signals STB0 to 3 and the signals READ0 to 1 are the same as those of the microcomputer and the shift register 10 as described above.
This is a signal used when data is sent and received between 4 and 4, where STB means strobe and MPU means CI.
This signal is "1" when M is set to MPU mode. Further, FIGS. 17 and 18 show signal processing timings by the circuit of FIG. 16, of which FIG. 17 shows the generation timing of the signals READ0 to READ3 and FIG. The respective generation timings of the signals STB0 to STB3 are shown. In these figures, which of the signals READ0 to READ3 and which of the signals STB0 to STB3 are generated is determined by the combination of the signals RS0 and RS1. This allows the shift register described above
The 104 groups Reg1, Reg2, Reg3 are selected.

By the way, the signals READ0 and STB0 among these signals READ0 to STB0 to STB0 to 3 are not used for the group selection of the shift register 104 described above, and the interrupt request signal ▲ described later.
Used to generate ▼. The interrupt request signal can be masked (invalidated), and a signal for this purpose is a signal MASKI described later.

Therefore, the selection state by the signals RS0 and RS1 is shown in FIG.

Next, FIG. 20 is an embodiment of an interrupt request signal ▲ ▼ generation circuit, which is also included in the control circuit 101 of FIG. 14, and this CIM 33 completes the data reception and completes the shift register 104.
Signal WR generated when the storage of received data is completed
One of the data lines D0 to D7 connected to the data bus of the microcomputer by the I / O terminal pins 7 to 14 and the circuit that generates the signal IRQ by the ITE STB (Fig. 9) and the signal READ0. One of them is, for example, a signal DATA from the data line D0 and a circuit for producing a signal MASK1 from the signal STB0, and its operation is shown in the timing charts of FIGS. 21 and 22. And among these figures, the signal DATA is ST
The operation when it is "0" at the generation timing of B0,
FIG. 19 shows the operation when the signal DATA is "1". In the circuit of FIG. 20, the flip-flop to which the signals DATA and STB0 are supplied is Reg0.
Say. Therefore, in the circuit of FIG. 20, when "1" is written in Reg0, the interrupt request signal ▲ ▼ is masked.

Next, the overall operation of data transmission when the embodiment of FIG. 14, that is, one embodiment of the CIM according to the present invention is set in the MPU mode, will be described with reference to the timing chart of FIG.

In the examples of the present invention, any of CIM30-33,
The operation is controlled by the count output of the sequence counter 303. Therefore, if the count output of the sequence counter 303 is set to a predetermined value, it is possible to shift the operation state to an arbitrary operation state. As explained in relation to figures etc., this is CIM
No matter what mode is set, there is no change.

By the way, as shown in FIG. 2, the CIM combined with the CIM 33 set in the MPU mode for data transmission as shown in FIG. 14 is the same as the CIMs 30 to 32 set in the DIO mode or the AD mode. I'm running. And this CIM is DI
When set to O mode or AD mode,
As explained in the figure, when data is received from another CIM, it then sends its own data,
The data transfer operation for one frame is performed, and so to speak, only a passive operation is performed.

On the other hand, when the MPU mode is set like the CIM33, the data from the microcomputer is the shift register.
When it is written in 104, it starts data transmission by itself, so to speak, requires an active operation.

Therefore, in this embodiment, in order to start this active data transmission, the signal STB3 of the signals STB1 to STB3 for selecting the group of the shift register 104 is used. This is because writing of transmission data to the shift register 104 by the microcomputer is performed in the order of Reg1, Reg2, and Reg3. Therefore, when the signal STB3 is generated, the writing of data to the shift register 104 from the microcomputer is just finished, This is because all the data to be transmitted this time has been stored in 104.

Therefore, returning to FIG. 23, it is now assumed that at some point, the microcomputer of the CCU 10 (FIG. 2) has prepared data to be transmitted to any of the LCUs.

Then, this microcomputer sends signals ▲ ▼, RW, RS0, RS1 via the input / output terminal pins 1-6 to the control circuit in the CIM33.
The signal is supplied to 101, and the signals STB0 to STB3 are generated as described with reference to FIGS. 15 to 19 (upper left end of FIG. 23), and 8-bit data is sequentially transferred from the data bus to the shift register 10.
Write to Reg1, Reg2, Reg3 of 4.

On the other hand, the control circuit 101 catches the generation of this signal STB3 and loads the sequence counter 303 with “49”. An embodiment of a circuit for setting the output data of the sequence counter 303 by this signal STB3 to "49" is shown in FIG. 24, and a timing chart showing the operation of this circuit is shown in FIG.

When the sequence counter 303 is set to S49 in this way, processing of the transmission frame starts at this time point t _x (FIG. 13).
The processing of the transmission frames from S49 to S122 is almost the same as the case of the DIO mode described in FIG.
Since data to be already transmitted to the shift register 104 in mode is written, only "1" is written for the start bit nothing is between from S49 to S73, only the Q ₂₄ of the shift register 104 The only difference is that it is in DIO mode.

Thus, when S122 is reached, the signal INITIAL is generated, and thereafter, the idle state including the minimum time from S0 to S24 is entered. In other words, in the MPU mode, unlike in the DIO mode, not only waiting for the data to be received from another CIM, but also forcing the data 49 to the sequence counter 303 when the microcomputer finishes writing the data to the shift register 104. , So that it will automatically start processing transmission frames.

Now, when the transmission of the transmission frame is started from the CIM 33 of the CCU 10, the transmission data TXD is received and processed as the reception data RXD by the CIMs 30 to 32 on the LCU side, as already described in FIG. CIM with matching address
As a result, the return data is transmitted, and this time it is received by the CIM 33 as the reception data RXD.

The processing of the received frame at this time is also DI in FIG.
It is almost the same as in the O mode, except that the MPU mode does not check the address match status. And
When S0 is changed to S48, the reception data is completely stored in the shift register 104, and no error is detected, when the signal WRITE STB rises due to the clock φS of S48, the signals shown in FIGS. As described with reference to FIG. 22, the interrupt request signal ▲ ▼ is generated, the signal INITIAL is generated by the subsequent clock φM, the CIM 33 enters the idle state, and the idle state is maintained until the next signal STB3 is generated.

When the interrupt request signal ▲ ▼ is generated in this way, CC
The microcomputer in U10 jumps to the interrupt processing routine by this signal ▲ ▼ and takes in the received data from the shift register 104. Shift register 104 at this time
The data is read from the shift register 104 by using the switch 400, to which signals READ1 to READ3 are sequentially supplied from the circuits described in FIGS. 15 and 16 and the 8-bit data buses D0 to D7. As described above, it is performed in the order of Reg1, Reg2, and Rege.

By the way, in this embodiment, as already described with reference to FIG. 20, the signal ▲ ▼ is configured to be maskable, and the microcomputer of the CCU 10 writes "1" in Reg0 (Fig. 20). The signal ▲ ▼ can be masked.

Therefore, as shown in FIG. 23, if the data bus D0 is set to “1” in time with the generation time of the signal STB0 (lower left of FIG. 23) before the generation time t _x of the signal STB3, the signal MASK will be generated. Becomes "1",
After that, even when the signal WRITE STB is generated, the interrupt request signal ▲ ▼ is not supplied to the microcomputer, which allows the microcomputer to preferentially perform other processing for a predetermined period as needed. In addition, the removal of this mask is the 20th
As is clear from the figure, it is sufficient to set the data bus D0 to "0" and write "0" to Reg0 when the signal STB0 is generated.

On the other hand, the microcomputer of CCU10 examines the signal IRQ in Fig. 20 while masking ▲ ▼ in this way, and if it is "1", it means that data reception has been completed. The data is fetched from 104, and if it becomes "0", it waits for the completion of data reception. It is apparent from FIG. 20 that the signal ▲ ▼ is canceled by the signal READ0 generated when data is taken in.

Therefore, according to this embodiment, since the microcomputer of the CCU can transfer the data to the CIM33 and then directly enter another processing operation, unnecessary waiting time becomes unnecessary and the processing capacity is fully utilized. It is also possible to use a masking system for other processing operations with higher priority, even if the data reception of the CIM33 is completed. It is possible to prevent the processing operation from being interrupted.

Here, as shown in FIG. 2, the CIM33 in MPU mode,
A state transition diagram shows the data transmission operation in combination with CIMs 30 to 32 set to DIO mode (or AD mode).
It looks like Figure 26.

〔The invention's effect〕

As described above, according to the present invention, a data transmission system such as an integrated wiring system in an automobile can be configured with only one type of communication processing circuit, which enhances the versatility of the communication processing circuit and its function. Highly specialized and configured LSI
Therefore, it is possible to easily provide a communication processing circuit that can sufficiently reduce the cost of the transmission system, except for the drawbacks of the conventional technology.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an example of an integrated wiring system in an automobile, FIG. 2 is a block diagram showing an example of a data transmission system, and FIG. 3 is a basic function of an embodiment of a communication processing circuit according to the present invention. A schematic block diagram shown as the configuration, FIG. 4 is an explanatory diagram of the operation mode switching by an address, and FIG. 5 is a DIO.
6 is a functional block diagram showing one embodiment of the present invention in the DIO mode, FIG. 6 is a block diagram showing one embodiment of the present invention in the DIO mode in more detail, and FIG. 7 is an explanatory diagram showing one embodiment of the data content. FIG. 8 is an explanatory diagram showing an embodiment of a transmission waveform, FIG. 9 is a timing chart for explaining the operation of the embodiment of the present invention in the DIO mode, and FIG. 10 is an example of the present invention in the AD mode. 11 is a functional block diagram showing an embodiment of the present invention in AD mode, and FIG. 12 is a functional block diagram showing an embodiment of the present invention in MPU mode. Figure 13
Explanatory diagram showing an example of a transmission waveform in the MPU mode,
FIG. 14 is a block diagram showing one embodiment of the present invention in more detail in MPU mode, FIGS. 15 and 16 are block diagrams showing one embodiment of the signal processing circuit, and FIGS. 17 and 18 are Timing chart for explaining the operation, FIG. 19 is an explanatory view showing a selection operation by a register select signal, FIG. 20 is a block diagram showing an embodiment of an interrupt request signal generating circuit, FIG.
21 and 22 are timing charts for explaining the operation, FIG. 23 is a timing chart for explaining the operation in the MPU mode, and FIG. 24 is a block diagram showing an embodiment of a circuit for setting the counter. FIG. 25 and FIG. 25 are timing charts for explaining the operation, and FIG. 26 is a state transition diagram showing a data transmission operation by a combination of the CPU mode and the DIO mode. 10 ... Central processing unit, 20 ... Signal transmission line, 30-32 ... Terminal processing unit, 33 ... Communication control type, 40 ... A / D (analog digital converter), 51-58 .... External load, 101 ...
Control circuit, 102 Synchronous circuit, 103 Address comparison circuit, 104 Shift register, 105 I / O buffer, 106
...... A / D control circuit, 107 …… Clock generator, 301 …… Synchronous circuit, 302 …… Counter, 303 …… Sequence counter, 304 …… Sequence decoder, 305 …… Abnormality detector,
306 ... Address decoder, 307 ... Comparator, 308
…… Error detection circuit, 310 …… Composite gate, 311 …… Exclusive or gate, 312 …… And gate, 320…
… Shift register, 321 …… Register, 322 …… Gate,
323 Counter, 324 A / D control signal generation circuit, 325
……counter.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Ken Hirayama 3-1-1, Saiwaicho, Hitachi City Hitachi Research Laboratory, Ltd. (72) Inventor Akira Hasegawa, Katsuta City, Inc. 2520 Takaba, Hitachi Ltd. Sawa Factory (56) Reference JP-A-58-136149 (JP, A) JP-A-57-147392 (JP, A)

Claims (2)

(57) [Claims] 1. A computer (CCU) for controlling data transmission operation.
And connected to this computer via the data transmission line (20)
The above terminal processing unit (LCU), a communication processing open circuit (CIM33) connected between the computer and the data transmission path for exchanging data between the computer and the terminal processing apparatus, and Connected between the terminal processor and the data transmission line,
The data received from the data transmission line is supplied to the vehicle driving means connected to each of the terminal processing devices, and the output from the external load connected to each of the terminal processing devices is supplied to the data transmission line when necessary. In a data transmission system for an automobile equipped with a communication processing circuit (CIM30 to 32) to be sent to each of the above, each communication processing circuit having the same configuration as an LSI operates in a plurality of different modes and has a predetermined input setting. An operation mode switching function for selecting one of the plurality of modes in accordance with the above, and in the selected mode, at least the communication processing circuit (CIM30 to 32) is provided with each of the terminal processing devices and the data transmission. The selected mode, in response to receiving data transmitted from the communication processing circuit (CIM33) through the data transmission line, when connected to the line. Means for transmitting data to a communication processing circuit connected to the computer via the data transmission path within a predetermined time, and the means for selecting one from the plurality of modes is the data Each of the communication processing circuits (CIM30 to 32) compares the specified address with the address supplied from the computer, and the result of this comparison indicates that the address is decoded by the computer. A data transmission system for an automobile, characterized in that it is configured to judge whether or not the received data of is addressed to itself. 2. The computer according to claim 1, further comprising means for supplying data including the address to the terminal processing device, and each communication processing circuit (CIM30 to CIM30 to CIM30) on the side of the terminal processing device. 3
2) determines whether or not the received data from the computer is for itself, based on the means for comparing the specified address with the address supplied from the computer and the comparison result by the comparing means. And a data transmission system for an automobile.