JP3974370B2 - Master-slave communication method and system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a master / slave communication method and system, and more particularly, to a master / slave communication method and system for performing communication by connecting a master and a slave via a parallel bus.
[0002]
[Prior art]
In a communication apparatus, a transmission apparatus, and the like, a slave such as an in-apparatus package is monitored and controlled by a master such as a processor. As a communication method between a master such as a processor and a slave which is a monitored unit, there are a method of performing serial communication and a method of performing parallel communication by connecting with a bidirectional parallel bus.
[0003]
In a general processor configuration, the address and data are connected as a parallel bus. Therefore, the method of accessing the monitored part on the slave side from the processor on the master side by serial communication is purely at the time of access. In addition to the time required for signal transfer, the time required for parallel / serial mutual conversion and the time required for the procedure for establishing synchronization in transmission / reception are required, and access efficiency is reduced.
[0004]
For this reason, in order to increase the access speed, it is necessary to transmit a high-speed signal in the access communication path, so that the transmission characteristics of the access communication path are important. Therefore, a method of ensuring transmission characteristics by using a star-type point-to-point connection to the slave has been used, but in a star-type point-to-point connection, the connection is concentrated on the central master. Therefore, there is a problem that the circuit scale of the master, that is, the processor tends to increase as the number of slaves, that is, monitored packages increases.
[0005]
FIG. 1 is a block diagram showing an example of a bus configuration using a conventional master-slave communication method. In the figure, the master 10 and the slaves 12a to 12x are connected by an address bus 14 and a data bus 16. The address bus 14 is a one-way bus and supplies signals from the master 10 to the slaves 12a to 12x. The data bus 16 is a bi-directional bus, so that a signal is supplied from the master 10 to the slaves 12a to 12x during writing, and a signal is supplied from the slaves 12a to 12x to the master 10 during reading. The tristate buffers 18 and 19a to 19x connected to the data bus 16 are switched inside the slaves 12a to 12x.
[0006]
As shown in FIG. 2, the address bus 14 is 24 bits, for example, and the data bus 16 is 16 bits, for example.
[0007]
[Problems to be solved by the invention]
When the bidirectional parallel bus configuration is used, the amount of data that can be communicated at the same clock speed as that of serial communication can be increased. Since the number of connections in the monitoring communication path increases according to the number of parallel connections, the number of connections in the master processor can be suppressed by using point-to-multipoint connection.
[0008]
However, in the case of the generally used bidirectional parallel bus configuration as shown in FIG. 1, switching control of data read and write, that is, switching control of the tri-state buffers 18, 19a to 19x is necessary. However, there is a problem that the overhead for switching is generated, the switching timing control is difficult, and the access speed is hindered.
[0009]
The present invention has been made in view of the above points, and has a bus configuration with the same number of bits as the conventional one, which eliminates the need for switching the bus direction, reduces overhead, and can achieve high-speed data communication. -It aims at providing the communication method between slaves, and its system.
[0010]
[Means for Solving the Problems]
According to the first and third aspects of the present invention, a first bus that supplies an address or address and data output from the master to the plurality of slaves, and data output from any of the plurality of slaves is supplied to the master. Separating from the second bus ,
The master generates parity from the output address and data, adds the parity to the address and data, and outputs the parity to the first bus.
The plurality of slaves generate a parity from the address and data supplied from the first bus and perform error detection in comparison with the parity added to the address and data supplied from the first bus;
The plurality of slaves generate parity from the output data, add the parity to the data, and output to the second bus,
The master performs error detection by generating parity from data supplied from the second bus and comparing with parity added to data supplied from the second bus;
The master terminates the bus access cycle when an error is detected on the first bus or the second bus,
Since there is no need to switch the bus direction, the timing calculation required for switching control is not required, and the control required for access can be simplified. In addition, the noise required for switching is not generated, reducing the overhead required for switching. , can increase the speed of data communication and Do Ri, it can be finished as soon as possible bus access cycle when an error occurs.
[0017]
In the second and fourth aspects of the invention, when an error is detected by the first parity calculation unit or the second parity calculation unit, the master holds an abnormality occurrence state for each slave.
It becomes possible to identify the slave in which an error occurred during access.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 shows a block diagram of an embodiment of a bus configuration using the master-slave communication method of the present invention. In the figure, the master 20 and the slaves 22a to 22x are connected by an address / data bus 24, a data bus 26, and a control line 28. The address / data bus 24 is a one-way bus that supplies signals from the master 20 to the slaves 22a to 22x. The address and data lines are shared, and the number of connections is reduced by sending addresses and data in a time-sharing manner. is doing. The data bus 26 is a one-way bus that supplies signals from the slaves 22 a to 22 x to the master 20. The control line 28 supplies a read / write control signal and a strobe signal from the master 20 to the slaves 22a to 22x, and supplies a response signal and an error signal to the master 20 from the slaves 22a to 22x.
[0019]
As shown in FIG. 4, the address / data bus 24 is, for example, 26 bits including 24 bits plus 2 parity bits, and the data bus 26 is, for example, 16 bits plus 18 parity bits.
[0020]
FIG. 5 shows a block diagram of an embodiment of the master 10. In the figure, an address and write data output from the processor unit 30 at the time of writing are supplied to a conversion unit 33 through an address bus 31 and a bidirectional data bus 32. The conversion unit 33 supplies the address and write data to the address / data bus 24 and the parity generation unit 34 in a time division manner. The parity generation unit 34 generates a 2-bit parity from each of the address and write data supplied in a time division manner and outputs it to the address / data bus 24.
[0021]
At the time of reading, the processor unit 30 outputs only the address, the conversion unit 33 supplies the address to the address / data bus 24 and the parity generation unit 34, and the parity generation unit 34 generates 2-bit parity from the 24-bit address. To the address / data bus 24.
[0022]
Also, read data from the slave supplied through the data bus 26 at the time of reading is supplied to the conversion unit 33 and the parity calculation unit 36, and 2-bit parity in the data bus 26 is supplied to the parity calculation unit 36. The parity calculation unit 36 generates a 2-bit parity from the 16-bit read data, compares it with the 2-bit parity in the data bus 26, and supplies an error detection signal to the conversion unit 33 only when there is a mismatch. The conversion unit 33 supplies read data to the processor unit 30 through the data bus 32 when the error detection signal is not supplied.
[0023]
FIG. 6 shows a block diagram of an embodiment of the slaves 22a to 22x. In the figure, the address and write data supplied by the time division from the master through the address / data bus 24 at the time of writing are supplied to the conversion unit 40 and the parity calculation unit 41, and the 2-bit parity in the address / data bus 24 is the parity. It is supplied to the calculation unit 41. The parity calculation unit 41 generates a 2-bit parity from each of the 24-bit address and write data, compares it with the 2-bit parity in the address / data bus 24, and converts the error detection signal only when there is a mismatch. 40.
[0024]
When the error detection signal is not supplied, the conversion unit 40 latches the address and write data and supplies them to the register 44 through the address bus 42 and the data bus 43, and the write data is written into the register 44.
[0025]
At the time of reading, the address supplied from the master through the address / data bus 24 is supplied to the conversion unit 40 and the parity calculation unit 41, and the 2-bit parity in the address / data bus 24 is supplied to the parity calculation unit 41. The parity calculation unit 41 generates a 2-bit parity from the 24-bit address, compares it with the 2-bit parity in the address / data bus 24, and supplies an error detection signal to the conversion unit 40 only when there is a mismatch. .
[0026]
When the error detection signal is not supplied, the conversion unit 40 latches the address and supplies it to the register 44 through the address bus 42, and read data read from the address in the register 44 is sent to the conversion unit 40 through the data bus 45. Supplied. The conversion unit 40 supplies the read data to the data bus 26 and the parity generation unit 46. The parity generation unit 46 generates a 2-bit parity from the read data and outputs it to the data bus 26.
[0027]
Next, an operation at the time of reading from the master 20 to acquire any of the register values of the slaves 22a to 22x will be described. FIG. 7 shows an operational flowchart of the master at the time of reading.
[0028]
Step S1. An address is output from the processor unit 30. Step S2. The parity value added to the address is calculated in the master 20.
[0029]
Step S3. The master 20 notifies the start of read access by supplying the strobe control signal and the read / write control signal shown in FIGS. 9B and 9C through the control line 28 to all the slaves 22a to 22x. Note that FIG. 9A shows a clock.
[0030]
Step S4. Simultaneously with step S3, the addresses shown in FIGS. 9D and 9E and the calculated parity values are transmitted from the master 20 through the address / data bus 24. The state at this time is shown in FIG.
[0031]
Step S5. Thereafter, it waits until a response signal is returned from the slave designated by the address. However, when the standby time exceeds a predetermined time, the processor unit 30 executes a time-out process, ends the bus cycle, and returns to the initial state. By holding the abnormal result in the built-in register of the processor unit 30 for each of the slaves 22a to 22x accessed here, it becomes possible to identify the slave in which the timeout has occurred.
[0032]
FIG. 8 shows an operation flowchart of the slave at the time of reading.
[0033]
Step S6. Each slave decodes the supplied address value, and the slave having a register corresponding to the address to be accessed calculates the parity value of the received address.
[0034]
Step S7. If the parity calculation result of the received address is normal in the slave to be accessed, the contents of the register at the corresponding address, that is, the return data is read, and the parity value added to the read data is calculated at the same time.
[0035]
Step S8. The read data and additional parity values shown in FIGS. 9F and 9G are sent to the data bus 26, and the response signal shown in FIG. The state at this time is shown in FIG.
[0036]
Step S9. If the parity calculation result of the received address is abnormal in the slave in step S6, the response signal is notified to the master through the control line 28, and the error signal shown in FIG. To do.
[0037]
The time until the response signal is returned on the slave side is set according to the response time of the device on the slave side.
[0038]
As a result, the master performs the operations of steps S10 to S13 shown in FIG.
[0039]
Step S10. When a response signal is returned from the slave, the parity value of the read data received is calculated.
[0040]
Step S11. If the parity calculation result of the read data in step S10 is abnormal, the processor unit 30 ends the bus cycle as parity error processing and returns to the initial state. By holding the abnormality result in the built-in register of the processor unit 30 for each of the slaves 22a to 22x accessed here, it becomes possible to identify the slave in which the parity abnormality occurred at the time of access.
[0041]
Step S12. When the error signal is notified together with the response signal from the slave in step S10, the processor unit 30 ends the bus cycle as the parity error processing and returns to the initial state.
[0042]
Step S13. If it does not correspond to the above steps S11 and S12, the processor unit 30 stores the read data, ends the access cycle, and returns to the initial state.
[0043]
Next, an operation at the time of writing for setting any register value from the master 20 to the slaves 22a to 22x will be described.
[0044]
FIG. 12 shows an operational flowchart of the master at the time of reading.
[0045]
Step S21. An address and write data are output from the processor unit 30.
[0046]
Step S22. A parity value added to the address and data is calculated in the master 20.
[0047]
Step S23. The master 20 notifies the start of the write access by supplying the strobe control signal and the read / write control signal shown in FIGS. 14B and 14C through the control line 28 to all the slaves 22a to 22x. Note that FIG. 14A shows a clock.
[0048]
Step S24. Simultaneously with step S23, the address and the calculated parity value are transmitted from the master 20 through the address / data bus 24 as shown in FIG.
[0049]
Step S25. Data and the calculated parity value are transmitted from the master 20 through the address / data bus 24 as shown in FIG.
[0050]
Step S26. Thereafter, it waits until a response signal is returned from the slave designated by the address. However, when the standby time exceeds a predetermined time, the processor unit 30 executes a time-out process, ends the bus cycle, and returns to the initial state. By holding the abnormal result in the built-in register of the processor unit 30 for each of the slaves 22a to 22x accessed here, it becomes possible to identify the slave in which the timeout has occurred.
[0051]
FIG. 13 shows an operation flowchart of the slave at the time of writing.
[0052]
Step S27. Each slave decodes the address value, and the slave to be accessed generates a selection signal as shown in FIG. 14 (F) and latches the address and data as shown in FIGS. 14 (G) and 14 (H). A slave having a register corresponding to the address to be accessed calculates the parity value of the received address.
[0053]
Step S28. The slave to be accessed calculates the parity value of the received data.
[0054]
Step S29. If the parity calculation result of the received address and received data is normal in the slave, a write pulse as shown in FIG. 14I is generated and data is written to the corresponding register.
[0055]
Step S30. A response signal shown in FIG. 14J is notified to the master 20 through the control line 28.
[0056]
Step S31. When the parity calculation result of the received address or received data is abnormal in the slave in step S27, a response signal is notified to the master through the control line 28, and an error signal shown in FIG. Notify the occurrence.
[0057]
As a result, the master performs the operations of the following steps S32 and S33.
[0058]
Step S32. When an access error is notified together with the response signal from the slave, the processor unit 30 notifies the end of the bus cycle as parity error processing, and returns to the initial state. By holding the abnormality result in the built-in register of the processor unit 30 for each of the slaves 22a to 22x accessed here, it becomes possible to identify the slave in which the parity abnormality occurred at the time of access.
[0059]
Step S33. If the above step S32 is not applicable, the processor unit 30 ends the access cycle and returns to the initial state.
[0060]
In the present invention, since each of the address / data bus 24 and the data bus 26 is a one-way bus, it is not necessary to provide a tri-state buffer in the data bus 26 in the master 20 and perform read / write switching. For this reason, in the prior art, the clock shown in FIG. 15A is switched by one clock as shown in FIG. 15B in order to perform read / write switching by the tristate buffer provided in the data bus in the master. Although time is required, in the present invention, as shown in FIG. 15C, the switching time is not required, and the access speed can be increased.
[0061]
(Supplementary Note 1) In a master-slave communication method for monitoring and controlling a plurality of slaves as monitored units by a master as a monitoring unit, an address or address and data output from the master are supplied to the plurality of slaves. A master-slave communication method characterized by separating a first bus and a second bus for supplying data output from any of the plurality of slaves to the master.
[0062]
(Supplementary Note 2) In a master-slave communication system in which a master serving as a monitoring unit monitors and controls a plurality of slaves serving as monitored units, a first address or address and data output from the master is supplied to the plurality of slaves. And the bus
A master-slave communication system comprising: a second bus that is separated from the first bus and supplies data output from any of the plurality of slaves to the master.
[0063]
(Supplementary note 3) The master-slave communication system according to supplementary note 2, wherein the master has time division means for outputting addresses and data to the first bus in a time division manner. .
[0064]
(Supplementary Note 4) In the master-slave communication system according to Supplementary Note 2 or 3, the master generates a parity from the output address and data, adds the parity to the address and data, and outputs the first parity to the first bus. A master-slave communication system characterized by comprising generation means.
[0065]
(Supplementary Note 5) In the master-slave communication system according to Supplementary Note 4, the plurality of slaves generate a parity from the address and data supplied from the first bus and supply the address and data from the first bus. A master-slave communication system comprising: first parity calculation means for performing error detection in comparison with the parity added to.
[0066]
(Supplementary Note 6) In the master-slave communication system according to Supplementary Note 2 or 3, the plurality of slaves generate a parity from the output data, add the parity to the data, and output the second bus to the second bus A master-slave communication system comprising:
[0067]
(Supplementary note 7) In the master-slave communication system according to supplementary note 6, the master generates parity from the data supplied from the second bus, and adds the parity added to the data supplied from the second bus. A master-slave communication system comprising second parity calculation means for comparing and performing error detection.
[0068]
(Supplementary Note 8) In the master-slave communication system according to Supplementary Note 5 or 7, the master includes termination means for terminating a bus access cycle when an error is detected by the first parity calculation means or the second parity calculation means. A master-slave communication system characterized by comprising:
[0069]
(Supplementary note 9) In the master-slave communication system according to supplementary note 8, when the master detects an error in the first parity calculation means or the second parity calculation means, the master holds the state of occurrence of abnormality for each slave. A master-slave communication system characterized by comprising means.
[0070]
The address / data bus 24 corresponds to the first bus described in the claims, the data bus 26 corresponds to the second bus, the conversion unit 33 corresponds to the time division means, and the parity generation unit 34 corresponds to the first bus. The parity generator 46 corresponds to the second parity generator, the parity calculator 41 corresponds to the first parity calculator, the parity calculator 36 corresponds to the second parity calculator, S11, S12, S32, and S33 correspond to end means, and the built-in register of the processor unit 30 corresponds to holding means.
[0071]
【The invention's effect】
As described above, according to the first and third aspects of the invention, it is not necessary to switch the bus direction, so that the timing calculation required for the switching control is not required, and the control required for access can be simplified. because There does not occur, reduces the overhead that was required for switching, can increase the speed of data communication and do Ri, it can be finished as soon as possible bus access cycle when an error occurs.
[0076]
According to the second and fourth aspects of the present invention, it is possible to specify a slave in which an error has occurred during access.
[Brief description of the drawings]
FIG. 1 is a block diagram of an example of a bus configuration using a conventional master-slave communication method.
FIG. 2 is a diagram for explaining a conventional bus configuration;
FIG. 3 is a block diagram of an embodiment of a bus configuration using the master-slave communication method of the present invention.
FIG. 4 is a diagram for explaining a bus configuration of the present invention.
FIG. 5 is a block diagram of an embodiment of a master.
FIG. 6 is a block diagram of an embodiment of a slave.
FIG. 7 is an operation flowchart of the master at the time of reading.
FIG. 8 is an operation flowchart of a slave at the time of reading.
FIG. 9 is a signal timing chart at the time of reading.
FIG. 10 is a diagram illustrating a state when an address and data are transmitted from a master.
FIG. 11 is a diagram illustrating a state when data is transmitted from a slave.
FIG. 12 is an operation flowchart of the master at the time of writing.
FIG. 13 is an operation flowchart of a slave at the time of writing.
FIG. 14 is a signal timing chart during writing.
FIG. 15 is a diagram for explaining the effect of the present invention.
[Explanation of symbols]
20 Master 22a to 22x Slave 24 Address / data bus 26 Data bus 28 Control line 30 Processor unit 31, 42 Address bus 32, 43, 45 Data bus 33, 40 Conversion unit 34 Parity generation unit 36, 41 Parity operation unit 44 Register

Claims (4)

In a master-slave communication method for monitoring and controlling a plurality of slaves that are monitored units by a master that is a monitoring unit, a first bus that supplies addresses or addresses and data output from the master to the plurality of slaves And a second bus that supplies data output from any of the plurality of slaves to the master ,
The master generates parity from the output address and data, adds the parity to the address and data, and outputs the parity to the first bus.
The plurality of slaves generate a parity from the address and data supplied from the first bus and perform error detection in comparison with the parity added to the address and data supplied from the first bus;
The plurality of slaves generate parity from the output data, add the parity to the data, and output to the second bus,
The master performs error detection by generating parity from data supplied from the second bus and comparing with parity added to data supplied from the second bus;
The master-slave communication method, wherein the master terminates a bus access cycle when an error is detected on the first bus or the second bus . In the master-slave communication method according to claim 1,
The master holds an abnormality occurrence state for each slave when an error is detected on the first bus or the second bus.
A master-slave communication method characterized by the above. In a master-slave communication system that monitors and controls a plurality of slaves that are monitored units by a master that is a monitoring unit
A first bus for supplying an address or address and data output by the master to the plurality of slaves;
A second bus that is separated from the first bus and supplies the master with data output from any of the plurality of slaves;
The master generates first parity from the address and data to be output, adds the parity to the address and data, and outputs to the first bus; and
The plurality of slaves generate a parity from the address and data supplied from the first bus and perform error detection by comparing with a parity added to the address and data supplied from the first bus. Parity calculation means
The plurality of slaves generate second parity generation means for generating parity from the data to be output, adding the parity to the data, and outputting the data to the second bus;
The master generates a parity from data supplied from the second bus, and performs error detection in comparison with the parity added to the data supplied from the second bus;
The master has end means for ending a bus access cycle when an error is detected by the first parity calculation means or the second parity calculation means.
A master-slave communication system characterized by comprising: The master-slave communication system according to claim 2,
The master-slave communication system characterized in that the master has holding means for holding an abnormality occurrence state for each slave when an error is detected by the first parity calculation means or the second parity calculation means .

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