JP2534836B2 - Data transmission system - Google Patents

Description

Detailed Description of the Invention [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system.
In particular, the integrated wiring system is
The present invention relates to a data transmission method suitable for a system. [0002] 2. Description of the Related Art For example, various lamps and motors are used in automobiles.
Electrical components, various sensors for vehicle control,
A large number of electric devices such as actuators are arranged,
Will continue to increase as automobiles become more electronic
I am following. Therefore, many of these
Wiring was performed independently for each electric device
Wiring becomes extremely complicated and large.
And increased cost, weight and space,
Alternatively, a big problem such as mutual interference occurs. Therefore, a method for solving such a problem
As an example, it is possible to transmit many signals with few wires.
For example, a system for simplifying wiring by the multiplex transmission system is
It is proposed in Japanese Laid-Open Patent Publication No. 57-17535. Figure
1 、 Integrated wiring in the car by such multiplex transmission system
An example of a system is shown. The system shown in FIG. 1 is used as a signal transmission line.
Central control unit CCU using optical fiber cable OF
(Hereafter, simply referred to as CCU. This is Central Cont
rol Unit) and multiple terminal processing units LCU (hereinafter,
Simply called LCU. This is the Local Control Unit
Abbreviations) are commonly connected by optical signal channels
At the branch point of the optical fiber cable OF
OC is provided. The CCU is located near the car dashboard.
Installed at an appropriate place to control the entire system
It has become. LCU is various operation switches S
W, indicator such as meter M, lamp L, sensor S, etc.
A certain number of devices near the electric devices installed in the vehicle.
Only distributed. CCU and each LCU are optical
The optical signal and the electric power are connected to the part that is connected to the fiber cable OF.
The photoelectric conversion module O / E that converts air signals in both directions
It is provided. The CCU is equipped with a microcomputer and
Has a data communication function with real data and supports it
Each LCU has a communication processing circuit CIM (hereinafter simply referred to as CI).
It is called M. This is Communication Interface Mod
(abbreviation of ule) is provided and the CCU selects one of the LCUs sequentially
, And exchanges data with that LCU.
1-channel optical fiber cable
It becomes possible to perform multiplex transmission via the OF, which is complicated and large-scale.
Wiring inside a car can be simplified. [0007] [Problems to be Solved by the Invention]
Is an external load such as a sensor that outputs an analog signal.
However, in the system described above,
For analog signal acquisition from an external load
Is not taken into consideration.
For importing the number, use the CCU input / output circuit separately.
Is running under the control of the CCU,
Therefore, an external load that generates such an analog signal is
In some cases, the wiring to the CU becomes long, and
There is a problem that the advantage of the line system is lost.
Was. The present invention has been made in view of the above circumstances.
To connect to an external load such as a sensor that outputs an analog signal.
In addition, the LCU close to the installation location collects analog signals.
The LCU can call in, and the LCU calls from the CCU.
Data that can be arbitrarily sent according to
To provide a transmission system. [0009] [Means for Solving the Problems] The above-mentioned purpose is applied to the LCU.
Analog-digital converter and analog-digital converter
And an analog-digital converter provided with the converter control means.
The control means is equipped with a shift register, and an interrogation from the CCU is made.
The above analog-digital at a timing independent of
It controls the converter and sends digital data to the shift register.
Is configured to execute the process of storing the data,
The digital data stored in this shift register is
Sequentially transmitted from LCU in response to calls from CCU
It will be achieved as you go. [0010] The analog-digital converter control means is a CC
The timing is independent of the call from U, and the shift is always
So that digital data is stored in the register
work. As a result, at what timing the CCU
Even if there is a call from the
Since the transmission process will not be affected, the LCU will not be affected.
Can capture analog signals. [0012] Embodiments of the data transmission system according to the present invention will be described below.
Examples will be described with reference to the drawings. FIG. 2 illustrates one embodiment of the present invention.
An example of the whole block configuration is shown, and 10 is a central processing unit.
(Corresponding to CCU in FIG. 1), 20 is a signal transmission line (optical fiber in FIG. 1)
(Corresponding to the fiber cable OF), 30 to 32 are terminal processing devices
(Corresponding to the LCU in FIG. 1), 40 is an A / D (analog-data
Digital converters) 51 to 58 are external loads. What
In this embodiment, the electric signal transmission is used as the signal transmission line 20.
The case of using the route is shown, and
The photoelectric conversion module 10 and the terminal processors 30 to 32 are photoelectric conversion modules.
Module is unnecessary, and therefore, the terminal processing devices 30 to 32
The content of is substantially only CIM. Including a computer (microcomputer)
The central processing unit 10 uses the transmission line 20 for each terminal processing unit 3
Combined with 0-32, various sensors, lamps, actuators
External load 51 consisting of electric devices such as data and motors
Of control data to 58 and
The acquisition is performed by the multiplex transmission method. At this time, Ana
External loads 57, 58 such as sensors that output log data
Is connected to the terminal processing device 32 via the A / D 40,
Being able to perform transmission operations using digital data
There is. If the signal transmission line 20 is bidirectional,
Not only the electrical signal transmission system,
Any communication system such as a signal transmission system is used.
The system is a so-called half-duplex system (central processing unit).
One of the plurality of terminal processing devices 30 to 32 from the device 10
One of the terminal processing devices and the central
Data is exchanged with the processing device 10 via the transmission line 20.
Are performed alternately. [0015] Multiplex transmission by such a half-duplex system
Therefore, the data sent from the central processing unit 10
An address indicating the destination is attached and received from the transmission path 20.
The address attached to the collected data is your own address
Only one of the terminal processing devices that
I'm supposed to answer. In this way, the address from the central processing unit 10 is
Address depending on the data sent with the address
Terminal processing that understands and determines that it is their own
Only one of the devices responds by centralizing its own data
By sending to the processing device 10, the above-mentioned half-duplex type
A data transmission operation according to the formula will be obtained. Further, in this embodiment, each terminal processing device 3
The functions of 0 to 32 are aggregated into a specific one, and these terminal processes are performed.
Easy to make devices 30-32 into LSI (large-scale integrated circuit)
are doing. And as a specific function at this time,
The data transmission function described, that is, multiplex transmission by half-duplex method
Functions required for sending and A / attached to each terminal processing unit
It has two types of functions to control external devices such as the D40.
You. As a result, the data transmission function is exclusively used.
Is becoming possible. For example, an integrated wiring system in a car
If you want to apply the
According to the appropriate transmission speed and the number of bits of the address
You can decide. Furthermore, in this multiplex transmission system,
To utilize the functions of the terminal processing device that has been implemented as an LSI
However, it is also applicable to the central processing unit 10,
As a result, the central processing unit 10 has a data transmission function.
A general-purpose computer that does not have
Etc., and the LSI terminal processing device 33 described above
The central processing unit 10 can be configured only by combining
Software required for the computer of the central processing unit 10
The load on the wear side can be reduced and the edge
The versatility of the end treatment device can be increased. In addition, this place
In the case of the terminal processing unit 33 that is combined with the central processing unit side,
Does not take advantage of some of the features it has
It remains, but this is unavoidable. Next, FIG. 3 shows each of the terminal processing devices 30 to 32.
An example of the above is shown in a rough block configuration.
The reception signal RXD input from the transmission path 20 is supplied to the synchronization circuit 10
2 of the clock from the clock generator 107
The control circuit 101 is synchronized and the reception signal RXD is clocked.
A clock that is start-stop synchronized to the black component is given.
The control circuit 101 generates a control signal, and the shift register
The data portion of the received signal is serially read into the data 104. On the other hand, the address comparison circuit 103 is previously provided with
Given the address assigned to the terminal processor
This address and the predetermined value of the shift register 104
The data read in the bit position is the address comparison circuit 1
Compared by 03, shift only when both match
The data in the register 104 is transferred to the I / O buffer 105.
It is sent and given to an external device. Further, the control circuit 101 advances by a clock.
Generates sequential control signals, including a counter
Then, the data by the received signal RXD is transferred to the I / O buffer 10
After giving it to 5, then I / O buffer
Parallel data from the file 105 to the shift register 104
To the central processing unit 10 from an external device.
Data in the shift register 104
Prepare as data. And this data is shift register
Serially read from the data 104 and used as the transmission signal TXD
And transmits it to the transmission line 20. At this time, if the received signal RXD is added,
The original address is sent as it is to the transmission signal TXD.
Therefore, the central processing unit 10 transmits the address transmitted by itself.
The transmission signal TXD
This makes it possible to perform one cycle by half-duplex method.
The transfer of the data for one minute is completed. Thus the central processing unit
10 sends data to the next terminal processing device.
By repeating this, each of the plurality of terminal processing devices 3
Data is exchanged between 0 and 32 periodically,
Multiplex transmission becomes possible. The A / D control circuit 106 is the end of FIG.
A / D40 required when used as the end treatment device 32
It is a feature of the present invention to provide a control function of
The analog-to-digital converter control means.
Therefore, an external negative signal such as a sensor that generates an analog signal
Digitize data from loads 57 and 58 by A / D 40
Necessary in order to convert the data into the shift register 104
Functions to provide various control functions. In addition, about the details
Will be described later. Next, FIG. 4 shows one of the terminal processing devices 30 to 33.
3 is a block diagram showing an embodiment, which is the same as or equivalent to FIG.
The parts are given the same reference numerals, and in FIG.
01 generates a clock that is start-stop synchronized with the received signal RXD.
Synchronous circuit for switching, 302 is a two-phase clock φ_S And φ
_M Generating counter, 303 is for sequential control
Counter, 304 indicates various values from the output of the counter 303.
Sequence decoder that produces control signal, 305 is abnormal
Detector, 306 is input / output switching selection of I / O buffer 105
Address decoder for selection, 307 is 4 for address comparison
Bit comparator, 308 is an error detection
The crucible OR gate 312 is an AND for data transmission.
Gates 313, 314 are tri-state buffers, 3
20 is an 8-bit shift register, 321 is a 32-bit
Register 322, 32 channel gate, 323
Is a counter for A / D control, 324 is a signal for A / D control
Generator circuit 325 is a counter for A / D channel selection
It is The shift register 104 has 25 bits
(24 bits + 1 bit), the I / O buffer 105 is 1
It has 4 ports (14 bits). The terminal processing devices 30 to 33 (hereinafter,
Are referred to as CIM) and select one of several operating modes
The CIMs 30 to 31 shown in FIG.
When used as DIO (Digital Input Outpu
t: Digital input output) mode
However, if the CIM of FIG.
, And MPU when used in the CIM 33 of FIG.
Each mode is selected. This mode selection
Will be described later. First, these CIMs are selected for the DIO mode.
If selected, the A / D control circuit 106 does not operate,
The data contents of the shift register 104 at this time are shown in FIG.
As shown in the figure, 6 bits from No. 0 to No. 5 are used.
14 bits of No. 6 to No. 19 are not used for I / O
It is assigned to the data DIO of the buffer 105. 4 bits from No. 20 to No. 23
No. 24 is assigned to address data ADDR.
It is assigned to the start bit. In addition, DIO day
The number of bits allocated to the data is 14
I / O buffer 105 has 14 bits
Because there is. Also, for this reason, C according to this embodiment
In IM, external load connectable to I / O buffer 105
The maximum number is 14. The data transmission method according to this embodiment is
This is called a step-synchronous, bi-directional, inverted duplex transmission method.
Digital data by NRZ (nonreturn to zero) method
The transmission waveform is shown in Fig.6.
It is supposed to be. That is, from the CIM on the CCU side
A frame for transmitting data to the CIM on the LCU side is received.
Frame, conversely the frame transmitted from the LCU side to the CCU side
If the frame is a transmission frame, the reception frame and the transmission frame are
Both frames are 74 bits, so one frame and transmit frame
Both have the same frame structure as the
There is a bit "0", then 1 for start / stop synchronization
A start bit consisting of a bit "1" is provided.
This is followed by 24-bit reception data RXD or transmission data.
Data TXD is transmitted in the NRZ signal format, and
Inverted data (RXD) or (TXD) of data is transmitted
It has become. Here, this inverted data (RXD) or
Is transmitting (TXD) because of the transmission error check
This is because. Regarding such inversion data,
In the drawing, a bar is added above the letters and symbols.
However, in this specification, parentheses are added. You
That is, the inverted data of the data RDX is as described above.
Is represented by (RDX). As described above, in this embodiment, the half
Since multiplex transmission is performed by the duplex method, the reception frame
The first four bits of the data RXD of the
Address data of the LCU to be called
Data ADDR is added as shown in FIG.
Data TX of the transmission frame transmitted from the LCU
The same address data ADDR is added to the first 4 bits of D.
And transmitted. The transmission frame is transmitted from the LCU side.
Is it limited to the LCU called on the CCU side?
, The address is not added to the transmission data TXD
However, on the CCU side, the data from which LCU
Whether it is a thing or not can be judged immediately. Therefore, the transmission frame
It is not necessary to attach an address to the data TXD of the system.
The first 4 bits of data TXD are LC such as (0000).
It may be data that does not match any address of U
Yes. Now, returning to FIG. 4, the CIM address is
explain about. As already mentioned, in this example
Is a different 4-bit CIM for the LCU.
An address is assigned, and based on this address, half
Multiplex transmission of data by the duplex system
ing. Then, this address is assigned to each CIM.
Input that functions to assign to
4 inputs that are 2⁰~ 2³And these inputs
Data to be given ADDR₀~ ADDR₃By the CI
The address of M is specified. For example, add the CIM
To specify the address as "10", the address data A
DDR₀= 0, ADDR₁= 1, ADDR₂= 0, ADD
R₃= 1 and input 2⁰~ 2³(1010) is input to
You can do it like this. In this example, the data
"0" is the ground potential, data "1" is the power supply voltage V_ccBy
Since it is displayed as
Power 2⁰Two²Ground and input 2¹Two³Can be connected to a power source
Becomes By the way, in this embodiment, address input
2⁰~ 2³Is also input to the address decoder 306, and the
The direction of the I / O buffer 105 is controlled by the output.
It has become. As a result, if you specify the address,
Which of the 14 terminals of the I / O buffer 105
It is determined whether it will be a data output port. And this
In the example, the address directly corresponds to the number of output ports
Therefore, the address is now "1".
If set to 0 ", of the 14 terminals of the I / O buffer
10 are output ports and the remaining 4 are input ports
Controlled to be. Although not shown in FIG. 4, this ad
The output of the response decoder 306 is the sequence of the control circuit 101.
7 is also given to the decoder 304.
As shown, the operation mode of this CIM can be switched.
It has become. That is, in this example, the address
CIM set to "0" is in MPU mode
The CIM set between "1" and "D" is the DIO module.
Mode, and the address is either "E" or "F"
Set the CIM to work in AD mode respectively
Is done. Next, the control circuit 101 and the synchronization circuit 102
The function will be described. This example relates to FIG.
As already explained, the start-stop synchronization method is adopted.
Therefore, for both received frames and transmitted frames,
When transmitting, be sure to insert 25 bits "0" before the start.
Is entered and after this as a 1-bit start bit
"1" data is inserted. Therefore, the synchronizing circuit 301 determines the maximum number of received frames.
Start bit following the first existing 25-bit "0"
Detects the rising edge of and synchronizes the internal clock bit.
Therefore, until the next received frame appears,
Operated by internal clock bit-synchronized with the timing of
Will be carried out. The counter 302 is synchronized by the synchronizing circuit 302.
Two-phase clock φ from the taken internal clock_S And φ_M To
produce. This makes the clock φ_S And φ_M Then enter
It is assumed that the received data RXD is phase-synchronized.
You. The sequence counter 303 is the synchronization circuit 3
02 shows the start bit rising detection timing
Signal, a specific count value, for example, count value 0
Set to the state of_S Or φ_M To
Therefore, it is counted. Therefore, according to the count output
The control procedure for the entire CIM can be defined and counted
CIM at any timing by checking the value
You can know in which step the operation of is. Therefore, the count output of this counter 303
To the sequence decoder 304, and the CIM
Required for operation, for example RXMODO, TXMODE, R
All control signals required internally such as EAD and SHIFT
Signal is generated by the sequence decoder 304.
There is. That is, in this embodiment, the clock φ_S , Φ_M By
The sequence control method is
Necessary to decode the output of the counter 303.
That is, all control is possible. Next, the transmitted data RXD is
Whether it is data for CIM, that is, from CCU
The challenge by transmitting the received frame is to itself
The operation of determining whether or not is described. As described above, the comparator 307
Input 2 to one input of⁰~ 2³Address data from
Is given to the other input and the shift register 1
04 Q₂₀Bit to Q_{twenty three}Given up to bits of data
It is supposed to be. And this comparator 30
7 is a match signal only when both input data match
Outputs MYADDR. Therefore, the shift register 10
Received data RXD is input to 4 and its Q₂₀From a bit
Q_{twenty three}The part up to the bit is added to the beginning of the data RXD
Timing data (see Fig. 5) stored
Control the output signal MYADDR of the comparator 307.
At that time, this signal MYADDR becomes "1".
If so, the data RXD is for you, CCU?
It turns out that these calls are for themselves. Therefore, the error detection circuit 308 receives a control signal.
No. COMPMODE is supplied and the specified timing
Take in the signal MYADDR and it becomes "0"
Output, INITIAL is generated and
Sequence counter 303 to count 0,
The operation of the entire CIM is restored and the next data transmission is input.
Be prepared for On the other hand, the signal MYADDR becomes "1".
The error detection circuit 308
Since TIAL does not occur, the operation of CIM remains unchanged.
-Set the count value of the Kens counter 303 at that time
After that, it continues. Next, the transmission error detection operation will be described.
You. In this embodiment, as already shown in FIG.
Data transmission by the continuous transmission method is adopted.
The transmission error can be detected. Soshi
Therefore, the first Q of the shift register 104 is₀ Bit
To and the last Q_{twenty four}Bit to Exclusive OR Gate
Data is given to 311 and the output of this gate 311 is
It is given to the error detection circuit 308 as a signal (ERROR).
It is supposed to be. The sequence decoder 304 has a start
Transmission period of received signals RXD and (RXD) (Fig. 6) following
And outputs a control signal RXMODE to output the composite gate 310.
Open the lower gate of the
Data to the shift register 104 as a serial signal SI.
input. At this time, the NOR gate is in the composite gate 310.
Since it is included, the data supplied from the transmission line 20
Data is inverted and input to the shift register 104. Therefore, the start frame of the reception frame (FIG. 6) is
The 24-bit data following the bit is stored in the shift register 10.
4 is input to this shift register 104
Q₀Bit to Q_{twenty three}Received signal R
The inverted data (RXD) of XD will be written. Next, as is clear from FIG.
After the received signal RXD is transmitted,
When a 24-bit inverted signal (RXD) is transmitted,
It is inverted by the composite gate 310 and becomes the data RXD.
Input to the shift register 104 as a serial signal SI.
Begins to be forced. As a result, the Q of the shift register 104₀ To
The first bit of the inverted signal (RXD) is inverted and input
At the timing, the reception signal RX that was written before that
The inverted data of the first bit of D is stored in the shift register 104.
Q_{twenty four}2nd bit of inverted signal (RXD)
Data is Q₀ At the timing written in
No. RXD second bit data is Q_{twenty four}Move to a bit of
In the end, the inverted signal (RXD) shifts
Serially written in the register 104 bit by bit
At each bit timing when, the shift register 104
Q of_{twenty four}Bit and Q₀ Inverts the received signal RXD in bits
Data of the same bit of signal (RXD) is always written in correspondence
Will be rare. By the way, as described above,
The shift register is connected to the two inputs of the Shiv OR gate 311.
Q of data 104₀ Bit and Q_{twenty four}Bit data is input
ing. Therefore, the received signal RXD and the inverted signal (RXD)
If no error occurred during transmission, the inverted signal R
Exclusive OR gate 311 during XD transmission
The output of should always be "1". Because the reception
Corresponding bits of signal RXD and its inverted signal (RXD)
Then, "1" and "0" should be always reversed.
As a result, the input of the gate 311 always shows a mismatch, so
It doesn't happen only when there is an error in transmission
Is. Therefore, the error detection circuit 308 outputs the inverted signal.
Signal (RXD) is being transmitted during the 24-bit period
(ERROR) is monitored and when it becomes "0" level
If the signal INITIAL is generated at the point
-Detection operation can be obtained. In addition, such a data
As a transmission error processing method in a data transmission system
When it detects a transmission error, it fixes it and
It is also known to obtain the data
Now, when a transmission error is detected, the frame
The data reception operation of the system is canceled and the next frame
It is a system to prepare for data reception.
For simplification. Next, the DIO mode of the embodiment shown in FIG.
The overall operation of data transmission in
It will be explained by a chart. Φ in the figure_S , Φ_M Is cow
The two-phase clock output from the input circuit 302
Internal clock generated by the clock oscillator included in 301
It is being generated based on the clock. On the other hand, (RESET) is the CI from the outside.
A signal supplied to M, which is used by microcomputers
It is the same as the set signal, and all CIMs in
And is required when power is turned on.
The external reset circuit supplies the
Initialize the entire system. After initialization, the sequence counter
The counter 303 sets the count value to 0, and
Φ_M By step by step. And the count value becomes 25
No action is taken until the count value reaches 25.
Then IDLE signal and (RXENA) signal are generated, and CIM
Becomes idle and the sequence counter 303
Sequential control by the und value is stopped,
The state buffer 313 opens and the signal can be received.
Become. At this time, after initialization, the
Until the count value of the cans counter 303 reaches 25
It is the synchronization time that is set so that the signal cannot be received.
This is because of the start-stop synchronization by the path 301, and the received signal RXD
Since it is 24 bits, a minimum of 25 bits "0" period is given.
This is because it is necessary to obtain it. In this way, when entering the idle state, the sequence
Counter 303 is clock φ_S, Φ_M By the count of
However, the sequence decoder 304 uses the control signal.
No. IDLE and INITIAL remained generated
Waiting for the incoming signal to be input.
You. For this reason, as shown in FIG.
25-bit “0” is added to the beginning of the frame and transmission frame
It is done. Thus, the idle state is entered and
Well, time t₀ It is assumed that the received signal RXD is input at. So
Then, a one-bit star is placed at the head of this signal RXD.
Tobit is attached. So this start bit
Is detected by the synchronization circuit 301, and bit synchronization of the internal clock is performed.
I take the. Therefore, after that, the transmission operation for one frame is performed.
Data RXD, RXD and clock until completion
φ_M, Φ_S Synchronization with the internal clock stability
Therefore, the start-stop synchronization function can be obtained. When the start bit is detected, the sequence
Counter 303 outputs count output 0 (hereinafter, this count
The output data of the data 303 is attached with S. For example, in this case,
Is represented by S0), which causes the sequence
The coder 304 stops the control signal IDLE and turns off the control signal RX.
Generate MODE. In parallel with this, shift shift
The shift pulse SHIFT is supplied to the register 104 as the clock φ.
_M It is supplied in synchronization with. As a result, 48 bits following the start bit
Received signal RXD and inverted signal (RXD) (Fig. 6)
From the route 20 through the compound gate 310,
The shift register 104 sequentially shifts one bit at a time.
While writing, it is written. At this time, the first 24
Received signal RXD is inverted by the composite gate 310.
The converted data (RXD) to the shift register 104.
Since it is written serially, it follows the start bit
The 24-bit period, that is, the sequence counter 303
At the time when S1 to S24 are reached, the shift register 10
Q of 5₀ Bit to Q_{twenty three}Received signal RX for bits up to
Data (RXD) with D inverted will be written.
You. Here, the clock φ of the next S25_M Rise
The control signal (COMPMODE) is output and an error
The detection circuit 308 functions. And in this state, continue
Then, the inverted signal (RXD) starts to be input. As a result, this time
Is the data RXD in which the inverted signal (RXD) is inverted,
Q of shift register 105₀ Write from bit to serial
I'm going down. As a result, in steps S1 to S24, the shift
The data (RXD) written in register 104 is the beginning
Bits of the shift register 104 to Q_{twenty four}Bit position
Yes, the sequence counter 303 changes from S25 to S48.
One bit at a time until it overflows
Go on. Meanwhile, in parallel with this, the shift register 104
Q of₀ Through the bit position, the data by the inverted signal (RXD)
The data RXD is written serially from the first bit.
It gets in, and during this time the exclusive agate 31
1 and the error detection circuit 308 detects a transmission error,
It will be carried out as described above. Therefore, the sequence counter 303 sets S4.
At the time when the value of the shift register 104 becomes₀ Bit
To Q_{twenty three}Up to the bit, the same data as the received signal RXD
The RXD will be written as it is. So this
At the timing of S48 of, the output signal of the comparator 307 is
By checking the number MYADDR, the above-mentioned address
Is confirmed, and the data RXD just received is addressed to myself.
Or not, that is, from the CCU at this time
A determination is made whether the call is for you
You. The sequence counter 303 sets the S25
A transmission error is detected during a period between
Alternatively, if an address mismatch is detected, the error detection
When the path 308 reaches S48, the control signal INITIA
L is generated, and the sequence counter 303 outputs S at this point.
It is set to 0 and returns to the 25-bit state before idle.
All reception operations for the reception frame of
To prepare for the input of the next signal. Now, the sequence counter 303 is set to S25.
No transmission error is detected during the period from
When no mismatch of the dress is detected, that is, S48
When the error detection circuit 308 becomes INITIAL,
When no signal is generated, when S48 is reached
At this point, the sequence decoder 304 outputs the control signal WRITE.
Generate STB. As a result, at the time of S48,
Is either the INITIAL signal or the WRITESTB signal
Either of them will be generated, and transmission error and address mismatch will occur.
When neither occurs, the former, and then the transmission error
-Or address mismatch, either
The latter will be output respectively. Thus, at the time of S48, the control signal WR
When ITESTB is output, the shift register at that time
Data from the data 104 to the I / O buffer 105 in parallel
Written and, as a result, received data RXD by C
The data provided by the CU is the I / O buffer 105.
Is supplied to any of the external loads 51 to 56 from the output port of
Is done. In addition, at this time, operating in DIO mode
Because it is, that Q₆ Bit to Q₁₉Up to a bit
Up to 14 bits can be transmitted as data RXD
And how many of those bits are in the I / O buffer 105
Is determined by the address
What has been done is as already explained in FIG. When S48 is reached in this way, the received frame
All the processing is completed, and the next S49 starts to process the transmission frame.
Enter (Fig. 6). First of all, no processing from S49 to S72
Do not do. This is the start-stop synchronization of CIM on the CCU side.
IDL in the processing of the received frame described above.
For the same purpose as the operation in the period set before E
Is. Upon entering S73, the sequence decoder 30
4 outputs the control signal PS, which causes the shift register
The star 104 operates to read parallel data, and the I / O
The external load 51 to 56 is connected to the input port of the O buffer 105.
Input the data given from either of
You. The number of bits of data read at this time is 14 bits.
Out of the ports of the I / O buffer 105
Left after subtracting the bits used as output ports
This is the number of bits. For example, as described above, this CI
When the address of M is set to 10, the output port
Since the number is 10, the input port is 4 bits at this time.
It becomes A parallel device for the shift register 104
The data is written in the shift clock SH together with the signal PS.
Since one bit of IFT is required, the clock of S73 is used.
φ_SAfter the signal SP is started by the clock of S74,
φ_S The shift pulse SHIFT synchronized with the control signal T
Supplied before the start of XMODE. At this time, as is clear from FIG.
, A start bit is added before the transmission data TXD,
Further, an address is added to the first 4 bits of data TXD
Must. Therefore, it is omitted in FIG.
However, only during the period when the signal PS is generated, the shift register
Q of data 104_{twenty four}The bit is a signal representing data "1"
But then Q₂₀Bit to Q_{twenty three}Input 2 in the bit part
⁰~ 2³Address data is supplied from each
It has become. Thus, the DUMM from S49 to S73
25 bits of data required for start / stop synchronization depending on the Y state
After the “0” transmission period is set, the control is performed when entering S74.
Signal TXMODE rises, which causes TX (transmission) state
become. The generation of this signal TXMODE causes the composite gate
The AND gate above 310 is activated and
The gate 312 is activated. As a result, the Q of the shift register 104 is_{twenty four}
Bit data, that is, the data that becomes the start bit
“1” is sent to the transmission line 20 through the AND gate 312.
Will be issued. Then, the subsequent clock φ after S75
_M Shift clock SHIFT generated in synchronization with
Therefore, the contents of the shift register 104 are transferred to the subsequent stage bit by bit.
Shifted, Q_{twenty four}AND gate 312 from bit to bit
Is transmitted to the transmission line 20 through which the transmission frame is transmitted.
Transmission of transmission signal TXD including start bit of system (Fig. 6)
Is performed. On the other hand, if such a shift register 104
In parallel with the data reading process from_{twenty three}Bit cell
The data read from the device passes through the composite gate 310 and is returned.
And is fed to the serial input of shift register 104.
Have been. As a result, after S75, the shift register 10
Q of 4₀ Bit to Q_{twenty three}Transmission that was written by bit
The transmission data TXD is generated by the shift clock SHIFT.
It is sent to the transmission line 20 bit by bit and inverted.
Of the shift register 104 as serial data SI.
Q₀ The data is sequentially written from the bit. Therefore, the period during which the control signal PS is generated
Inside the shift register 104 Q₀Bit to Q_{twenty three}Bit
All the transmission data TXD written in the cell
At the time of completion, this Q₀ Bit to Q_{twenty three}Up to a bit
Inverts the transmission data TXD up to that point in the cell
This means that the data (TXD) is stored. Therefore, the transmission data (TXD) is read.
After the completion of the
Readout of inverted data (TXD) from the register 104 is started.
Then, as shown in FIG. 6, the inverted data (TXD) is transmitted.
Data will be sent to the transmission line 20 after the TXD.
You. In this way, when S122 is reached, the shift register
Q of data 104_{twenty three}Bit to Q₀ Inverted data up to bit
Has been completely read, the control signal TXMODE is
Falling, supply of shift clock SHIFT is also stopped
The transmission status ends. And the next clock following S122
φ_M Control signal INITIAL is generated by
Counter 303 is set to S0, CIM is idle
(IDLE) Return to the previous signal reception preparation state. Therefore, according to this embodiment, start-stop synchronization,
Half-duplex multiplex communication by bidirectional, two-way reverse transmission
Can be reliably performed between the CCU and the LCU,
The transmission lines can be integrated wiring. Next, the AD mode of the CIM according to this embodiment will be described.
The operation in the mode will be described. As mentioned above, C
Electrical equipment to exchange data with CCU via IM
For output, it outputs analog signals from various sensors.
There are external loads 57, 58 (FIG. 2), which is why
The embodiment includes an A / D control circuit 106,
Also has the function of controlling the A / D 40
There is. Then, the CIM operation mode at this time is the AD mode.
It is a card. Now, as described above, this actual
In the example, input 2⁰~ 2³Address data to be given to
Therefore, the operation mode is set.
The address data corresponding to the AD mode is shown in Fig. 7.
As can be seen, they are "E" and "F". Next, this CIM operates in the AD mode.
Shift register 10 when set to perform work
The contents of the data stored in 4 are as shown in FIG.
8 bits from No. 0 to No. 7 are transmitted via A / D40.
Then, the AD data case acquired from the external load 57, 58, etc.
For payment, 2 bits of No. 8 and No. 9 are AD channel data.
Data storage, so that for DIO data,
It is 10 bits from No. 10 to No. 19, and other
Is the same as in the DIO mode. Here, the AD channel data and
Is a channel when using multi-channel A / D.
This is data for specifying the channel, and in this embodiment, A / D4
Since it uses 4 channels as 0, 2 bits
Are assigned. The shift register 320 has 8 bits
Then, the Digi captured serially from the external A / D40
Tal data (data from external loads 57, 58, etc.)
A / D conversion of analog data is stored)
Readout and A / D40 channel
2 bits provided from the counter 325 for designating
Receive the channel selection data of
It functions to read out serially and supply it to the A / D 40. The register 321 is of 32 bits and is
/ D40 is 8 bits and 4 channels.
Use as 8-bit 4-channel register
Data taken from A / D40 in 8 bits
Is stored for each channel. The gate 322 also corresponds to the register 321.
32-bit (8-bit 4-channel)
Q of shift register 104 for data transmission₈ Bit and Q₉ B
The AD channel data (Fig. 5) read from the cell
Controlled by one of the channels of register 321
Select the 8-bit data, shift register Q₀
Bit to Q₇ Set the AD data (Fig. 5) in the bit cell
Function to write. The counter 323 has a clock φ._M The coun
The A / D control circuit 106 as a whole.
-Sequential and cyclic control
do. The A / D control signal generation circuit 324 is a counter.
It includes a decoder and a logic circuit for decoding the output of H.323.
Only the various controls required for the operation of the A / D control circuit 106 as a whole.
It functions to generate control signals. Next, the operation of the entire A / D control circuit 106 will be described.
Describe the work. In this embodiment, the counter 323
Sequentially corresponding to each of the count outputs
The control proceeds, the number of steps is 27, and the count output is 0.
(This is called S0) count output 26 (this is S2
6 cycle), 1 cycle of control is completed, and A / D4
Data of one channel of 0 is taken into register 321
Be done. First, when the control of one cycle is started,
Signal INC causes a channel selection counter 325 to
The counter 325 output is
The data is (0,0) → (0,1) →
It changes from (1, 1) to (0, 0). The output data of the counter 325 is a shift
Write to the top 2 bit positions of the register 320 in parallel
Rarely, then read as serial data ADSI
It is supplied to the A / D 40. In parallel with this, cow
The output data of the input terminal 325 is a decoder (not shown).
Is also supplied to the register 321 via the register 321.
8 bits of the corresponding channel of are selected. Subsequently, the A / D 40 outputs the serial data A
Depending on the channel selection data input as DSI,
Select the corresponding analog input channel and
8 after converting analog data to digital data
Shift register as bit serial data ADSO
Store in 320. After that, the data is stored in this shift register 320.
The converted 8-bit digitally converted data AD is
The data is read out in parallel at a predetermined timing,
Register 3 previously selected by the output data of
Transferred to 8 bits of 21 predetermined channels,
End the control operation of the module. Thus, for example, the output data of the counter 325 is
If the data is (0,0), the A / D40
Analog data of channel 0 is digitized and
Stored in the 8 bits of channel 0 of
Then, the counter 323 is reset to S0, and the next cycle
The counter 325 is incremented.
Output data becomes (0, 1), and this time the channel
The analog data of 1 is digitized to register 32
It is stored in 8 bits of channel 1 of 1. Therefore, according to this embodiment, A / D control
The data acquisition operation from the A / D 40 by the circuit 106 is
Sequence counter 303 and sequence decoder 304
Performed independently of data transmission process by timing
The data of each channel of the register 321 is 4 cycles.
Is refreshed once per AD control operation of the
Input to four channels of A / D40 in the register 321
Analog data is stored for each channel.
And always prepared as 8-bit digital data
Will be there. Therefore, now, the received signal RXD from the transmission line is
Is input, and the address data attached to
Assume that it was for CIM. In this case,
As described above, the address data is “E” or
"F". Then, the input of the reception frame is completed.
At the point of time (S48 in FIG. 8).
The format of the data is the AD mode shown in Fig. 5.
Therefore, the Q of this shift register 104₈ Bit Q
₉ AD channel data consisting of 2 bits
Is stored. Therefore, this AD channel data is S
Read when signal WRITESTB occurs at 48
Which allows the gate 322
Is selected. As a result, in S73 (FIG. 8), the signal
When PS and SHIFT occur, register 321
Of the four channels, the Q of the shift register 104
₈ , Q₉ The AD data of the channel selected by the two bits of
Data of the shift register 104 is read out.
>₀ Bit to Q₇ Write to the 8-bit part up to the bit
This is included in the transmission signal TXD in the transmission state after S74.
In rare cases, it will be transmitted to the CCU. By the way, in this embodiment, as described above
The reception processing of the reception signal RXD and the subsequent transmission signal T
Regardless of the XD transmission process, always in the register 321
Is prepared with AD data. Therefore, this embodiment
According to this, at what timing the received signal R addressed to itself
Even if XD appears, the transmission signal T by AD data is immediately transmitted.
XD transmission can be performed and the operation of A / D 40
A / D conversion operation without affecting transmission processing
There is a risk that the transmission speed will decrease due to the time required for
Absent. In this embodiment, the CIM is made into an LSI.
When using the A / D40 as an external device
When it comes to commercialization, it is designed to reduce costs. Tsuma
Therefore, as described with reference to FIG.
Depending on the setting, one type of CIM is set as LCU30-31
, LCU32, or CIM3 of CCU10
It can be used as 3. At this time, however, by incorporating the A / D
If you use it as a CIM 30, 31, 33
Wasteful and, in general, integrated wiring for automobiles
When applied to the system, it is used as CIM32.
The number that is used is used as the other CIM 30, 31, 33
A / D is included in all CIMs
There is not much merit to store it. for that reason,
The A / D is externally attached. By the way, since this A / D is attached externally,
As is clear from 4, 4 for external A / D40
Book connection terminals are required, and terminal pins when integrated into an LSI
This may lead to an increase in the number. Therefore, in one embodiment of the present invention, the CIM is
When the AD mode is set, the I / O buffer 10
4 out of 14 ports of 5 connect to A / D40
It can be switched as a continuous terminal. I.e. the book
In the embodiment of the invention, the I / O buffer 105 has 14 ports.
And these are, as is clear from FIG.
When M is set to DIO mode
There is a possibility that it will be used as a
At most, only 10 ports are used and 4 ports
It is not used for inputting / outputting DIO data and remains.
Therefore, switch the remaining 4 ports in AD mode,
If used as a terminal pin for / D40, A / D
Even if externally attached, the number of terminal pins does not increase,
As a result, versatility increases and cost reduction becomes possible. Next, the MPU of the CIM according to this embodiment
The operation in the mode will be described. Clear from Figure 7
As described above, the CIM according to this embodiment is set to the MPU mode.
To switch and set, the address ADDR0 to ADD
Address setting by DR3 is "0", that is, input 2²~
2³Keep all of them at the ground potential and set it to (0000)
Yes. The MPU mode is the CI shown in FIG.
To give necessary functions when used as M33
Used in DIO mode and AD mode
Unlike the case, the CCU10 microcomputer (below
When data is given from (below, simply called a microcomputer),
Pair it with any of the CIMs 30-31 of a given LCU.
And send the data, and receive the data returned in response.
If you receive it, you can transfer the data to the microcomputer.
It performs a transmission interface operation. By the way, in the above description, referring to FIG.
As I explained in a row, the explanation as seen from the CIM on the LCU side
Was mainly used, so CIM on the CCU side
The frame that transmits data to the CIM is the received frame
On the other hand, a frame transmitted from the LCU to the CCU
I've called it Laem, but after that, from the perspective of each CIM
A frame that sends data by sending
Frame when accepting data as received frame
explain. Therefore, after that, a CIM, for example, CIM
The transmission frame at 33 is sent to another CIM, for example CIM3.
0 indicates a received frame, while CIM30 transmits
The frame is a received frame in the CIM 33. Now, FIG. 9 shows a CI according to an embodiment of the present invention.
Address “0” is set in M, and the CPU operates in the CPU mode.
Is a rough functional block diagram when it is controlled to
3 shows a state of the CIM 33 in FIG. In addition,
As described above, in this embodiment, the address setting
CIM with the same configuration has three modes, that is, CPU
Mode, DIO mode, AD mode
It is possible to add a function, and
The state of FIG. 9 represents the functional blocks in CPU mode.
The configuration of the CIM according to this embodiment is different from that of FIG.
It does not mean that it is different. As is apparent from FIG. 9, the CPU mode is
I / O buffer 105 (Fig. 3) and A / D 40
The function is stopped, and the microcomputer is a 14-bit data bus.
Tied together. The terminal pin at this time is the I / O buffer.
It is commonly used as the I / O port of the 105 and has more terminal pins.
Needless to say, the reduction does not occur at all.
Yes. And 8 of the 14-bit (14) input / output
Bits are for data, and the remaining 6 bits are for control signals
Has become. First, in this CPU mode, shift
The data contents of the register 104 are, as shown in FIG.
Q₀ To Q_{twenty three}The 24 bits up to are all MPU data.
The microcomputer uses an 8-bit data bus to
I came to access this shift register 104
There is. On the other hand, the control circuit 101 is a control signal from the microcomputer.
Of the shift register 104₀ ~ Q_{twenty three}All of the
Data from the microcomputer is stored in the
Time t at which this data is stored after the receiving operation is started_X Or
Then, as shown in FIG. 10, transmission of the transmission frame is started.
You. Thus, the transmission frame is transmitted from the CIM 33.
When sent, CIMs 30-32 on the LCU side will be sent accordingly.
One of them responds, and then the CIM starts sending.
Therefore, time t_X From 1 frame (148 bits)
Time t when time has passed_Y Then, the shift register 10
CIM that interrogated from CIM33 in 4
Data transmitted from (one of CIMs 30-32)
Will be stored and will end. Therefore, the control circuit 101 of the CIM 33 is
At this time t_Y Generated an interrupt request (IRQ) at
The microcomputer reads the data in the shift register 104 according to
Then, the data transmission for one cycle is completed. In addition, this
Figure 3 shows the data transfer operation between CIMs at
Same as in the related DIO mode
Needless to say, Next, FIG. 11 shows CIM 33, that is, MP.
Machine showing an embodiment of CIM when set to U mode
Function block diagram, functions required in MPU mode
Only the blocks corresponding to are shown in FIG.
1, 1, 400 and 402 are 8-bit switches, 4
04 is an 8-bit data latch, and the others are shown in FIG.
Same as the embodiment. In this MPU mode, the shift register 1
04 Q₀ Bit to Q_{twenty three}8-bit input / output up to bit
Connected to the data bus of the microcomputer via the force pin
Data is sent to and received from
Q of shift register 104₀~ Q_{twenty three}Bits of three groups
Loop, Q₀~ Q₇(Reg3), Q₈~ Q_Fifteen(Reg2),
Q₁₆~ Q_{twenty three}Treated as divided into (Reg1), hours and minutes
I try to access them in sequence. Therefore, for this reason, the 8-bit switch 4
Register given from microcomputer using 00 and 402
The combination of select signals RS0 and RS1 makes the switch
Switch 400 control signals READ1 to READ3 and switch 402
I / O terminal pins 7-1
4 is sequentially connected from Reg1 to Reg2, and then to Reg3
So that it will continue for 3 times with 8 bits each.
Data transfer between the microcomputer and shift register 104
It is designed to receive money. And in this case my
Writing data from the controller to the shift register 104
Depending on the time, the data read time from the microcomputer and the shift
Compensate for the difference with the data writing time to register 104
A latch 404 is provided to compensate
Data is latched and then written
You. In this MPU mode, data reception
Address added at the beginning of 24-bit data at the time
Is not performed in the CIM 33. Follow
And input 2⁰~ 2³The address (0000) given to
The address decoder 306 enables the MPU mode
Used only to set the CIM of
The comparator 307 does not operate. Next, in this MPU mode, CIM33
Input / output terminal pins 1 to 6
It is a transmission line, which allows C
For the IM control circuit 101, the clock E and the chip set are
Rect signal (CS), read / write signal RW, and the above
Register select signals RS0 and RS1 of
However, from this CIM, the interrupt request signal (IRQ) is
Output. 12 and 13 show the processing times of these signals.
Although not shown in FIG. 11, the control circuit
It is included as a part of 101.
The clock E is supplied to the circuit of FIG.
Two-phase clocks EH and EL are generated by being processed together with K.
Be done. And these clocks EH, EL and myco
The signals RW, CS, RS0, RS1 from the
Signal STB0-3, READ0-1 are processed
Be born As for the signal MPU, CIM is in MPU mode.
This signal becomes "1" when set to. Further, signal processing by the circuit of FIG.
The timing is shown in FIGS. 14 and 15, and these figures are shown.
Of these, FIG. 14 shows the generation timing of the signals READ0-3.
In addition, FIG. 15 shows the generation timing of the signals STB0 to STB3.
Are respectively shown. In addition, in these figures
And any of the signals READ0-3 are generated.
And which of the signals STB0 to STB 3 occurs.
Is determined by the combination of the signals RS0 and RS1.
As a result, the shift register 104 described above is
Loops Reg1, Reg2, Reg3 are selected.
You. By the way, these signals READ0-3,
The signals READ0 and STB0 of STB0 to 3 are
Used for group selection of shift register 104
Not used to generate the interrupt request signal (IRQ) described later.
Be done. Therefore, the selection state by the signals RS0 and RS1 is shown.
The result is as shown in FIG. Next, FIG. 17 shows the generation of an interrupt request signal (IRQ).
In an embodiment of the raw circuit, the control circuit 101 of FIG.
This CIM33 is included in the
When the storage of the received data is completed in the soft register 104
Signal WRITESTB (Fig. 8) and signal REA
A circuit that generates a signal (IRQ) with D0, and input / output
Connect to microcomputer data bus with terminal pins 7-14
One of the data lines D0 to D7, for example,
The signal DATA from the data line D0 and the signal STB0 from the signal line
No. MASK1 circuit and its operation
Are shown in the timing charts of FIGS. 18 and 19.
You. Of these, FIG. 18 shows the signal DA.
TA was "0" at the timing of STB0.
19 and the signal DATA becomes "1" in FIG.
It shows the operation of each of the above. What
In the circuit of FIG. 17, the signals DATA and STB0 are supplied.
The flip-flop that is provided is called Reg0. Therefore,
In the circuit of FIG. 17, "1" is written in Reg0.
The interrupt request signal (IRQ) is masked if
become. Next, according to the embodiment of FIG. 11, that is, the present invention,
CIM is set to MPU mode
The overall operation of data transmission in
It will be explained by a chart. In the embodiment of the present invention
The operation of all CIMs 30 to 33 is sequential.
Controlled by the count output of the counter 303,
The sequence counter 303 count output
If you set it to a constant value, you can shift it to an arbitrary operating state.
What can be done has already been explained with reference to FIG. 4 and FIG.
This is what the CIM is doing.
Even if it is set to mode, it does not change. By the way, as shown in FIG.
The CIM set in the mode is as shown in FIG.
CIM3 set to DIO mode or AD mode
It is 0 to 32. And this CIM is DIO
When the mode and the AD mode have been set, FIG.
Received data from another CIM as described in
Then, after that, it sends its own data,
This is a data transfer operation for one frame.
Only passive operation is performed. On the other hand, like the CIM 33, the MPU
If the mode is set to
When the data is written to the shift register 104,
It requires active movement, so to speak, to start communication. Therefore, in this embodiment, this active
To start data transmission, the glue of the shift register 104
Signal STB among signals STB1 to STB1 to 3 for selecting
I am trying to use 3. This is a shift register
Writing the transmission data to the 104 by the microcomputer is R
This is done in the order of eg1, Reg2, Reg3.
Therefore, the microcomputer shifts when the signal STB3 is generated.
Because all the data for register 104 is stored
is there. Then, returning to FIG. 20, at some point,
The CCU10 (Fig. 2) is connected to either LCU
It is assumed that data to be transmitted is prepared. Do so
And, this microcomputer, via the input and output terminal pins 1 to 6,
Signal (CS), RW, RS0, RS1 in CIM33
It is supplied to the control circuit 101 and described with reference to FIGS.
As shown in FIG. 20, the signals STB0 to 3 are generated.
Part), and data from the data bus in sequence of 8 bits each
Registers Reg1, Reg2, Reg3 of the shift register 104
Write it down. On the other hand, the control circuit 101 sends the signal STB
3, the sequence counter 303 stores “4”.
9 "is loaded. Sequence by this signal STB3
Time for setting the output data of the counter 303 to “49”
An example of a circuit is shown in FIG.
The mining chart is shown in FIG. 22, respectively. In this way, the sequence counter 303 sets the S
When set to 49, at this time t_X(Figure 10) Send frame
Processing is started. Transmission from S49 to S122
The frame processing is in the case of the DIO mode described in FIG.
This is almost the same as
Data to be transmitted has already been written in the register 104.
Therefore, nothing is done between S49 and S73, just
Q of shift register 104_{twenty four}For start bit
The point that only writing "1" is in DIO mode
Is only different. When S122 is reached in this way, the signal INIT
When IAL occurs and then the minimum time from S0 to S24
Entering the idle state including the interval. In other words, in MPU mode
Is different from the DIO mode,
Shift from the microcomputer instead of waiting for the data to be received.
When writing of data to the
Data 49 is forcibly loaded into the
This will automatically start sending frames
-ing Now, in this way, CIM33 of CCU10
If the transmission of the transmission frame starts from, already explained in FIG.
As described above, this transmission data TXD is the CIM on the LCU side.
Received data RXD is processed by 30 to 32.
And fold according to the CIM where the address is located
Return data is transmitted, so this time it is received data.
The data is received by the CIM 33 as the data RXD. The processing of the received frame at this time is also shown in FIG.
MPU mode is almost the same as DIO mode in
The only difference is that the address
Is. Then, from S0 to S48, the shift register
Data has been stored in the
If not detected, the clock φ of S48_S By
When the signal WRITE STB rises, the signal shown in FIG.
7 to 19, the interrupt request signal (IRQ) is
Occurrence and subsequent clock φ_M Signal INITIA
L occurs and this ZCIM33 enters the idle state.
The idle state until the next signal STB3 is generated.
One. Thus, the interrupt request signal (IRQ) is generated.
Then, the microcomputer in the CCU 10 receives this signal IRQ.
Jump to the interrupt processing routine and shift register 10
The received data is fetched from 4. Shift at this time
A switch is used to fetch the received data from the register 104.
400 is used, and the number of times described in FIGS.
The signals READ1 to READ3 are sequentially supplied from the channel, and the 8-bit
R of the shift register 104 via the data bus D0 to D7
It is performed in the order of eg1, Reg2, Reg3.
This is as already explained. By the way, in this embodiment, in FIG.
As explained, this signal (IRQ) is maskable
The CCU10 microcomputer is Reg0 (Fig. 17)
By writing "1" to this signal (IR
Q) can be masked. Therefore, as shown in FIG. 20, the signal STB3
Occurrence time t_X Before the generation of the signal STB0 (see FIG.
Set the data bus D0 to "1" according to (lower left)
For example, the signal MASK becomes “1”, and then the signal WRI
Interrupt request signal (IRQ) even when TESTB occurs
Is not supplied to the microcomputer, which makes the microcomputer necessary.
Accordingly, other processes may be prioritized during the predetermined period.
it can. It should be noted that this mask release is apparent from FIG.
As is clear, when the signal STB0 is generated, the data bus D
It is sufficient to set 0 to “0” and write “0” to Reg0. On the other hand, the microcomputer of the CCU 10
When masking the signal (IRQ),
Check the signal IRQ of the
Since the data reception has been completed, the shift register
Data is fetched from 104 and it becomes "0".
If so, wait for completion of data reception. The signal (IR
Q) is a signal R generated when data is taken in
It is clear from FIG. 17 that it is canceled by EAD0.
is there. Here, as shown in FIG. 2, the MPU mode is set.
To the CIM33 that was set and DIO mode (or AD mode)
Data in combination with the set CIMs 30-32
The state transition diagram of the transmission operation is shown in FIG. Next, the transmission control by the microcomputer of CCU10 is performed.
I will explain about you. CCU microcomputer is
Data from loads such as various switches and sensors
Ingest, and accordingly various types of load on each LCU
Data for controlling lamps and actuators
To send to each LCU,
At start-up when the transmission system is powered on
Processing and each LCU when data transmission is in steady state
CIM operation is monitored. FIG. 24 shows an embodiment of the CCU 10, which is 500
Is the central processing unit (CPU
), 502 is a read-only memory for storing programs.
Memory (called ROM), 504 is random for data storage
・ Access memory (RAM), 506 is a peripheral
Is a Ral interface adapter (called PIA)
In addition, the CIM33 and the light set to CPU mode
Electrical conversion module O / E and optical fiber cable O
The bidirectional transmission line 20 including F is described in FIGS.
As you have revealed. Next, the operation of the embodiment shown in FIG. 24 will be described with reference to FIG.
It will be described with reference to the flowchart of FIG. Car engine
Data transmission system
The power supply for operation of the entire system is turned on and transmission operation is
When started, the process according to this flow starts and the first
Step S1 (Hereinafter, steps will be omitted and simply S1, S
2). At S1, system startup prepared in advance is started.
Flag for use. In S2, after starting the system,
Has the data transmission from the CCU to the LCU made one round?
Check whether or not the result is NO, that is, CCU is still running after startup
Data transmission from the LCU, that is, an LCU that has not been challenged
To S3 while remains, otherwise S9
Head to. At S3, after the system is activated, the CCU
Check whether data transmission has been done even once, and
Determine whether to transmit. And when the result is YES
Goes to S4, and if NO goes to S10. S
In the case of No. 4, a specific value created in advance and stored in the ROM 502
Control data for this specific LCU, which is also predetermined
Send to. As specific control data at this time
Controls the load on the particular LCU that should receive it
Make sure that the status is appropriate when the system starts up.
Data. For example, if the LCU load is a lamp
If so, it will be the data to erase it anyway
Leave it to me. After finishing the process of S4, S5
Proceed to. At S5, the data from any one of the LCUs is
Data is transmitted, and when the result is NO,
Proceeds to S6, and if the result is YES, jump to S8
To Data transmitted from LCU to CCU
Is a switch or a part of the load coupled to the LCU.
Data from the sensors, etc., indicating their operating status.
Therefore, this is called monitor data. At S6, the judgment result at S5 continues to be 2
Judgment whether or not the result is NO, and the result is YES
Then, the process proceeds to S7, and if the result is NO, the process returns to the determination of S3.
In S7, warning processing of the occurrence of abnormality is performed, and at this time,
To the LCU that did not send the monitor data twice,
The fact that an abnormality has occurred due to a failure is displayed on DIS508.
After that, the process proceeds to S8. At S8, the next data is transmitted from the CCU.
The LCU to be used is determined as the next LCU. This
Therefore, after starting the system in S4, the first data from CCU
The specific LCU that should send the
Numbers can be attached to LCUs in advance and can be specified sequentially
Needless to say, it is necessary to do so. Soshi
After S8, the process returns to S2. On the other hand, when the result in S2 is YES
To S9, the result after S9 and S3 is NO.
When it becomes, it proceeds to S10, but first, in S9, the system
A process for clearing the system start flag is performed.
Then, in S10, the monitor data received from each LCU is
Control data for each LCU created based on
Data to the corresponding LCU.
U In S4 and S10 described above,
The transmission process is performed from the CPU 500 of the microcomputer to the CIM 33.
Writing 24-bit data to the shift register 104
Automatically when the signal STB3 is generated
Starting with is as described above. On the other hand, a microcomputer including a CPU 500 and the like
Is operating according to S1 to S10
At this time, the CIM33 associated with this receives the data.
Then, an interrupt request signal (IRQ) is generated, and already
As described above, the processing of the microcomputer is performed from the CIM33.
Jump to the interrupt processing for data acquisition. Soshi
Then, as shown in FIG. 26, the CIM
Based on the monitor data received from each LCU via 33
Each time, the required control data is newly added.
Processing for displaying on the DIS 508 is performed. Thus, the data created in the interrupt process
Is the corresponding LCU in the processing of S10 of FIG.
Will be sent to. In addition, interrupt required
If the request signal (IRQ) was masked, unmask it
It has already been explained that the operation depends on the state at the time.
It is Ri. Next, the processing of FIGS. 25 and 26 is performed.
The results obtained will be explained. First, S2, S3, S4
The first data transmission after the power is turned on due to the existence of each processing of
The operation is to send specific control data to a specific LCU.
Becomes As a result, this particular LCU is provided
The load is abnormally controlled by undefined data when the power is turned on.
Immediately from the state, fully valid with specific control data
It will be in a controlled state. On the other hand, after the power is turned on, the monitor can
Data is received, the control data based on it is received.
Since it can be created, after that, except for a specific LCU
Due to the data transmission in S10, it is quite reasonable for LCU
Control data will be sent, which means data transmission
It is emphasized as the number of transmissions increases, and the number of data transmissions
If it is close to the number of LCU, it is almost the same as the steady state.
It is possible to obtain almost complete control. Therefore, according to this embodiment, when the power is turned on.
To minimize the abnormal load control status, etc.,
It is possible to perform controls that are practically not a problem.
You. Next, according to this embodiment, S in FIG.
Due to the existence of the processing of 5, S6 and S7, the CCU has a certain LC.
When data is transmitted to U, the monitor from that LCU
If the data cannot be received, the CCU
The operation of transmitting data to the same LCU is repeated, and
If monitor data is received in response, it is an accidental event.
Directly to the next LCU as a temporary abnormality due to emotion
However, the monitor data is transmitted twice in a row.
If it is not received, the LCU may have a malfunction.
It is determined that an abnormality has occurred, which is DIS508.
Will be displayed in. Therefore, according to this embodiment, data transmission
During operation, monitoring for data response operation of all LCUs
It is carried out, and when an abnormality occurs, it is temporary
It will be automatically confirmed whether it is a thing or not,
The abnormal occurrence can be displayed normally. Incidentally, in the embodiment of FIG. 25, in S6
Judgment is twice whether or not reception is possible in succession.
The number of times is not limited to 2 times, but any number of times is possible
Yes. For example, in a noisy environment, temporary data transmission
If the probability of error occurrence is high, 3 times, 4 times, or 5 times
On the contrary, it is installed in a good environment and
If the probability of data transmission error occurrence is low,
As you can see, there are times when even two times is sufficient.
not. By the way, in the embodiment of FIG. 25, the power is turned on.
After that, the data transmitted first from the CCU to the LCU is
Specific for one specific LCU
It becomes the control data, and monitor data for other LCUs.
Control data created each time based on the data
However, for each LCU, a specific control data
First prepared for each LCU
For the transmission of the
The fixed control data may be transmitted. Next, FIG. 27 shows another embodiment of the CCU 10.
In the example, the number of loads included in the data transmission system increases and L
Suitable when multiple CIMs are needed in a CU
FIG.
0, 512, 514 are O / E (photoelectric conversion module),
20a, 20b, 20c are signal transmission lines by OF, 30
a, 30b, 31a, 31b are in DIO mode or AD mode.
It is the CIM set in the mode, and the other is the implementation of FIG.
Same as the example. O / E 510, 512, 514 are PIA5
The selection of the OF's 20a, 20
One of b and 20c is a signal transmission line T of the CIM 33.
It works to combine with X and RX. For each LCU
Each of a plurality of CIMs 30a, 31a, 30b, 31b
OF, 20a, 20b, 20
bound to CCU by c. As the CPU 500, HD4680 is used.
2 is known as IC, and PIA506 has
For each IC known as HD46821
Of these, HD46802 has ROM and RAM
Since these are built-in, these are provided as external
You don't have to. According to this embodiment, the CPU 500 or the like
Consisting of O / E512 via PIA506
~ 514 are selected and controlled, and data transmission is performed by CIM33.
Since you can specify the LCU to be performed, each
Provide a CIM with the same address for each LCU
And the number of CIMs on the LCU side than the number of addresses
The function of the data transmission system can be sufficiently large
Can be easily expanded. According to the invention,At what timing
Even if there is a call from the central processing unit, the analog
Capable of capturing signals from external loads that generate
Therefore, there is no risk that the transmission process will be affected, and
It can be processed in the same way as digital data. Also books
According to the invention, the terminal processing device is provided with an analog-digital converter.
Since it is possible to have a conversion function, the same transmission system can be used.
Output both analog and digital signals of the load
Data transmission becomes possible, and the advantages of the integrated wiring system
Make good use ofbe able to.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing an example of an integrated wiring system in a vehicle. FIG. 2 is a block diagram showing an embodiment of a data transmission system according to the present invention. FIG. 3 is a block diagram showing an embodiment of each terminal processing device. FIG. 4 is a block diagram showing the embodiment of FIG. 3 in more detail. FIG. 5 is an explanatory diagram showing an example of data contents. FIG. 6 is an explanatory diagram showing an example of a transmission waveform. FIG. 7 is an explanatory diagram showing an example of mode selection. FIG. 8 is a flowchart for explaining the operation of the embodiment of the present invention in the DIO mode. FIG. 9 is a CPU of an embodiment of the terminal processing device according to the present invention.
It is the functional block diagram which set and showed the mode. FIG. 10 is an explanatory diagram showing an example of transmission waveforms in a CPU mode. FIG. 11 is a functional block diagram explaining the embodiment of FIG. 9 in more detail. FIG. 12 is a block diagram showing an embodiment of a signal processing circuit. FIG. 13 is a block diagram showing an embodiment of a signal processing circuit. FIG. 14 is a timing chart for explaining the operation of one embodiment of the signal processing circuit. FIG. 15 is a timing chart for explaining the operation of one embodiment of the signal processing circuit. FIG. 16 is a block diagram showing a selection operation by a register select signal. FIG. 17 is a block diagram showing an embodiment of an interrupt request signal generation circuit. FIG. 18 is a timing chart for explaining the operation of one embodiment of the interrupt request signal generation circuit. FIG. 19 is a timing chart for explaining the operation of one embodiment of the interrupt request signal generation circuit. FIG. 20 is a timing chart for explaining the operation in the CPU mode. FIG. 21 is a block diagram showing an embodiment of a circuit for setting a counter. FIG. 22 is a timing chart for explaining the operation of the embodiment of the circuit for setting the counter. FIG. 23 is a state transition diagram showing a data transmission operation by a combination of the CPU mode and the DIO mode. FIG. 24 is a block diagram showing an embodiment of a central processing unit. FIG. 25 is a flow chart for explaining the operation of the central processing unit. FIG. 26 is a flow chart for explaining the operation of the central processing unit. FIG. 27 is a block diagram showing another embodiment of the central processing unit. [Explanation of Codes] 10 Central Processing Unit 20 Signal Transmission Lines 30 to 32 Terminal Processing Unit 33 Communication Control Unit 40 A / D (Analog to Digital Converter) 51 to 58 External Load 101 Control Circuit 102 Synchronous Circuit 103 Address Comparison Circuit 104 Shift register 105 I / O buffer 106 A / D control circuit 107 Clock generator 301 Synchronous circuit 302 Counter 303 Sequence counter 304 Sequence decoder 305 Abnormality detector 306 Address decoder 307 Comparator 308 Error detection circuit 310 Composite gate 311 Exclusive OR gate 312 AND Gate 320 Shift register 321 Register 322 Gate 323 Counter 324 A / D control signal generation circuit 325 Counter 500 CPU 502 ROM 504 RAM 506 PIA 508 display

   ────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akira Hasegawa               No. 2520 Takaba, Katsuda City, Ibaraki Prefecture Co., Ltd.                 Hitachi Sawa Factory                (56) References JP-A-56-159799 (JP, A)

Claims (1)

(57) [Claims] 1 . In a data transmission system comprising a central processing unit and a terminal processing unit, in which data transmission / reception in a frame unit between the central processing unit and the terminal processing unit is started in response to a call from the central processing unit, A shift register for exchanging data with the terminal processing device ,
An analog-digital converter and an analog-digital converter control means are provided, and the analog-digital converter control means has the above-mentioned analog.
-Shift register for storing output data of digital converter
And the analog-to-digital converter control means is
Above at a timing independent of the call from the processor
Controls the analog-digital converter and outputs the above output data.
A process for storing digital data in the storage shift register
The terminal processing unit is configured to execute the processing from the central processing unit.
Depending on each case, the above-mentioned data transfer shift register
And the shift register for storing the above output data
The digital data stored in the
Process that is sent from the terminal processing device as the data of
A data transmission system, wherein the data transmission system is configured to perform . 2. In the invention of claim 1, the data transfer shift register and the output data storage
Shift register is composed of the same shift register
A data transmission system characterized in that