JP2612433C - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex data transmission system. Vehicle data that is particularly suitable for integrated wiring systems in vehicles
Related to transmission systems. [0002] 2. Description of the Related Art For example, automobiles have various transmission products such as lamps and motors, and
Numerous electrical devices such as various sensors and actuators for vehicle control are arranged.
The number is increasing steadily as automobiles become more electronic. [0003] Therefore, as in the prior art, each of these many electrical devices has
Wiring would be extremely complicated and large-scale if wiring was performed independently.
Cost increase, weight and space increase, or mutual interference
Problems arise. Therefore, as one of the methods for solving such a problem, a small distribution is required.
It has been proposed to simplify wiring by a multiplex transmission method that can transmit a large number of signals over a wire.
As an example, Japanese Patent Application No. 57-17535 filed by the present applicant (Japanese Patent Application
No. 8-70657). FIG. 1 shows an integrated wiring system in an automobile using such a multiplex transmission system.
An example is shown below.   The system of FIG. 1 uses an optical fiber cable OF as a signal transmission path,
Control unit CCU (hereinafter simply referred to as CCU. This is a Central Control Unit)
) And a plurality of terminal processing units LCU (hereinafter simply referred to as LCU.
cal Control Unit), which is commonly connected with an optical signal channel.
An optical branch connector OC is provided at a branch point of the fiber cable OF. [0006] The CCU is installed in an appropriate place such as near the dashboard of a car.
, And controls the entire system.   LCU includes various operation switches SW, indicators such as meters M, lamps L, Distributed by a predetermined number in the vicinity of electrical devices such as sensors S installed in a large number of vehicles
It is arranged.   An optical signal and an electrical signal are connected to a portion where the CCU and each LCU are connected to the optical fiber cable OF.
A photoelectric conversion module O / E that converts air signals into two directions is provided. [0007] The CCU has a microcomputer, and stores data by serial data.
In response to this, each LCU has a communication processing circuit CIM (hereinafter simply referred to as “CIM”).
Called CIM. Note that this is an abbreviation for Communication Interface Adapter)
The CCU sequentially selects one of the LCUs and exchanges data with that LCU
And repeat this to obtain a one-channel optical fiber cable OF
Multiplex transmission over the vehicle, simplifying complex and large-scale vehicle wiring.
Can be. FIG. 2 illustrates an example of such a transmission system in more detail.
10 is a block diagram of a central processing unit (corresponding to the CCU in FIG. 1),
Is a signal transmission line (corresponding to the optical fiber cable OF in FIG. 1), and 30 to 32 are terminal processing devices.
(Corresponding to the LCU in FIG. 1), 40 is an A / D, and 51 to 58 are external loads. In addition,
In this example, a case where an electric signal transmission line is used as the signal transmission line 20 will be described.
Therefore, the central processing unit 10 and the terminal processing units 30 to 32 have photoelectric conversion modules.
Module is unnecessary, and the contents of the terminal processing devices 30 to 32 are substantially CIM.
It has become. A central processing unit 10 including a computer (microcomputer) includes:
Various sensors and lamps are connected to each of the terminal processing devices 30 to 32 by the transmission line 20.
, Actuators, motors and other external devices 51-58
Data transmission and data fetching are performed by a multiplex transmission system.
At this time, analog data is output. External loads 57 and 58 such as sensors to be connected to the terminal processor 32 via the A / D 40.
Thus, a transmission operation using digital data can be performed. The signal transmission line 20 may be anything as long as it is bidirectional, and may be an electric signal transmission system.
Not limited to this, any type of optical fiber transmission system such as an optical fiber is used.
The communication system is a so-called half-duplex system (Half Duplex).
In response to a call to one of the terminal processing devices 30 to 32, the terminal processing device
Of data between one of them and the central processing unit 10 alternately via the transmission line 20
Is being done. For multiplex transmission in such a half-duplex system, the central processing unit 10
The data transmitted from the transmission line 20 is provided with an address indicating the destination.
Recognized that the address attached to the received data is its own address,
Only one of the terminal processors responds. As described above, an address is sent from the central processing unit 10 and transmitted.
The end that understands the address according to the data and determines that it is its own
Only one of the end processors sends its data to the central processor 10 in response
By doing so, it is possible to obtain the above-described half-duplex data transmission operation.
Become. In this system, the central processing unit 10 is provided with a microcomputer.
And a CIM 33 having a data communication function using serial data.
The data transmission operation according to the half-duplex method described above is performed via the IM 33,
This allows a general-purpose microcomputer without a data transmission function as a microcomputer
It can be used. [0014] In the above prior art, a data transmission system for an automobile is used.
Communication processing circuit located at the input / output unit of the central processing unit and the terminal processing unit in the system
No consideration is given to the disclosure of the specific configuration of the communication processing circuit.
There was a problem in making the SI module. An object of the present invention is to provide an LSI module.
Disclose the specific configuration of the communication processing circuit required for the chip of the vehicle system and
To provide an automotive data transmission system that can be made sufficiently compact
is there. [0015] [0016] [0017] In order to achieve this object, the present invention provides a communication control program.
Communication control module for controlling data transmission to and from the terminal processing device according to the program.
Computer and the communication control computer, and are connected to the terminal processing device.
A register for temporarily storing reception data and transmission data to the terminal processing device
A central processing unit having a first communication processing circuit provided with the first communication processing circuit;
Data indicating the state of the external load connected to the terminal processing device.
And a I / O connected between the register and the external load.
A second communication processing circuit including an O buffer; a first communication processing circuit;
A data transmission system for vehicles is connected to a communication processing circuit and a communication line connected to enable data transmission.
The feature is that the system is configured. [0018] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
I do. FIG. 3 is a schematic functional block diagram showing a basic configuration in one embodiment of the present invention.
, A control circuit 101 for sequentially controlling the entire operation, and a transmission line 20
Start-up with received signal RXD input from Circuit 102 for synchronizing clocks according to synchronization method, 4-bit data from outside
ADDR given in advance as_0-3Select the operation mode
, An address comparison circuit 103 for comparing the address of the input data,
Shift register 104 for serially fetching and sending, data input / output
Buffer 105 and an external A / D 40 for performing the
A / D control circuit 106 for enabling transmission of analog data, and
And a clock generator 107 for generating a clock necessary for the operation of
Indicates that the LSI has been implemented. The address data input to the address comparison circuit 103 is as described above.
By selecting the data ADDR to be given by these 4 bits,
DIO mode, AD mode, and MPU mode
The internal functions are switched so as to operate in one operation mode. First, the DIO mode means that the CIM is a terminal processing device described in FIG.
This is an operation mode for providing functions required when used as devices 30-31.
For this purpose, the address data ADDR is set to any one of "1" to "D".
Just set it to a dress. Next, the AD mode refers to the CIM of the terminal processor 32 in FIG.
This operation mode can provide the necessary functions when used as
To do so, set the address data ADDR to either "E" or "F".
Good.   And the MPU mode means that when used as the CIM 33 in FIG.
An operation mode for providing a required function. In this case, the address data AD
DA is set to "0".   FIG. 4 shows the relationship between the address setting and the operation mode as shown in FIG. become. Therefore, according to this embodiment, a transmission system as shown in FIG.
It can be configured with only one type of CIM, and generalization of CIM becomes possible.
Therefore, it is possible to sufficiently obtain the advantages of the dedicated product and the LSI.
. Next, the operation of the embodiment of the present invention in each of these operation modes will be described.
The work will be described sequentially.   The CIM according to the embodiment of the present invention shown in FIG.
Is set to any of the above, the functional block is in the state shown in FIG.
The reception signal RXD input from the control circuit 20 is supplied to a synchronization circuit 102, and a clock generator
The control circuit 101 synchronizes the clock from the receiving signal RXD.
A clock synchronized with the start component is given to the clock component, whereby the control circuit 101
Generates a signal and serially reads the data portion of the received signal into shift register 104
No. On the other hand, the address comparison circuit 103 stores addresses “1” to “D”.
The address assigned to the terminal processor in advance is given.
, This address and the data read into the predetermined bit position of the shift register 104
Are compared by the address comparison circuit 103, and only when both match,
The data in the register 104 is transferred to the I / O buffer 105 and given to an external device.
Can be The control circuit 101 includes a counter that increments by a clock,
Generates a sequential control signal and transfers the data based on the received signal RXD to the I / O buffer.
105, then shift from I / O buffer 105
The data is fetched in parallel to the register 104 and the central processing unit 10
Is prepared as serial data in the shift register 104.
You. Then, this data is read out serially from the shift register 104.
Then, the signal is transmitted to the transmission line 20 as a transmission signal TXD. At this time, the address given to the received signal RXD is
The central processing unit 10 transmits the transmission signal TXD because it is transmitted by itself.
The transmission signal TXD is fetched because the address matches the address.
Thus, the transfer of data for one cycle by the half-duplex method is completed. Thus, the central processing unit 10 transmits data to the next terminal processing unit.
The transmission is performed, and by repeating this, the communication with each of the plurality of terminal processing devices 30 to 32 is performed.
Data transmission and reception are performed periodically, and multiplex transmission becomes possible. FIG. 6 shows an embodiment of the CIM in the DIO mode shown in FIG.
In the block diagram shown in more detail, the same reference numerals are used for the same or equivalent parts as in FIG.
In FIG. 6, reference numeral 301 denotes a clock synchronized with the reception signal RXD.
A synchronization circuit 302 for generating clocks 302 generates two-phase clocks φS and φM.
Counter, 303 is a counter for sequential control, 304 is a counter 303
305 is a sequence decoder that produces various control signals from the output of
, 306 are address decoders for input / output switching selection of the I / O buffer 105;
7 is a 4-bit comparator for address comparison, 308 is an error detection circuit, 310
Is a composite gate consisting of two AND gates and one NOR gate, 311 is an error
Exclusive OR gate for detection, AND gate 312 for data transmission,
313 and 314 are tri-state buffers. Note that the shift register 104
Is 25 bits (24 bits + 1 bit), and the I / O buffer 105 has 14 ports
(14 bits). First, when the DIO mode is selected, the A / D control circuit 106 does not operate, and the data contents of the shift register 104 at this time are shown in FIG.
The 6 bits from No. 0 to No. 5 are not used, and No. 6 to No. 19 are used.
Are allocated to the data DIO of the I / O buffer 105. And
Four bits from No. 20 to No. 23 are allocated to the address data ADDR,
.24 is assigned to the start bit. In addition, it is assigned to DIO data.
The number of bits stored is 14 because the I / O buffer 105 has 14 bits.
It is because of that. For this reason, in the CIM according to this embodiment,
, The maximum number of external loads that can be connected to the I / O buffer 105 is 14. The data transmission method according to this embodiment includes start-stop synchronization, bidirectional
Digital data is transmitted continuously using the NRZ (nonreturn to zero) method.
, And the transmission waveform is as shown in FIG.
. That is, data is transmitted from the CIM on the CCU side to the CIM on the LCU side.
Frame transmitted from the LCU to the CCU.
Is a transmission frame, both the reception frame and the transmission frame are 74 bits, and
Therefore, one frame has 148 bits. The reception frame and the transmission frame have the same frame configuration.
The first is a 25-bit "0", followed by a start-stop synchronization.
A start bit consisting of 1 bit “1” is provided, followed by 24 bits
Is transmitted in the form of an NRZ signal, and
The inverted data RXD (with bar) or TXD (with bar) of these data is transmitted.
It is supposed to be. It should be noted that this inverted data RXD (bar superscript) or TXD
The transmission of (bar superscript) is for transmission error checking. As described above, in this embodiment, the half-duplex system is used. Since multiplex transmission is performed, the first four bits of data RXD of the received frame are
, Address data ADD of the LCU with which the CCU will then make a call
R is attached as shown in FIG. 7, and in response to this, the transmission message transmitted from the LCU is sent.
The same address data ADDR is added to the first four bits of the frame data TXD.
Transmitted. The transmission of the transmission frame from the LCU is performed by the CCU.
Since the address is limited to the multiplied LCU, no address is added to the transmission data TXD
However, the CCU immediately determines which LCU the data is from
it can. Therefore, it is not always necessary to assign an address to the data TXD of the transmission frame.
And the first 4 bits of the data TXD are set to any address of the LCU such as (0000).
The data may not match the data. Here, returning to FIG. 6, the address of the CIM will be described. Already explained
As described above, in this embodiment, the CIM on the LCU side has four different bits.
Address is assigned, and based on this address, data in half-duplex format is used.
Multiplex transmission of data. Then, an input serving to assign this address to each CIM is provided.
4 inputs 2 whose forces are connected to a comparator 307⁰~ 2^ThreeAnd these
Data ADDR to be given to input₀~ ADDR₁Indicates the address of the CIM
Is determined. For example, to specify the address of the CIM as "10",
Dress data ADDR₀= 0, ADDR₁= 1, ADDR_Two= 0, ADDR_Three= 1,
And input 2⁰~ 2^Three(1010) may be input to the. Note that this
In the embodiment, data “0” is represented by the ground potential, and data “1” is represented by the power supply voltage Vcc.
Input, address 2 is input for address "10".⁰, 2^TwoTo ground and input 2
¹, 2^ThreeTo connect to the power supply become. In this embodiment, the address input 2⁰~ 2^ThreeIs address deco
The direction of the I / O buffer 105 is controlled by the output.
It is supposed to be. As a result, when the address is specified, the I / O buffer 10
5. It is determined whether any of the 14 terminals becomes a data output port.
. In this embodiment, the address directly corresponds to the number of output ports.
It is supposed to.   Therefore, if the address is defined as “10”, the 14 ends of the I / O buffer
Control so that 10 of the children are output ports and the remaining 4 are input ports
Is done. Although omitted in FIG. 6, the output of the address decoder 306 is
The power is also provided to the sequence decoder 304 of the control circuit 101, which
As described above, the operation mode of the CIM can be switched.
You. That is, in this embodiment, the CIM whose address is set to “0” is
CTM with address set between “1” and “D” in DIO mode
CIM with address set to either "E" or "F" is AD mode
, Respectively. Next, the functions of the control circuit 101 and the synchronization circuit 102 will be described.
In this embodiment, the start-stop synchronization method is employed as described above with reference to FIG.
Therefore, when data is transmitted for both received and transmitted frames,
25 bits of “0” are always inserted before the start bit, and then 1 bit of the start bit is inserted.
"1" data is inserted as the default (FIG. 8). Therefore, the synchronization circuit 301 exists at the beginning of the received frame. The rise of the start bit following the 25-bit “0” is detected, and the internal clock
Synchronization. Therefore, until the next received frame appears,
The operation is performed by an internal clock that is bit-synchronized with the clocking.
The counter 302 is a two-phase clock from the internal clock synchronized by the synchronization circuit 302.
Hook φ_SAnd φ_MTo produce This makes the clock φ_SAnd φ_MIs then entered
The phase is synchronized with the reception data RXD. The sequence counter 303 outputs the start bit
Receiving a signal indicating the rise detection timing, a specific count value, for example, a count
0, then the clock φ_SOr φ_MCounted by.
Therefore, the control procedure of the entire CIM can be determined by the count output, and
By checking the count value, the CIM operation at an arbitrary timing
You can know if it is in the tap. Therefore, the count output of the counter 303 is output to a sequence decoder.
304, and control signals necessary for the operation of the CIM, for example, RXMODO,
All control signals required internally such as TXMODE, READ, SHIFT
It is generated by the sequence decoder 304. In other words, this embodiment
Clock φ_S, Φ_MIs a sequence control method by
By decoding the output of the counter 303, all necessary controls can be performed.
It becomes. Next, the transmitted data RXD is data for the CIM.
Whether the call by transmitting the received frame from the CCU
The operation of determining whether or not the above is the case will be described. As already explained,
One input of the lator 307 is input 2⁰~ 2^ThreeGiven the address data from
And the other input has a shift Q of register 104₂₀Bit to Q_{twenty three}Data up to the bit
ing. The comparator 307 determines that both input data match.
Only when is the match signal MYADDR output. Therefore, the shift register 104
Received data RXD is input and its Q₂₀Bit to Q_{twenty three}Data up to the bit
The timing at which the address data (see FIG. 7) added to the head of the data RXD is stored.
The output signal MYADDR of the comparator 307 is checked by the
If YADDR is "1", the data RXD is addressed to itself and CCU
It turns out that the call from is to himself. Therefore, the error detection circuit 308 supplies the control signal COMPMODE,
The signal MYADDR is fetched at the predetermined timing described above and becomes “0”.
TNITIAL is generated when the sequence counter 3
03 is set to count 0, the operation of the entire CIM is restored, and the next data transmission is started.
Prepare to be entered. On the other hand, when the signal MYADDR is "1", error detection is performed.
Since no INITIAL is generated by the output circuit 308, the operation of the CIM
It continues according to the count value of the sequence counter 303 at that time.
It is. Next, the transmission error detecting operation will be described. In this embodiment,
As described in FIG. 8, the data transmission by the inverted double transmission system is adopted.
As a result, transmission errors can be detected. For this reason, the first Q of the shift register 104₀Bit and
Later Q_{twenty four}The data is supplied from the bit to the externship OR gate 311,
Output of the gate 311 is a signal ERROR (bar superscript) To the error detection circuit 308. The sequence decoder 304 receives the reception signal RX following the start bit.
During the transmission period of D and RXD (with bar superimposed) (FIG. 8), the control signal RXMODE is output.
To open the lower gate of the composite gate 310, thereby
Is input to the shift register 104 as a serial signal SI. At this time,
Since the data 310 includes a NOR gate, the data supplied from the transmission
The data is inverted and input to the shift register 104. Therefore, 24 bits following the start bit of the received frame (FIG. 8)
At the time when the minute data is input to the shift register 104, the shift register
104 Q₀Bit to Q_{twenty three}Inverted data of the received signal RXD
RXD (bar superscript) will be written. Next, as is apparent from FIG. 8, the reception signal RXD of 24 bits is transmitted.
After being sent, a 24-bit inverted signal RXD (bar superscript) is transmitted following it
Then, it is inverted by the composite gate 310 to become data RXD,
It starts to be input to the shift register 104 as the signal SI. As a result, Q of shift register 104₀Signal RXD (bar superscript)
At the timing when the first bit is inverted and input,
The inverted data of the first bit of the received signal RXD_{twenty four}Bi
The data of the second bit of the inverted signal RXD is₀Tag written in
In the imaging, the data of the second bit of the reception signal RXD is Q_{twenty four}Moved to a bit of
As a result, the inverted signal RXD is transmitted to the shift register 104 one bit at a time.
At each bit timing when data is actually written, the shift register 104
Q of_{twenty four}Bit and Q₀The bits of the reception signal RXD and the inversion signal RXD (bar superscript) The same bit data is always written correspondingly. As described above, the exclusive OR gate 311
The two inputs include the Q of shift register 104₀Bit and Q_{twenty four}Bit data
It is empowered. Therefore, during transmission of the reception signal RXD and the inversion signal RXD (bar superscript)
If no error occurs during the transmission of the inverted signal RXD (with bar superimposed)
The output of the exclusive OR gate 311 should always be "1". Accident
Then, with each corresponding bit of the reception signal RXD and its inverted signal RXD (bar superscript),
Must always be “1” and “0” inverted. As a result, the input of the gate 311
Always indicates a mismatch, and does not occur only if there is an error in transmission
It is. Therefore, the error detection circuit 308 transmits the inverted signal RXD (bar superscript).
During the 24 bits being sent, monitor the signal ERROR (bar superscript)
If the signal INITIAL is generated when the signal becomes "0" level,
Error detection operation is obtained. A method of handling a transmission error in such a data transmission system
As a formula, if a transmission error is detected, repair it and obtain the correct data.
However, in this embodiment, when a transmission error is detected,
At that point, cancels the data reception operation for that frame, and receives the data for the next frame.
In order to simplify the configuration. Next, the entire data transmission in the DIO mode of the embodiment of FIG.
The typical operation will be described with reference to the timing chart of FIG. φ_M, Φ_SIs counter 3
02, which is a two-phase clock output in the synchronization circuit 301
It is generated based on an internal clock by an oscillator. On the other hand, RESET (bar superscript) is supplied to this CIM from outside.
This is the same as the reset signal of a microcomputer, etc.
Is supplied for every CTM in the system.
When necessary, it is supplied from an external reset circuit to initialize the entire transmission system.
Perform the rise. When the initialization is completed, the sequence counter 303
0 and the clock φ_MBy step by step. And the count value
When it reaches 25, the IDLE signal and RXENA (bar superscript) signal are generated, and the CIM
In the idle state, sequential by the count value of the sequence counter 303
Control is stopped, and the tri-state buffer 313 is opened to change to a signal receivable state.
Become. At this time, after initialization, the sequence counter 303
Until the count value reaches 25, the signal is not ready to be received.
, For the start-stop synchronization by the synchronization circuit 301, and the reception signal RXD has 24 bits.
Therefore, it is necessary to provide at least a 25-bit "0" period. When entering the idle state, the sequence counter 302
Φ_S, Φ_M, But the sequence decoder 304 controls
The signal IDLE and INITIAL remain generated and the received signal is input.
It's a bear just waiting to run. Note that, as shown in FIG.
A 25-bit "0" is added to the head of the frame and the transmission frame. In this way, the system enters the idle state.₀With received signal
It is assumed that RXD is input. Then, at the head of this signal RXD, one bit
A start bit is attached. Therefore, this start bit is used for the synchronization circuit 301.
Detect and synchronize the bit of the internal clock. Therefore, after this, the data RXD, R until the transmission operation for one frame is completed is completed.
XD (with bar) and clock φ_MAnd φ_SSynchronization with the internal clock depends on the stability of the internal clock.
As a result, a start-stop synchronization function is obtained. When the start bit is detected, the sequence counter 303 counts down.
Output 0 (hereinafter, the output data of the counter 303 is denoted by S, for example,
In this case, it is set to S0).
The signal IDLE is stopped, and the control signal RXMODE is generated. In parallel with this
The shift register 104 receives a shift pulse SHIFT by a clock φ._MSynchronized with
Be paid. As a result, the received signal RXD of 48 bits following the start bit is inverted.
The inverted signal RXD (with bar superimposed) (FIG. 8) passes through the composite gate 310 from the transmission line 20.
While shifting one bit at a time into the shift register 104 as serial data
It is written. At this time, the first 24-bit reception signal RXD is supplied to the composite gate 31.
In the shift register 104 as data RXD (bar superscript) inverted by 0
Since the data is sequentially written serially, during the 24-bit period following the start bit,
When the sequence counter 303 reaches S24 from S1, the shift register
105 Q₀Bit to Q_{twenty three}Data in which the received signal RXD is inverted to the bits up to
RXD (bar superscript) will be written. Here, the clock φ of the next S25_MControl signal COMPMO at the rising edge of
DE (bar superscript) is output, and the error detection circuit 308 functions. And this state
Signal RXD (bar superscript) starts to be input, and as a result,
The data RXD obtained by inverting the signal RXD (with superscript bar) is
₀Serially written from bit. As a result, the data written to the shift register 104 in S1 to S24
Data RXD (superscript on the bar) indicates the Q of the shift register 104 from the first bit._{twenty four}Bi
Between the time when the sequence counter 303 goes from S25 to S48
, Sequentially overflowing one bit at a time. On the other hand, in parallel with this,_{twenty four}Through bit position
Therefore, the data RXD based on the inverted signal RXD (superscript bar) is sequentially transmitted from the first bit.
Is written serially, during which exclusive OR gate 311 and
The detection of the transmission error by the error detection circuit 308 is performed as described above.
Going on. Therefore, when the sequence counter 303 reaches S48, the sequence
Q of shift register 104₀Bit to Q_{twenty three}Up to the same bit as the received signal RXD
The same data RXD is written as it is. Therefore, the output signal of the comparator 307 is output at the timing of S48.
By checking MYADDR, the above-mentioned address is confirmed, and it is received now.
Whether the received data RXD is addressed to itself, that is, from the CCU at this time.
Is determined whether or not the call is addressed to oneself. The period when the sequence counter 303 is between S25 and S48
If a transmission error is detected during this time, or an address mismatch is detected, error detection is performed.
The output circuit 308 generates a control signal INITIAL at S48,
At this point, the sequence counter 303 is set to S0, and the state of 25 bits before idle is set.
And all the receiving operations for this received frame are canceled and the next signal
Prepare for input. Now, while the sequence counter 303 is in the state from S25 to S48, the transmission is performed.
No transmission error was detected and no address mismatch was detected When the error detection circuit 308 has reached INITIAL
When a signal is not generated, the sequence decoder
304 generates a control signal WRITESTB. As a result, at the time of S48, the INITIAL signal and the WRITE signal
Either of the ESTB signal is generated and transmission error and address mismatch do not occur.
If none of the above occur, the former, and either transmission errors or address mismatches
When one of them occurs, the latter is output. When the control signal WRTTESTB is output at the time of S48,
The data of the shift register 104 at that time is transferred to the I / O buffer 105 in parallel.
Written, and as a result, the data given from the CCU by the received data RXD.
From the output port of the I / O buffer 105 to any of the external loads 51 to 56.
Be paid. At this time, since the camera is operating in the DIO mode,
As described with reference to FIG.₆Bit to Q₁₉Up to 14 bits are data
RXD, and how many bits of the I / O buffer 10
It has already been explained that the output port 5 is determined by the address.
It is as stated. When the process reaches S48, the processing of the received frame is completed, and the next S is executed.
From 49, processing for a transmission frame is started (FIG. 8). First, what is from S49 to S72
Is not performed. This is for start-stop synchronization of the CIM on the CCU side.
Same purpose as the operation in the period set before IDLE in the processing of received frames
Is for At S73, the control signal PS is output from the sequence decoder 304.
As a result, the shift register 104 performs a parallel data reading operation,
External load 51 is applied to the input port of I / O buffer 105. To 56 are input in parallel. At this time, the number of bits of the data read is a 14-bit I / O buffer.
Out of the ports of the camera 105 used as the output port in the processing of the received frame.
This is the number of bits remaining after subtracting the number of bits. For example, as described above, this CIM ad
When the number of ports is set to 10, the number of output ports becomes 10,
Means that the input port is 4 bits. When writing parallel data to the shift register 104, a signal
Since one bit of the shift clock SHIFT is required together with the PS, the clock of S73 is required.
Lock φ_SAfter the signal SP rises, the clock φ of S74_SShifts synchronized to
The pulse SHIFT is supplied before the rise of the control signal TXMODE. At this time, as is clear from FIG. 8, the transmission data TXD
, A start bit is added, and an address is added to the first four bits of the data TXD.
Must be added. Therefore, although omitted in FIG. 6, the signal PS is generated.
Q of the shift register 104 only during the_{twenty four}Bits represent data "1"
Signal and Q₂₀Bit to Q_{twenty three}Input 2 in the bit part⁰~ 2^ThreeAddress from
Data is supplied. In this manner, start-stop synchronization is performed by the DUMMY state from S49 to S73.
After the necessary 25-bit data “0” transmission period is set,
The control signal TXMODE rises, thereby becoming a TX (transmission) state bearer. The generation of this signal TXMODE causes the upper gate of composite gate 310 to be turned off.
The gate is activated, and the AND gate 312 is activated. This
Q of shift register 104_{twenty four}Bit data, that is,
"1" is transmitted through AND gate 312 It is sent to the road 20. Then, the subsequent clock φ from S75_MOccurs in sync with
The contents of the shift register 104 are shifted one bit later by the shift clock SHIFT.
Shifted to the next step, Q_{twenty four}From the bit to the transmission line 20 through the AND gate 312
The transmission signal TX including the start bit of the transmission frame (FIG. 8)
D transmission is performed. On the other hand, in parallel with the data read from shift register 104,
And that Q_{twenty three}The data read from the bit cell passes through composite gate 310
It is inverted and supplied to the serial input of the shift register 104. As a result,
After S75, the Q of the shift register 104₀Bit to Q_{twenty three}Written by a bit
The transmitted data TXD is transmitted one bit at a time by the shift clock SHIFT.
The data is sent out to the transmission path 20, and is inverted and shifted as serial data SI.
Q of the register 104₀The data is sequentially written from the bit. Therefore, during the period when the control signal PS is generated, the shift register 10
Q of 4₀Bit to Q_{twenty three}All transmission data TXD written in bit cell is read
When completed, this Q₀Bit to Q_{twenty three}Bit cell transmitted up to then
Inverted data TXD (bar superscript) is stored instead of data TXD.
Become. Therefore, after reading of the transmission data TXD is completed,
Following this, inverted data TXD from the shift register 104 (bar superscript)
Of the transmission data TD as shown in FIG.
The data is transmitted to the transmission line 20 following the XD. When the process reaches S122, the Q of the shift register 104_{twenty three}Bit
La Q₀Inverted data up to the bit is controlled because the front reading is completed The signal TXMODE falls and the supply of the shift clock SHIFT is also stopped and transmitted.
End the bear. Then, the clock φ that follows S122_MControl signal INI
TIDL occurs, the sequence counter 303 is set to S0, and the CIM
It returns to the signal reception preparation state before the dollar (IDLE). Therefore, according to this embodiment, the start-stop synchronization, bidirectional, inverted double transmission system
In order to reliably perform half-duplex multiplex communication between the CCU and the CLU,
It is possible to obtain a CIM that has the DIO mode operation function required by the CU.
You. Next, the operation of the CIM according to the present embodiment in the AD mode will be described.
explain. As mentioned above, data should be exchanged with CCU via CIM
External loads 57 and 58 for outputting analog signals such as various sensors as electric devices.
(FIG. 2), and therefore, in the embodiment of the present invention, the A / D control circuit 106
, And also has a function of controlling the external A / D 40. Soshi
The operation mode of the CIM at this time is the AD mode. As described above, in this embodiment, the input 2⁰~ 2^Three
The operation mode is set according to the address data to be given to the
The address data corresponding to the AD mode includes “E” and “E” as shown in FIG.
F ". Therefore, the CIM according to this embodiment is added to the address “E” or “F”.
Once set, the functional block state is as shown in FIG. And this
The contents of the data stored in the shift register 104 when the settings are made as shown in FIG.
The 8 bits from No. 0 to No. 7 are externally negative via the A / D 40.
No.8 and No.9 2 bits for storing AD data taken from loads 57, 58, etc.
AD channel data storage 10 bits for DIO data from No. 10 to No. 19
It has become. The rest is the same as in the DIO mode. The AD channel data at this time is a multi-channel data.
This is data for channel designation when AD is used. In this embodiment, A /
Since D40 uses 4 channels, 2 bits are allocated.
It is. FIG. 11 is a block diagram showing the embodiment of FIG. 10 in more detail.
11, 320 is a shift register, 312 is a register, and 322 is
A gate 323 is an A / D control counter, and 324 is an A / D control signal generation circuit.
, 325 are A / D channel selection counters. The others are the places shown in FIG.
This is the same as described above. The shift register 320 is an 8-bit shift register and has an external A / D 40
Digital data (provided from external loads 57, 58, etc.)
A / D converted analog data) to enable parallel reading
And a counter 325 for specifying the channel of the A / D 40.
2 bit channel selection data received in parallel and read it serially
Out and supply it to the A / D 40. The register 321 has 32 bits, and the A / D 40 has 8 bits and 4 bits.
It's a channel, so it's an 8-bit 4-channel register
The data captured by the A / D 40 in 8 bits is used for each channel.
And housed in. The gate 322 also has 32 bits (8 bits) corresponding to the register 321.
, 4 channels), and Q of the shift register 104 for data transmission.₈Bit
And Q₉AD channel data read from bit cell Data (FIG. 7), selects one of the channels of register 321 and
The 8-bit data is transferred to the shift register Q₀Bit to Q₇AD cell in bit cell
It functions to write as data (FIG. 7). The counter 323 has a clock φ_MA / D system
Function to control the operation of the entire control circuit 106 sequentially and cyclically
do. A / D control signal generation circuit 324 decodes the output of counter 323.
Including various decoders and logic circuits necessary for the operation of the entire A / D control circuit 106.
It serves to generate control signals. Next, the operation of the entire A / D control circuit 106 will be described. This
In the embodiment, the sequence corresponds to each of the count outputs of the counter 323.
The control proceeds to the next step, the number of steps is 27, and the count output is 0 (this is called S0).
) To the count output 26 (this is called S6), one cycle of control is completed.
Then, data for one channel of the A / D 40 is taken into the register 321. First, when control of one cycle starts, the channel is controlled by the signal INC.
The counter 325 for selecting the counter is incremented.
The output data is (0,0) → (0,1) → (1,0) →
(1,1) → (0,0). The output data of the counter 325 is stored in the shift register 320 at the top 2
It is written in parallel to the bit position and then read out as serial data ADSI.
It is supplied to the A / D 40. In parallel with this, the output data of the counter 325 is
Is also supplied to a register 32 via a decoder (not shown).
1. Select 8 bits of the corresponding channel. Subsequently, A / D 40 is a channel input as serial data ADSI.
Analog input channel corresponding to the channel selection data 8 bits after converting the analog data to digital data
Is supplied to the serial input of the shift register 320 as the serial data ADSO.
Are stored in the shift register 320. Thereafter, the 8-bit digital data stored in shift register 320 is read.
The data AD that has undergone the total conversion is read out in parallel at a predetermined timing, and
A predetermined channel of the register 321 selected in advance by the output data of the
The control is transferred to the 8 bits of the channel, and the control operation of one cycle is completed. Thus, for example, the output data of the counter 325 becomes (0, 0).
The analog data of channel 0 of the A / D 40 is digitized.
After being stored in the 8 bits of channel 0 of the register 321, the counter 32
3 is reset to S0, the operation proceeds to the next cycle, and the counter 325 sets the
And the output data becomes (0, 1).
The log data is digitized and stored in the 8-bit channel 1 of the register 321.
Is accepted. Therefore, according to this embodiment, the A / D control circuit 106
The data fetch operation from 40 is performed by the sequence counter 303 and the sequence decoder
The processing is performed independently of the data transmission processing by the timing 304,
The data of each channel is refreshed once every four cycles of the AD control operation.
And the register 321 is input to four channels of the A / D 40.
Analog data is converted to 8-bit digital data for each channel.
Will always be available. Therefore, the received signal RXD is now input from the transmission path, and is attached to it.
It is assumed that the address data stored is for this CIM. Note that this
The address data at the time is "E" as described above. Or "F". Then, at the time when the input of the received frame is completed (S48 in FIG. 9).
The data reformatted in the shift register 104 is the same as the AD mode shown in FIG.
Therefore, the Q of the shift register 104₈Bit and Q₉Two bits
AD data is stored. So, this AD channel
The data is read at the time when the signal WRITESTB is generated in S48.
One of the four channels of the gate 322 is selected. As a result, when the signals PS and SHIFT are generated in S73 (FIG. 9)
Thus, of the four channels of the register 321, Q of the shift register 104₈,
Q₉Only the AD data of the channel selected by the two bits of
Q of shift register 104₀Bit to Q₇Written to the 8-bit part up to the bit
You. Then, this is included in the transmission signal TXD in the transmission state after S74, and
Will be transmitted. In this embodiment, the reception processing of the reception signal RXD is performed as described above.
Irrespective of the process and the subsequent transmission processing of the transmission signal TXD,
Contains AD data. Therefore, in this embodiment,
Even if a reception signal RXD addressed to itself appears at the time of the
Transmission signal TXD, and the transmission processing is affected by the operation of the A / D 40.
The transmission rate is reduced due to the time required for the A / D conversion operation without being affected.
There is no danger of being lost. In this embodiment, when the CIM is formed into an LSI, the A / D 40
Externally, to reduce the cost of general-purpose CIM
. That is, as described with reference to FIG. 2, in this embodiment, one type
CIM of LCU30-31 as CIM of LCU30-31 Also used as CIM of LCU32 or CIM33 of CCU10
I can do it. However, at this time, if the A / D is built in, the CIMs 30, 31,
When it is used as 33, it becomes useless and, in general, the centralized wiring of automobiles
When applied to the system, the number used as the CIM 32 is
Since the number of IMs 30, 31, and 33 is smaller than the number used,
There is not much merit by incorporating / D. Therefore, external A / D
That is. However, due to the external connection of the A / D, as shown in FIG.
, Four connection terminals are required for the external A / D 40.
There is a possibility that the number of terminal pins may increase. Therefore, in one embodiment of the present invention, CI
When M is set to the AD mode, 14 ports of the I / O buffer 105
Four of them are switched as connection terminals for the A / D 40. That is, in the embodiment of the present invention, the I / O buffer 105 has 14 ports.
These are, as is clear from FIG. 7, the CIM is set to the DIO mode.
When set, all ports may be used as input / output ports.
At the time of loading, only 10 ports are used at the maximum, and No. 11 to No. shown in FIG.
Fourteen 14 ports are not used for inputting / outputting DIO data and are left. Therefore, the remaining four ports are switched in the AD mode, and are switched to the A / D 40.
If it is used as a terminal pin, the number of terminal pins will not increase even if the A / D is connected externally.
In addition, the versatility is increased when implementing the LSI, and the cost can be reduced. Next, the operation of the CIM according to this embodiment in the MPU mode will be described.
Will be explained. As is clear from FIG. 4, the CIM according to this embodiment is To switch to MPU mode, the address ADDR₀~ ADDR_ThreeAd by
Address setting to “0”, that is, input 2⁰~ 2^ThreeAre kept at the ground potential, and (0000) and
Do it. This MPU mode means that the MPU 33 is used as the CIM 33 shown in FIG.
Used in DIO mode and AD mode to give necessary functions
When the data is given to the microcomputer of CCU10,
Transmit to any of the CIMs 30-31 of a given LCU and return
When receiving the transmitted data, a message is sent to transfer the data to the microcomputer.
A transmission interface operation is performed. In the above description, as described with reference to FIG.
The explanation was mainly from the point of view of the CIM on the LCU side.
A frame for transmitting data to the U side CIM is a received frame, and conversely, from the LCU side
Although the frame to be transmitted to the CCU side has been used as the transmission frame,
A transmission frame is a frame that sends data as seen from the IM, and the data is received by itself.
The frame at the time of receiving is described as a received frame. Therefore, after that, the transmission frame in a certain CIM, for example, CIM33
Is a received frame in another CIM, for example, CIM30, while
Is a received frame in the CIM 33. FIG. 12 shows an example in which an address “0” is set in the CIM according to the embodiment of the present invention.
Rough functional blocks when controlled to operate in CPU mode
The figure shows the state of the CIM 33 in FIG. As described above, in this embodiment, the setting of the address
CIM of the same configuration has three modes, namely, CPU mode, A device that can function in either DIO mode or AD mode
Therefore, the state in FIG. 12 represents a functional block in the CPU mode.
Therefore, it is noted that the configuration of the CIM according to this embodiment is different from that of FIG.
It does not represent. As is apparent from FIG. 12, in the CPU mode, the I / O buffer
105 (FIG. 3) and A / D 40 have their functions stopped, and a 14-bit
Connected by data bus. At this time, the terminal pins are connected to the input / output of the I / O buffer 105.
Used in common with the output port, so that there is no increase or decrease in terminal pins
Needless to say. Then, 8 bits of the 14-bit (14) input / output
Are for data, and the remaining 6 bits are for control signals. In this CPU mode, the data in the shift register 104
As shown in FIG.₀To Q_{twenty three}Up to 24 bits are all MPU data
The microcomputer uses an 8-bit data bus to control the shift register 1
04 is accessed. On the other hand, the control circuit 101 receives a control signal from the microcomputer and receives a shift signal.
Q of the register 104₀~ Q_{twenty three}Data from microcomputer is stored in all bits of
At the same time, the transmission operation is started, and the time t when this data is stored is finished._xFrom FIG. 13
As shown, transmission of a transmission frame is started. When the transmission frame is transmitted from the CIM 33 in this manner,
One of the CIMs 30 to 32 on the LCU side responds, and the CIM continues to transmit.
At time t_xTime when one frame (148 bits) transmission time has elapsed since
t_x, The shift register 104 calls from the CIM 33
The data transmitted from the CIM (one of the CIMs 30 to 32) is stored and terminated.
Will be. The control circuit 101 of the CIM 33 determines at this time t_yTo Generates an interrupt request IRQ (with bar superimposed), and the microcomputer responds accordingly.
The data in the register 104 is read, and the data transmission for one siggle is completed. In addition,
At this time, the data transfer operation between the CIMs is performed in accordance with the DI described with reference to FIG.
Needless to say, this is the same as in the I mode. Next, FIG. 14 shows a case where the CIM 33 is set, that is, the MPU mode is set.
Is a functional block diagram showing one embodiment of the CIM, which is required in the MPU mode.
Only the prog corresponding to the function is shown.
An 8-bit switch, 404 is an 8-bit data latch, and the others are shown in FIG.
This is the same as the embodiment. In this MPU mode, Q of shift register 104₀Bit to Q_Two
ThreeUp to bits are connected to the microcomputer data bus via 8-bit input / output pins.
, Exchange data with each other.
04 Q₀~ Q_{twenty three}Bits of three groups, Q₀~ Q₇(Reg3), Q₈~ Q₁₅
(Reg2), Q₁₆~ Q_{twenty three}(Reg1)
The next access is. For this reason, the 8-bit switches 400 and 402 are used to
Switch by the combination of register select signals RS0 and RS1 given from the
Control signals READ1 to 3 of the switch 400 and control signals STB1 to STB1 of the switch 402.
3 and input / output terminal pins 7 to 14 in order from Reg1 to Reg2, and then to Reg3.
Connect to microcomputer and shift register by accessing 8 bits 3 times
Data is exchanged with the data 104. In this case, data from the microcomputer to the shift register 104 is stored.
When writing data, the data read time from the microcomputer and the In order to compensate for the difference from the time for writing data to the shift register 104,
Switch 404 is provided so that data from the microcomputer is temporarily latched and then written.
It has become. In the MPU mode, 24-bit data at the time of data reception is used.
The collation of the address added to the head of the data is not performed in the CIM 33.
. Therefore, input 2⁰~ 2^ThreeIs given to the address decoder 306.
Used only to set this CIM to MPU mode by
The comparator 307 does not operate. Next, in this MPU mode, the input / output terminal pins 1-6 of the CIM 33
Is a control signal transmission path to the microcomputer, which allows the microcomputer to
The clock E and the chip select signal CS (on the bar) are sent to the CIM control circuit 101.
), The read / write signal RW, and the register select signals RS0, R
S1 is provided, while an interrupt request signal IRQ (superscript on the bar) is generated from this CIM.
Output to the icon. FIGS. 15 and 16 show an embodiment of a processing circuit for these signals.
Is omitted, but is included in a part of the control circuit 101, and first, the clock E is
It is supplied to the circuit shown in FIG. 15 and is processed together with the internal clock CLOCK to generate a two-phase clock.
The locks EH and EL are generated. And these clocks EH, EL and microcomputer
RW, CS (bar superscript), RS0, and RS1 are processed by the circuit of FIG.
Then, signals STB0 to STB3 and RESD0 to STSD1 are generated. The signal MPU is CI
This signal is "1" when M is set to the MPU mode. Further, the timing of signal processing by the circuit of FIG. 16 is shown.
17 and FIG. 18, among these figures, FIG. 17 shows signals READ0 to READ0. 3, and FIG. 18 shows the generation timing of the signals STB0 to STB3.
Each is shown. In these figures, any of signals RED0 to RED3 is generated.
Is generated, and which of the signals STB0 to STB3 is generated depends on the signals RS0 and R0.
The shift register 1 is determined by the combination of S1 and S1.
04, the groups Reg1, Reg2, Reg3 are selected. By the way, of these signals READ0 to STB3 and STB0 to STB3,
The signals READ0 and STB0 are used to select the group of the shift register 104 described above.
Are not used, but are used to generate an interrupt request signal IRQ (bar superscript) described later.
Therefore, FIG. 19 shows a selection state by the signals RS0 and RS1. FIG. 20 is a circuit diagram of a circuit for generating an interrupt request signal TRQ (with superscript bar).
In the embodiment, the CIM 33 is also included in the control circuit 101 of FIG.
Occurs when reception is completed and storage of received data in shift register 104 is completed.
The signal IRQ is generated by the signal WRITE STB (FIG. 9) and the signal READ0.
Generated circuit and connected to microcomputer data bus by input / output terminal pins 7-14
Signal from any one of the data lines D0 to D7, for example, the data line D0.
It is composed of DATA and a circuit for generating a signal MASK1 from the signal STB0.
Is shown in the timing charts of FIGS. 21 and 22. Of these figures, FIG. 18 shows that the signal DATA is the generation of STB0.
FIG. 19 shows the operation when the signal DATA is "1".
The operation of the circuit shown in FIG. 20 is shown.
, The flip-flop to which the signals DATA and STB0 are supplied is referred to as Reg0.
. Therefore, in the circuit of FIG. If "1" is written to Reg0, the interrupt request signal IRQ (bar superscript) is masked.
Will be multiplied. Next, the embodiment of FIG. 14, that is, one embodiment of the CIM according to the present invention is M
The overall operation of data transmission in the state set in the PU mode is shown in FIG.
This will be described with reference to a mining chart. In the embodiment of the present invention, all of the CIMs 30 to 33 operate in the same manner.
The operation is controlled by the count output of the sequence counter 303.
If the count output of the sequence counter 303 is set to a predetermined value,
The ability to transpose to the state has already been described with reference to FIGS.
This is true no matter what mode the CIM is set to.
Absent. By the way, as shown in FIG. 14, CIM3 set to MPU mode
3 are combined to transmit data, as is apparent from FIG.
CIMs 30 to 32 set in the mode or the AD mode. And
When the CIM is set in the DIO mode and the AD mode,
As explained in the above, when data from another CIM is received,
It transmits its own data and performs data transfer operation for one frame.
In other words, it only performs passive operations. On the other hand, the MPU mode is set as in CIM33.
When data from the microcomputer is written into the shift register 104,
Initiate data transmission, so to speak, requires an action that is athletic. Therefore, this embodiment
In order to start the active data transmission, the group of the shift register 104
The signal STB3 among the signals STB1-3 for selection is used.
. This is because the transmission to the shift register 104 by the microcomputer is performed. The writing of the communication data is performed in the order of Reg1, Reg2, Reg3.
When the signal STB3 is generated, data from the microcomputer to the shift register 104 is output.
Data has just been written, and the shift register 104 contains all the data to be transmitted this time.
This is because they are stored. Therefore, returning to FIG. 23, the CCU 10 (FIG. 2)
It is assumed that data to be transmitted to one of the LCUs is prepared in the icon. so
Then, the microcomputer uses the input / output terminal pins 1 to 6 to output a signal CS (with a bar),
RW, RS0, and RS1 are supplied to the control circuit 101 in the CIM 33, and FIG.
Then, the signals STB0 to STB3 are generated as described with reference to FIG.
The data of 8 bits are sequentially transferred from the bus to Reg1 and Re of the shift register 104, respectively.
g2, Reg3. On the other hand, control circuit 101 catches the generation of signal STB3, and
"49" is loaded into the can counter 303. Sequence by this signal STB3
FIG. 24 shows an embodiment of a circuit for setting the output data of the counter 303 to "49".
FIG. 25 is a timing chart showing the operation of this circuit. When the sequence counter 303 is set to S49 in this way,
t_xThe processing of the transmission frame starts in (FIG. 13). From S49 to S122
Is substantially the same as that in the case of the DIO mode described with reference to FIG.
In this MPU mode, data to be transmitted is already written in the shift register 104.
No operation is performed between S49 and S73.
04 Q_{twenty four}The point that only "1" for the start bit is written in DIO mode
It is just different from the time. When the signal reaches S122, a signal INITIAL is generated. Thereafter, the apparatus enters an idle state including the minimum time from S0 to S24. That is, M
In PU mode, unlike in DIO mode, data is received from another CIM.
Instead of waiting for data to be written, write data from the microcomputer to the shift register 104.
Is completed, the data 49 is forcibly loaded into the sequence counter 303, and
Thus, the processing of the transmission frame is automatically started. Thus, transmission of a transmission frame from the CIM 33 of the CCU 10 starts.
Then, as already described with reference to FIG. 9, the transmission data TXD is
The received data is received as RXD by 0 to 32, and the address of
Return data is transmitted by the matching CIM.
The CIM 33 receives the received data RXD. The processing of the received frame at this time is also performed in the case of the DIO mode in FIG.
The difference is that the MPU mode does not check the address match state.
It just works. Then, from S0 to S48, the received data is stored in the shift register 104.
If the communication data has been stored and no error is detected, the process proceeds to S48.
When signal WRITESTB rises due to clock φS, this causes
As described in the above, the interrupt request signal IRQ (bar superscript) is generated and the subsequent clock
The signal INITIAL is generated by φM, and this CIM 33 enters the idle state.
And the idle state is maintained until the next signal STB3 is generated. When interrupt request signal IRQ (bar superscript) is generated in this way, CCU
The microcomputer in 10 jumps to the interrupt processing routine by this signal IRQ (bar superscript).
Fetches received data from the shift register 104. At this time
The data is taken in from the shift register 104 using the switch 400,
15 and FIG. READ1 to READ3 are sequentially supplied, and are shifted through 8-bit data buses D0 to D7.
Are performed in the order of Reg1, Reg2, Reg3 of the register 104.
This is as described above. In this embodiment, as described with reference to FIG.
The signal IRQ (with bar) is configured to be maskable, and the microcomputer of CCU10 is
By writing "1" in g0 (FIG. 20), the signal IRQ (bar superscript)
Can be master. Therefore, as shown in FIG. 23, the point in time t when the signal STB3 is generated._xSignal before
The data bus D0 is set to “1” in accordance with the time of occurrence of STB0 (lower left of FIG. 23).
In this case, the signal MASK becomes “1” and then the signal WRITE STB is generated.
At this point, the interrupt request signal IRQ (with bar superimposed) is not supplied to the microcomputer.
The microcomputer can give priority to other processing during a predetermined period if necessary.
Wear. It should be noted that the release of the mask is, as is apparent from FIG. 20, the generation of the signal STB0.
It is sufficient to set the data bus D0 to "0" at the time of birth and write "0" to Reg0. On the other hand, the microcomputer of the CCU 10 has a
When the disk is performing a screening, the signal IRQ shown in FIG. 20 is checked and it becomes "1".
If it is, it means that data reception has been completed.
The data is fetched, and if it is "0", the reception of data is completed.
It should be noted that the signal IRQ (with superscript bar) is a signal RQ generated when data is taken in.
The release by EAD0 is apparent from FIG. Therefore, according to this embodiment, the microcomputer of the CCU transmits the data to the CIM.
33, the process can proceed to another processing operation.
Time is not required, and a system that fully utilizes the processing capacity can be created.
, And at this time, data reception of the CIM 33 Is completed, the mask is activated for other processing operations with higher priority.
And there is no possibility that the processing operation having a higher priority is interrupted.
I can do it. Here, as shown in FIG. 2, the CIM 33 in the MPU mode and the DIO
Data in combination with the CIM 30-32 set in the mode (or AD mode).
FIG. 26 shows the data transmission operation in a state transition diagram. [0156] According to the present invention,Communication circuitIncluding registers and I / O buffers
BecauseAs a result, the LSI modulehandIt is not only easy to make chips
After storing the data in the register once, move the data to the I / O buffer,
Data can be provided to external loads, during which time data can be
Check possible input, so wrong data is suddenly output to external load
There is no danger that it will always be high even when the nozzle level is high in a car.
Reliability can be maintained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing an example of an integrated wiring system in a vehicle. FIG. 2 is a block diagram illustrating an example of a data transmission method. FIG. 3 is a schematic block diagram showing one embodiment of a communication processing circuit according to the present invention as a basic functional configuration. FIG. 4 is an explanatory diagram of operation mode switching by an address. FIG. 5 is a functional block diagram showing an embodiment of the present invention in a DIO mode. FIG. 6 is a block diagram illustrating one embodiment of the present invention in DIO mode in more detail. FIG. 7 is an explanatory diagram showing one embodiment of data contents in the present invention. FIG. 8 is an explanatory diagram showing one embodiment of a transmission waveform in the present invention. FIG. 9 is a timing chart for explaining the operation of one embodiment of the present invention in the DIO mode. FIG. 10 is a functional block diagram showing an embodiment of the present invention in an AD mode. FIG. 11 is a block diagram showing one embodiment of the present invention in the AD mode in further detail. FIG. 12 is a functional block diagram showing one embodiment of the present invention in the MPU mode. FIG. 13 is an explanatory diagram showing one embodiment of a transmission waveform in the MPU mode of the present invention. FIG. 14 is a block diagram showing an embodiment of the present invention in the MPU mode in further detail. FIG. 15 is a block diagram showing one embodiment of a signal processing circuit according to the present invention. FIG. 16 is a block diagram showing one embodiment of a signal processing circuit according to the present invention. FIG. 17 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 18 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 19 is an explanatory diagram showing a selecting operation by a register select signal in the present invention. FIG. 20 is a block diagram showing an embodiment of an interrupt request signal generation circuit according to the present invention. FIG. 21 is a timing chart for explaining the operation of an embodiment of an interrupt request signal generation circuit according to the present invention. FIG. 22 is a timing chart for explaining the operation of an embodiment of an interrupt request signal generation circuit according to the present invention. FIG. 23 is a timing chart for explaining an operation in the MPU mode in one embodiment of the present invention. FIG. 24 is a block diagram showing one embodiment of a circuit for setting a counter. FIG. 25 is a timing chart for explaining the operation of one embodiment of a circuit for setting a counter. FIG. 26 is a state transition diagram illustrating a data transmission operation by a combination of a CPU mode and a DIO mode in one embodiment of the present invention. DESCRIPTION OF SYMBOLS 10 Central processing unit 20 Signal transmission path 30 to 32 Terminal processing unit 33 Communication control unit 40 A / D (analog-digital converter) 51 to 58 External load 101 Control circuit 104 Shift register 105 I / O buffer 106 A / D control circuit 107 Clock generator 301 Synchronous circuit 302 Counter 303 Sequence counter 304 Sequence decoder 305 Abnormality detector 306 Address decoder 307 Comparator 308 Error detection circuit 310 Complex gate 311 Exclusive OR gate 312 AND gate 320 Shift register 321 Register 322 Gate 323 Counter 324 A / D control signal generation circuit 325 Counter

Claims (1)

[Claims] 1. A communication control computer for controlling transmission and reception of data to and from the terminal processing device in accordance with the communication control program; and a communication control computer connected to the communication control computer for temporarily receiving data from the terminal processing device and transmitting data to the terminal processing device. Both to store
A central processing unit including a first communication processing circuit having a single register common to data; receiving data from the first communication processing circuit; and a state of an external load connected to the terminal processing device. A second communication processing circuit including one register common to both data for temporarily storing data to be indicated and an I / O buffer connected between the register and the external load; and the first communication processing. A data transmission system for a vehicle, comprising a communication line connecting a circuit and a second communication processing circuit so that data can be transmitted. 2. 2. The communication control computer according to claim 1, wherein when the reception data from the terminal processing device is established in a register of the first communication processing circuit, the communication control computer stores the data in an attached storage device. Characteristic automotive data transmission system. 3. 2. The communication control computer according to claim 1, wherein the communication control computer transmits data to the terminal processing device in a programmed order, and the terminal processing device that has received the transmission data transmits an external device connected to the terminal processing device. A data transmission system for a vehicle, wherein data indicating a load state is returned to the communication control computer. 4. In Claim 1, the second communication processing circuit stores its own address, compares the address of communication data with an address present on the communication line with its own address, and finds a match. Only the terminal processing device receives the communication data, and the second communication processing circuit of the terminal processing device that has received the communication data transmits data indicating a state of an external load connected to the terminal processing device to the communication line. A data transmission system for an automobile, wherein the data is transmitted back to the first communication processing circuit via the first communication processing circuit. 5. The vehicle data transmission system according to any one of claims 1 to 4, wherein the communication data is formed as one frame in which address data is followed by transmission data and reception data. 6. A communication control computer that controls data transmission and reception with the terminal processing device according to the communication control program, and is connected to the communication control computer, and receives data from the terminal processing device and transmits data to the terminal processing device. A central processing unit having a first communication processing circuit having a register for temporarily storing the data, receiving data from the first communication processing circuit, and data indicating a state of an external load connected to the terminal processing device; In a system, comprising: a second communication processing circuit having a register for temporarily storing data; and a communication line connected to the first communication processing circuit and the second communication processing circuit so that data can be transmitted. The processing circuit includes one register common to transmission / reception data, and an I / O connected between the register in the second communication processing circuit and the external load.
A buffer, an address comparator for comparing address data temporarily stored in a predetermined bit of the register with known address data, and a timing for latching communication data to the register in synchronization with a clock generated in a predetermined cycle. And a control circuit for controlling the timing of transferring communication data to the I / O buffer. The register temporarily stores encoded communication data, and the I / O buffer stores a known address. A data transmission system for a vehicle, wherein when data matches address data temporarily stored in a register, communication data following the address data is received from the register. 7. 7. The I / O buffer according to claim 6, wherein the I / O buffer has a function of outputting communication data stored in the register to an external load, and a function of inputting data from an external load to the register. An automotive data transmission system characterized by the following. 8. The vehicle data transmission system according to claim 1, wherein the register and the I / O buffer are built in the same chip as an LSI module. 9. The vehicle according to claim 1, wherein writing of communication data from the register to the I / O buffer is performed after confirming that there is no transmission error and no address mismatch. Data transmission system.