JPH0451850B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of the configuration of an example (Fig. 2, Fig. 3) (b) Explanation of the operation of one embodiment (Fig. 4, Fig. 5, Fig. 6, Fig. 7) (c) Explanation of another embodiment Effects of the Invention [Summary] In a command preemption control method for a magnetic tape device that is equipped with a buffer capable of storing a plurality of commands given from a higher level and that preempts commands, the present invention detects that the magnetic tape has reached the vicinity of the end area, and The number of preemptive write instructions that can be stored in the buffer is reduced so that all preemptive write instructions loaded into the buffer can be executed on the magnetic tape.

[Industrial application field]

The present invention relates to an instruction prefetch control method and apparatus for prefetching instructions from a higher level into the buffer in a magnetic tape device having a buffer capable of storing a plurality of instructions.

Magnetic tape devices are widely used as external storage devices for computers, and in recent years have been used particularly for backing up other external storage devices such as magnetic disk devices.

In such a magnetic tape device, as shown in FIG. 8, a tape drive unit 1 includes a magnetic head for writing and reading data on the magnetic tape, and a magnetic tape drive unit for driving the magnetic tape.
and a control unit CT that controls this based on instructions from a host controller.

In recent years, a buffer BF has been installed within this control unit CT,
A system has been developed that performs command prefetch control that preempts commands and data from the host controller, stores them in the buffer BF, and causes the tape drive section 1 to sequentially execute the commands and data in the buffer BF, and has been put into practical use. ing.

Such a magnetic tape device is called a buffered magnetic tape device, and can operate the tape drive unit 1 asynchronously in response to commands from the host controller, so the host controller side can operate the tape drive unit 1 in response to one command. Since commands can be issued continuously without having to wait for completion, and the tape drive section 1 can also perform operations continuously without waiting for commands from the host controller, processing efficiency can be improved, especially in streaming mode. Operational efficiency can be improved.

[Conventional technology]

In order to have such a buffer BF and preempt instructions, the buffer BF is composed of an instruction buffer that can store multiple instructions and a data buffer that can store multiple data. 32 instructions, maximum for data buffer
It is designed to be able to store 256KBytes of data, allowing for prefetch instructions and data to be increased.

On the other hand, as shown in FIG. 9A, the magnetic tape 16 does not have an infinite length but a finite length, so at the end there is an EOT
(END OF TAPE) marker is attached,
After EOT is detected, it can only be used for about 3m.

Therefore, in write-based processing, if the prefetch command/data is 3 m or more when EOT is detected,
It becomes impossible to write this onto the magnetic tape 16,
Some kind of countermeasure is required.

Conventionally, this is why EOT, the end of magnetic tape,
Before detecting the tape end near signal EWA,
For example, this occurred about 20 m before EOT, and as a result, the amount of data that can be stored in the buffer BF (number of data bytes) was reduced, as shown in FIG. 9B. For example, for a data buffer that can store up to 256 KB of data as shown in Figure 9B,
Until the amount of data accumulated in the data buffer becomes 128KByte or less, acceptance of write data from the host controller is not permitted, thereby preventing such writing failure.

[Problem that the invention seeks to solve]

In such conventional technology, the number of prefetched data bytes of write data is limited for write-related instructions to prevent write failure, but generally write-related instructions do not contain write data such as erase or write tape mark. There are also commands that are not accompanied.

Therefore, according to the prior art, it is possible to prevent write-related commands accompanied by write data from being unable to write, but no restrictions are applied to erase or write tape marks that are not accompanied by write data. ,
There was a problem that all write-related commands could not be executed within the range that could be written after EOT.

In view of the above problems, the present invention provides an instruction preemption control method and apparatus for a magnetic tape device, which limits write instructions that do not involve write data and allows all preempted write instructions to be executed. The purpose is to provide

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the present invention, in a magnetic tape device having the aforementioned buffer BF and capable of prefetching instructions, the number of write instructions that can be stored in the instruction buffer is determined in response to an EWA signal indicating that the vicinity of the end area of the magnetic tape has been detected. It is something that decreases.

For example, if the number of write instructions that can be accumulated in the instruction buffer is 32, then the number of write instructions that can be accumulated in the instruction buffer is 4, as shown by the solid line in Figure 1.
be limited to.

Alternatively, the number of write instructions that can be accumulated may be gradually reduced as indicated by the dotted line in FIG.

[Effect]

In the present invention, in order to limit the number of write instructions that can be stored, erase without write data,
Since write-related commands such as write tape marks are also restricted, all write-related commands can be executed on the magnetic tape, and inability to process write-related commands can be prevented.

〔Example〕

(a) Description of configuration of one embodiment FIG. 2 is an overall configuration diagram for explaining one embodiment of the present invention.

In the figure, the same components as those shown in FIG. reel) 11 and supply reel (file reel) 1
A magnetic tape 16 is placed between the tension arm 1
5 roller 15a, the magnetic head 14, and the idler 13 to reach the take-up reel 11, and on both sides of the magnetic head 14 there are guides 17a,
17b.

On the other hand, the take-up reel 11 and the supply reel 12 are rotationally driven by drive motors 10a and 10b, respectively, and rotary encoders 18a and 18b are provided on the drive motors 10a and 10b to detect the amount of rotation of the drive motors 10a and 10b. I'm trying to make it possible. The idler 13 is also provided with a rotary encoder 19a, which enables monitoring of the actual tape running position, while the tension arm 15 is provided with a tension detector 19b, which detects tape tension. It is possible.

2 is a drive control unit, which executes commands and commands to be described later.
It performs tape running drive and head writing or reading drive according to commands and data from the data prefetch control section, and monitors the running state by receiving outputs from each rotary encoder 18a, 18b, and 19a, and also uses a tension detector. The tension is monitored from the output of the magnetic head 19b, and both drive motors 10a and 10b are controlled via drive circuits 20 and 21 to drive the tape to run while keeping the tape tension constant, and write data is given to the magnetic head 14 to perform writing. It also receives read data from the magnetic head 14.

3 is an instruction/data prefetch control unit that receives write or read instructions and write data from the host controller, stores them,
If it is a write-related command, it sends a write command and write data to the drive control unit 2, causing it to perform a write operation, and if it ends normally, it sends the next block write command and write data, and if it does not end normally, it causes the drive control unit 2 to perform a write retry operation. It is.

The command/data prefetch control section 3 has a command buffer and a data buffer to be described later, and is an adapter that operates as a magnetic tape device for the host controller and as a host controller for the drive control section 2.

FIG. 3 is a block diagram of the main part in the configuration of FIG. 2, that is, the instruction/data prefetch control section 3.

In the figure, 30 is a microprocessor (hereinafter referred to as
It controls the reception of commands and data from the host controller and the transmission of data and status according to the microprogram in the program memory described later, and also controls the transmission of commands and data to the drive control unit 2. 31a is a program memory that stores programs to be executed by the MPU 30; 31b is a random access memory (hereinafter referred to as It stores various data, instructions, and parameters necessary for the processing of the MPU 30, and is an instruction buffer area.
It has a CBA, an instruction buffer management area CA, and a data buffer management area DA.

The instruction buffer area CBA stores instructions from the host controller, as well as the addresses and byte counts in the data buffer of data transferred by the instructions, and the instruction buffer management area CA stores instructions that are stored in the instruction buffer area CBA but have not yet been executed. The instruction memory number CN, which is the number of instructions that are not stored, and the instruction storage area number (possible number of instructions) AN, which indicates the number of write-related instructions that can be stored in the instruction buffer area CBA, are stored. Buffer capacity indicating the free space in units (in units of 1KByte), Buffer address indicating the start address of the buffer when transferring data to write to the data buffer, and Maximum block indicating the maximum length of the data block to be processed. The length is stored.

32a is a drive interface circuit for exchanging control signals etc. with the drive control unit 2; 32b is a host interface circuit for exchanging control signals etc. with the host controller. thing, 3
Reference numeral 3 denotes a data transfer control circuit, which controls a data buffer to be described later to control data transfer between the host controller or the drive control section 2, and issues a data transfer request signal to the host controller and also controls the drive control section 2. It controls data transfer in response to a data transfer request signal from the data buffer, and includes a store address counter SAC to the data buffer, a load address counter LAC from the data buffer, and a byte counter BC at the time of loading.

34 is a data buffer, which is controlled by the data transfer control circuit 33, stores write data from the host controller and transfers it to the drive control unit 2, and conversely stores read data from the drive control unit 2 and sends it to the host controller. 35 is a data bus, which is used for data transfer, and has a capacity of, for example, 256 kilobytes.
RAM31b, drive interface circuit 32a, host interface circuit 32b,
It is connected to the data transfer control circuit 33 to exchange commands and data.

36a is a control signal line for transmitting commands etc. to the drive control unit 2 and conversely receiving status etc. from the drive control unit 2;
6b is a tape end vicinity area detection signal line, which is for a tape end vicinity area detection (EWA) signal from the drive control unit 2; 36c;
37a is an interrupt line that notifies the MPU 30 of an interrupt from the drive interface circuit 32a, and 37a is a data transfer request signal line.
3 for transmitting a data transfer request signal from the drive control unit 2 to the data transfer control circuit 33;
7b is a write data bus for transmitting write data from the data buffer 34 to the drive control unit 2; 37c is a read data bus for transmitting read data from the drive control unit 2 to the data buffer 34;
8 is a control signal line for exchanging commands and status with the host controller; 39a is a data transfer request signal line;
3 is a write data bus for transmitting a data transfer request signal to the host controller; 39b is a write data bus for transmitting write data from the host controller to the data buffer 34;
A read data bus 9c is used to transmit read data from the data buffer 34 to the host controller.

Therefore, the MPU 30 connects the RAM 31b, the host interface circuit 32b, and the drive interface circuit 32 via the data bus 35.
a, writing between data transfer control circuit 33;
Read and perform desired processing.

That is, the host controller and the control signal line 38
The host interface circuit 32b exchanges commands and status under the control of the MPU 30 via the drive control unit 2 and the control signal line 36a, and the drive interface circuit 32a exchanges commands and status under the control of the MPU 30 via the drive control unit 2 and the control signal line 36a.

On the other hand, in response to instructions from the MPU 30, the data transfer control circuit 33 issues a data transfer request to the host controller via the data transfer request signal line 39a, and in response, the host controller sends write data to the data buffer 34 via the write data bus 39b. , let it accumulate. Also, the data transfer request signal line 37 from the drive control unit 2
In response to the data transfer request a, the data transfer control circuit 33 issues write data from the data buffer 34 to the drive control unit 2 via the write data bus 37b.

Furthermore, the data transfer control circuit 33 is connected to the MPU 30.
According to instructions from the drive controller 2, the read data via the read data bus 37c is stored in the data buffer 34, and is sent to the host controller via the read data bus 39c to the data buffer 34.
Send lead data.

The drive control unit 2 detects the vicinity of the tape end area by monitoring the running position using the rotary encoder 19a, and issues an EWA signal to the signal line 36, and sends an EWA signal to the signal line 36 by detecting the EOT.
Emit at 6a.

(b) Description of the operation of one embodiment FIG. 4 is a flowchart of the startup processing of the operation of one embodiment of the present invention, FIG. 4A is a diagram showing the startup processing routine from the host, and FIG. FIG. 3 is a diagram showing an initial setting processing routine.

When the power is turned on, the initial setting process shown in FIG. 4B is performed.

That is, first, the MPU 30 checks whether the execution processing mode is the write mode, and if it is not the write mode, sets the number AN of instruction storage areas in the instruction buffer management area CA of the RAM 31 to 32, which is the maximum. If it is the write mode, it is checked whether the EWA signal on the signal line 36b is on or off via the drive interface circuit 32a, and if it is off (the area near the end of the tape has not been reached yet), the command buffer of the RAM 31 is changed as described above. Number of instruction storage areas in management area CA
Set AN to maximum 32.

If the EWA signal is on, the number AN of instruction storage areas is set to the minimum value of 2.

Next, the MPU 30 clears the instruction memory number CN of the instruction buffer management area CA of the RAM 31 to zero, and sets the buffer capacity (data buffer) of the data buffer management area DA to the maximum.
256, set the data buffer address to “00”, and complete the initial setting.

Next, after the initial settings are completed when the power is turned on, or in the routine waiting for startup from the host, the MPU
30 checks the contents of the register of the host interface circuit 32b via the bus 35 to check whether there is a start (GO) from the host.

If there is no activation from the host, it waits for activation and repeats this routine.

When it is determined that there is activation from the host, that is, a GO signal has been received, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35, and determines what the given command is.

If the given command is not a write command such as a read command, the processing routine is executed.

On the other hand, if the given command is light type,
The MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not currently being executed.

If the execution processing mode is read type, drive processing is stopped. That is, the drive control section 2
When the process that is being executed is completed, the control line 36 is sent via the drive interface circuit 32a.
From a, the drive control unit 2 is not instructed to perform any new processing, and the read-related processing is stopped. Next, in order to adjust the tape position, a command (space or backspace) for adjusting the tape position is given to the drive control section 2 via the drive interface circuit 32a.

After this step is completed or if the drive control unit 2 is not running, perform initial settings for the step and write-related processing routine (fifth
Proceed to figure).

On the other hand, if the execution processing mode in the step is write type, the process immediately advances to the write type processing routine.

Therefore, if the activation from the host is a write-related command, even if read-related processing is in progress, it switches to write-related processing, and if it is write-related processing, write-related processing is continued.

Figure 5 is a process flow diagram for host write system, Figure 6
The figure is an explanatory diagram of prefetching of write-related commands.

When the MPU 30 is activated by a write command from the host controller as shown in FIG.
The number of instruction storage areas CN of CA and the number of instruction storage areas AN are read out via the bus 35 and compared. AN≦CN,
That is, if more write-related instructions are stored in the instruction buffer CBA than the number of instructions that can be stored, storage of the write-related commands in the instruction buffer CBA is suspended.

On the other hand, if AN > CN, write instructions can be stored in the instruction buffer CBA, so the MPU
30, such write-related commands are sent to the data buffer 34.
Find out if you want to use it. Erase,
If the data buffer 34 of the write tape mark is not used, the data busy DB is turned on and the process advances to the instruction storage step.

As shown in FIG. 6A, when a start (GO) command is given from the higher level (host), the lower level (preemption control unit 3) sends a data busy DB signal indicating that the command is being executed, if it is possible to execute the command. Turn it on and return to the top. This relationship is the same even when the prefetch control section 3 is placed at the upper level and the drive control section 2 is placed at the lower level.

Conversely, if the write-related instruction is a normal write instruction that uses the data buffer 34, the MPU 30 prepares for automatic transfer to the data buffer 34.

That is, first, the MPU 30 reads the free buffer capacity (parameter data buffer) and maximum block length in the data buffer management area DA of the RAM 31b, and checks whether the buffer capacity is greater than or equal to the maximum block length. If the buffer capacity is less than the maximum block length, reception of write data is suspended and waits until the data buffer 34 becomes free, and if the buffer capacity is greater than or equal to the maximum block length, transfer is permitted. Therefore, the aforementioned data busy DB signal is turned on to notify the host controller that transfer is possible.

Next, the MPU 30 reads the buffer address from the beginning of the data buffer management area DA of the RAM 31b, sets it in the store address counter SAC of the data transfer control circuit 33, and activates the data transfer control circuit 33. As a result, the data transfer control circuit 33 issues a data transfer request to the host controller from the data transfer request signal line 39a as shown in FIG. 6A.

Therefore, the host controller transfers the write data from the write data bus 39b to the data buffer 34, and the write data is stored in the data buffer 34 according to the address of the store address counter SAC of the data transfer control circuit 33. The store address counter SAC counts up every time one byte of write data is transferred.

When the data transfer control circuit 33 determines that the data transfer has ended, the MPU 30 reads the store address counter SAC of the data transfer control circuit 33 and calculates the number of bytes of the transferred write data, taking into account the difference from the buffer address in the data buffer management area DA. demand.

Next, the MPU 30 updates the instruction buffer CBA and data buffer management area DA of the RAM 31b.

First, the buffer address (ie, the start address of the write data) of the data buffer management area DA of the RAM 31b and the calculated number of bytes of the write data are stored in the relevant instruction column of the instruction buffer CBA of the RAM 31b.

Next, the number of used units of the data buffer 34 is subtracted from the free space of the data buffer management area DA of the RAM 31b to update this free space, and the number of used units is added to the buffer address to update the start address.

Next, the MPU 30 performs storage processing of the received write-related command.

First, the MPU 30 connects the host interface circuit 32 to the instruction buffer CBA of the RAM 31b.
b Store the received command.

Next, the MPU 30 adds "1" to the number of stored instructions to update the instruction buffer management area CA of the RAM 31b.

Furthermore, the MPU 30 checks the drive interface circuit 32a and checks the control line 36b.
Find out if the EWA signal is on or off. If it is off, the magnetic tape 16 has not reached the vicinity of the end of the tape, so the process advances to step.

On the other hand, if it is on, it has reached near the end of the tape, so the number AN of instruction storage areas in the instruction buffer management area CA of the RAM 31b is the minimum value "2".
If it is the minimum value, there is no need to update AN, so proceed to step.

On the other hand, if AN is not the minimum value, set AN to "3"
Decrease, update, and proceed to step.

Therefore, when the tape reaches near the end and the EWA signal turns on, the number AN of instruction storage areas decreases from the maximum value ``32'' by ``3'' every time a write command is received from the host controller, that is, the number of instruction storage areas permitted is reduced. gradually decreases.

Next, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), performs a drive activation process shown in FIG. 7, which will be described later.

During processing or when drive startup processing is performed, the MPU 30 controls the drive control unit 2 via the drive interface circuit 32a to
The TWA signal indicating that the
Check whether it is occurring from a.

If the TWA signal is generated, MPU30
It is checked whether the number of stored instructions (number of unexecuted instructions) CN in the instruction buffer management area CA of the RAM 31b is zero, and if it is not zero, it waits until it becomes zero through drive execution. This is to synchronize the commands from the host and the commands executed by the drive in processing after EOT.

When the TWA signal is not generated or when CN becomes zero, the MPU 30 notifies the host controller of completion from the host interface circuit 32b, turns off the data busy DB signal, and returns to the startup waiting routine of FIG. 4.

In this way, when a start (GO) is received from the host controller and a write command is given, it is first checked to see if it is within the number of instructions that can be stored in the instruction buffer, and if it is within the number of instructions that can be stored, the command If the command is accepted and the number of commands that can be stored is exceeded, the acceptance of this command is suspended and the data busy DB is
I don't raise it.

That is, as shown in FIG. 6B, the drive side executes the instructions in the instruction buffer as described later in FIG. Increases the busy level and notifies the host controller that the process is being executed.

Then, when the EWA signal is turned on, the number of commands that can be stored is gradually reduced each time a write-related command is received from the host controller. Furthermore, when the TWA signal is issued, no completion report is made until the number of stored instructions reaches zero.

Therefore, the number of instructions that can be stored gradually decreases as shown by the dotted line in FIG.

This gradual decrease prevents the host controller from taking an extremely long time to accept the next command. On the other hand, if it decreases all at once, the host controller will
(Number of stored instructions) - (Number of instructions that can be stored after reduction -
Since the next command cannot be accepted until the drive executes the number of commands equal to 1), the host controller's time monitoring will treat this as an abnormality in the device due to a timeout, resulting in an inconvenience.

Gradual reduction can therefore prevent this disadvantage.

Next, write-related processing of the drive will be explained using FIG. 7. FIG. 7A is a flow diagram of the drive startup process, and FIG. 7B is a process flow diagram of the end of the drive process.

() In FIG. 7A, the MPU 30 buffers the instruction buffer of the RAM 31b in order to start the drive.
Reads the next instruction to be executed from CBA and checks whether it is a write type instruction.

If it is not a write-related command, the process proceeds to the corresponding read-related processing routine.

() If the instruction is a write type instruction, check whether the instruction uses the data buffer 34. If the command does not use the data buffer 34, such as erase or write tape mark, the process advances to step ().

Conversely, if the instruction uses the data buffer 34, the MPU 30 uses the start address and number of bytes of the instruction buffer CBA in the RAM 31b in the load address counter of the data transfer control circuit 33.
Set LAC and byte counter BC respectively.

Furthermore, the data transfer control circuit 33 is activated.

() Next, the MPU 30 issues the read command and a start (GO) signal to the drive control unit 2 via the drive interface circuit 32a and the control line 36a.

On the other hand, if the drive control unit 2 returns data busy and the command uses the buffer, the data transfer request signal line 37a is sent after data transfer preparation is completed.
The data transfer request is sent to the data transfer control circuit 33.
send to As a result, the data transfer control circuit 33
sends write data corresponding to the number of bytes of the byte counter BC from the start address indicated by the load address counter LAC of the data buffer 34 to the drive control unit 2 via the write data bus 37b, and causes it to be executed and written to the magnetic tape 16.

On the other hand, the MPU 30 returns to the routine shown in FIG. 5 after issuing the step () instruction.

() Next, when the execution of the write-related command in the drive control section 2 is completed, a completion report is sent to the drive interface circuit 32a via the control line 36a. The drive interface circuit 32a thereby interrupts the MPU 30 and interrupts the processing shown in FIGS. 5 to 4.

The MPU 30 thereby starts the process shown in FIG. 7B.

First, the MPU 30 checks whether the instruction is a write type instruction. If the instruction is not a write type command, the process proceeds to the corresponding read type processing routine. If the instruction is a write type instruction, it is checked whether the instruction uses the data buffer 34, and if the instruction is used, the number of used units is added to the free capacity (parameter data buffer) of the data buffer management area DA of the RAM 31b, and the free capacity is updated.

() Next, after this update or data buffer 3
4 is not in use, set the number of instructions stored in the instruction buffer management area CA of RAM31b to "1".
Subtract and update.

Furthermore, the MPU 30 checks whether the number of instructions stored in the RAM 31b is zero, and if it is zero, returns to the routine of FIG. 6, and if it is not zero, executes step () and subsequent steps of FIG. 7A.

In this way, the drive sequentially executes the instructions in the instruction buffer asynchronously with the host controller.

(c) Description of other embodiments In the above embodiment, the number of write-related commands that can be stored is gradually reduced each time a write-related command is received from the host, but it may be reduced all at once as described above. , may be gradually decreased each time a plurality of instructions are executed on the drive side.

Further, the drive control section 2 and the command data prefetch control section may be integrated, and the drive 1 may also have a tape buffer.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, since write-related instructions are restricted, it is possible to execute all the write-related instructions stored in the instruction buffer, and the buffer is Inconveniences occurring at the end of the tape due to command prefetching of the magnetic tape device having the present invention can be prevented.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an overall configuration diagram of an embodiment of the invention, Fig. 3 is a diagram showing the main part of the configuration of Fig. 2, and Fig. 4 is an embodiment of the invention. 5 is a flowchart of write-related processing for the host according to an embodiment of the present invention; FIG. 6 is an explanatory diagram of command preemption according to an embodiment of the present invention; FIG. 7 is a diagram of an embodiment of the present invention. FIG. 8 is an explanatory diagram of instruction prefetch control, and FIG. 9 is an explanatory diagram of the prior art. In the figure, 1...magnetic tape drive unit, 2...drive control unit, 3...command/data prefetch control unit, CBA...command buffer.

Claims (1)

[Scope of Claims] 1. A magnetic tape drive unit having a magnetic head and a magnetic tape drive mechanism; a buffer unit capable of storing a plurality of commands given from a higher level; In a magnetic tape device comprising a control unit that controls a tape drive unit and executes the command, the control unit detects a vicinity of a terminal area of a magnetic tape run by the magnetic tape drive unit, 1. An instruction prefetch control method for a magnetic tape device, characterized in that the number of write instructions that can be accumulated in the buffer section is reduced based on proximity detection. 2. An instruction prefetch control method for a magnetic tape device according to claim 1, wherein the number of instructions is gradually reduced. 3. A magnetic tape drive unit having a magnetic head and a magnetic tape drive mechanism; an instruction prefetch control unit having a buffer unit capable of storing a plurality of commands given from a higher level; A magnetic tape device comprising: a drive control unit that controls a drive unit to execute the instructions; the instruction prefetch control unit manages the number of instructions that can be stored in the buffer unit; An instruction prefetch control device for a magnetic tape device, characterized in that the number of write instructions that can be accumulated is reduced based on a detection signal indicating the vicinity of the end region of the magnetic tape.