JPS6295755A - Method and apparatus for controlling instruction prefetching of magnetic tape device - Google Patents

Abstract

PURPOSE:To improve the processing efficiency by providing the 1st mode detecting the tape end logically to control the instruction prefetching and the 2nd mode detecting the actual tape end so as to control the instruction prefetching. CONSTITUTION:When the magnetic tape 16 of a magnetic tape section 1 runs and a region near the end EWA of the tape 16 is detected, a prefetching control section 3 counts the running distance of the tape 16 from the point of time near the end region and when the count reaches a prescribed value, a simultaing tape end EOT is obtained. Thus, the tape warning area TWA is prolonged by quickening the EOT detection point of time in this way. Thus, the performance deterioration of the streaming running is prevented. When the tape running distance reaches the limit, a logical EOT is set. In this mode, the number of prefetching instructions is not reduced until this point is arrived. Then in the physical EOT mode, the number of the prefetching instructions is reduced during the detection of EOT of the tape 16 based on the EWA detection.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples (Al-Overall Examples) Explanation of the configuration (Figure 2) (b) Explanation of the configuration of the preemption control unit (Figures 3 and 4) (C) Explanation of the startup processing operation (Figures 5 and 6) (d) Processing for host Explanation of operation (Fig. 7, Fig. 8) (e) Explanation of drive processing operation (Fig. 9, Fig. 10) (f) Explanation of overall operation (Fig. 11) (g) Other embodiments Description Effects of the Invention [Summary] In an instruction preemption control method for a magnetic tape device that preempts instructions and is equipped with a buffer capable of storing a plurality of instructions transferred from a higher level, a first method for controlling instruction preemption by logically issuing an EOT is provided. By providing one mode and a second mode in which command prefetch control is performed based on actual EOT detection, writing by streaming control in the vicinity of the tape end area is effectively performed.

[Industrial application field]

The present invention relates to an instruction prefetch control method and apparatus for prefetching instructions from a higher order into the buffer in a magnetic tape device having a buffer capable of storing a plurality of instructions.

Magnetic tape devices are widely used as external storage devices for computers, and in recent years have been particularly used for bank amplifiers of external storage devices in addition to magnetic disk devices.

In such a magnetic tape device, as shown in FIG. A controller CT is provided to control the controller based on commands from the controller.

In recent years, a buffer BF has been provided in the control unit CT to prefetch commands and data from the host controller, store them in the buffer BF, and instruct the tape drive unit 1 to sequentially execute the commands and data in the buffer BF. A system that performs proactive control has been developed and is in practical use.

This type of magnetic tape device is called a buffered magnetic tape device, and responds to instructions from the host controller.
Since the tape drive section 1 can be operated asynchronously, the host controller side can issue commands continuously without having to wait for the operation of the tape drive section 1 to complete in response to one command, and the tape drive section 1 can also issue commands from the host controller. Since the operation can be executed continuously without waiting for the operation, processing efficiency can be improved, and in particular, the operation efficiency in streaming mode can be improved.

[Conventional technology]

In order to have such a buffer BF and prefetch instructions, the buffer BF is composed of an instruction buffer that can store a plurality of instructions and a data buffer that can store a plurality of data.

Up to 64 instructions in the file, up to 256 instructions in the data buffer
It is designed to be able to store KB of data, thereby increasing the number of prefetch instructions and data.

On the other hand, as shown in FIG.
OF TAPE) marker is attached, and the EOT
Tape walking area (TWA) after detection is approximately 3m
L cannot be used.

Therefore, in write-related processing, if the pre-fetch command/data is 3 m or more at the time of EOT detection, it will not be possible to write it onto the magnetic tape 16, and some kind of countermeasure will be required.

Conventionally, for this reason, before detecting EOT, which is the end of the magnetic tape, a tape end near signal EWA is generated, for example, about 20 m before EOT, and as a result, as shown in FIG. 13(B), the data buffer of the buffer BF is The amount of data that can be stored (number of data bytes) was reduced. For example, Fig. 13 (B
), the data buffer can store up to 256 KB of data, but this is reduced to 128 KB, and the amount of data stored in the data buffer is reduced to 128 KB.
Unless the value becomes less than te, acceptance of write data from the host controller is not permitted, thereby preventing such writing failure.

[Problem that the invention seeks to solve]

According to the related art, the number of prefetching of write-related instructions is indirectly limited by limiting the capacity of the data buffer.

On the other hand, the performance of such a buffered magnetic tape device is greatly influenced by the number of prefetched instructions, and the larger the number of prefetched instructions, the longer the streaming can be maintained and the better the performance.

However, the length that can be written to the tape warning area (TWA) after EOT is limited, and
If the number of prefetched instructions is too large at the time of detection, it becomes impossible to execute all prefetched instructions.

For this reason, it is necessary to increase the number of pre-fetches as much as possible until near the EOT, and reduce the number to a writable number as the EOT approaches.

However, in the conventional technology, since the capacity of the data buffer is limited, the write-related instructions themselves that are pre-fetched may be unfairly limited in pre-fetching, and some write-related instructions may not be pre-fetched. The problem was that it was difficult to get a good streaming experience.

In other words, write-related instructions near the tape end area are too preemptively restricted and streaming is not performed, or too many write-related instructions are prefetched and even if streaming is performed, all instructions are executed within the TWA. There was a situation where I couldn't do it.

The present invention enables efficient streaming in the vicinity of the tape end area, and also allows write-related commands taken in advance to be transferred to the TW.
An object of the present invention is to provide a command prefetch control method for a magnetic tape device that can be reliably executed within A, and an apparatus therefor.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the present invention, the area near the end of the magnetic tape 16 (EWA)
It has two modes.

In the first mode (referred to as the logical EOT mode), the magnetic tape drive unit l runs the magnetic tape 16, and the EW
When A is detected, the control unit CT counts the traveling distance of the magnetic tape from the time of EWA detection, and when the count value F and CTR reach a certain value EPTR, it is assumed that the tape end area has been detected and a pseudo EOT is obtained. , No. 1 in EWA during this period.
As shown by the solid line in Figure (B), the number of instructions prefetched is not reduced.

This pseudo-EOT has the same effect as normal EOT detection, and thereby detects the EOT actually provided on the magnetic tape.
EOT handling occurs before that without detecting the marker.

In this first mode, the EWA detection point is set to pseudo EOT.
Pseudo EOT is performed after the magnetic tape 16 has traveled a certain distance.
This is because the EWA detection mechanism uses the servo control mechanism of the drive and does not have enough precision to set the EWA detection point at an arbitrary point in time with a small error. Increasing the accuracy of the water control mechanism excessively in order to improve EWA detection accuracy increases the cost of the device.

On the other hand, the second mode (referred to as physical EOT mode)
Here, the period from the EWA detection to the actual detection of the EOT marker is defined as an early warning area EWA, and the number of instructions that can be prefetched in EWA during this period is reduced as shown by the dotted line in FIG. 1(B).

Switching between the first mode and the second mode is performed in the EWA when execution of the first mode becomes impossible due to execution of a read-related command during operation in the first mode.
You can perform efficient streaming runs. Alternatively, the first mode and the second mode may be selected by selecting the mode using the operation panel.

[Effect]

In the present invention, since a logical pseudo-EOT is obtained in the first mode, the TWA can be lengthened by advancing the EOT detection time as shown in FIG.
Since the number of blocks that can be written to the TWA increases, there is no need to reduce the number of prefetching write instructions in the EWA, as shown by the solid line in FIG. 1(B).

Therefore, streaming can be continued in EWA and all prefetch write-related commands can be executed in TWA.

That is, as shown by the solid line in Figure 1 (C), up to the vicinity of EOT,
Ideal prefetch control is possible in which the number of instructions prefetched is as large as possible (and when the EOT approaches, the number is reduced to a writable number).

On the other hand, in the second mode, in the same EWA as normal, the number of write-related instructions that can be stored is limited, and write-related instructions such as erase and write tape mark that do not involve write data are also limited. All write-related instructions can be executed within the same time period, and inability to process write-related instructions can be prevented.

In other words, erase and write tape marks, which are write-related commands that do not involve write data, are also restricted, so that write-related commands can be written as shown in the dotted line in FIG.
All prefetched write instructions can be executed within the TWA.

〔Example〕

(a) Description of overall configuration of one embodiment FIG. 2 is an overall configuration diagram for explaining one embodiment of the present invention.

In the figure, the same components as those shown in FIG. A magnetic tape 16 is placed between the tension arm 1 and the supply reel (file reel) 12.
5, the magnetic head 14, and the idler 13 are connected to the take-up reel 11.
4 is guided by guides 17a and 17b on both sides.

On the other hand, the take-up reel 11 and the supply reel 12 are rotationally driven by drive motors 10a and 10b, respectively, and furthermore, the drive motors 10a and 10b have rotary encoders 18a and 18a.
8b is provided so that the amount of rotation of the drive motors 10a, 10b can be detected. The idler 13 is also provided with a rotary encoder 19a, which enables monitoring of the actual tape running position, while the tension arm 15 is provided with a tension detector 19b, which allows detection of tape tension. .

Reference numeral 2 denotes a drive control section, which drives tape running and drives head writing or reading according to commands and data from a command/data prefetch control section, which will be described later. The running condition is monitored, and the tension is monitored from the output of the tension detector 19b, and the re-drive motors 10a and LOb are controlled via the drive circuits 20 and 21 to drive the tape to run while keeping the tape tension constant. It supplies write data to the head 14 to perform writing, and receives read data from the magnetic head 14.

3 is a command/data prefetch control unit which receives write or read commands and write data from the host controller, stores them, and if it is a write command, sends a write command and write data to the drive control unit 2, and performs a write operation. If the process ends normally, the write command and write data for the next block are sent, and if the process does not end normally, the drive control unit 2 is caused to perform a write retry operation.

The command/data prefetch control section 3 has an instruction buffer and a data buffer, which will be described later, and is an adapter that operates as a magnetic tape device for the host controller and as a host controller for the drive control section 2.

(1)) Description of structure of prefetch control section FIG. 3 is a block diagram of the main part in the structure of FIG. 2, that is, the instruction data prefetch control section 3.

In the figure, 30 is a microprocessor (hereinafter referred to as MPU)
It controls the reception of commands and data from the host controller and the transmission of data and status according to the microprogram in the program memory described later, and also controls the transmission of commands and data to the drive control unit 2 and sends data from the drive control unit. , which performs status reception control and also processes the state control of drive 1, 3
1a is a program memory that stores programs to be executed by the MPU 30; 31b is a random access memory (hereinafter referred to as RAM);
It stores various data, instructions, and parameters necessary for processing 0, and has an instruction buffer area CBUF, an instruction buffer management area CA, a data buffer management area DA, various mode management areas EA, and a read instruction register RC. It is something.

The instruction buffer area CBUF contains the command prefetched from the host controller and the start address and byte count in the data buffer of the data transferred by the command in the case of a write command, and the read execution result of the prefetched block in the case of a read command. , the start address in the data buffer of read data, the number of bytes, etc. are stored, and the instruction buffer management area CA contains the number of stored instructions CBSTK, the Hough 7y size CB51ZE,
The final limit value CBE is stored. Instruction memory number CBSTK
For a write type command, the number of prefetched instructions that have not yet been executed is stored in the instruction buffer area CBUF, and for a read type command, the number of prefetched blocks is stored, and the buffer size CBS i ZE is stored in the instruction buffer area CBUF. The size of the CBUF is expressed by the number of instructions, and the final limit value is the final limit value for the number of write-related instructions prefetched in EWA in the physical EOT mode when not in the logical EOT mode.

The data buffer management area DA contains a buffer free capacity FSEG indicating the free capacity of the data buffer in units (I KByte) and a buffer address BADR indicating the start address of the data buffer at the time of data transfer for writing to the data buffer. and a maximum block length MAXL indicating the maximum diameter of the data block to be processed.

The mode management area EA has recording density (1600rpi or 6250rpi) when writing from the beginning to the end point.
The write recording density to determine the logical EOT mode, the LEOT flag indicating the logical EOT mode, and the logical EOT
In the mode, a travel counter ECTR is stored which stores the tape travel distance after EWA detection.

32a is a drive interface circuit for exchanging control signals and the like with the drive control unit 2; 32b is a host interface circuit for exchanging control signals and the like with the host controller; 33 is a data transfer control circuit that controls a data buffer to be described later to control data transfer with the host controller or drive control unit 2;
The device that issues a data transfer request signal to the host controller and receives the data transfer request signal from the drive control unit 2 performs data transfer control, and includes a store address counter 5CTR to the data buffer, a load address counter LCTR from the data buffer, It has a byte counter BCTR and the like during buffer loading.

34 is a data buffer, and the data transfer control circuit 33
It stores write data from the host controller and transfers it to the drive control unit 2, and conversely stores read data from the drive control unit 2 and transfers it to the host controller. For example, it has a capacity of 256 kilobytes. The one with 35 is the data bus, and the MPU
30, program memory 31 a, RAM3 l b,
The drive interface circuit 32a, host interface circuit 32b, and data transfer control circuit 33 are connected to exchange commands and data.

36a is a control signal line for transmitting commands etc. to the drive control unit 2 and conversely receiving status etc. from the drive control unit 2; 36b is a tape end vicinity area detection signal line 1; 2 for the transfer of tape end near area detection (EWA) signals from
36c is an interrupt line that notifies the MPU 30 of an interrupt from the drive interface circuit 32a; 37;
37b is a data transfer control signal line for transmitting a data transfer request signal from the drive control unit 2 to the data transfer control circuit 33 and a data transfer end signal to the drive control unit 2; 37b is a write data bus; , 37C is a read data bus for transmitting write data from the data buffer 34 to the drive control unit 2, 38 is a control signal line. 39a is a data transfer control signal line, which is used to transmit a data transfer request signal to the host controller and a data transfer end signal from the host controller. , 39b is a write data bus for transmitting write data from the host controller to the data buffer 34, and 39c is a write data bus for transmitting read data from the data buffer 34 to the host controller. .

Therefore, the MPU 30 connects the RAM 3 via the data bus 35.
l b, host interface circuit 32b1 drive interface circuit 32a, data transfer control circuit 33
Write and read between the two and perform the desired processing.

That is, the MP
The host interface circuit 32b is controlled by U30.
The drive interface circuit 32a exchanges commands and status with the drive control unit 2 under the control of the MPU 30 via the control signal line 36a.

On the other hand, the data transfer control circuit 33
issues a data transfer request to the host controller via the data transfer control signal line 39a, and in response, the host controller sends write data to the data buffer 34 via the write data bus 39b to be stored therein. Further, in response to a data transfer request from the drive control section 2 on the data transfer control signal line 37a, the data transfer control circuit 33 issues write data from the data buffer 34 to the drive control section 2 via the write data bus 37b.

Furthermore, the data transfer control circuit 33 stores read data from the drive control unit 2 via the read data bus 37c in the data buffer 34 according to instructions from the MPU 30, and transmits the read data from the data buffer 34 to the host controller via the read data bus 39c. .

Note that the drive control section 2 includes a rotary encoder 19a.
By monitoring the running position, the vicinity of the tape end area is detected and an EWA signal is issued to the signal line 36b, and when EOT is detected, a TWA signal is issued to the signal line 36a.

As shown in FIG. 4(A), such an interface between the preemption control unit 3, the host controller, and the device 1 is such that the MPU 30 activates the host interface circuit 32b by receiving the activation signal GO and command signal from the host controller. A response signal FBY is sent to the host controller via the host controller, and a data busy DBY indicating that the command is being executed is given to the host controller.

If the command signal is a write-related command that involves data transfer, the data transfer control circuit 33 gives a write strobe pulse WSTB to the host controller, and the host controller transfers the write data in synchronization with the write strobe pulse WSTH to the data buffer. Stored sequentially. The host controller sends the last word signal LWD to the data transfer control circuit 33 at the same time as the final write data.
The control circuit 33 sends this last word signal LWD to
When detected, it stops sending out the write strobe pulse WSTB, ends the data transfer, gives a status signal indicating normality/abnormality of the reception operation to the host controller, turns off the data busy DBY, and ends the write data transfer operation. Note that the received command is stored in the command buffer CBUF.

On the other hand, if the command is a read command, the read data read from the tape drive 1 is transferred to the host controller together with the read strobe pulse RSTB. The end of the read data transfer is notified to the host controller by turning off the data busy DBY.

Such an interface procedure is the same between the prefetch unit 3 and the drive 1 as shown in FIG. 4(B), and the instruction buffer CBUF and data buffer 34 of the prefetch unit 3
In the full state, even if a GO double signal write command arrives from the host controller, the data busy DBY is not raised until the buffer CBUF and data buffer 34 are free, so that data transfer is made to wait.

(Explanation of startup processing operation of C1 embodiment) FIG. 5 is a startup processing flow diagram of an embodiment of the present invention, and FIG. 6 is an initialization processing flowchart in FIG. 5.

(2) When the power is turned on, the MPU 30 checks the write recording density setting of the drive via the drive interface circuit 32a, and stores the write recording density setting of the drive in the write recording density of the area EA of the RAM 3 lb. Then, the initial setting process (1) shown in FIG. 6(A) is performed.

That is, the MPU 30 clears the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 31 to zero, sets the buffer free capacity FSEG in the data buffer management area DA to the maximum of 256 units (256 KB), and sets the data buffer address BADR to "00". Set.

Furthermore, the maximum block length MAIL of the data buffer management area DA is set to the minimum 8 units (8 KB), and the logical EOT mode flag of the area EA is turned off to complete the initial setting (1).

■Next, when the power is turned on, after the initial settings are completed after executing the REW command or the UNL command, or in the startup waiting routine from the host, the MPU 30 sends the magnetic tape to the supply reel 1 via the bus 35 and the drive interface circuit 32a.
Check whether it is in the online state set to 2.

If the MPU 30 is in the online state, the MPU 30 checks the register contents of the host interface circuit 32b via the bus 35, and receives a REW (rewind) command or UN from the host.
Check whether an L (unload) command has arrived.

■If a REW command or UNL command has arrived, the MPU
30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not being executed.

If the execution processing mode is read type, pre-reading of drive 1 is stopped. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped.

On the other hand, if the execution processing mode is write, the instruction buffer C
Executes all write instructions in the BUF.

Then, after all instructions have been executed, if there is no process being executed, or after the prefetch process of the drive has stopped, the MPU 30 sends a REW instruction (returns the tape to BOT) or a UNL instruction (winds up the tape) via the drive interface circuit 32a.
is given to drive 1 to execute this, and the process returns to step (2) initialization +1).

(2) On the other hand, if the REW instruction or UNL instruction has not arrived, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35 to see if there is activation (GO) from the host.

If there is no activation from the host, the process waits for activation and returns to step (■).

(2) When it is determined that there is activation from the host, that is, a GO signal has been received, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35, and determines what the given command is.

If the given command is a read-related command, the process goes to step [phase], and if it is a recording density setting, goes to step (2) to execute the processing routine.

■If the command is recording density setting, the MPU 30 notifies the host interface circuit 32b that the data busy DBY is turned on, and also notifies the drive interface circuit 32
It is checked whether the magnetic tape 16 of the drive 1 is located at the load point LDP, ie, BOT, via a.

If it is at the load point LDP, the recording density setting command is valid, so the MPU 30 executes the recording density setting command to the drive via the drive interface circuit 32a, and then changes the write recording density of the area EA of the RAM 3ib from the host. Cent the indicated recording density.

(Load point) If it is not in the LDP, the recording density setting command is invalid, and there is no need to execute the recording density setting command to the drive and write recording density cents.

After that, the MPU 30 uses the host interface circuit 32
A completion report is sent to the host via b, the data busy DBY is turned off, and the process returns to step (2).

(2) On the other hand, if the given command is a write type command, the MPU 30 checks whether the execution processing mode of the drive control section 2 is read type, write type, or is not currently being executed.

If the execution processing mode is read type, the preread processing of drive 1 is stopped. That is, when the drive control unit 2 finishes the process being executed, the drive interface circuit 32
The drive control section 2 is not instructed to perform new processing from the control line 36a via the control line 36a, and the read-related processing is stopped.

Next, execute the initial setting (2) in FIG. 6(B), and
30 clears the instruction storage number CBSTK of the instruction buffer management area CA of the RAM 31b to zero, and sets the buffer free capacity FSEG of the data buffer management area DA to the maximum of 256.
and set the data buffer address BADR to '00''.

(2) After completing this step (2) or if the drive control unit 2 is not in execution, the buffer 1 size cents in the initial setting (3) of FIG. 6(C) is performed.

First, the MPU 30 is a drive interface circuit 3.
Check whether the EWA (area near the end of the tape) signal on the signal line 36b is on or off via the signal line 2a, and if it is off (has not yet reached the area near the end of the tape), set the LIF and OT mode flags in area EA of RAM3 lb. Turn on and clear the travel counter ECTR to zero.

On the other hand, if the EWA signal is on, RAM3 l bOLE
Check whether the OT mode flag is on (YES) or off (No), and if it is off, move the final limit value CBE of the instruction buffer management area CA to the buffer size CBS i ZE,
Return.

Conversely, after the LEOT mode flag is turned on or the aforementioned travel counter ECTR is cleared to zero, the MPU 30 controls the RAM 3
Buffer size C of instruction buffer management area CA of b
Set the maximum value r64J to BS i ZH and return.

Next, in order to adjust the tape position, the MPU 30 sends a tape position adjustment command (space or backspace) to the drive control unit 2 to the drive interface circuit 3.
Command via 2a.

The program then proceeds to a write-related processing routine in FIG. 7, which will be described later.

(2) On the other hand, if the execution processing mode is write type in step (2), the process immediately proceeds to the write type processing routine.

[Phase] If the instruction transferred in step ■ is a read type, M
The PU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not currently being executed.

If the execution processing mode is a read system, the MPU 30 first checks whether the read directions match and stops the preread processing of the drive 1 if the read directions do not match. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped.

Furthermore, the MPU 30 has the same initial settings as step ■ (2)
, and then perform the same tape position adjustment as in step (3).

On the other hand, if the execution processing mode is write, the instruction buffer C
Execute all instructions in BUF.

Then, after all instructions have been executed, if there is no process being executed, or after the drive process has stopped, the above-mentioned prefetch read instruction is
Set in read command register RC of AM3 lb.

After this set or if the lead direction matches, the 8th
Proceed to the read-related processing routine shown in the figure.

Therefore, if the activation from the host is a write-related command, even if read-related processing is in progress, it switches to write-related processing, and if it is write-related processing, write-related processing is continued.

In the initial setting (1), the maximum block length MAXL is set to the minimum unit of 8, and in the initial setting (1) or (2), the instruction memory number C
BSTK is 0, data buffer free space FSEG is maximum 256, data buffer address BADR is (OO)
In addition, in the initial setting (3), the buffer size CBS i
ZE is up to 6 depending on LEOT mode on/off.
4 or the final limit value CBE.

Also, the recording density at the time of writing from the load point LDP is set in area EA of the RAM 31b.

(Explanation of d1 vs. host processing operation FIG. 7 is a flowchart of host write system processing.

■When the MPU 30 is activated by a write command from the host controller as shown in FIG. Read and compare via . If CB51ZE≦CBSTK, that is, the write-related commands are stored in the instruction buffer CBUF up to the number of instructions that can be stored, storage of the write-related commands in the instruction buffer CBUF is suspended.

On the other hand, if CBS i ZE>CBSTK, write instructions can be stored in the instruction buffer CBUF, so M
The PU 30 checks whether the write-related instruction uses the data buffer 34 or not.

If the erase/write tape mark data buffer 34 is not to be used, the data busy DBY is turned on and the process proceeds to step (2), the step of initializing the final limit value CBH.

As shown in Figure 5 (A), the startup (G
When the command O) is given, the lower order (preemption control unit 3
) turns on the data busy DBY signal indicating that the instruction is being executed and returns it to the upper level. This relationship is the same even when the prefetch control section 3 is placed at the upper level and the drive control section 2 is placed at the lower level.

Conversely, the MPU 30 writes write instructions to the data buffer 34.
If it is a normal write command using , it is determined whether automatic transfer to the data barafuna 34 is permitted.

That is, first, the MPU 30 reads the free buffer capacity FSEG and the maximum block length MAXL of the data buffer management area DA of the RAM 31b, and reads the free buffer capacity FSEG.
Check whether or not is greater than or equal to the maximum block length MAXL. If the free buffer capacity FSEG is less than or equal to the maximum block length MAXL, reception of write data is suspended and waits until the data buffer 34 becomes free by the maximum block length MAXL, and if the free buffer capacity FSEG is greater than or equal to the maximum block length MAXL, transfer is permitted. Therefore, the aforementioned data busy DBY signal is turned on to notify the host controller that transfer is possible.

[F] Next, the MPU 30 checks whether the magnetic tape 16 of the drive 1 is located at the load point 1-LDP via the drive interface circuit 32a.

If it is not at the load point LDP, the final limit value CBE has already been set, and the process proceeds to the next automatic transfer step (2). On the other hand, if it is at the load point LDP, the final limit value CBE is initialized according to the write recording density.

That is, the MPU 30 uses the mode area EA of the RAM 31b.
Check the write recording density of , and find that the write recording density is 1600r
For pi, the final limit value CBE of the instruction buffer management area CA of RAM3 lb is initially set to ``8'', and for 6250rpt, the final limit value CBE is initially set to ``16''.
Proceed to step ■.

Next, the MPU 30 checks whether the write-related instruction uses the data buffer 34 or not.

If the data buffer 34 is not used, step [
Proceed to the instruction storage step of [F].

On the other hand, if the data buffer 34 is used, data transfer is executed.

That is, the MPU 30 reads the first buffer address BADR of the data buffer management area DA of the RAM 3 lb, sets it in the store address counter 5CTR of the data transfer control circuit 33, and activates the data transfer control circuit 33. As a result, the data transfer control circuit 33 issues a data transfer request to the host controller via the data transfer control signal line 39a.

Therefore, the host controller transfers the write data from the write data bus 39b to the data buffer 34, and stores the write data in the store address counter 5CTR of the data transfer control circuit 33.
The write data is transferred to the data buffer 34 according to the address of
is stored in The store address counter 5CTR performs a count amplification every time one byte of write data is transferred.

O When the data transfer control circuit 33 determines that the data transfer has ended, the MPU 30 reads the store address counter 5CTR of the data transfer control circuit 33, calculates the difference between it and the buffer address BADR of the data buffer management area DA, and calculates the difference between the data transfer control circuit 33 and the buffer address BADR of the transferred write data. Find the number of bytes BC.

Next, the MPU 30 uses the instruction buffer C of the RAM 3 lb.
Updates the BUF and data buffer management area DA.

First, the data buffer management area DA of RAM3 lb is placed in the relevant instruction column of the instruction buffer CBUF of RAM31b.
buffer address (that is, the start address of write data) BADR and the calculated number of bytes of write data BC
Store.

Next, the number of used units USF, G of the data buffer 34 is subtracted from the free capacity FSEG of the data buffer management area DA of the RAM 31b, this free capacity FSEG is updated, and the number of used units USE is added to the buffer address BADR.
G is added and the start address BADR is updated.

Next, the MPU 30 compares the above-mentioned number of used units (reception block length) USEG with the maximum block length MAXL of the data buffer management area DA of the RAM 3 lb.

By this comparison, if the number of used units USEG is larger than the maximum block length MAXL, the data buffer management area DA
The maximum block length MAIL is updated to the number of used units USEG. Furthermore, the final limit value CBE is changed according to the recording density and the maximum block length MAXL.

That is, the MPU 30 reads the write recording density of area EA of RAM3 lb and the maximum block length MAIL of area DA, and when the recording density is 1600 rpi, if the maximum block length MAIL is greater than "16", the final limit value is set to the minimum value. If the maximum block length is "16" or less, the final limit value CBE is set to "4".

Similarly, when the recording density is 6250 rpi, if the maximum block length MAXL is greater than "32", the final limit value CBE
is set to "2", and the maximum block length MAXL is set to "17" to "3".
2", the final limit value CBE is set to "4", and if the maximum block length MAXL is "16" or less, the final limit value CBE is set to "4".
8”.

Conversely, if the number of used units USEG is less than or equal to the maximum block length MAXL, the maximum block length MAXL and the final limit value CBE are not updated and the process proceeds to step.

(2) Next, the MPU 30 performs storage processing of the received write-related command.

First, the MPU 30 uses the instruction buffer C of the RAM 3 lb.
The received command of the host interface circuit 32b is stored in the BUF.

Next, the MPU 30 sets the instruction storage number CBSTK to "
1” is added and updated.

(2) Furthermore, the MPU 30 checks the drive interface circuit 32a and checks whether the EWA (tape end vicinity detection) signal on the control line 36b is on or off. If it's off,
Since the magnetic tape 16 has not reached the vicinity of the end of the tape,
Proceed to step ■.

On the other hand, if it is on, the tape has reached the vicinity of the end, so check the LEOT flag in area EA of RAM 31b.
In EOT mode, instruction buffer size CBS i Z
Since there is no need to change E, proceed to step (■).

Conversely, if it is not the LEOT mode, the MPU 30 is RAM
3lb area CA instruction buffer size CBS
Read and compare i ZE and final limit value CBE.

Instruction buffer size CBS i ZE is the final limit value CB
If it is less than E, the instruction buffer size CB51ZE is not changed and the process proceeds to step (2). Conversely, the instruction buffer size CB
If S i ZE is greater than the final limit value CBE, "2" is subtracted from the instruction buffer size CBS i ZE, updated, and the process proceeds to step (2).

Next, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), performs a drive activation process which will be described later with reference to FIG.

■During processing or when drive startup processing is performed, MP
U30 is TWA indicating that the drive control unit 2 has detected EOT via the drive interface circuit 32a.
Check whether a signal is generated from the control line 36a.

In addition, in the LEOT mode, the MPU 30 operates in the first
It is checked whether the traveling counter ECTR updated by the drive-related processing shown in FIG.

If the TWA signal is generated upon EOT detection, or if LEOT is detected (on), the MPU 30 stores the number of stored instructions (number of unexecuted instructions) C in the instruction buffer management area CA of the RAM 31b.
Check whether BSTK is zero, and if it is not zero, wait until it becomes zero by executing the drive. This is to synchronize the commands from the host and the commands executed by the drive in the processing after EOT and LEOT.

When the TWA signal is not generated or when LEOT is off, the MPU 30 checks the state of the data transfer control circuit 33 to determine whether the write data transfer in step (3) has overflowed due to insufficient free space in the data buffer 34.

If an overflow occurs, in order to synchronize as described above, the MPU 30 checks whether the number of stored instructions (number of unexecuted instructions) CBSTK in the instruction buffer management area CA of the RAM 3 lb is zero, and if it is not zero, executes the drive. Wait until it becomes zero.

When no buffer overflow occurs or CBST
When K becomes zero, the MPU 30 reports completion (normal reception or error) to the host controller from the host interface circuit 32b, turns off the data busy DBY signal, and returns to the start-up waiting routine of FIG.

FIG. 8 is a flowchart of host read system processing.

■When a read-related command is received in step [phase] of the startup processing flow in FIG. 5 and startup processing is performed, the MPU 30
turns on the data busy DBY via the host interface circuit 32b and notifies the host controller of the start of execution.

0 Next, the MPU 30 uses the area CA of RAM 3 l b.
"1" is subtracted from the number of pre-read blocks CBSTK.

Furthermore, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), the MPU 30
Drive startup processing, which will be described later in the figure, is performed.

In addition, the MPU 30 checks whether the instruction storage number (preread block number) CBSTK in the area CA mentioned above is "0" or more, and determines whether it is "0" or more.
”, the read data has not been transferred to the data buffer 34, so CBSTK is “0”.
'', that is, wait until one or more blocks of read data from the drive 1 is transferred to the data buffer 34.

When the number of pre-read blocks CBSTK becomes rOJ or more, the read data should have been transferred from the drive 1 to the data buffer 34, so the MPU 30 transfers the read data from the RAM 3.
The read execution result from the instruction buffer CBUF of lb,
Leading address RA of read data in data buffer 34
Read DR and number of read bytes RBC.

0 Next, the MPU 30 checks whether the load point LDP was detected when the drive processed the block based on the read execution result read from the instruction buffer CBUF of the RAM 31b in step (3) described above. If so, check the read direction, and if it is in the read reverse direction, the BOT has been reached before block detection, and the read data has not been transferred to the data buffer 34, so proceed to step (2).

On the other hand, if the read direction is the read forward direction, the first block was read from the load point LDP, so the recording density is checked from the read execution result. The recording density of the read execution result indicates the recording density of the read magnetic tape.

If the recording density is 1600 rpi, the final limit value CBE of the instruction buffer management area CA of the RAM 31b is set to "8".
”, and if the speed is 6250rpi, the final limit value CBE is “
16” cents.

Furthermore, if the load point LDP has not been detected or after setting the final limit value CBH, the MPU 30 checks from the read execution result whether a tape mark indicating a file break was detected at the time of read execution, and determines whether a tape mark is detected. If so, the read data is stored in the data buffer 34.
Since the data has not been transferred, the data is not transferred and the process proceeds to step (■).

Conversely, if no tape mark is detected, step @
Proceed to the automatic transfer step.

[Phase] First, the MPU 30 determines whether the aforementioned read-related command involves data transfer. Read commands that do not involve data transfer include Space,
There are backspace (Back-3pace), space file (Space Fi 1 e), and backspace file (BackSpace File).

If it is a read-related command that involves data transfer, the data transfer to the host controller is executed.

That is, the MPU 30 inputs the first buffer address RADR read from the instruction buffer CBUF of the RAM 3 lb to the load address counter LC of the data transfer control circuit 33.
The number of read bytes is set in TR and the byte counter BCTR, and the data transfer control circuit 33 is activated.

Thereby, the data transfer control circuit 33 transfers the read data in the data buffer 34 to the host controller in accordance with the address of the load address counter LCTR together with the read strobe pulse R3TB (FIG. 4(A)). The load address counter LCTR counts up every time one byte of read data is transferred.

(2) When the data transfer control circuit 33 determines that the data transfer for the number of read bytes has been completed, the MPU 30 adds the number of used units USEG to the free capacity FSEG of the area DA of the RAM 31b and updates it.

On the other hand, since the read data is transferred to the data buffer 34 even in a read-related instruction that does not involve data transfer, the free capacity PSEG is updated in the same way.

Next, the MPU 30 checks whether the above-mentioned read-related command is a file search (File 5 search)-based command (space file or backspace file), and if it is a file search-based command, returns to step (2). In other words, the file search type command is divided into read commands.

■On the other hand, if it is not a file search type command in step O, or if the read direction is reverse in step ■, or if a tape mark is detected, the MPU3 is sent to the host controller.
0 indicates completion report from host interface circuit 32b (
Normal reception or error) and data busy DBY
The signal is turned off and the process returns to the startup waiting routine shown in FIG.

In this way, in write-related processing, in the logical EOT mode, the buffer size CB51ZE is not reduced and limited in step (2), but when logical EOT is turned on, prefetching instructions are prohibited in step (2) in the same way as when normal EOT is turned on.

On the other hand, when the physical EOT mode is not the logical EOT mode, the final limit value CBE is changed according to the recording density and the maximum block length MAXL (step ■), and E
In the WA, the buffer size is sequentially reduced in step (2).

Further, in read-related processing, prefetching is performed regardless of the type of read-related instruction.

(e) Explanation of drive processing operation FIG. 9 is a flowchart of drive activation processing.

(i) The MPU 30 uses the RAM 3 to start the drive.
The next instruction to be executed is read from the instruction buffer CBUF of lb, and it is checked whether it is a write type instruction.

If it is not a write-related instruction, that is, if it is a read-related instruction, M
PU30 checks whether the number of pre-read blocks CBSTK in area CA of RAM3 lb is a negative value smaller than zero.
If BSTK is greater than or equal to zero, prefetching has already been performed, so check whether it is okay to start. Returns if it cannot be started (an error was detected during read ahead and stopped).

On the other hand, if activation is possible, it is checked whether the number of pre-read blocks CBSTK in area CA of RAM3 lb is smaller than "63". If it is not, the instruction buffer CBUF in the RAM 31b is full, and the process returns.

On the other hand, if the number of pre-read blocks is less than 63, it is checked whether the free space FSEG is 64 bytes or more, and if it is less than 64 bytes, the process returns as data transfer is not possible.

(ii) If the free space FSEG is 64 bytes or more in step (i), it is possible to transfer data from drive 1, so the MPU 30 moves to the starting address BA of RAM 3 l b.
DR is set in the store address counter 5CTR of the data transfer control circuit 33, and the data transfer control circuit 33 is placed in a standby state.

Next, the MPU 30 drives the drive interface circuit 32
Check whether the EWA signal is on or off from a, and turn it on (YE
S), it is in EWA, so LEOT of RAM31b
Turn off the mode flag and cancel LEOT mode.

Furthermore, the MPU 30 determines whether the read-related command is a read reverse, and if it is a read reverse, turns off the logical EOT.

After this off, or when the EWA signal is not off or read reverse, the MPU 30 issues a start (GO) signal and the read related command to the drive 1 via the drive interface circuit 32a, and returns.

(iii) On the other hand, if it is determined in step (i) that it is a write-related command, preparations for automatic transfer to the drive are made.

That is, MPtJ30 is the instruction buffer CB of RAM31b.
Read the write-related instruction from the UF and check whether this instruction involves data transfer. If the instruction involves data transfer, the MPU 30 uses the instruction buffer CBU of the RAM 31b.
The start address WADR and the number of bytes WBC of F are sent to the load address counter LATR of the data transfer control circuit 33,
Set each byte counter BCTR.

Furthermore, the data transfer control circuit 33 is put into a standby state.

After this standby state, or write commands that do not involve data transfer as described above (erase, write tape mark, etc.)
If so, the MPU 30 reads the read instruction and starts (GO)
A signal is issued to the drive control section 2 from the control line 36a via the drive interface circuit 32a, and then returned.

On the other hand, the drive control B2 performs step (ii) described above.
, (iii) When receiving the activation signal and command, it responds by turning on data busy 0BY and starts executing the command.

For example, in the case of a write command that involves data transfer, a data transfer request is sent to the data transfer control circuit 33 from the data transfer control signal line 37a after data transfer preparation is completed. As a result, the data transfer control circuit 33 sends write data for the number of bytes of the byte counter BCTR from the start address indicated by the load address counter CTR of the data buffer 34 to the drive control unit 2 via the write data bus 37b, and executes the write data. The tape 16 is written.

Furthermore, when the execution of the write-related command in the drive control section 2 is completed, a completion report is sent to the drive interface circuit 32a via the control line 36a. The drive interface circuit 32a thereby
0 and interrupts the processing shown in FIGS. 5 to 8.

FIG. 10 is a flowchart of the drive drive/read processing.

(iv) When the MPU 30 receives the completion report from the drive, it checks whether the type of the completed instruction is read or write, and if it is read, it proceeds to step (vi).

On the other hand, if the completed instruction type is a write type, the MPU 30 checks whether the EWA signal is on or off via the drive interface circuit 32a. If it is off (No), proceed to step (vi).

If the EWA signal is on (YES), the area near the termination (
EWA), the MPU 30 uses RAM 3 l b
Open the LEOT mode flag of area EA to determine whether it is in LEOT mode.

If it is not the LEOT mode, it is the normal physical EOT mode, and the process proceeds to step (vi).

Conversely, in LEOT mode, the progress of the travel counter and the LE
Proceed to step (v) to detect the OT detection point.

(v) First, the MPU 30 uses area E of RAM 3 l b.
Check the write recording density of A.

The determination as to whether the recording density is 6250rpi or 1600rpi is made by changing the write tape mark length WTM, erase length ER3, IBG length, and judgment value EPTR in the following travel counter increment and LH, OT detection point detection processing. Yes, and the processing itself is exactly the same.

That is, the MPU 30 checks whether the instruction in the instruction buffer CBUF is a write instruction, erase variable pull instruction, write tape mark instruction, or fixed erase instruction.

If the instruction is a write instruction or an erase variable pull instruction, the number of bytes RBC of the instruction buffer CBUF is the number of units used US
It is converted into EG and updated by adding it to the travel count value ECTR in area EA of RAM3 lb. If the command is a write tape mark command, the write tape mark length WTM, which is a fixed value, is similarly added and updated to the running count value ECTR.

Furthermore, if the instruction is a fixed erase instruction, the fixed erase length E
Similarly, R8 is added and updated to the traveling count value ECTR.

Further, the IBG length is added to the running count value ECTR and updated.

Next, the MPU 30 compares this running count value ECTR and the determination value EPTR in order to detect the LEOT detection point.

If ECTR≧EPTR, the LEOT detection point has been reached, so logical EOT is turned on. If ECTR<EPTR, logical EOT is not turned on.

(vi) Next, the MPU 30 checks whether the write-related instruction uses the data buffer 34, and if the instruction uses the data buffer 34, the MPU 30 sets the number of used units USEG to the free capacity FSEG of the data buffer management area DA of the RAM 3 lb. is added and the free capacity FSEG is updated.

Next, after this update, or when the data buffer 34 is not in use, the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 3 lb is subtracted by "1" and updated.

Furthermore, the MPU 30 has the instruction storage number C of the RAM 3 lb.
Check whether BSTK is zero, and if it is zero, return to the routine in Figure 5 or Figure 7; if not, go to step (iii) in Figure 9.
) and the rest.

In this way, the drive sequentially executes the instructions in the instruction buffer asynchronously with the host controller.

(vii) On the other hand, if the instruction type is determined to be read in step (iv>), the MPU 30 checks whether the instruction is a read reverse, and if it is a read reverse, the drive 1 performs the load via the drive interface circuit 32a. Check whether point LDP is detected.If the load point detection signal is not rising,
If the command is read forward, it is checked whether the tape mark detection signal is rising via the drive interface circuit 32a.

If the tape mark detection signal is not rising, the number of bytes BC of read data transferred to the data buffer 34 upon completion of drive processing is calculated.

That is, the MPU 30 reads out the store address counter 5CTR of the data transfer control circuit 33, calculates the difference between it and the buffer address BADR of the data buffer management area DA, and obtains the number of bytes BC of the transferred read data.

Next, the MPU 30 uses the instruction buffer CBU of the RAM 31b.
F and data buffer management area DA are updated.

First, the data buffer management area D of RAM3 lb is placed in the relevant instruction column of the instruction buffer CBUF of RAM31b.
The buffer address of A (i.e., the start address of pre-read read data) BADR and the calculated number of bytes of read data BC are stored.

Next, data buffer management area D of RAM3 lb
The number of used units USEG of the data buffer 34 is subtracted from the free capacity FSEG of A, this free capacity FSEG is updated, and the number of used units USEG is added to the buffer address BADR.
EG is added and the start address BADR is updated.

Furthermore, the MPU 30 checks whether the drive 1 operates in the forward direction and detects EOT.

If YES, read execution result (EOT)
Detection) is stored in the corresponding read data storage column of the instruction buffer CBUF, and the process returns to the routine of FIG. 5 or FIG. 8.

Similarly, in the case of tape mark detection and load point LDP detection in read reverse, the instruction buffer CBUF
This is stored in , and the process returns to the routine shown in FIG. 5 or 8.

On the other hand, if the result of the above-mentioned EOT detection etc. of the MPU 30 is No, the read execution result (non-detection) is similarly stored in the corresponding read data storage column of the instruction bar 7 CBUF.

Furthermore, the MPU 30 checks whether the number of pre-read blocks CBSTK in area CA of RAM3 lb is 63 or more, and if it is 63 or more, returns to the routine of FIG. 5 or FIG. To do so, return to step (i) in FIG.

(f) Description of overall operation The operations shown in FIGS. 5 to 10 can be summarized as follows.

In the write system operation, (1) A logical EOT mode is provided in addition to the normal physical EOT mode.

That is, as shown in FIG. 11(A), when the magnetic tape drive unit 1 runs the magnetic tape 16 and detects an area near the end of the magnetic tape (EWA), the prefetch control unit 3 starts the magnetic tape from the time near the end area. The running distance of the tape is counted, and when the counted value ECTR reaches a certain value EPTR, it is considered that the tape end area has been detected, and a pseudo EOT is obtained.

This pseudo EOT (logical EOT) has the same effect as normal physical EOT detection, whereby the EOT is handled before actually detecting the EOT marker provided on the magnetic tape.

As a result, as shown in FIG. 11(A), the TWA can be lengthened by making the EOT detection time earlier. Therefore, the number of blocks that can be written to the TWA increases, as shown in FIG. 11(B). As shown by the solid line, there is no need to reduce the number of write instructions in EWA.

Therefore, the host controller is not subject to any prefetch restrictions for write-related commands in the EWA, so it is possible to prevent performance deterioration in streaming running.

That is, as shown by the solid line in FIG. 11(C), ideal prefetch control is possible in which the number of instructions prefetched is as large as possible until near the EOT, and as the EOT approaches, the number is reduced to a writable number.

As a result, it will not become impossible to write to TWA,
Performance deterioration can be prevented.

(2) Therefore, the initial setting (III) of step ■ in Figure 5
That is, in FIG. 6(C), in the LEOT mode, the buffer size CBS i ZE is the maximum "64" and is not subject to reduction restrictions.

That is, in the logical EOT mode, the buffer size CB51ZE is not gradually reduced, ie, the reduction limit is not performed in step (2) in FIG.

Then, in step (V) of FIG. 10, the tape running distance from the detection of the early warning area EWA is measured as the running count value ECTR, and this is the limit value E
When the PTR is reached, LEOT is turned on as logical EOT point detection, and the same treatment as normal physical EOT detection is performed in step (2) in FIG.

Therefore, in LEOT mode, the first
As shown by the solid line in Figure 1 (B), the buffer size CBS i Z
Without being limited by H, when LEOT point is detected, CBS i ZE becomes substantially zero as in the EOT mode.

Therefore, in the LEOT mode, the number of stored instructions CBSTK decreases from the detection of the LEOT point, as shown by the solid line in FIG. 1(C).

(3) Furthermore, in the LEOT mode, as shown in step (ii) in FIG.
After turning on), when the count value cannot be guaranteed due to reception or execution of a read-related command, the logical EOT mode is turned off and shifts to the physical EOT mode.

(4) On the other hand, in normal physical EOT mode,
Initial setting (■) of step ■ in Fig. 5, that is, Fig. 6 (C
), the buffer size CB51ZE is the final limit value C
Changed by BE.

Also, in step ① of Fig. 7, this final limit value CB
E changes depending on the recording density and maximum block length.

That is, the final limit value CBE is as shown in FIG. 11 (C1 and (D)
This is determined based on the recording density and maximum block length, as shown in FIG.

For example, in high-density recording with a recording density of 6250 rpi as shown in FIG.
4" and "2", in low-density recording with a recording density of 1600 rpi, the final limit value CBE for instruction preemption is changed from "8" to "4" and "2" according to the maximum block length MAXL. It is.

Therefore, at the time of EOT detection, it is possible to pre-fetch write-related commands that can fully utilize TWA according to the recording density and maximum block length, and it is possible to use TWA effectively.

Furthermore, in the physical EOT mode, the buffer size CBS i ZE is equal to the final limit value CB in the early warning area EWA in step ① of FIG.
If it is E or higher, it will decrease by "2".

For example, the number of write instructions that can be accumulated in the instruction buffer is 64.
is gradually decreased as shown by the dotted line in FIG. 11(B).

Therefore, in order to limit the number of write-related instructions that can be stored, write-related instructions such as erase and write tape mark that do not involve write data are also limited, so all write-related instructions can be stored within the magnetic tape (especially within the TWA). can be executed, and can prevent write-related instructions from being unable to be processed.

That is, when the tape reaches near the end and the EWA signal turns on, the buffer size CBS i ZE is decreased from the maximum value "64" by "2" each time a write command is received from the host controller, that is, the number of commands allowed to be stored gradually decreases. Decrease. Furthermore, when the TWA (EOT) signal is issued, no completion report is made until the instruction storage number CBSTK becomes zero.

Therefore, the number of prefetch instructions gradually decreases as shown by the dotted line in FIG. 1(C).

This gradual decrease prevents the host controller from taking an extremely long time to accept the next command. On the other hand, if the number decreases all at once, the host controller will wait until the drive executes the number of instructions equal to (Number of accumulated instructions) - (Number of instructions that can be accumulated after reduction - 1) until the next instruction is executed. Since the request is not accepted, the host controller's time monitoring detects that the device is abnormal due to a timeout, resulting in an inconvenience.

Therefore, this inconvenience can be prevented by gradual reduction.

This gradual reduction is performed when the value is equal to or greater than the final limit value CBE, and the final limit value CBE is sequentially changed according to the recording density and the maximum block length.

(5) Also, as shown in step ① in Figure 7, when the host controller activates (Go) and a write command is given, it is first checked to see if the number of instructions that can be stored in the instruction buffer is within the number of instructions that can be stored. If the number is within the allowable number, this command is accepted; if the number exceeds the storable number of commands, acceptance of this command is suspended and the data busy DBY is not raised.

That is, as shown in FIG. 4(B), the drive side executes the instructions in the instruction processor and does not increase the data busy until the number of instructions is within the storable number of instructions. Notify the host controller that it is being executed.

Similarly, in step (2), it is checked whether the free space in the data buffer is greater than or equal to the maximum block length, and if it is greater than or equal to the maximum block length, the write data is transferred from the host controller, and if it is less than the maximum block length, data transfer is not performed. Do not raise data busy DBY on hold.

Therefore, the drive side executes the instructions in the instruction buffer,
Data busy is not raised until the free capacity of the data buffer exceeds the maximum block length, and when it becomes equal to or greater than the maximum block length, data busy is raised to enable transfer acceptance.

Then, in step (2), if the transferred block length is larger than the maximum block length, the actually transferred block length is adopted as the maximum block length from next time onwards.

Therefore, the effect of reducing the number of retries and shortening waiting time is produced.

(g + Description of other embodiments In the above embodiment, when the count value of the running counter cannot be guaranteed as explained in (3) above due to the reception and execution of a read-related command while operating in the logical EOT mode, the physical I am trying to transition to EOT mode, but
Area EA of RAM 3 l b can be set using the operation panel.
By forcibly turning off the LEOT mode flag of
It may be possible to enable operation only in the physical EOT mode.

Furthermore, in the above embodiment, in the physical EOT mode, the number of write-related commands that can be stored is gradually reduced each time a write-related command is received from the host, but it may be reduced all at once, and The number may be gradually decreased each time a plurality of instructions are executed.

Further, the drive control s2 and the command data prefetch control section may be integrated, and the drive 1 may also have a tape buffer.

Moreover, the maximum block length MAXL may not be changed depending on the received block, but may be changed in steps.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, there are two modes: a first mode (logical EOT mode) and a second mode (physical EOT mode).
Since it has both instruction prefetch control modes (T mode), even in early warning area EWA, the first mode does not limit the number of write instructions prefetch and can maintain streaming for a long time, and in EWA , the number of prefetching of write instructions is moderately limited, and the streaming run is made efficient (while maintaining the tape walking area T
The second mode that can maximize the number of blocks that can be written to the WA can be selected automatically or manually, and command preemption control that allows streaming operations to be executed smoothly and efficiently in the area EWA near the end of the tape is possible. becomes.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an overall configuration diagram of an embodiment of the present invention, Fig. 3 is a main part configuration diagram of the configuration shown in Fig. 2, and Fig. 4 is a data transfer diagram of the configuration shown in Fig. 2. 5 is a flowchart of startup processing according to an embodiment of the present invention, FIG. 6 is a flowchart of initialization processing of FIG. 5, and FIG. 7 is a flowchart of write-related processing for a host according to an embodiment of the present invention. Figure 8 is a flow diagram of read processing for the host, Figure 9 is a flow diagram of startup processing for the drive, Figure 10 is a flow diagram of write/read processing for the drive, Figure 11 is an explanatory diagram of the overall operation, The figure is an explanatory diagram of command prefetch control of a magnetic tape device, and FIG. 13 is an explanatory diagram of the prior art. In the figure, 1--magnetic tape drive section, 2-- drive control section, 3-- instruction/data prefetch control section, CBUF-- instruction buffer, 34-- data buffer.

Claims (2)

[Claims] (1) A magnetic tape drive unit having a magnetic head and a magnetic tape drive mechanism; a buffer unit capable of preemptively storing multiple commands given from a higher level; and controlling the magnetic tape drive unit according to the commands stored in the buffer unit. and a control unit that executes the command, after the control unit detects the vicinity of the end area of the magnetic tape run by the magnetic tape drive unit, the end area of the magnetic tape is detected during execution of the write command. The running distance of the magnetic tape was counted from the time of detecting the vicinity of the area, and when the counted value reached a certain value, it was considered that the tape end area was detected, and the detection of the vicinity of the end area was considered as the detection of the tape end area. Detecting the vicinity of the terminal area when executing the first mode that does not reduce the number of instructions that can be prefetched until the end of the first mode, and interrupting the execution of the first mode or not executing the first mode. A method for prefetching instructions in a magnetic tape device, characterized in that the number of instructions that can be prefetched until detection of the end area of the magnetic tape is reduced based on the following. (2) a magnetic tape drive section having a magnetic head and a magnetic tape drive mechanism; an instruction prefetch control section having a buffer section capable of preemptively storing a plurality of instructions given from a higher level; A magnetic tape device comprising: a drive control unit that controls a magnetic tape drive unit to execute the instruction; the instruction prefetch control unit manages the number of instructions that can be prefetched into the buffer unit; During execution, the running distance of the magnetic tape is counted based on a detection signal indicating the vicinity of the end area of the magnetic tape from the drive control unit, and when the counted value reaches a certain value, it is considered that the end area of the tape has been detected. , a first mode in which the number of instructions that can be prefetched is not reduced from the detection of the vicinity of the end area until the time when the tape end area is deemed detected; An instruction prefetch control device for a magnetic tape device, comprising a second mode in which the number of instructions that can be prefetched is reduced until an end area is detected from a drive control unit.