JPS6284331A - Method and device for controlling prefetch of instruction of magnetic tape device - Google Patents

Abstract

PURPOSE:To draw out the performance of a device at its maximum in a range where all instructions in a TWA are executable by restricting the number of instructions of write system capable of prefetching instructions to accumulate them in a buffer section basing on detection near the termination area of a magnetic tape. CONSTITUTION:In write system operation, a logical EOT mode is provided separately from ordinary physical EOT (end of tape) mode, and when a magnetic tape driving section travels a magnetic tape 16 and detects an area near termination (EWA) of the magnetic tape, an advance taking controlling section calculates distance of run of the magnetic tape from the position near termination area, and when the measured value ECTR reached a fixed value EPTR, regard it as the detection of terminal area of the tape and obtains pseudo-EOT. By such a pseudo-EOT, the number of prefetched instructions are increased as much as possible to the position near by the EOT, then prefetching is controlled to decrease the number of writable instructions when the EOT has approached.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples (Al-Overall Examples) Explanation of the configuration (Figure 2) (b) Explanation of the configuration of the prefetch control unit (Figures 3 and 4) Explanation of the fcl startup processing operation (Figures 5 and 6) (d) Description of the host processing operation Explanation (Fig. 7, Fig. 8) fe) Explanation of drive processing operation (Fig. 9, Fig. 10) (fl Explanation of overall operation (Fig. 11) (g) Description of other embodiments Effects of the invention [Summary] In an instruction prefetching method for a magnetic tape device that is equipped with a buffer that can store multiple instructions transferred from a higher level and that preempts instructions, a write-related instruction that can be prefetched to a buffer section based on detection near the end area of a magnetic tape is provided. By limiting the number by determining the final limit value based on the recording density and maximum block length, the number of prefetch instructions can be appropriately limited in the area near the end of the tape.

[Industrial application field]

The present invention relates to an instruction prefetch control method and apparatus for prefetching instructions from a higher order into the buffer in a magnetic tape device having a buffer capable of storing a plurality of instructions.

Magnetic tape devices are widely used as external storage devices for computers, and in recent years have been used particularly for hacking up external storage devices in addition to magnetic disk devices.

In such a magnetic tape device, as shown in FIG. 12, there is a tape drive unit 1 having a magnetic head for writing and reading data on the magnetic tape, a magnetic tape drive unit for driving the magnetic tape, and a host controller. A controller CT is provided to control the controller based on instructions from the controller.

In recent years, a buffer BF has been provided in the control unit CT to prefetch commands and data from the host controller, store them in the buffer BF, and instruct the tape drive unit 1 to sequentially execute the commands and data in the buffer BF. A system that performs proactive control has been developed and is in practical use.

This type of magnetic tape device is called a buffered magnetic tape device, and responds to instructions from the host controller.
Since the tape drive section 1 can be operated asynchronously, the host controller side can issue commands continuously without having to wait for the operation of the tape drive section 1 to complete in response to one command. Since operations can be executed continuously without waiting for instructions, processing efficiency can be improved, and in particular, operation efficiency in streaming mode can be improved.

[Conventional technology]

In order to have such a buffer BF and prefetch instructions, the buffer BF has M$AI of multiple instructions.

It consists of an instruction buffer that can store multiple instructions, and a data buffer that can store multiple data.For example, the instruction buffer can store up to 64 instructions, and the data buffer can store up to 256 KB.
data can be stored, and the number of prefetch instructions and data can be increased.

On the other hand, as shown in FIG. 13(A), the magnetic tape 16 does not have an infinite length but a finite length, so at the end there is an EOT (END).
OF TAPR) marker is attached, and EOT detection (Mugi tape walking area (TWA) is approximately 3 m.
L cannot be used.

Therefore, in write-related processing, if the pre-fetch command/data is 3 m or more at the time of EOT detection, it will not be possible to write it onto the magnetic tape 16, and some kind of countermeasure will be required.

Conventionally, for this reason, before detecting EOT, which is the end of the magnetic tape, a tape end near signal EWA is generated, for example, about 20 m before EOT. The buffer storage capacity (data high 1 to number) was reduced. For example, as shown in Figure 13 (
For a data buffer that can store up to 256 KB of data as shown in B), this is reduced to 128 KB, and the amount of data stored in the data buffer is 128 KB.
This writing failure is prevented by not allowing write data to be accepted from the host controller unless the size is less than Byte.

[Problem that the invention seeks to solve]

According to the related art, the number of prefetching of write-related instructions is indirectly limited by limiting the capacity of the data buffer.

On the other hand, the performance of such a buffered magnetic tape device is greatly influenced by the number of prefetched instructions, and the larger the number of prefetched instructions, the longer the streaming can be maintained and the better the performance.

However, the length that can be written to the tape warning area (TWA) after EOT is limited, and
If the number of prefetched instructions is too large at the time of detection, it becomes impossible to execute all prefetched instructions.

For this reason, it is necessary to increase the number of pre-fetches as much as possible until near the EOT, and reduce the number to a writable number as the EOT approaches.

The length of a block recorded on this tape varies depending on the recording density and the number of bytes of the block, so the number of blocks that can be written in the tape walking area (TWA) also varies depending on the recording density and the number of bytes of the block.

For example, at a recording density of 1600 rpi, the block length is 64KB.
If this is the case, the length of one block is approximately 1 m, and the number of blocks that can be written in the tape walking area (TWA) is 3 blocks, but the recording density is also 1600 r.
Even with p i, if the block length is 8 KB, the length of one block is approximately 14.5 cm including the IBG, and the number of blocks that can be written to the tape walking area (TWA) is approximately 20.
It's a block.

Further, if the recording density is 6250 rpm and the block length is 8 KB, the width of one block is approximately 4 cm including the IBG, and approximately 75 programs/7 units can be written in the tape walking area (TWA).

Therefore, it is desirable to limit the number of instructions to be prefetched when the EOT approaches, taking into consideration the recording density and the number of bytes of a block.

However, in the conventional technology, the number of instructions prefetched varies depending on the number of bytes of a block, but since the recording density is not taken into consideration, the number of prefetched instructions is too large at 1600 rpm, and T
There have been cases where there is a risk that all instructions cannot be executed within the WA, or where the number of prefetched instructions is excessively limited at 6250 rpm, resulting in excessive deterioration of device performance.

The present invention provides an instruction preemption control method for a magnetic tape device and its device, which can perform instruction preemption control that can maximize the performance of the device within the range in which all instructions can be executed within the TWA. The purpose is to

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the present invention, the EWA (
(Early Warning Area), Figure 1 (B)
As shown in Figure 1 (C) and (D), the number of write instructions that can be preempted CBS i ZE is limited gradually as shown by the solid line or all at once as shown by the dotted line, and the final limit value CBE is determined by the recording density and the maximum block as shown in Figures 1 (C) and (D). The decision was made based on the length.

For example, in high-density recording with a recording density of 6250 rpi as shown in FIG.
”, “2”, in low-density recording with a recording density of 1600 rpi, the instruction prefetch final limit value Cl5E is changed from “8” to “4” to “2” according to the maximum block length MAXL. be.

[Effect]

In the present invention, the final limit value CBE of the number of instructions that can be prefetched CB51ZE is determined by the recording density and the maximum block length MAXL, so the instruction prefetch limit can be set to an optimal value and all instructions can be executed within the TWA. The performance of the device can be maximized to the extent possible.

In addition, in the present invention, instead of limiting the capacity of the data buffer, the number of write-related instructions that can be read in advance is limited, so write-related instructions such as erase and write tape mark that do not involve write data are also limited. All write-related instructions can be executed within the tape, and write-related instructions can be prevented from being unable to be processed.

〔Example〕

(a) Description of overall configuration of one embodiment FIG. 2 is an overall configuration diagram for explaining one embodiment of the present invention.

In the figure, the same components as those shown in FIG. A magnetic tape 16 is arranged between a (machine reel) 11 and a supply reel (file reel) 12 to reach the take-up reel 11 via a roller 15a of a tension arm 15, a magnetic head 14, and an idler 13. It is guided on both sides by guides 17a, 17b.

On the other hand, the take-up reel 11 and the supply reel 12 are rotationally driven by drive motors tOa and 10b, respectively, and the drive motors 10a and 10b have rotary encoders iaa and 1
8b is provided so that the amount of rotation of the drive motors 10a, 10b can be detected. The idler 13 is also provided with a rotary encoder 19a, which enables monitoring of the actual tape running position, while the tension arm 15 is provided with a tension detector 19b, which allows detection of tape tension. .

Reference numeral 2 denotes a drive control section, which drives tape running and drives head writing or reading according to commands and data from a command/data prefetch control section, which will be described later. The running state is monitored, and the tension is monitored from the output of the tension detector 19b, and both drive motors 10a and 10b are controlled via drive circuits 20 and 21 to drive the tape to run while keeping the tape tension constant. It supplies write data to the head 14 to perform writing, and receives read data from the magnetic head 14.

3 is a command/data prefetch control unit which receives write or read commands and write data from the host controller, stores them, and sends write commands and write data to the drive control unit 2 for write commands; If one block is completed normally, the next block's write command and write 1 data are sent, and if the block is not completed normally, the drive control section 2 is made to perform a write retry operation.

The command/data prefetch control section 3 has an instruction buffer and a data buffer, which will be described later, and is an adapter that operates as a magnetic tape device for the host controller and as a host controller for the drive control section 2.

(b) Description of structure of prefetch control section FIG. 3 is a block diagram of the main part in the structure of FIG. 2, that is, the instruction data prefetch control section 3.

In the figure, 30 is a microprocessor (hereinafter referred to as MPU)
It controls the reception of commands and data from the host controller and the transmission of data and status according to the microprogram in the program memory described later, and also controls the transmission of commands and data to the drive control unit 2 and sends data from the drive control unit. , which performs status reception control and also processes the state control of drive 1, 3
1a is a program memory that stores programs to be executed by the MPU 30; 31b is a random access memory (hereinafter referred to as RAM);
It stores various data, instructions, and parameters necessary for processing 0, and has an instruction buffer area CBUF, an instruction buffer management area CA, a data buffer management area DA, various mode management areas EA, and a read instruction register RC. It is something.

In the instruction buffer area CBUF, when a write command is used, the instruction prefetched from the host controller and the start address in the data buffer of the data transferred by that instruction, byte count (-number, etc.) are used for read commands, and the read address of the prefetched block is stored. The execution result, the start address in the data buffer of the read data, the number of bytes, etc. are stored, and the instruction buffer management area CA stores the instruction storage number CBSTK, buffer size CBS i ZE, and final limit value CBE. Instruction memory number CBST
K stores the number of prefetched instructions that are stored in the instruction buffer area CBUF and has not yet been executed in the case of a write-related command, and the number of prefetched blocks in the case of a read-related command. The size is expressed by the number of instructions, and the final limit value C, o' is the final limit value for the number of write-related instructions prefetched in EWA in the physical EOT mode when not in the cull EOT mode.

The data buffer management area DA contains a buffer free capacity 1FsEG indicating the free capacity of the data buffer in units (IKByte units), and a buffer address BADR indicating the Ml address of the data buffer at the time of data transfer for writing to the data buffer. , the maximum block length MAXL indicating the maximum length of the data block to be processed are stored.

The mode management area EA has recording density (1600rpi or 6250rpi) when writing from the load point.
The write recording density to determine the logical EOT mode, the LEOT flag indicating the logical EOT mode, and the logical EOT
In the mode, a travel counter ECTR is stored which stores the tape travel distance after EWA detection.

32a is a drive interface circuit for exchanging control signals etc. with the drive control unit 2; 32b is a post interface circuit for exchanging control signals etc. with the host 1-controller. 33 is a data transfer control circuit, which controls a data buffer to be described later to control data transfer between the host controller 1 and the roller or drive control unit 2, and issues a data transfer request signal to the host controller. In addition, the unit that receives the data transfer request signal from the drive control unit 2 performs data transfer control, and includes a store address counter 5CTR to the data buffer, a load address counter LC'FR from the data buffer, and a hide counter when loading the data buffer. It has BCTR etc.

34 is a data buffer, and the data transfer control circuit 33
It stores write data from the host controller and transfers it to the drive control unit 2, and conversely stores read data from the drive control unit 2 and transfers it to the host controller. , 35 is a data bus, and MP
U30 and program memory 31a, RAM311)
, the drive interface circuit 32a, the host interface circuit 32b, and the data transfer control circuit 33 for exchanging commands and data.

36a is a control signal line for transmitting commands etc. to the drive control unit 2 and conversely receiving status etc. from the drive control unit 2; 36b is a tape end vicinity area detection signal line; for the transfer of the tape end vicinity area detection (EWA) signal from the
36c is an interrupt line that notifies the MPU 30 of an interrupt from the drive interface circuit 32a; 37;
37b is a data transfer control signal line for transmitting a data transfer request signal from the drive control unit 2 to the data transfer control circuit 33 and a data transfer end signal to the drive control unit 2; 37b is a write data bus; , 37C is a read data bus for transmitting write data from the data buffer 34 to the drive control unit 2, 37C is a read data bus for transmitting write data from the drive control rxB 2 to the data buffer 34, and 38 is a control signal line. 39a is a data transfer control signal line for transmitting a data transfer request signal to the host controller and a data transfer completion signal from the host controller. 39b is a write data bus for transmitting write data from the host controller to the data buffer 34; 39C is a read data bus;
This is for transmitting read data from the data buffer 34 to the host controller.

Therefore, MPL+30 is connected to RAM3 via data bus 35.
l b, host interface circuit 32b1 drive interface circuit 32a1 data transfer control circuit 3
3, and performs desired processing.

That is, the MP
The host interface circuit 32b is controlled by U30.
The drive interface circuit 32a exchanges commands and status with the drive control unit 2 under the control of the MPU 30 via the control signal line 36a.

On the other hand, the data transfer control circuit 33
issues a data transfer request to the host controller via the data transfer control signal line 39a, and in response, the host controller sends write data to the data buffer 34 via the write data bus 39b to be stored therein. Further, in response to a data transfer request from the drive control section 2 on the data transfer control signal line 37a, the data transfer control circuit 33 issues write data from the data buffer 34 to the drive control section 2 via the write data bus 37b.

Further, the data transfer control circuit 33 stores read data from the drive control unit 2 via the read data bus 37c in the data buffer 34 according to instructions from the MPU 30, and transmits the read data from the data buffer 34 to the host controller via the read data bus 39C. .

Note that the drive control section 2 includes a rotary encoder L9a.
The area near the end of the tape is monitored by monitoring the running position.
Upon detection, an EWA signal is issued to the signal line 36b, and upon EOT detection, a TWA signal is issued to the signal line 36a.

As shown in FIG. 4(A), such an interface between the prefetch control unit 3, the host controller, and the device 1 is such that the MPU 30 activates the host interface circuit 32b by receiving the activation signal Go and command signal from the host controller. A response signal FBY is sent to the host controller via the host controller, and a data busy DBY indicating that the command is being executed is given to the host controller.

If the command signal is a write command that involves data transfer, a write strobe pulse WSTB is given from the data transfer control circuit 33 to the host controller, and write data is transferred from the host controller in synchronization with the write strobe pulse WSTB. Stored in buffer sequentially. The host 1 controller i-roller sends the last word signal LWD to the data transfer control circuit 33 at the same time as the final write data. When the control circuit 33 detects this last word signal LWD, it stops sending the write strobe pulse WSTB, and the data transfer control circuit 33 stops sending the write strobe pulse WSTB. Finishes the transfer, sends a status signal indicating normal/abnormal reception operation to the host controller,
The data busy DBY is turned off to end the write data transfer operation. Furthermore, the received command is sent to the instruction buffer CBUF.
is stored in

On the other hand, if the command is a read command, the data read from the tape drive 1 is transferred to the host controller together with the read goob pulse R3TB. The end of the read data transfer is notified to the host controller by turning off the data busy DBY.

Such an interface procedure is the same between the prefetch unit 3 and the drive 1 as shown in FIG. 4(B), and the instruction buffer CBUF of the prefetch unit 3 and the data buffer
4 is full, even if a Go times signal write command arrives from the host controller, the data busy DBY is not raised until the buffer CBUF and the data buffer 34 are free, so that data transfer is made to wait.

(C) Description of startup processing operation in one embodiment FIG. 5 is a startup processing flow diagram of one embodiment of the present invention, and FIG. 6 is an initialization processing flow diagram in FIG. 5.

(2) When the power is turned on, the MPU 30 checks the write recording density setting of the drive via the drive interface circuit 32a, and stores the write recording density setting of the drive in the write recording density of the area EA of the RAM 3 lb. Then, the initial setting process (1) shown in FIG. 6(A) is performed.

That is, the MPU 30 clears the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 31 to zero, sets the buffer free capacity FSEC in the data buffer management area DA to the maximum of 256 units (256 KB), and sets the data buffer address BADR to "00". Set.

Further, the maximum block length MAXL of the data buffer management area DA is set to the minimum 8 units (8 KB), and the logical EOT mode flag of the area EA is turned off to complete the initial setting (1). Note that the logical EOT mode is set separately from the normal physical EOT mode, and will be described later.

■Next, when the power is turned on, after the initial settings are completed after executing the REW command or the UNL command, or in the startup waiting routine from the host, the MPU 30 sends the magnetic tape to the supply reel 1 via the bus 35 and the drive interface circuit 32a.
Check whether the online state is set to 2.

If the MPU 30 is in the online state, the MPU 30 checks the register contents of the host interface circuit 32b via the hash 35, and receives a REW (rewind) command or UN from the host.
Check whether an L (unload) command has arrived.

■If a REW command or UNL command has arrived, the MPU
30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not being executed.

If the execution processing mode is read type, pre-reading of drive 1 is stopped. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped.

On the other hand, if the execution processing mode is a write type, all write type instructions in the instruction bar CBUF are executed.

Then, after all instructions have been executed, if there is no process being executed, or after the prefetch process of the drive has stopped, the MPU 30 sends a REW instruction (returns the tape to BOT) or a UNL instruction (winds up the tape) via the drive interface circuit 32a.
and have the drive l execute this, and return to the initialization in step ① (return to step 11).

(2) On the other hand, if the REW command or UNL command has not arrived, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35, and checks whether there is activation (Go) from the host.

If there is no activation from the post, the process waits for activation and returns to step ■.

(2) When it is determined that there is activation from the host, that is, a Go signal has been received, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35, and determines what the given command is.

If the given command is a read-related command, the process goes to step [phase], and if it is a recording density setting, goes to step (2) to execute the processing routine.

■If the command is recording density setting, the MPU 30 notifies the host interface circuit 32b that the data busy DBY is turned on, and also notifies the drive interface circuit 32
It is checked whether the magnetic tape 16 of the drive 1 is located at the load point LDP, ie, BOT, via a.

If it is at the load point LDP, the recording density setting command is valid, so the MPLI 30 executes the recording density setting command to the drive via the drive interface circuit 32a, and then changes the write recording density from the host to the area EA of the RAM 31b. Cent the indicated recording density.

If it is not at the load point LDP, the recording density setting command is invalid, and there is no need to execute the recording density setting command to the drive or to set the write recording density.

After that, the MPU 30 uses the host interface circuit 32
A completion report is sent to the host via b, the data busy DBY is turned off, and the process returns to step (2).

(2) On the other hand, if the given command is a write type command, the MPU 30 checks whether the execution processing mode of the drive control section 2 is read type, write type, or is not currently being executed.

If the execution processing mode is read type, the preread processing of drive 1 is stopped. That is, when the drive control unit 2 finishes the process being executed, the drive interface circuit 32
The drive control section 2 is not instructed to perform new processing from the control line 36a via the control line 36a, and the read-related processing is stopped.

Next, execute the initial setting (2) in FIG. 6(B), and
30 is the instruction puffer management area CA of RAM3 lb
Clear the instruction storage number CBSTK to zero, and set the buffer free capacity FSEG of the data buffer management area DA to the maximum of 2.
56, and the data buffer address BADR is “00’.
Set to .

(2) After this step (2) is completed, or if the drive control section B 2 is not being executed, the buffer size is set in the initial setting (3) of FIG. 6(C).

First, the MPU 30 is a drive interface circuit 3.
Check whether the EWA (area near the end of the tape) signal on the signal line 36b is on or off via the signal line 2a, and if it is off (has not yet reached the area near the end of the tape), turn on the LEOT mode flag in area EA of RAM3 lb. Then, the travel counter ECTR is cleared to zero.

On the other hand, if the EWA signal is on, the LE of RAM3 l b
It is checked whether the OT mode flag is on (YES) or off (No), and if it is off, the final limit value CBE of the instruction buffer 1 management area CA is moved to the buffer size CB51ZE, and the process returns.

Conversely, after the LEOT mode flag is turned on or the aforementioned travel counter ECTR is cleared to zero, the MPU 30 controls the RAM 3
Buffer size C of instruction buffer management area CA of b
Set the maximum value "64" to BS i ZE and return.

Next, in order to adjust the tape position, the MPU 30 sends a tape position adjustment command (space or backspace) to the drive control unit 2 to the drive interface circuit 3.
Command via 2a.

The program then proceeds to a write-related processing routine in FIG. 7, which will be described later.

(2) On the other hand, if the execution processing mode is write type in step (2), the process immediately proceeds to the write type processing routine.

If the instruction transferred at step 0 is a read type, the MPU
30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not being executed.

If the execution processing mode is a read system, the MPU 30 first checks whether the read directions match and stops the preread processing of the drive 1 if the read directions do not match. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped.

Furthermore, MPtJ30 has the same initial settings (2
), and then perform the same tape position adjustment as in step (2).

On the other hand, if the execution processing mode is write, the instruction buffer C
Execute all instructions in BUF.

Then, after all instructions have been executed, if there is no process being executed, or after the drive process has stopped, the above-mentioned prefetch read instruction is
AM3 LB Read command register RC is set to 1-.

After this set or if the lead direction matches, the 8th
Proceed to the read-related processing routine shown in the figure.

Therefore, if the activation from the host is a write-related command, even if read-related processing is in progress, it switches to write-related processing, and if it is write-related processing, write-related processing is continued.

In the initial setting (1), the maximum block length MAXL is set to the minimum unit of 8, and in the initial setting (1) or (2), the instruction memory number C
BSTK is 0, data buffer free space (IFSEG is maximum 256, data buffer address BADR is (00
), and further initialize (3) the buffer size CBS i
ZE is cented to the maximum 64 or the final limit value CBE depending on whether the LEOT mode is on or off.

Also, the recording density at the time of writing from the load point I-LDP is set in the area EA of the RAM3 lb.

(Explanation of dl vs. host processing behavior FIG. 7 is a flowchart of host write system processing.

■When the MPU 30 is activated by a write command from the host controller as shown in FIG. Read and compare via . CB51ZE≦CBSTK,,! I] If write-related commands are stored in the instruction buffer CBUF up to the number of instructions that can be stored, storage of the write-related commands in the instruction buffer CBUF is suspended.

On the other hand, if CBS i ZE>CBSTK, Rai I
- Since related instructions can be stored in the instruction buffer CBtJF, the MPU 30 stores related write instructions in the data buffer 34.
Find out if you want to use it.

If the erase/write tape mark data buffer 34 is not to be used, the data busy DBY is turned on and the process proceeds to step (2), the step of initializing the final limit value CBE.

As shown in Figure 5 (A), the startup (G
o) When the command is given, the lower order (preemption control unit 3
) turns on the data busy CBY signal indicating that the instruction is being executed and returns it to the upper level. This relationship is the same even when the prefetch control section 3 is placed at the upper level and the drive control section 2 is placed at the lower level.

Conversely, the MPU 30 writes write instructions to the data buffer 34.
If it is a normal write instruction using , it is determined whether automatic transfer to the data buffer 34 is permitted.

That is, first, the MPU 30 reads the free buffer capacity 1FSEG and the maximum block length MAXL of the data buffer management area DA of RAM3 lb, and determines the free buffer capacity FS.
Check whether EG is greater than or equal to the maximum block length MAXL. If the free buffer capacity 1FsEG is less than or equal to the maximum block length MAXL, the reception of write data is suspended and the data buffer 3
4 waits until the maximum block length MAXL becomes free, and if the free buffer capacity 1FsEG is greater than or equal to the maximum block length MAXL,
Allow transfer. Therefore, the aforementioned data busy DBY signal is turned on to notify the host controller that transfer is possible.

Next, the MPU 30 checks whether the magnetic tape 16 of the drive 1 is located at the load point I-LDP via the drive interface circuit 32a.

If it is not at the load point LDP, the final limit value CBE has already been sent, and the process proceeds to the next automatic transfer step (2). On the other hand, if the load point is at the position of 1-LDP, the final limit value CBE will be set depending on the write recording density.
First 1 [JJ set i.

That is, the MPU 30 checks the write recording density of the mode area EA of the RAM 3 lb, and finds that the write recording density is 160.
If it is 0rpj, set "8" to the final limit value CBE of the instruction buffer management area CA of RAM3 lb, and set 6250rpj.
If i, the final limit value CB is similarly initialized to "16" and the process proceeds to step (2).

Next, the MPU 30 checks whether the write-related instruction uses the data buffer 34 or not.

If the data buffer 34 is not used, step ■
Proceed to the instruction storage step.

On the other hand, if the data buffer 34 is used, data transfer is executed.

That is, the MPU 30 reads the first buffer address BADR of the data buffer management area DA of the RAM 3 lb, sets it in the store address counter 5CTR of the data transfer control circuit 33, and activates the data transfer control circuit 33. As a result, the data transfer control circuit 33 sends a data transfer request from the data transfer control signal line 39a to the host controller).
・Send to Laura.

Therefore, the host controller transfers the write data from the write data bus 39b to the data buffer 34, and stores the write data in the store address counter 5CTR of the data transfer control circuit 33.
The write data is transferred to the data buffer 34 according to the address of
is stored in The store address counter 5CTR counts up every time one write data is transferred.

■When the data transfer control circuit 33 determines that the data transfer has ended, the MPU 30 reads the store address counter 5CTR of the data transfer control circuit 33, calculates the difference between the buffer address BADR of the data buffer management area DA, and stores the transferred write data. Find the number of bytes BG.

Next, the MPU 30 uses the RAM 31. b's instruction buffer CB
Updates the UF and data buffer management area DA.

First, the buffer address BADR of the data buffer management area DA of RAM3 lb (i.e., the start address of the write data) and the calculated hide number BC of the write data are stored in the relevant instruction column of the instruction buffer CBUF of RAM3 lb. .

Next, data buffer management area D of RAM3 lb
The number of used units USEG of the data buffer 34 is subtracted from the free space 1FsEG of A, this free space (iFsEG is updated, and the number of used units U is added to the buffer address BADR.
Add SEG and update the start address BADR.

Next, the MPU 30 compares the above-mentioned number of used units (reception block length) USEG with the maximum block length MAXL of the data buffer management area DA of the RAM 3 lb.

By this comparison, if the number of used units USEG is larger than the maximum block length MAXL, the data buffer management area DA
The maximum block length MAXL is updated to the number of used units USEG. Furthermore, the final limit value CBE is changed according to the recording density and the maximum block length MAXL.

That is, the MPU 30 reads the write recording density of area EA and the maximum block length MAXL of area DA of RAM3 lb, and when the recording density is 1600 rpi, if the maximum block length MAXL is greater than "16", the final limit value is set to the minimum value. If the maximum block length is "16" or less, the final limit value CBE is set to "4".

Similarly, when the recording density is 6250 rpi, if the maximum block length MAXL is greater than "32", the final limit value CBE
is set to "2", and the maximum block length MAXL is set to "17" to "3".
2", the final limit value CBE is set to "4", and if the maximum block length MAXL is "16" or less, the final limit value CBE is set to "4".
8”.

Conversely, the number of units used USEG7'l<maximum block length MA
If it is less than XL, the maximum block length MAXL, final limit value C
Proceed to the next step without updating the BE.

Next, the MPU 30 performs storage processing of the received write-related command.

First, the MPU 30 uses the instruction buffer C of the RAM 3 lb.
The received command of the host interface circuit 32b is stored in the BUF.

Next, the MPU 30 sets the instruction storage number CBSTK to "
1” is added and updated.

(2) Furthermore, the MPU 30 checks the drive interface circuit 32a to check whether the EV/A (tape end vicinity detection) signal on the control line 36b is on or off. If it's off,
Since the magnetic tape 16 has not reached the vicinity of the end of the tape,
Proceed to step ■.

On the other hand, if it is on, the tape has reached the vicinity of the end, so check the LEOT flag in area EA of RAM3 l b and if it is in LEOT mode, set the instruction buffer size CBS i
Since there is no need to change ZE, proceed to step (2).

Conversely, if it is not the LEOT mode, the MPU 30 is RAM
Instruction buffer size CBS i of area CA in 31b
Read and compare ZE and final limit value CBE.

Instruction buffer size CBS i ZE is the final limit value CB
If it is less than E, the instruction buffer size CB51ZE is not changed and the process proceeds to step (2). Conversely, the instruction buffer size CB
If S i ZE is larger than the final limit value CBE, "2" is subtracted from the instruction buffer size cBsiZE, updated, and the process proceeds to step (2).

Next, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), performs a drive activation process which will be described later with reference to FIG.

■During processing or when drive startup processing is performed, MP
U30 is TWA indicating that the drive control unit 2 has detected EOT via the drive interface circuit 32a.
Check whether a signal is generated from the control line 36a.

In addition, in the LEOT mode, the MPU 30 operates in the first
It is checked whether the traveling counter ECTR updated by the drive-related processing shown in FIG.

If TWA signal is generated by EOT detection or LE Oi
゛If it is on, the MPU 30 checks whether the number of stored instructions (number of unexecuted instructions) CBSTK in the instruction buffer management area CA of the RAM 31b is zero, and if it is not zero, waits until it becomes zero due to drive execution. . This is EOT, LE
This is to synchronize the commands from the host and the commands executed by the drive in the processing after OT.

When the TWA signal is not generated or when LEOT is off, the MPU 30 checks the state of the data transfer control circuit 33 to determine whether the write data transfer in step (3) has overflowed due to insufficient free space in the data buffer 34.

If an overflow occurs, in order to synchronize as described above, the MPU 30 checks whether the number of stored instructions (number of unexecuted instructions) CBSTK in the instruction buffer management area CA of the RAM 3 lb is zero, and if it is not zero, executes the drive. Wait until it becomes zero.

When there is no panf overflow or CBST
When K becomes zero, the MPU 30 reports completion (normal reception or error) to the host controller from the host interface circuit 32b, turns off the data busy DBY signal, and returns to the start-up waiting routine of FIG.

FIG. 8 is a flowchart of host read system processing.

■When a read-related command is received in step [phase] of the startup processing flow in FIG. 5 and startup processing is performed, the MPU 30
turns on the data busy DBY via the host interface circuit 32b and notifies the host computer 1-o-rah of the start of execution.

[Yes] Next, the MPU 30 subtracts "1" from the number of pre-read blocks CBSTK in the area CA of the RAM3 lb.

Furthermore, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), the MPU 30
Drive startup processing, which will be described later in the figure, is performed.

In addition, the MPU 30 checks whether the instruction storage number (preread block number) CBSTK of the area CA mentioned above is equal to or greater than rOJ, and determines "0.
”, the read data has not been transferred to the data buffer 34, so CBSTK is “0”.
'', that is, wait until one or more blocks of read data from the drive 1 is transferred to the data buffer 34.

When the number of pre-read blocks CBSTK becomes "0" or more, the read data should have been transferred from the drive 1 to the data buffer 34, so the MPU 30 transfers the data to the RAM 31.
The read execution result from the instruction buffer CBUF of b and the start address RADR in the read data data sofa 34.
Then, the read-hide number RBC is read out.

0 Next, the MPU 30 determines whether load point 1-LDP was detected at the time when the drive processed the block based on the read execution result issued from the instruction buffer CBUF of the RAM 31b in the above-mentioned step (3). If D P is detected, change the lead direction, and if it is the lead reverse direction, B before block detection.
Since the OT has been reached and the read data has not been transferred to the data buffer 34, the process advances to step (2).

On the other hand, if the read direction is the read forward direction, the first block was read from the load point LDP, so the recording density is checked from the read execution result. The recording density of the read execution result indicates the recording density of the read magnetic tape.

If the recording density is 1600 rpi, the final limit value CBE for the instruction buffer management area C of the RAM 31b is "8".
”, and if the speed is 6250rpi, the final limit value CBE is “
16” cents.

Furthermore, if the MPU 30 has not detected the load point I-D P or after setting the final limit value CBE,
From the read execution result, it is checked whether a tape mark indicating a file break was detected at the time of read execution, and if a tape mark was detected, the data is not transferred to the data buffer 34, so no data transfer is performed.
Proceed to step ■.

If no tape mark is detected in J, step [
Proceed to the automatic transfer step.

(2) First, the MPU 30 determines whether the above-mentioned read-related command involves data transfer. Read commands that do not involve data transfer include Space, Back-5pace, Space File (3pace File), and Pax Base File (13ack5pace File).

If it is a read-related command that involves data transfer, the data transfer to the host 1-controller is executed.

That is, the M P LJ 30 is the first address RA read from the address CBUF of the RAM 31b.
DR is sent to the load address counters LC and TR of the data transfer control circuit 33, and the read/hide number is sent to the byte counter BC.
TR is set, and the data transfer control circuit 33 is activated.

As a result, the data transfer control circuit 33 transfers the read data in the data buffer 34 to the host controller in accordance with the read strobe pulse R3TB (FIG. 4(A)) and the addresses of the load address counters L and CTR. The load address counter LCTR counts up every time one read data is transferred.

■When the data transfer control circuit 33 determines that data transfer for the number of read bytes has been completed, the MPU 30 transfers data from the RAM3 l b
Number of units USEG used in area DA vacant 8 FSEG
Add and update.

On the other hand, since the read data is transferred to the data buffer 34 even in a read-related instruction that does not involve data transfer, the free capacity PSEG is updated in the same way.

Next, the MPU 30 checks whether the aforementioned read-related command is a file search (File 5 search)-based command (space file or bank space file), and if it is a file search-based command, returns to step (2). In other words, the file search type command is divided into read commands.

■On the other hand, if step ■ is not a file search type command, or if step ■ is a reverse read direction, or if a tape mark is detected, MPU3 is sent to the host controller.
0 indicates completion report from host interface circuit 32b (
Normal reception or error) and data busy DBY
The signal is turned off and the process returns to the start j wait routine shown in FIG.

In this way, in the light system processing, the logical E
In O'r mode, the buffer size CBS i ZE
In step (2), the logical EOT is turned on without reducing the limit, and in step (2), the prefetch command is prohibited in the same way as when normal EOT is turned on.

On the other hand, when the physical EOT mode is not the logical EOT mode, the final limit value CBE is changed according to the recording density and the maximum block length MAXL (step ■), and E
In the WA, the buffer size is sequentially reduced in step (2).

Further, in read-related processing, prefetching is performed regardless of the type of read-related instruction.

(Explanation of ell drive processing operation FIG. 9 is a flowchart of drive activation processing.

(i) The MPU 30 uses the RAM 3 to start the drive.
The next instruction to be executed is read from the instruction buffer CB U'F of lb, and it is checked whether it is a write type instruction.

If it is not a write-related instruction, that is, if it is a read-related instruction, M
PU30 checks whether the number of pre-read blocks CBSTK in area CA of RAM3 lb is a negative value smaller than zero.
If BSTK is greater than or equal to zero, prefetching has already been performed, so check whether it is okay to start. Returns if it cannot be started (an error was detected during read ahead and stopped).

On the other hand, if activation is possible, it is checked whether the number of pre-read blocks CBSTK in area CA of RAM3 lb is smaller than "63". If it is not small, RAM3 l b instruction buffer CBU
Returns because F is full.

On the other hand, if the number of pre-read blocks is less than 63, it is checked whether the free space 1.''SEG is greater than or equal to 64 bytes, and if it is less than 64 bytes, the process returns as data transfer is not possible.

(ii) If the free space 1FsEG is 64 bytes or more in step (i), it is possible to transfer data from drive 1, so the MPU 30 moves to the starting address BA of RAM 3 l b.
DR is set in the address counter 5CTR of the data transfer control circuit 33, and the data transfer control circuit 33 is placed in a standby state.

Next, the MPU 30 drives the drive interface circuit 32
Check whether the EWA signal is on or off from a, and turn it on (YE
S), it is in EWA, so LE of RAM3 l b
Turn off the OT mode flag and cancel LEOT mode.

Furthermore, the MPU 30 checks whether the read-related command is a read reverse, and if it is a read reverse, turns off the logical EOT.

After this off, or when the EWA signal is not off or read reverse, the MPU 30 activates (G) via the drive interface circuit 32a.

) signal and the relevant read-related command to the drive 1, and return.

(iii) On the other hand, if it is determined in step (i) that it is a write-related command, preparations for automatic transfer to the drive are made.

That is, the MPU 30 uses the instruction buffer C of the RAM 3 lb.
The relevant write-related instruction is read from the BUF, and it is checked whether this instruction involves data transfer. If the instruction involves data transfer, the MPU 30 uses the instruction buffer CB of the RAM 31b.
The start address WADR of the UF and the number of bytes WBC are sent to the load address counter LATR of the data transfer control circuit 33.
, respectively set in the byte counter BCTR.

Furthermore, the data transfer control circuit 33 is put into a standby state.

After this standby state, or if it is a write-related command that does not involve the aforementioned data transfer (erase, write 1-tape mark, etc.), the MPU 30 will read the read command and start < Go
") signal is issued to the drive control unit 2 from the control line 36a via the drive interface circuit 32a, and returns.

On the other hand, the drive control unit 2 performs the step (ii) described above.
, (mountain) receives a start signal and command, it responds by turning on data busy DBY and starts executing the command.

For example, in the case of a write command that involves data transfer, a data transfer request is sent to the data transfer control circuit 33 from the data transfer control signal line 37a after data transfer preparation is completed. As a result, the data transfer control circuit 33 sends write data corresponding to the number of bytes of the byte counter BCTR from the start address indicated by the load address counter LCTR of the data buffer 34 to the drive control unit 2 via the write data bus 37b, and causes the magnetic tape to be executed. Write to 16.

Furthermore, when the execution of the write-related command in the drive control section 2 is completed, a completion report is sent to the drive interface circuit 32a via the control line 36a. The drive interface circuit 32a thereby
0 and interrupts the processing shown in FIGS. 5 to 8.

FIG. 10 is a flow diagram of the drive write 1-/read processing.

(iv) Upon receiving the completion report from the drive, the MPU 30 checks whether the type of the completed command is read or write, and if it is read, the process proceeds to step (vii).

On the other hand, if the completed instruction type is Lie 1-type, the MPU30
checks whether the EWA signal is on or off via the drive interface circuit 32a. If it is off (No), proceed to step (vi).

If the EWA signal is on (YES), the area near the termination (
EWA), the MPU 30 checks the LEOT mode flag in the area EA of the RAM 31b to determine whether it is in the LEOT mode.

If not in LEOT mode, normal physical rEOT
mode, proceed to step (vi).

Conversely, in LEOT mode, the progress of the travel counter and the LE
Proceed to step (v) to detect the OT detection point.

(■) First, MPU30 is RAM3 l b area E.
Check the write recording density of A.

Whether the recording density is 6250rpi or 1600rpi is determined by the write tape mark length WTM1. This is to make the erase length ER3, IBG length, and determination value EPTR different, but the processing itself is completely the same.

That is, the MPU 30 checks whether the instruction in the instruction buffer CBUF is a write instruction, erase variable pull instruction, write tape mark instruction, or fixed erase instruction.

If the instruction is a write instruction or an erase variable pull instruction, the number of bytes RBC of the instruction buffer CBUF is the number of units used US
It is converted into EG and updated by adding it to the travel count value ECTR in area EA of RAM3 lb. Furthermore, if the command is a write tape mark command, the fixed value of write 1-tape mark length WTM is similarly added to and updated to the running count value ECTR.

Furthermore, if the instruction is a fixed erase instruction, the fixed erase length E
Similarly, R3 is added and updated to the traveling count value ECTR.

Further, the IBG length is added to the running count value ECTR and updated.

Next, the MPU 30 compares this running count value ECTR and the determination value EPTR in order to detect the LEOT detection point.

If ECTR≧EPTR, the LEOT detection point has been reached, so logical EOT is turned on. If ECTR<EPTR, logical EOT is not turned on.

(vi) Next, the MPU 30 asks whether the write-related instruction uses the data buffer 34, and if it uses the data buffer 34, the MPU 30 determines the number of units used in the free space 1FsEG of the data buffer management area DA of the RAM 3 lb. Add USEG and update free capacity FSEG.

Next, after this update or when the data buffer 34 is not in use, the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 3 lb is subtracted by "1" and updated.

Furthermore, the MPU 30 has the instruction storage number C of the RAM 3 lb.
Check whether BSTK is zero, and if it is zero, return to the routine in Figure 5 or Figure 7; if not, go to step (iii) in Figure 9.
) and the rest.

In this way, the drive sequentially executes the instructions in the instruction buffer asynchronously with the host controller.

(vi) On the other hand, if the instruction type is determined to be a read type in step (1v), the MPU 30 checks whether the instruction is a read reverse, and if it is a read reverse, the drive 1 is loaded via the drive interface circuit 32a. Test 8 times to see if point LDP is detected. If the load point detection signal is not rising, and if the command is read forward, it is checked via the drive interface circuit 32a whether the tape mark detection signal is rising.

If the tape mark detection signal is not rising, the number of bytes BC of read data transferred to the data buffer 34 upon completion of drive processing is calculated.

That is, the MPU 30 reads out the store address counter 5CTR of the data transfer control circuit 33, calculates the difference between it and the buffer address BADR of the data buffer management area DA, and obtains the number of hides BC of the transferred read data.

Next, the MPU 30 uses the instruction buffer C of the RAM 3 lb.
, BUF and data buffer management area DA.

First, in the instruction column of the instruction buffer CBUF of RAM3 lb, write the low sofa address (■1st address of the first J selling data) BADR of the data buffer management area DA of RAM3 lb and the calculated read data. The number of bytes BC is stored.

Next, data buffer management area D of RAM3 lb
Subtract the number of used units of the data buffer 34 USEG from the free capacity FSEG of A, and calculate this free capacity F S E G
Then, the number of used units USEG is added to the buffer address BADR, and the start address BADR is updated.

Furthermore, the MPLJ 30 checks whether the drive 1 operates in the forward direction and detects EOT.

If YES, read execution result (EOT)
nip) is stored in the corresponding read data storage column of the instruction buffer CBUF, and the process returns to the routine of FIG. 5 or FIG. 8.

Similarly, in the case of LDP detection (load point in tape mark detection and read reverse), the instruction buffer CBUF
This is stored in , and the process returns to the routine shown in FIG. 7 or 8.

On the other hand, if the result of the above-mentioned EOT detection etc. of the MPU 30 is NO, the read execution result (non-detection) is similarly stored in the corresponding read data storage column of the instruction buffer CBUF.

Furthermore, the MPU 30 checks whether the number of pre-read blocks CBSTK in area CA of RAM3 lb is 63 or more, and if it is 63 or more, returns to the routine of FIG. 5 or FIG. To do so, return to step (1) in FIG.

(f) Description of overall operation The operations shown in FIGS. 5 to 10 can be summarized as follows.

In the write system operation, (1) A logical EOT mode is provided in addition to the normal physical EOT mode.

That is, as shown in FIG. 11(A), when the magnetic tape drive section l runs the magnetic tape 16 and detects an area near the end of the magnetic tape (EWA), the prefetch control section 3 detects the magnetic tape from the time near the end area. The running distance of the tape is counted, and when the counted value ECTR reaches a certain value EPTR, it is considered that the tape end area has been detected, and a pseudo EOT is obtained.

This pseudo EOT (logical EOT) has the same effect as normal physical EOT detection, whereby the EOT is handled before actually detecting the EOT marker provided on the magnetic tape.

As a result, as shown in FIG. 11(A), the TWA can be lengthened by making the EOT detection time earlier. As a result, the number of blocks that can be written to the TWA increases, so there is no need to reduce the number of prefetching write-related instructions in the EWA, as shown by the solid line in FIG. 11(B).

Therefore, the host controller is not subject to any prefetch restrictions for write-related commands in the EWA, so it is possible to prevent performance deterioration in streaming running.

That is, as shown by the solid line in FIG. 11 (tc), ideal prefetch control is possible in which the number of instructions prefetched is as large as possible until near the EOT, and as the EOT approaches, the number is reduced to a writable number.

As a result, it will not become impossible to write to TWA,
Performance deterioration can be prevented.

(2) Therefore, in the initial setting (1) of step (2) in FIG. 5, ie, fcl in FIG. 6, in the LEOT mode, the buffer size CBS i ZE is the maximum "64" and is not subject to reduction restrictions.

That is, in the logical EOT mode, the buffer size CB51ZE is not gradually reduced, ie, the reduction limit is not performed in step (2) in FIG.

Then, in step (v) of FIG. 10, the tape running distance from the detection of the early warning area EWA is measured as the running count value ECTR, and this is the limit value E
When PTR is reached, LEOT is turned on as a logical EOT point detection, and the normal E is turned on in step
The same treatment as OT detection is performed.

Therefore, in LEOT mode, the first
As shown by the solid line in Figure 1 (B), the buffer size CBS i Z
CBS i ZE is not limited by E, and when the LEOT point is detected, CBS i ZE becomes substantially zero as in the EOT mode.

Therefore, in the LEOT mode, the number of stored instructions CBSTK decreases from the detection of the LEOT point, as shown by the solid line in FIG. 11(c).

(3) Furthermore, in the LEOT mode, as shown in step (ii) in Figure 9, if the count value cannot be guaranteed due to reception or execution of a read-related command after tape travel distance counting starts (after EWA is turned on),・Logical EOT mode turns off and shifts to normal EOT mode.

(4) On the other hand, in normal physical EOT mode,
Initial setting (■) of step ■ in Fig. 5, that is, Fig. 6 (C
1, the buffer size CB51ZE is the final uniform value C
Changed by BE.

Also, in step ① of Fig. 7, this final limit value CB
E is changed depending on the recording density and maximum block length.

If it is physical EOT mode, step ■ in Figure 7
In the early warning area EWA, the bar size CBS i ZE decreases by "2" if it is equal to or larger than the final limit value CBE.

For example, the number of write instructions that can be accumulated in the instruction buffer is 64.
is gradually decreased as shown by the dotted line in FIG. 11(B).

Therefore, in order to limit the number of write-related instructions that can be stored, write-related instructions such as erase and write tape mark that do not involve write data are also limited, so all write-related instructions can be stored within the magnetic tape (especially within the TWA). can be executed, and can prevent write-related instructions from being unable to be processed.

That is, when the tape reaches near the end and the EWA signal turns on, the buffer size CBS i ZE is decreased from the maximum value "64" by "2" each time a write command is received from the host controller, that is, the number of instructions allowed to be stored gradually decreases. Decrease. Furthermore, when the TWA (EOT) signal is issued, no completion report is made until the instruction storage number CBSTK becomes zero.

Therefore, the number of prefetch instructions gradually decreases as shown by the dotted line in FIG. 11(C).

This gradual decrease prevents the host controller from taking an extremely long time to accept the next command. On the other hand, if the number decreases all at once, the host controller will not accept the next instruction until the drive executes the number of instructions equal to (Number of accumulated instructions) - (Number of instructions that can be accumulated after reduction - 1). Therefore, the host controller's time monitoring will treat the device as abnormal due to a timeout, causing inconvenience.

Therefore, this inconvenience can be prevented by gradual reduction. This gradual reduction is performed when the final limit value CBE is greater than or equal to the final limit value CBE, and the final limit value CBE is sequentially changed according to the recording density and the maximum block length.

(6) Also, as shown in step ① in Figure 7, when a host controller activates (Go) and a write command is given, it is first checked to see if the number of instructions that can be stored in the instruction buffer is within the number of instructions that can be stored. If the number is within the allowable number, this command is accepted; if the number exceeds the storable number of commands, acceptance of this command is suspended and the data busy DBY is not raised.

That is, as shown in FIG. 4(B), the drive side executes the instructions in the instruction buffer and does not increase the data busy until the number of instructions is within the storable number of instructions. Notify the host controller that it is being executed.

Similarly, in step (2), it is checked whether the free space in the data buffer is greater than or equal to the maximum block length, and if it is greater than or equal to the maximum block length, the write data is transferred from the host controller, and if it is less than the maximum block length, data transfer is not performed. Do not raise data busy DBY on hold.

Therefore, the drive side executes the instructions in the instruction buffer,
Data busy is not raised until the free space of the data buffer exceeds the maximum block length, and when it becomes equal to or greater than the maximum block length, data busy is raised to enable transfer acceptance.

Then, in step (2), if the transferred block length is larger than the maximum block length, the actually transferred block length is adopted as the maximum block length from next time onwards.

Therefore, the effect of reducing the number of retries and shortening waiting time is produced.

(g) Description of other embodiments In the embodiments described above, in the physical EOT mode,
The number of write-related commands that can be stored is gradually reduced each time a write-related command is received from the host, but it may be reduced all at once, or it may be gradually reduced each time multiple instructions are executed on the live side. Good too.

Further, the drive control section 2 and the command data prefetch control section may be integrated, and the drive 1 may also have a tape buffer.

Furthermore, there is no logical EOT mode, and physical RO
Even if it is only T-mote, the maximum block g M A
XI- may also be changed in steps instead of being changed depending on the receiving block.

Although the present invention has been described above with reference to examples, the present invention can be modified in various ways according to the gist of the present invention, and these modifications are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the final limit value C in the early warning area EWA of write-related instructions
Since BE is determined according to the recording density and maximum block length, the final limit value CBE can be set to the optimal value, and prefetch control of write-related instructions that can maximize the performance of the device is possible. This has the effect of making it possible.

In addition, since the number of write-related instructions that do not involve data transfer is also limited in the number of pre-fetching instructions, it is possible to execute all write-related instructions stored in the instruction buffer.
Inconveniences occurring at the tape end can be prevented by prefetching instructions in a magnetic tape device having such a buffer.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an overall configuration diagram of an embodiment of the present invention, Fig. 3 is a main part configuration diagram of the configuration shown in Fig. 2, and Fig. 4 is a data transfer diagram of the configuration shown in Fig. 2. 5 is a flowchart of the startup process of an embodiment of the present invention, FIG. 6 is a flowchart of the initial setting process of FIG. 5, and FIG. Write-related processing flowchart, Fig. 8 is a read-related processing flowchart for the host, Fig. 9 is a start-up processing flowchart for the drive, Fig. 10 is a write/read processing flowchart for the drive, and Fig. 11 is an explanation of the overall operation. FIG. 12 is an explanatory diagram of instruction prefetch control of the gftft-pull device, and FIG. 13 is an explanatory diagram of the prior art. In the figure, 1-magnetic tape drive unit, 2-drive control unit, 3-instruction/data prefetch control unit, CBUF-instruction buffer, 34-data buffer.

Claims (2)

[Claims] (1) A magnetic tape drive unit having a magnetic head and a magnetic tape drive mechanism; a buffer unit capable of preemptively storing multiple commands given from a higher level; and controlling the magnetic tape drive unit according to the commands stored in the buffer unit. and a control section that executes the instructions, wherein the control section detects the vicinity of an end region of the magnetic tape run by the magnetic tape drive section, and controls the buffer based on the detection of the vicinity of the end region. Instruction prefetch control for a magnetic tape device, characterized in that the number of write instructions that can be preemptively accumulated in a section is limited, and the final limit value is determined based on a recording density and a maximum block length of write instructions. Method. (2) a magnetic tape drive section having a magnetic head and a magnetic tape drive mechanism; an instruction prefetch control section having a buffer section capable of preemptively storing a plurality of instructions given from a higher level; A magnetic tape device comprising: a drive control section that controls a magnetic tape drive section to execute the instructions, the instruction prefetch control section managing the number of instructions that can be stored in the buffer section, and controlling the drive control section. The number of preemptive write instructions that can be accumulated is limited based on a detection signal indicating the vicinity of the end area of the magnetic tape from the storage unit, and the final limit value is determined based on the recording density and the maximum block length of write instructions. An instruction prefetch control device for a magnetic tape device, characterized in that it is configured to: