JPH07104817B2 - Data record transfer method - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to data processing subsystems, particularly DASD data storage subsystems which have a large cache and which are connected to the host processor through one channel having a higher data rate than the peripheral device. It is about the system.

[0002]

BACKGROUND OF THE INVENTION Peripheral data storage systems attached to large scale host processors are direct access storage devices (DASD).
, But the device typically takes the form of a rotatable magnetic memory device. Between the host processor and DASD to increase performance,
Large random access memory caches are selectively interleaved to increase the data transfer rate between the host processor and peripheral subsystems. That is, the cache helps hide the latency delay of DASD. Conventionally, algorithms have been developed to handle the relationship between the host processor, cache and DASD. Without such an algorithm, performance would have been reduced by the intervention of the cache. However, performance and integrity issues have always been of interest. Therefore, new controls and procedures are needed. Machine operations have been devised to solve these problems in situations where the data burst rate of the channel connecting the host processor to the peripheral subsystem is close to the burst data rate of DASD. Host processor and DASD
Using one channel between peripheral subsystems with a larger burst data rate requires other algorithms and controls to ensure high performance while maintaining data and system integrity. Become. Yet another problem is that the length of the channel cable between the host processor and the peripheral subsystem becomes long and the signal propagation time increases. Such increases in signal propagation delay as data rates increase significantly translate into performance when many control signals that cannot be overlapped in time have to be exchanged between the host computer and peripheral subsystems. Will be lowered.

In cache memory peripheral subsystems, it is common practice to provide so-called branch writes. These operations transfer data from the host processor to DASD and to cache at the same time.
A control unit or controller creates a new set of cache memory segments (one segment is an allocatable storage unit in the cache) when the DASD switches from one track to another that is not currently stored in the cache. Assign If the cache is full enough, especially when the subsystem is switching from the current track to the next, there will be no cache segment available to store the data for the upcoming track. There is a risk that it will be sufficient. In the above prior art, if sufficient cache segments are not available, the peripheral controller causes a track switch and channel command retry (CCR) (a known way for the peripheral controller to communicate with the host processor). Is to be done. This communication indicates a delay in the transfer of incoming data, and then the current command is retransmitted. The system then waits for the cache segment to become available. Once available, the peripheral controller is reconnected to the channel and continues with the branch write above. Also, newer peripheral subsystems operate in so-called asynchronous mode, in which the peripheral subsystem accepts data from the host processor for writing to cache and DASD, and presents an exit status to each command, Causes a data transfer even if the received data is not actually written to DASD. Therefore, when the subsystem process determines that track switching is needed and that an insufficient number of cache segments are currently available, it will not receive any more data until after the CCR above. When sending the CCR to the host processor, the peripheral subsystem is already accepting data from the host processor for the incoming track and thus presenting an exit status to the host processor, i.e. the data is already effectively stored on DASD. May indicate that CCR ensures data integrity without dedicating a channel to one data transfer. Such dedicated use reduces the availability of channels and therefore reduces the throughput of the overall data processing system. Data integrity problems can arise when the channel is subject to some kind of failure with loss of data in the peripheral subsystem when it is dedicated. When the peripheral data subsystem supplies an exit status to the host processor, the peripheral data subsystem is effectively informing the host processor that it is storing and holding the received data in the peripheral subsystem. Therefore, it is desired to provide an efficient and complete solution to the above problems.

US Pat. No. 4,040,027 (van Es) describes a method of controlling buffer memory to dictate available memory space. According to it, the data transfer is carried out from the first memory to the user device via the temporary storage and the intermediate second buffer memory. The system includes a measuring device that determines the extent to which the second buffer memory is filled with the information provided by the first memory while transferring the information from the second buffer memory to the user device. Upon detection of a predetermined first degree of filling, the measuring device generates a first alarm signal, which temporarily blocks further reading of information from the first memory after a given delay. That is, the data transfer is interrupted. After measuring a certain second degree of filling of the second buffer memory, the measuring device generates a second alarm signal, which signal after a given second delay from the first memory to the second buffer memory. Enable to resume reading information to. This patent provides a synchronous solution to the problems described in the background of the invention, but it is not suitable for efficient use in the case of high speed channels with long control signal delays.

US Pat. No. 4,298,954 (Bigelow et al.) Shows a buffer storage device with two buffers that alternately receive and supply data signals. The function of the buffer alternates between the two buffers; when one buffer is empty, the other buffer is receiving a predetermined number of signals, although it is not yet full of data.
If the data is transferred in blocks of data bytes, the switching between the buffers takes place on predetermined alignment boundaries of the data blocks. Alternation of functions among the buffers is accomplished by combining multiple individual data burst units, such as host processors and data storage units, using multiple buffer stores to determine which of the multiple address boundaries within the data receive buffer is to be used. Occurs in one or the other. Each data burst unit has a high speed buffer access for performing the data transfer. This patent also describes a mode in which there is a short response time in the control signal.

US Pat. No. 4,583,166 (Hartung et al.) Shows a cached peripheral data subsystem using a direct access storage device (DASD). This patent forms the background of a cache data storage system. In US Pat. No. 4,571,674, Hartung has another
Shows two cache data storage subsystems,
Here, one slow channel is connected via a data buffer to DASD with a higher burst rate than this slow channel. This cache provides two services. That is, one service is to cache data for the high speed channel and the other is rate changing buffering for the low speed channel.

[0007]

However, none of the above cited references address the data integrity and system integrity issues associated with high speed channels having long response times due to signal propagation delays. Not in.

[0008]

SUMMARY OF THE INVENTION In the method of operating a cached DASD peripheral subsystem of the present invention, an incoming update write operation instruction is first received. The instructions include the area of the file to be written to DASD and the cache. The amount of free cache space available is measured by allocating cache space to the records in the write area. Since the size of the write area is limited by the availability of cache storage space, the area is subset to allow maximum data transfer without causing the data integrity problems described above. . Ensures that at least one DASD track is stored in cache to recheck the number of available cache segments during track switching, eliminating track switching delays and allowing fast data transfer from the host processor. is doing.

In another aspect of the invention, an update write operation (ie, updating a file by the host processor) calculates the maximum cache size requirement that can occur. During data transfer, the calculated maximum cache requirements are adjusted according to the fragmentation of the data on DASD to maximize the availability of cache storage space for all purposes of this peripheral subsystem. In format writing, the calculation of available cache segments is performed at each track switching.

A data transfer length factor (TLF) is generated by the host processor. This factor contains a measurement of the data for one record in the file and the write area indicates the number of records. The maximum number of storage spaces or segments in the cache is determined to control the data transfer between the host processor and DASD.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Referring now to the drawings, like parts and structural features are designated by like numerals in the various views. In FIG. 1, the host processor 1
0 through the fiber optic channel 12 to the peripheral subsystem 19
It is connected to the. The subsystem 19 is the connection mechanism circuit 11,
Rate change buffer 13, controller / microprocessor
(Hereinafter referred to as microprocessor) 14, cache 16,
It comprises a data transfer circuit 18 and a plurality of DASDs 20, 21. Channel 12 is between a plurality of host processors 10 and a plurality of peripheral subsystems (of which many may be data storage subsystems and others may be other types of peripheral subsystems). The characteristics of the connector 12 are that the burst rate of data transfer is much larger than the burst data transfer rate of DASD 20,21, and the signal propagation time along the optical fiber between the host processor 10 and the peripheral subsystem is considerable. Something like that. The signal transit time, which depends on the length of the connection, hinders interactive control of data transfer on a real-time basis. That is, the host processor 10
And the time required for the DASD 20 to scan the gap previously used to exchange control signals between the peripheral data storage subsystem 19 is less than the bidirectional signal propagation time of the channel connector 12. Such imbalances in data transfer rates and signal propagation times give rise to data integrity and system integrity issues. The write operation, ie the transfer of data from the host processor 10 to the DASD 20 involves a so-called branch write operation. The data transferred from the host processor 10 via the connection mechanism circuit 11 is supplied via the rate change buffer 13 and the data transfer circuit 18, and DASD 2
Recorded on 0. The slow data rate is determined by the DASD 20 data rate. IBM's Extended Count Key Data (ECKD) control architecture is DA
Allows accommodating burst data transfers of several records without intervening SD 20 read control data mechanism. When writing data to DASD, a copy of the data to be written is also stored in cache 16. This operation is called a branch operation. The cache copy causes machine operations after writing data to DASD 20 to be performed at electronic speed between host processor 10 and subsystem 19. In a branch operation, the data is a rate change buffer.
The data is transferred not only on the buses 24 and 22 through the data transfer circuit 13 and the data transfer circuit 18, but also on the bus 23 and stored in an available segment of the cache 16. Similarly, branch read occurs during the read operation. In the branch read, the read data from the DASD 20 supplied via the data transfer circuit 18 is transferred via the rate change buffer 13 to the host processor.
In addition to being transferred to 10, it is stored in cache 16 via cable or bus 23. Although all of the operations described above are controlled and sequenced by the microprocessor 14, the microcomputer 14 sends control signals to and from all of the components of the peripheral subsystem via a set of electrical connections, generally designated by the reference numeral 27. Receive a data signal. Such operations include the update write control and the format write control described herein.

Referring now to FIG. 2, this machine operation flow chart illustrates the control performed by microprocessor 14 on the peripheral subsystem in response to commands provided by host processor 10. 1 of the present invention
In the preferred embodiment, command chaining is used between the host processor 10 of FIG. 1 and the peripheral subsystem. This command chaining is a well-known I / O control mechanism used by IBM for many years. The flow chart here reflects the use of command chaining.

The first command in the chain (FIG. 2) consists of two channel commands from the host processor 10. The DEFINE EXTENT command 30 limits the peripheral subsystem 19 to the address range on DASD 20 where the file to be processed in the next command chain resides. The DEFINE EXTENT command 30 contains a so-called file mask, which allows or disallows certain types of write operations in subsequent commands.
(For example, prohibit the format write described later, prohibit the update write, prohibit the cylinder seek, and allow the home address or the control record to be written on the DASD 20 or other control device.) DEFINE
The EXTENT command also indicates the block size, the beginning of the range (ie the starting address) and the ending address of the range. DEFIN
E EXTENT command 30 is followed by LOCATE RECORD command 31. This command establishes a write area that defines the range of subsequent write operations during this sequential command chain. This LOCATE RECORD command 31 creates a processing area for a write command issued within the channel processor of host processor 10 from a chained channel command word (CCW) in host processor memory. Various parameters are used in the known LOCATE RECORD command of IBM Corporation. LOCATE REC
The ORD contains the number of records or tracks to be processed (the number of records to be processed in this example). This command also contains the seek address (ie the location of the first record in the write area on DASD 20), the search argument and the sector number, and a transfer length factor can also be provided. In the CKD record architecture, the transfer length factor TLF is the number of bytes in each record in the file. Channel commands 30 and 31 are peripheral subsystems
Command 19 to prepare for incoming write operations.

In the peripheral subsystem designed and built by IBM, the machine operation step 32 and subsequent steps in FIG. 2 represent the operation of the peripheral subsystem commanded by the write command. LOCATE
The RECORD command 31 indicates the type of write operation to be performed at machine operation step 32 regardless of whether the received write command FORMAT WRITE command in the chain is being evaluated by the microprocessor 14. If FO
If the RMAT WRITE command should be executed, the TLF does not have to be accurate about the write area. However, with the FORMAT WRITE command (known IBM peripheral operation),
The host processor 10 knows when switching occurs between tracks on the DASD 20. Therefore, the host processor 10 uses the WRIT for switching to the next track.
Issue the E CKD NEXT TRACK command. This command indicates that the host processor 10 is instructing the peripheral subsystem to begin formatting the next or new track. Therefore, the largest available cache segment required for the FORMAT WRITE command is the cache segment for storing one track of DASD data in the cache, as is apparent from the machine operation shown in FIG.

If the operation instructed in step 32 is
If it is an UPDATE WRITE command rather than a FORMAT WRITE command then the available segment of the cache needs to be measured and compared to the size of the write area specified above in the LOCATE RECORD command 31. Peripheral subsystem controller is LOCA of current file to process
This state requires a worst-case state calculation, since it does not know the fragmentation of the record indicated by the TE RECORD command.

Fragmentation under worst-case conditions is assumed in order to avoid unintended interruptions of data transfer to maximize channel utilization and preserve data integrity. Step 33
Then, check the record size, that is, TLF. Here, the record length is the same in the same file, but may be fundamentally different in different files.

The TLF is used during calculation to ascertain the number of cache segments needed to store one record. For the sake of explanation, it is assumed that one track of DASD stores a certain amount of data in records of various sizes. For example, the record length is 250 bytes in one file, 10,000 bytes in another file, and 2 bytes in the third file.
It is 5,000 bytes. For cache efficiency, each cache segment stores approximately an integer fraction of the data storage capacity of each track. Such an arrangement is shown in U.S. Pat.No. 4,499,539 (Vosacek), where
Store the contents of one data track using three cache segments. In one embodiment of the invention, up to five cache segments are used to store an entire data set from a data track. Note that three of these five segments may be completely full and two may be partially filled.

In step 34 described in detail in FIG. 4, the maximum write area size (hereinafter referred to as WDMAX) is calculated. Due to fragmentation, the calculation assumes that one record is stored per DASD track, except that the last track in the write area is a full track. The DASD track cache image should be one complete track image. The first track in the write area may have a partial track image immediately adjacent to this track and not the first record in the index mark on this track but starting with the record circumferentially displaced from the index mark. . Therefore, DA
A variable number of cache segments is needed in cache 16 to store the actual data contents of the SD track. The cache storage requirement can be one segment, and a maximum of five segments. For small records, multiple records are stored in each of the cache segments when multiple records are on the track. Worst-case use of cache space is when only one record is stored in a cache segment and the record can be any size less than the capacity of each cache storage segment. In any case, the worst-case WDMAX requirement for the cache is calculated in step 34, as will be described in more detail below. This WDMAX requirement requires that track data beginning on a record other than the first record on the track (the record HA in the CKD track) be stored on a cache segment boundary and that the first record HA be stored on a cache segment boundary. It results from

Then, in step 35, the calculated
Compare WDMAX to the number of available cache segments (enough free cache space to store a record).
If the number of free cache segments available is greater than or equal to the calculated WDMAX, subsystem 19 is ready to receive data in the write area. If not, the write area data transfer needs to be subset. As a result, at machine step 36, the microprocessor 14 calculates the size of the largest region subset using the currently available cache segments as detailed in FIG. Once this calculation is complete, the peripheral subsystem 19 writes the data to DASD 20 and is ready to efficiently and safely respond to the next WRITE command from the host processor 10 during the current command chain. .

Each track of DASD 20 that has a copy of the data stored in cache 16 is a separately allocated cache space. This is because cache addressing is based on addressing DASD 20 tracks. As a result, if only one record is recorded in one DASD track, one cache segment is allocated to store a copy of one record.
If there are 2 or more records in one DASD track, all the track records, if they are small,
It could be stored within one minimum cache allocation of one segment. The cache segment is allocated in step 37 from step 32 during FORMAT WRITE or from step 35 or 36 during update writing. 1 FORMAT WRIT
While assigning 5 segments (1 track) to E,
Assign the calculated WDMAX (YES in step 35) or the maximum subset size (step 36) to one update write.

Receipt of the WRITE command is indicated by the numeral 40, and the host processor 10 sends the write command for receipt by the peripheral data storage subsystem shown in FIG. The description of this flowchart assumes that all operations are in accordance with the requirements presented in the prepare channel commands 30,31. If in step 41 WRITE
If the command is FORMAT WRITE, go through A 42
Executes the machine operation shown in 3. If the command is FORMAT
If it is not WRITE, it is UPDATE WR in this example.
It is ITE. In step 43, the microprocessor 14 checks if the current command chaining for writing data has to be subset, that is, if WDMAX is greater than the number of cache segments available. If such a condition exists, B 44
After that, the steps of FIG. 5 described later are executed. Write data to DASD 20 whenever the number of available cache segments allows all data to be stored for use under worst case cache 16 Step 45-
Execute 51. In step 45, the write command received in step 40 is initiated to write one or more records to DASD 20 via rate change buffer 13 and data circuit 16. Record changing buffer 13
At the same time it reads from DASD 20 into the cache, it stores a copy of the record in cache 16 via bus 23. Store records in cache 16 already or currently cached
Includes overwriting data from the write area stored in 16. Such writes or cache hits are well known, and the addressing and organization of cache segments corresponding to such cache hits is well known and will not be described further.

Cache hits affect the calculation of WDMAX requirements. This effect reduces the number of cache segments required for UPDATE WRITE operations. Upon completion of writing each record, in step 46, the microprocessor 14
Has reached the end of track (EOT) by a record transfer from attachment mechanism circuit 11 to buffer 13, i.e., the last record to be recorded in DASD 20 is buffered for later recording in DASD 20 and cache 16. It is judged whether or not it is received within 13. The detection of the end of the track at the channel connection end of the buffer 13 corresponds, as is known, to the index mark 102 (FIG. 6) on the current track, the detection being shown later by the DASD 20 scanning the mark. Since the current machine operation is UPDATE WRITE, if there is only one data track to be written or if one record is stored in one track, only one record is DA
It will be written during one rotation of the SD 20 disk (not shown). If the end of the track is not reached and additional records must be written on the current track being accessed, the additional records provided by the WRITE commands received at step 47 are written at step 45. . However, no additional record is written to the DASD track between the last record and the index mark (EOT) previously recorded on the current track of DASD 20. In step 50, at the end of each track being written, the amount of data stored in the cache 16, that is, the number of cache segments available to store the data used to update the track of the DASD 20, is measured. If only one record was recorded on the current track, then there is no extra cache segment because the maximum number of cache segments is needed to store the record for the current track. On the other hand, if 30 records were written for the current track, those 30 records would be
It can be stored in two cache segments. In maximum fragmentation, 34 cache segments are allocated to the write area of the first 30 records, assuming 1 record per track. In practice it is possible to store update data in cache 16 using only two cache segments, so the remaining 32 allocated cache segments are still available to store other data. It is possible. Such cache segments are referred to as excess segments, and when they are detected, they are deallocated at each end of the track. Then, in step 51, whether the end of this write area has been reached is detected when the latest command is received via the attachment mechanism circuit 11. This detection is DASD 20
Occurs before receiving and storing all records in the write area. That is, it is detected not when the record is transferred to the DASD 20 via the bus 22 but at the time when the record is transferred to the buffer 13 via the bus 24. If it is not the end of the write area, steps 45, 46, 47 and 50 are repeated until the end of the write area, and when done, machine operation transitions to another operation via path 52. Subsystem 19 from path 52 may receive an additional LOCATE RECORD command, and when it does, repeat steps 32 and below. Note that in step 50 the deallocation of excess segments varies from track to track, ie the number of records stored on each track in the file range changes. U.S. Pat. No. 4,499,539 (Vosacek) shows a method of controlling cache deallocation for those purposes.

FIG. 3 illustrates the machine operation of performing a FORMAT WRITE via A 42 from the flowchart shown in FIG. The LOCATE RECORD command 21 above indicates that the WRITE command should format the track, ie write a new count field. In step 60, subsystem 19 determines whether the command is a WRITE CKD NEXT TRACK command. If not a command,
The record is received at step 61 and stored in cache 16 and DASD 20. This step 61 involves providing the end status to the host processor. Then, in step 62, the subsystem determines whether it is the end of the write area or the end of the chain. At the end of this transfer, the process exits via path 63. If not, the subsystem receives the next write command in step 64, and upon receipt, repeats the operation shown in FIG.

WRITE NEXT T in either step 40 or 64
Upon receipt of the RACK command, the subsystem 19 in step 65.
Determines the number of available cache segments and stores that number. In step 66, the subsystem 19 determines whether the number of available cache segments is sufficient to store one track of data (that is, five cache segments in this embodiment). If yes, switch to DASD track and step
67 to 5 cache segments host processor 10
Allocate to receive a record from and FORMAT WRITE the next track on DASD 20. Then, step 61 and subsequent steps are repeated. If the available cache segment is the next DASD
If not enough to store the data in the track, the subsystem 19 sends a CCR (Channel Command Retry) to the host processor 10 in step 70. In step 71, subsystem 19 suspends the current set of machine operations until there are enough cache segments available to store data from one complete track. And when it is enough, step 72
Then, DEVICE END (DE) is sent to the host processor 10 to instruct re-sending of the command that has just been CCR'd, and then the command is received at step 64. Steps 72 to 64 and 60 and subsequent steps are repeated. From step 66, before executing step 61, allocate a cache segment for storing data for the next track in step 67.

Next, referring to FIG. 4, step 34
Two steps 80 and 81 for the calculations mentioned in
For more details. The first calculation in step 80 is about the data in the write area stored in the cache, which affects the utilization of the cache. In each file, all records are sequentially numbered from 1 (record 1 or R1) to record N (RN). However, N is an integer. Record 0 (R0) in CKD
Is reserved for control purposes and is not available for user data. A record stored in cache 16 while being written to DASD 20 causes a cache hit during a write operation. Such a cache hit can be predicted based on the write area specified in the channel command 31. WDMAX is incremented whenever the first record in such a write area has a copy currently stored in cache.
That is, the first referenced record in the DASD track and all subsequent records are processed within the current write area without additional allocation of segments in the cache 16. Assume that those records in the cache are initially stored at one record per DASD track. The equation in step 80 of FIG. 4 shows an increase in the write area size C. Note that M is the total number of records currently stored as the track cache image in the DASD track, the value S is the record number of the first record identified by the channel command 31 in the write area, and F is the track cache. It is the number of the first record in the image.

Step 81 calculates WDMAX for the worst case fragmentation of the file on DASD 20. This WDMAX
Is equal to the available cache segment (CAS) minus twice the number of cache segments required for a full track (T equals 5 in the example shown, and the difference in step 81 is 10) ). The value R, which is the number of cache segments required for each record, is added to the difference.
This R is the quotient of the value TLF divided by the cache segment capacity, rounded to the next digit. Divide the above value by R.
Then add the C value to get the maximum size of the write area represented by a number of records.

FIG. 5 shows that the required write area size WDSIZE is W
It shows how to sub-set the data transfer within the write area when it is greater than the DMAX value. The size of the remaining write area is calculated in step 36 by subtracting the WDMAX value from WDSIZE.

B 44 shows the machine operation which flows from the set of machine operations shown in FIG. 2 to step 90. Step 90
Then, the subsystem receives the record of the write command received in step 40 and stores the received record in the cache and DASD. This step 90 also increments the record count in the microprocessor 14. Each time buffer 13 receives one record from attachment circuit 11, microprocessor 14 stores an increment value and also records the record count in its own internal memory (not shown).
Store in. In step 91, whether or not the data transfer is completed at the channel connection end of the buffer 13, that is, DASD 20
The end of the write area or the end of the chain represented by the host processor 10 supplying the last record to be recorded on top and in the cache 16 is determined. At this point, DASD 20 and cache 16 have not yet received the final record in the write area. If it is the end of the data transfer, the operation exits as shown at 92. Otherwise, in step 93, microprocessor 14 determines if the record count incremented in step 90 is equal to WDMAX calculated in step 34. If the maximum number of records received is not the WDMAX calculated in step 34, a write command is received in step 98, and steps 90, 91 and 93 are received.
Repeat. This loop repeats until WDMAX is reached. Here, the counting is performed for the records transferred from the connection mechanism circuit 11 to the rate change buffer via the bus 24.

Depending on the subsystem 19, the cache 16
Some have multiple independent storage paths indicating. Each memory path is its own circuit in the attachment mechanism circuit 11,
Its own rate change buffer 13 and data transfer line 18
It also contains an independent access path to the cache 16. Microprocessor 16 controls some or all of these storage paths. The number of cache segments available for each storage path can either be from a common or shared pool of unallocated cache segments, or from the segment pool for each storage path. In either case, a load balance or need for such cache segments and current data transfer rates in the various storage paths can be realized. The above control of the present invention uses the same inventive principle in any case.

To sub-set the data transfer and write areas, subsystem 19 shown in FIG. 1 sends a CCR to the host processor in step 94 to momentarily stop the data transfer. The subsystem CCR indicates to the host processor 10 that the channel command that was just received, that is, the channel write command immediately after the count reached the maximum value, was rejected by the peripheral data storage subsystem. CCR is an external interrupt that effectively interrupts the data transfer. That is, the operation of the channel 12 is in the hold state. In this example, the device operation is the channel
Continue until 16 sufficient number of available cache segments are available. Therefore, in step 95, microprocessor 14 determines whether there are enough cache segments, or five segments, to store the next data track. If not, the wait loop consisting of repeated executions of step 95 (the wait loop can be interleaved with other operations as is well known) is repeated until at least 5 segments are available. Then, when it becomes available, the device end (DE) is supplied to the host processor 10 in step 96.
After that, the path 97 is traced again to execute step 33 and the following steps. That is, the rest of the write area may require more WDMAX available than there are currently available segments. That is, additional sub-grouping may occur. The size of each subset varies depending on the number of cache segments currently available. Such a device end DE indicates to the host processor 10 that the peripheral subsystem is now ready for the next data transfer. When switching tracks occurs in this mode, FO
Note that there is no interruption of the data transfer itself as done during the RMAT WRITE operation. All of the above provide efficient and efficient machine control to ensure writes to DASD 20 with minimal loss of disk rotation and to ensure that cache 16 can store a copy of all records.

A method of using the cache and a method of allocating the data stored on one DASD track will be described with reference to FIG. One disk 100 in DASD 20 has multiple data storage tracks, such as track 101. truck
101 starts with an index mark 102 extending in the radial direction of the recording area on the disc 100 and ends there. The ellipsis 103 indicates that there are many such tracks. Each of these tracks can store a variable amount of data or a variable number of records. In the file with the most fragmentation, some of the tracks 101, 103 store only one record. The record with the next highest number in this file is stored in the next track. A portion of cache 16 is logically depicted as having a plurality of allocatable and addressable data storage segments AY. When track 101 is full of data, it takes up to 5 segments specified by numbers 110 and 111 to store one track.
(Segment AE and segment FJ store one track each). A single record is stored on one DASD track and it is one of the cache segments
If stored in one, the entire contents of this DASD track can be stored in a single segment in cache 16, for example segment K. Also, for another DASD track that has enough records to store the track contents in three segments, for example
Can be stored in P, Q, R segments. In this way, the cache 16 can be fully utilized. Under the maximum fragmentation situation above, it is assumed that each DASD track has only one record. Therefore, one of those cache segments would be allocated for the data for each track to be written into DASD 20, assuming that one segment stores a single record. Index 102
When the end of the track is reached, the peripheral subsystem 19 knows how many records were stored in the update write operation for one track. For example, if 18 records are stored in the cache segment numbered 110 and they occupy 4 segment AD, then the first 18 allocated segments in cache 16 will be 14 are available for other machine operations. This process is repeated each time the end of one track 102 is reached during a write operation. This description assumes that cache 16 is allocated on a track basis and that the data stored in a given track of DASD 20 occupies a variable amount of cache 16.

Although the present invention has been described and illustrated with reference to preferred embodiments and with reference thereto, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention. It can be carried out.

[Brief description of drawings]

FIG. 1 is a simplified block diagram of a peripheral data storage subsystem connected to a host processor such that the present invention may be used to advantage.

2 is a simplified set of machine operations of the system shown in FIG. 1 for practicing the present invention in the best way; FIG.

FIG. 3 is a simplified flowchart showing the operation of the system of FIG. 1 during a format write operation.

FIG. 4 is a simplified flowchart showing determination of available cache segments required for update write data transfer in the system shown in FIG.

FIG. 5 is a machine operation flowchart for subsetting data transfers between a host processor and a device to accommodate a small number of cache segments less than the WDMAX cache segments required for data transfers.

FIG. 6 is a diagram showing cache utilization and allocation of data stored in DASD tracks.

[Explanation of symbols]

 10 ・ ・ ・ Host processor 12 ・ ・ ・ Optical fiber channel 19 ・ ・ ・ Peripheral subsystem 11 ・ ・ ・ Connection mechanism circuit 13 ・ ・ ・ Rate change buffer 14 ・ ・ ・ Controller / microprocessor 16 ・ ・ ・ Cache 18 ・..Data transfer circuits 20,21 ... DASD (Direct Access Storage Device) 100 ... Disks in DASD 101 ... Tracks 102 ... Index marks 103 ... Tracks 110,111 ... Cache segments

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michael Thomas Benhase 4857 North Tolasson, Tucson, Arizona, USA 85749 (72) Inventor Gail Andrea Spear, USA 85715, Tucson, Arizona, East East Fieldstone Lane 6822 (72) Inventor William Dennis Williams 4079 West Tobira, Tucson, Arizona, USA 85741

Claims (4)

[Claims] 1. A data record between the DASD, the cache and the host processor channel means in a cached peripheral data storage subsystem having a hosted processor channel means connected to the DASD and a cache connected to the DASD. Transferring a first predetermined number of data records between the channel means and the DASD and copying the first predetermined number of data records in the cache in the subsystem. Establishing a write area for the first predetermined number of data records to be stored on the DASD, in the subsystem prior to transferring the data records, a second Determine and point to a given available cache store for storing a given number of data records If a step in the subsystem, the indicated available cache memory is smaller than the space required to store the first predetermined number of data records to be transferred,
Dividing the transfer of the data records into a predetermined number of subsets of the second predetermined number of data records, and in the subsystem, transferring the data records to a plurality of subsets of data records. ,
Assigning a third predetermined number of cache segments for storing data records in each subset data record transfer prior to each subset data record transfer,
A data record transfer method comprising the steps of sequentially transferring the subset data records between the channel means and the DASD and storing a copy of the subset data records in an available area of the cache storage. 2. The DASD has a plurality of addressable data storage tracks each storing a predetermined number of data records, the method comprising: a method for indicating a number of records of a file to be written to the DASD; In the step of setting the write area and the step of judging and instructing, the maximum number of cache segments WDMAX necessary for storing the data record in the data record transfer is WDMAX = (CAS-2T + R) / R + C where CAS: 2. The data according to claim 1, further comprising: determining and instructing an available cache segment T: the number of cache segments required for a full track R: the number of cache segments required for each record Record transfer method. 3. The DASD comprises a plurality of addressable data storage tracks each storing a predetermined number of data records of a predetermined amount of data storage capacity, the method comprising: in each of the subset data record transfers. The step of limiting the predetermined number of data records to a value that does not exceed the predetermined number of data records that can be stored in one of the DASD data storage tracks; and, when transferring the predetermined number of data records, The steps of determining and indicating are repeated to determine and indicate whether the available cache storage can store the record of the predetermined amount of data storage capacity, and if so, execute the next subset data record transfer. , If not, then the available cache store has a sufficient number of cache segments to store the predetermined number of data records. 2. The method of claim 1, further comprising delaying the next subset data record transfer until the end of the step, repeating the limiting step and the delaying step until the desired data record transfer is complete. Data record transfer method. 4. The DASD includes a plurality of addressable data storage tracks each having a predetermined amount of data storage capacity, the subsystem including an input / output end for the channel means and an input / output end for the DASD. Comprising a rate change buffer having, wherein said method supplies all data records from said channel means to be recorded on said DASD to said channel means input / output end of said rate change means to temporarily store in said rate change buffer. Storage, and then supplying and storing a copy of the data record supplied from the channel means and stored in the rate change buffer to the cache and to the DASD from the DASD input / output end for storage. At the channel means input / output end of the buffer, the currently available cache storage is the predetermined amount of data storage capacity. It is determined whether or not the data record is lower than the current track, and an instruction to stop the subset data record transfer is made at the end of the track address of the current track of the data storage track of the DASD receiving and storing the data record, and Addressing the data storage track of the DASD to restart the next partial data record transfer, and after the instruction to stop the subset data record transfer and the addressing, repeat the steps of determining and instructing The method of claim 1, further comprising: detecting available cache storage that is not less than a predetermined amount of data storage capacity.