JPH0456334B2 - - Google Patents

Description

[Detailed description of the invention]

[Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means and operations for solving the problems (Fig. 1,
(Figure 2) Embodiment (a) Explanation of the configuration diagram of one embodiment (Figure 3) (b) Explanation of the configuration of the preemption control section (Figures 4 and 5)
Figure) (c) Explanation of startup processing operation of one embodiment (d) Explanation diagram of host processing operation (e) Explanation of drive processing operation Effects of the invention [Summary] Reel-reel direct drive type that performs command prefetch control In magnetic tape devices, physical EOT processing mode or logical
Enables processing based on the selection of EOT processing mode,
In the physical EOT processing mode, it is further possible to select buffer mode (pre-emptive access) processing and non-buffered (normal access) processing. Particularly in non-buffer mode processing, detection of the physical EOT and logical EOT of the magnetic tape coincide. [Industrial Application Field] The present invention relates to a device for prefetching instructions that can preempt instructions from a higher level in a magnetic tape device having a buffer capable of storing a plurality of instructions and write data in advance. Magnetic tape devices are widely used as external storage devices for computers, and in recent years have been particularly used for backing up external storage devices in addition to magnetic disk devices. In such a magnetic tape device, the 16th
As shown in the figure, there is a tape drive section 1 having a magnetic head for writing and reading data on a magnetic tape, a magnetic tape drive section for running and driving the magnetic tape, and a control section CT for controlling this in accordance with commands from a host controller. It is set up and configured. In recent years, a buffer BF has been installed within this control unit CT,
A system has been developed that performs command prefetch control that preempts commands and data from the host controller, stores them in the buffer BF, and causes the tape drive section 1 to sequentially execute the commands and data in the buffer BF, and has been put into practical use. ing. Such a magnetic tape device is called a buffered magnetic tape device, and can operate the tape drive unit 1 asynchronously in response to commands from the host controller, so the host controller side can operate the tape drive unit 1 in response to one command. Since commands can be issued continuously without having to wait for completion, and the tape drive section 1 can also perform operations continuously without waiting for commands from the host controller, processing efficiency can be improved, especially in streaming mode. Operational efficiency can be improved. [Prior art and problems to be solved by the invention] In order to have such a buffer BF and preempt instructions, the buffer BF has an instruction buffer that can store multiple instructions and a buffer that can store multiple data. For example, the instruction buffer can store up to 64 instructions, and the data buffer can store up to 64 instructions.
It is designed to be able to store 256KBytes of data, allowing for prefetch instructions and data to be increased. On the other hand, as shown in FIG. 17A, the magnetic tape 16 is not infinite in length but has a finite length, so at the end there is an EOT
(END OF TAPE) marker is attached,
The tape walking area (TWA) after EOT detection can only be used for approximately 3m. Therefore, in write (data writing) processing, if the prefetch command and write data are 3 m or more at the time of EOT detection, this will be transferred to the magnetic tape 1.
It becomes impossible to write on 6, and some kind of countermeasure is required. One such countermeasure is to generate a tape end vicinity signal WA, for example, approximately 20 m before EOT, before detecting EOT, which is the end of the magnetic tape.
As a result, as shown in Figure 17B, the amount of data that can be stored in the buffer BF (number of data bytes)
was decreasing. For example, as shown in Figure 17B, the maximum
When entering EWA, this data buffer can store 256KB (kilobytes) of data.
The data buffer is limited to 128 KB, and unless the amount of data accumulated in the data buffer becomes 128 KB or less, acceptance of write data from the host controller is not permitted, thereby preventing such writing failure. In other words, by limiting the capacity of the data buffer, the number of write instructions that can be prefetched is indirectly limited. On the other hand, the performance of such a buffered magnetic tape device is greatly influenced by the number of instructions prefetched, and the larger the number of instructions prefetched, the longer streaming can be maintained and the performance is superior. However, the length that can be written to the tape warning area (TWA) after EOT is limited, and if the number of prefetched instructions is too large when EOT is detected, it becomes impossible to execute all prefetched instructions. For this reason, it is necessary to increase the number of pre-reads as much as possible until near EOT, and then reduce the number to a writable number as ETO approaches. However, in the conventional technology, since the capacity of the data buffer is limited, the prefetched write instructions themselves are unreasonably prefetched, and some write instructions are not prefetched. The problem has arisen that it is difficult to get a good streaming experience. In other words, writing instructions in the vicinity of the tape end area are too preemptively restricted and streaming is not performed, or too many write instructions are being prefetched and streaming is performed but TWA is not performed.
A situation has arisen in which all commands cannot be executed within the system. In addition, as a method to limit the number of command preemptions,
In the EWA area, methods have been proposed to limit the limit all at once to the minimum level or to gradually limit the limit according to the acceptance of commands (for example, Japanese Patent Application No. 1983-
153831, “Instruction prefetch control method and device for magnetic tape device”). Similarly, a method has been proposed for controlling the number of instructions prefetched at the logical EOT point before the EOT after early warning detection (for example, Japanese Patent Application No. 60-214248, ``Instruction prefetching control method for magnetic tape device and its Device"). Furthermore, a method has been proposed in which the number of instructions prefetched is limited by the maximum number of blocks (for example, Japanese Patent Application No. 60-222498, ``Instruction Prefetch Control Method and Apparatus for Magnetic Tape Device''). The above method has the effect of increasing the usage efficiency of magnetic tape. On the other hand, since the number of instructions prefetched is limited, performance from the viewpoint of buffer control is degraded. Apart from the above method, when executing a write instruction,
When detecting that TWA is close, virtually EOT
After all preemption instructions are executed, assuming detection,
Something has been proposed that reports EOT detection to the host computer (for example, Japanese Patent Application 1986-
235807, "Instruction prefetch control method and device for magnetic tape device"). According to this method, the actual
While a virtual EOT (logical EOT) is detected before EOT is detected, instructions are prefetched until the logical EOT without reducing the number of instructions prefetched, resulting in excellent performance from a buffer control perspective. As mentioned above, both have advantages and disadvantages in performance, but
In both cases, there is a difference between the actual EOT marker and the detected EOT. In other words, according to the former method that emphasizes tape usage efficiency, there is instruction preemption even near the EOT, so from the host's perspective, the actual EOT
There appears to be an EOT marker later. On the other hand, according to the latter method that emphasizes the performance of buffer control, the EOT marker appears to be located before the actual EOT. It is originally desirable that the actual EOT and the reported EOT match, but if the EOT report blocks at read and write times do not match as described above, some systems may have problems. Therefore, it is desired to make the actual EOT match the reported EOT while taking advantage of the advantages of the buffer control described above. [Means and effects for solving the problem] In the present invention, as shown in FIGS. 1 to 3, a magnetic tape having a magnetic tape drive mechanism for driving a magnetic tape wound around a magnetic head and a reel is provided. a drive unit, a buffer control means for preemptively storing a plurality of access commands to the magnetic tape given from a higher-order unit, and transmitting a result of accessing the magnetic tape to the higher-order unit; A magnetic tape device is provided that includes a magnetic tape control means that controls the magnetic tape drive section in response to an access command or individual access commands, and performs an operation in response to the access command. Based on a pre-given physical termination processing mode or logical termination processing mode, and a preemptive access mode or normal access mode, the buffer control means (a) in the case of the physical termination processing mode;
In the preemptive access mode, the number of preemptive instructions in the area before the end area of the magnetic tape is reduced to a predetermined value, and when the magnetic tape reaches the end area, the number of preemptive instructions is reduced to zero, and in the normal access mode, the number of preemptive instructions is reduced to a predetermined value. When the area before the end area of the magnetic tape is reached, the number of preemption instructions is set to zero; (b) in the case of the logical termination processing mode, when the area before the end area of the magnetic tape is reached, the end area is notified to the upper layer; The number of prefetch instructions is set to zero, and the magnetic tape is accessed according to the termination processing mode and access mode. [Embodiment] (a) Explanation of a block diagram of an embodiment FIG. 3 shows an overall block diagram of a magnetic tape device and related parts according to an embodiment of the present invention. Magnetic tape device 10
0 is a magnetic tape reel drive motor (not shown), a servo system 22 for driving the motor,
It has a drive section 1 consisting of a drive circuit and the like, a drive control section 2 for controlling the drive section, a read/write amplifier section 23, an operator panel 24, and a preemption control section 3. As a host (upper level) of the preemption control unit 3, an MT control adapter 203 in a host computer system 200 is connected to the CPU 201 via a common bus 210.
A disk control adapter 2 is connected to the common bus 210.
02, memory 204 etc. is MT control adapter 203
are connected as well. The preemption control section 3 is lower than the MT control adapter 203, in other words, the MT control adapter 203 is above the preemption control section 3, and when viewed from the drive control section 2, the preemption control section 3 is above the MT control adapter 203. FIG. 4 shows the configuration of the magnetic tape device shown in FIG. 3. In the figure, the same components as those shown in FIG. )1
1 and a supply reel (file reel) 12, a magnetic tape 16 is attached to the roller 1 of the tension arm 15.
5a, a magnetic head 14, an idler 13, and a take-up reel 11.
4 is guided by guides 17a and 17b on both sides. On the other hand, the take-up reel 11 and the supply reel 12 are rotationally driven by drive motors 10a and 10b, respectively, and rotary encoders 18a and 18b are provided on the drive motors 10a and 10b to detect the amount of rotation of the drive motors 10a and 10b. I'm trying to make it possible. Further, the idler 13 is also provided with a rotary encoder 19a, which makes it possible to monitor the actual running position of the tape, while the tension arm 15 is provided with a tension detector 19b.
is provided to enable detection of tape tension. Reference numeral 2 denotes a drive control section, which drives the tape running and drives the head for writing or reading according to commands and data from a command/data prefetch control section, which will be described later.
a, 18b, and 19a to monitor the running state, and also monitor the tension from the output of the tension detector 19b.
a and 10b to drive the tape to run while keeping the tape tension constant, and also to drive the magnetic head 14.
It supplies write data to perform writing and receives read data from the magnetic head 14. Reference numeral 3 denotes a command/data prefetch control unit which receives write-type or read-type commands and write data from the host controller 203 and stores them in a buffer. For write-related commands, drive control unit 2
A write command and write data are sent to the block to perform a write operation, and if the write operation is completed normally, a write command and write data for the next block are sent. If the process does not end normally, the drive control section 2 is caused to perform a write retry operation. Command/data prefetch control unit 3
The adapter has a command buffer and a data buffer, which will be described later, and operates as a lower-level magnetic tape device for the host controller as described above, and operates as a higher-level device equivalent to the host controller for the drive control unit 2. be. (b) Description of the structure of the prefetch control section FIG. 5 is a block diagram of the main part in the structure of FIG. 4, that is, the instruction data prefetch control section 3. In the figure, 30 is a microprocessor (hereinafter referred to as MPU).
), which controls the reception of commands and data from the host controller and controls the transmission of data and status according to the microprogram in the program memory, which will be described later. Controls reception of data and status from the control unit,
Furthermore, the state control processing of the drive 1 is performed. 31a
is a program memory in which programs to be executed by the MPU 30 are stored. 31b is a random access memory (hereinafter referred to as RAM);
It stores various data, instructions, and parameters necessary for the processing of the MPU 30, and has an instruction buffer area CBUF, an instruction buffer management area CA, a data buffer management area DA, various mode management areas EA, and a read instruction register RC. . In the instruction buffer area CBUF, at the time of a write-related command, the instruction prefetched from the host controller, the start address in the data buffer of data transferred by the instruction, the number of bytes, etc. are stored. At the time of a read-related command, the read execution result of the prefetched block, the start address in the data buffer of the read data, the number of bytes, etc. are stored. Command buffer management area
CA stores the instruction storage number CBSTK, buffer size CBSIZE, and instruction prefetch limit value CBE. As the instruction storage number CBSTK, at the time of a write command, the number of prefetch instructions that are stored in the instruction buffer area CBUF and that have not yet been executed is stored. At the time of a read type command, the number of prefetch blocks is stored as the instruction storage number CBSTK. The buffer size CBSIZE is the instruction buffer area.
This shows the size of CBUF in terms of the number of instructions. The limit value CBE is a limit value for the number of write instructions to be prefetched in the early warning area EWA when not in the logical EOT mode, that is, in the physical (in other words, actual) EOT mode. The data buffer management area DA contains a buffer free capacity FSEG that indicates the free capacity of the data buffer in units of IKB, a buffer address BADR that indicates the start address of the data buffer at the time of data transfer for writing to the data buffer, and The maximum block length MAXL indicating the maximum length of the target data block is stored. The mode management area EA has a recording density of 1600 rpi (row per
EOT mode that determines the write recording density and termination processing mode (inch) or 6250rpi), and a travel counter ECTR that stores the tape travel distance after EWA detection in logical EOT mode.
A distance count valid flag indicating that the value of ECTR is valid, a redused flag indicating that the number of prefetched instructions should be reduced, and a LET flag indicating that logical ET has been detected are stored. A drive interface circuit 32a is used to exchange control signals and the like with the drive control section 2. 32b is a host interface circuit that exchanges control signals and the like with the host controller. Reference numeral 33 denotes a data transfer control circuit, which controls a data buffer to be described later and controls data transfer with the host controller or drive control section 2. The data transfer control circuit 33 issues a data transfer request signal to the host controller, and receives a data transfer request signal from the drive control unit 2 and performs data transfer control. The data transfer control circuit 33 includes a store address counter SCTR to the data buffer, a load address counter LCTR from the data buffer, and a byte counter BCTR when loading the buffer. A data buffer 34 is controlled by the data transfer control circuit 33, stores write data from the host controller, and transfers it to the drive control unit 2. Conversely, it is used to store read data from the drive control unit 2 and transfer it to the host controller. The data buffer 34 has a capacity of, for example, 256KB. 35 is a data bus, which connects the MPU 30 and the program memory 31a,
RAM31b, drive interface circuit 3
2a, a host interface circuit 32b, and a data transfer control circuit 33 are connected to exchange commands and data. 36a is a control signal line, which is connected to the drive control unit 2.
This is for transmitting commands and the like to the drive control unit 2, and conversely receiving status and the like from the drive control unit 2. 3
6b is a tape end vicinity area detection signal line;
This is for transferring the tape end vicinity area detection (EWA) signal from the drive control unit 2. 3
6c is an interrupt line, which notifies the MPU 30 of an interrupt from the drive interface circuit 32a. 37a is a data control signal line;
This is for transmitting a data transfer request signal from the drive control section 2 to the data transfer control circuit 33, and transmitting a data transfer end signal to the drive control section 2.
A write data bus 37b is used to transmit write data from the data buffer 34 to the drive control section 2. A read data bus 37c is used to transmit read data from the drive control section 2 to the data buffer 34. A control signal line 38 is used to exchange commands and status with the host controller. A data transfer control signal line 39a is used to transmit a data transfer request signal to the host controller and a data transfer end signal from the host controller. A write data bus 39b is used to transmit write data from the host controller to the data buffer 34. A read data bus 39c is used to transmit read data from the data buffer 34 to the host controller. Therefore, the MPU 30 communicates via the data bus 35.
RAM31b, host interface 32b,
Writes and reads between the drive interface circuit 32a and the data transfer control circuit 33,
Performs desired processing for magnetic tape access, which will be described later. That is, the host interface circuit 32b exchanges commands and statuses with the host controller under the control of the MPU 30 via the control signal line 38, and the drive interface circuit 32a exchanges commands and statuses with the host controller 2 under the control of the MPU 30 via the control signal line 36a. exchanges commands and status. On the other hand, in response to instructions from the MPU 30, the data transfer control circuit 33 issues a data transfer request to the host controller via the data transfer control signal line 39a, and in response, the host controller transfers the write data to the write data bus 39b.
The data is sent to the data buffer 34 via the buffer and stored therein. Further, in response to a data transfer request from the drive control section 2 on the data transfer control signal line 37a, the data transfer control circuit 33 issues write data from the data buffer 34 to the drive control section 2 via the write data bus 37b. Further, the data transfer control circuit 33 stores read data from the drive control unit 2 via the read data bus 37c in the data buffer 34 according to instructions from the MPU 30, and transmits the read data from the data buffer 34 to the host controller via the read data bus 39c. The drive control unit 2 detects the vicinity of the tape end area by monitoring the running position using the rotary encoder 19a, and transmits the EWA signal to the signal line 36b.
and sends a TWA signal to signal line 3 upon EOT detection.
Emit at 6a. As shown in FIG. 6, the interface between the preemption control unit 3, the host controller, and the device 1 receives a start signal from the host controller.
By being given the GO and command signals (FIGS. 6a and 6b), the MPU 30 sends a response signal: formatta.
Returns the busy signal FBY to the host controller,
Furthermore, a data busy signal indicating that a command is being executed
Give DBY to the host controller (Figure 6c,
d). If the command signal is a write command that involves data transfer, the data transfer control circuit 33 applies a write strobe pulse WSTB to the host controller (FIG. 6f), and the host controller transmits write data in synchronization with the write strobe pulse WSTB. The data are transferred (FIG. 6b) and sequentially stored in the data buffer. The host controller sends the write word signal LWD at the same time as the final write data.
is sent to the data transfer control circuit 33 (Fig. 6h), and the control circuit 33 receives this last word signal LWD.
When detected, it stops sending the write strobe pulse WSTB, ends the data transfer, gives a status signal indicating normal/abnormal reception operation to the host controller, turns off data busy DBY, and ends the write data transfer operation ( Figure 6d). still,
The received command is stored in the command buffer CBUF. On the other hand, if the command is a read command, the read data read from the tape drive 1 is transferred to the host controller together with the read strobe pulse RSTB (FIG. 6i). The end of the read data transfer is notified to the host controller by turning off the data busy DBY (FIG. 6d). Such an interface procedure is the same between the prefetch unit 3 and the drive 1 as shown in FIG. Even if a write command arrives (FIGS. 7a and 7b), the data busy DBY is not turned on until the buffer CBUF and data buffer 34 are free (FIG. 7c) so that the data transfer waits. (c) Description of startup processing operation in one embodiment FIG. 8 is a startup processing flow diagram of an embodiment of the present invention, and FIGS. 9 and 10 are initial setting processing flowcharts in FIG. 8. Steps: S101 to S102 When the power is turned on, the MPU 30 checks the write recording density setting and termination processing mode setting of the drive set from the host controller 203 or the operator panel 24 via the drive interface circuit 32a, and reads the data of the RAM 31b. Area EA
The write recording density setting of the drive is stored in the write recording density of the drive, and the termination processing mode setting is stored in the EOT mode. In this example, the write recording density is
6250rpi or 1600rpi. Then, initial setting processing 1 shown in FIG. 9 is performed. That is, the MPU 30 is
RAM3 since no command has been given yet.
Clear the instruction stack number CBSTK in the instruction buffer management area CA of No. 1 to zero, and reduce the preemption instruction capacity.
S151 to set CBSIZE to maximum 64. then
The MPU 30 sets the buffer free capacity (free segment) FSEG of the data buffer management area DA to a maximum of 256 units (however, 1 segment represents 1 KB, so the maximum is 256 KB), and sets the data buffer address BADA to the initial address "00". (Hereinafter, “XX” indicates the hexadecimal value XX), the maximum block length of the data buffer management area DA
MAXL is the minimum of 8 units (however, 1 block is
Since it represents 1KB, it is set to 8KB (step S152). Furthermore, the MPU 30 turns off the distance valid flag of area EA, turns off the reused flag, and turns off the logical EOT flag (S153 to S155), and ends the initial setting 1. Steps: S103 to S104 When the MPU
30 checks whether the magnetic tape is set on the supply reel 12 and is in the ON-LINE state via the drive interface circuit 32a via the bus 35. If it is online, MPU30 will connect to bus 3.
5, the contents of the register of the host interface circuit 32b are checked, and the REW command or
Check to see if a UNL command has arrived. Steps: S131 to S134 If the REW command or UNL command has arrived,
The MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not currently being executed. If the execution processing mode is read type, pre-reading of drive 1 is stopped. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped. On the other hand, if the execution processing mode is write type, all write type instructions in the instruction buffer CBUF are executed. Then, in S133 after all instructions have been executed, or if there is no process being executed or after the prefetching process of the drive has stopped, in S132, the MPU 30 transfers the magnetic tape to the starting point BOT via the drive interface circuit 32a.
(Begin of Tape) REW command or UNL command to wind the magnetic tape to the drive 1
is executed, and the process returns to initial setting 1 in step S102. Step: S105 If the REW command or UNL command has not arrived,
The MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35 to see if there is a start command GO (FIG. 6a) from the host. If there is no activation from the host, the process waits for activation and returns to step S103. Step: S106 When it is determined that there is activation from the host, that is, a GO signal has been received, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35, and determines what the given instruction code is. If the given instruction code is read type, go to step S141; if it is recording density setting, go to step S121.
and execute the processing routine. Steps: S121 to S126 If the command is recording density setting, the MPU 30 sets data busy via the host interface circuit 32b.
Notification is made that DBY is turned on, and further, it is checked via the drive interface circuit 32a whether the magnetic tape 16 of the drive 1 is at the load point LDP, ie, BOT. If the recording density setting command is at the load point LDP, the recording density setting command is valid, so the MPU 30 executes the recording density setting command for the drive via the drive interface circuit 32a, and then transfers the recording density setting command to the RAM 3.
The recording density instructed by the host is set in the recording density storage section of the various mode management area EA of 1b. If it is not at the load point LDP, the recording density setting command is invalid and there is no need to execute the recording density setting command to the drive and set the write recording density. Thereafter, the MPU 30 reports the completion to the host via the host interface circuit 32b, turns off the data busy DBY, and returns to step S103. Steps: S107 to S111 If the given command is a write type instruction, the MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not being executed. If the execution processing mode is read type, the preread processing of drive 1 is stopped. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped. Next, initial setting 2 shown in FIG. 10 is executed.
That is, the MPU 30 clears the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 31b to zero, and in S161, clears the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 31b.
S162 sets the buffer free capacity FSEG of DA to the maximum 256 and sets the data buffer address BADR to "00". After the above processing is completed or if the drive control unit 2 is not in execution, the MPU 30 sends a command (space or backspace) to the drive control unit 2 to adjust the tape position to the drive interface circuit 32a. command through. The process then proceeds to a write-related processing routine to be described later. On the other hand, if the execution processing mode is write type in step S107, the process immediately advances to the write type processing routine. Steps: S141 to S147 If the transferred command is a read type instruction, the MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not being executed. If the execution processing mode is read, the MPU 30 first checks whether the read directions match, that is, whether the forward direction is the forward direction and the reverse direction is the reverse direction. to stop. That is, when the drive control unit 2 finishes the process being executed, the drive interface circuit 32
a to the drive control unit 2 from the control line 36a,
Prevent new processing from being ordered and stop read processing. Further, the MPU 30 executes the initial setting 2 similar to that described in step S109 in step S144, and then performs tape position adjustment similar to that described in step S111 in step S145. On the other hand, if the execution processing mode is write, all instructions in the instruction buffer CBUF are executed. Then, after all instructions are executed, if there is no process being executed, or after the drive process is stopped, a read-related instruction for prefetching is set in the read instruction register RC of the RAM 31b. After this setting, or if the read directions match, the process advances to a read-related processing routine. Therefore, if the activation from the host is a write-related command, even if read-related processing is in progress, it switches to write-related processing, and if it is write-related processing, write-related processing is continued. With the initial setting 1, the maximum block length MAXL is the minimum 8 units, and with the initial setting 1 or 2, the number of instructions stored
CBSTK is 0, data buffer free space FSEG is maximum 256, data buffer address BADR
is set to “00”. Also, the recording density at the time of writing from the load point LDP is set in area EA of the RAM 31b. (d) Description of host-related processing operations Figures 11a and 11b are flowcharts of host-based write processing. The processing of each step will be described below. Steps: S200 to S203 When the MPU 30 is activated by a write command from the host controller shown in FIG.
To check whether write-related commands can be stored,
RAM31b instruction buffer management area CA instruction memory number CBSTK and instruction buffer size CBSIZE
are read out via bus 35 and compared. CBSIZE≦
When write-related instructions are stored in the instruction buffer CBUF up to CBSTK, that is, the number of instructions that can be stored, storage of the write-related commands in the instruction buffer CBUF is suspended. On the other hand, if CBSIZE>CBSTK, the write-related instruction can be stored in the instruction buffer CBUF, so the MPU 30 checks whether the write-related instruction uses the data buffer 34. If the data to be written, such as erase ERS and write tape mark WTM, is not sent from the host controller and does not use the data buffer 34, turn on data busy DBY and proceed to the next initialization step of the final limit value CBE. . As shown in Fig. 8, when a start (GO) command is given from the higher level (host), the lower level (preemption control unit 3) sends a data busy DBY signal indicating that the command is being executed, if the command is executable. Turn it on and return to the top. This relationship is the same even when the prefetch control section 3 is placed at the upper level and the drive control section 2 is placed at the lower level. Conversely, if the write-related instruction is a normal write instruction that uses the data buffer 34, the MPU 30 will
A decision is made to permit automatic transfer to the data buffer 34. That is, first, the MPU 30 uses the free buffer capacity of the data buffer management area DA of the RAM 31b.
Read FSEG and maximum block length MAXL, and check whether the free buffer capacity FSEG is greater than or equal to the maximum block length MAXL. If the free buffer capacity FSEG is less than the maximum block length AMXL, reception of write data is suspended and waits until the data buffer 34 becomes free for the maximum block length MAXL. Free buffer capacity
If FSEG is greater than or equal to the maximum block length MAXL, transfer is permitted. Therefore, the aforementioned data busy DBY signal is turned on to notify the host controller that transfer is possible. Steps: S204 to S207 The MPU 30 checks whether the magnetic tape 16 of the drive 1 is located at the load point LDP via the drive interface circuit 32a. If it is not at the load point LDP, the final limit value CBE has already been set, and the process advances to the next automatic transfer step S208. On the other hand, if it is located at the load point LDP,
Initial setting of limit value CBE according to write recording density is performed. That is, the MPU 30 checks the write recording density of the mode area EA of the RAM 31b, and if the write recording density is 1600rpi, it sets 8 to the limit value CBE of the instruction buffer management area CA of the RAM31b and sets it to 6250rpi.
If so, the limit value CBE16 is similarly initialized and the process advances to step S208. Steps: S208 to S214 The MPU 30 checks whether the write-related instruction uses the data buffer 34 or not. If the data buffer 34 is not used, step S
Proceed to 225. On the other hand, if the data buffer 34 is used, data transfer is executed. That is, the MPU 30 is
Read the first buffer address BADR of the data buffer management area DA of the RAM 31b and use the store address counter of the data transfer control circuit 33.
SCTR and activates the data transfer control circuit 33. As a result, the data transfer control circuit 33 issues a data transfer request to the host controller via the data transfer control signal line 39a. Therefore, the host controller transfers the write data from the write data bus 39b to the data buffer 34, and stores the write data in the store address counter of the data transfer control circuit 33.
Write data is stored in the data buffer 34 according to the address of SCTR. The store address counter SCTR counts up every time one byte of write data is transferred. When the data transfer control circuit 33 determines that the data transfer is completed, the MPU 30
Read the store address counter SCTR of the buffer address of the data buffer management area DA.
Calculate the difference from BADR to find the byte count BC of the transferred write data. Next, the MPU 30 updates the instruction buffer CBUF and data buffer management area DA of the RAM 31b. First, the buffer address (ie, the start address of the write data) BADR of the data buffer management area DA of the RAM 31b and the calculated byte count BC of the write data are stored in the relevant instruction section of the instruction buffer CBUF of the RAM 31b. Next, the data buffer 34 is transferred from the free capacity FSEG of the data buffer management area DA of the RAM 31b.
Subtract the number of used units USEG and get this free space
Update FSEG and also update the buffer address BADR
Add the number of units used, USEG, to the start address
Update BADR. Steps: S215 to S224 The MPU 30 reads the usage segment USEG indicating the number of usage units (reception block length) mentioned above and the RAM 31b.
and the maximum block length MAXL of the data buffer management area DA. As a result of this comparison, if the used segment USEG is larger than the maximum block length MAXL, the maximum block length MAXL of the data buffer management area DA is updated to this used segment USEG. Furthermore, the final limit value depends on the recording density and maximum block length MAXL.
Update CBE. That is, the MPU 30 reads the write recording density of the mode area EA and the maximum block length MAXL of the area DA of the RAM 31b, and when the recording density is 1600 rpi, if the maximum block length MAXL is greater than 16, the final limit value is set to the minimum value of 2. , if the maximum block length is 16 or less, set the final limit value CBE to 4. Similarly, if the recording density is 6250rpi. , if the maximum block length MAXL is greater than 32, the final control value CBE
When the maximum block length MAXL is between 17 and 32, the final limit value CBE is set to 4.
If MAXL is 16 or less, set the final limit value CBE to 8. Conversely, the used segment USEG is the maximum block length.
If it is less than MAXL, S216 does not update the maximum block length MAXL and final limit value CBE mentioned above.
The process advances to step S225. Steps: S225 to S233 S225 reads the ET mode of area EA of the RAM 31b and determines the termination processing mode. If it is in logical ET mode or physical ET mode and buffered mode, see Figure 2 c.
As shown in FIG.
If the flag and the actual ET detection signal are not on, a high-speed running instruction is added to the command given from the host controller and the command buffer area is
Store in CBUF. If the LET flag or the actual ET detection signal is on, the synchronization flag is turned on in steps S229 to S231 to perform non-buffered processing. If the mode is physical ET mode and non-buffered mode in S225, it is checked whether the redused flag is set. If the redeployed flag is off, the process moves to step S229 to perform instruction prefetch processing. If the redeployed flag is on, the synchronization flag is turned on to perform non-buffered processing, and the high-speed driving instruction is removed from the command given by the host controller.
Store in CBUF. The reason why the magnetic tape runs at a low speed is as follows. In non-buffered mode, the interval between issuing commands to the drive becomes longer, so even if high-speed running is instructed, unless the interval between issuing commands from the host controller is very short, it is necessary to maintain high-speed running (high-speed streaming operation). The next command cannot be issued to the drive within a certain amount of time, so the drive stops running the magnetic tape and performs repositioning. As a result, repositioning occurs in one instruction, resulting in extremely poor performance. When running at low speed, the interval time between issuing commands required to maintain streaming operation becomes longer, which reduces the possibility of repositioning occurring.Even if repositioning occurs, repositioning is completed in a shorter time than when running at high speed. There are also drives that do not require repositioning when driving at low speeds. By running at such a low speed, performance deterioration due to frequent repositioning can be prevented. Note that both the LET flag and the redused flag are flags that are set in the drive side processing routine, and after detecting the early warning point EWP as shown in FIG. may be of a different length or even zero), that is, the logical E
When reaching the T point LET, determine the ET processing mode, and if it is the logical ET mode, LET
The flag and redused flag are turned on, and in the case of physical ET mode, only the redused flag is turned on. Furthermore, if the distance information is lost (a read-related command is executed) after EWP is detected but before reaching LET, only the redeployed flag is turned on regardless of the ET processing mode. After the above processing, the MPU 30 determines the number of instructions stored
S233 adds 1 to CBSTK and updates the instruction buffer management area CA of the RAM 31b. Steps: S234 to S236 If the reused flag is not set, the instruction buffer size CBSIZE is set to 64. Otherwise, set the instruction buffer size CBSIZE to the final limit value CBE. Steps: S237 to S238 If the drive is not executing an instruction, drive startup processing, which will be described later with reference to FIG. 13, is performed. Steps: S239 to S240 If the synchronization flag is set, it is a non-buffer mode, so the process waits until the drive finishes executing the instruction. Steps: S241 to S244 After the drive processing is completed, the MPU 30 sends the host interface circuit 32b to the host controller.
At the same time, it reports completion (normal completion or error), turns off the data busy DBY signal, and returns to the startup waiting routine shown in FIG. If actual EOT is being detected and if the LEOT flag is on, EOT detection will be reported at the same time as the completion report. FIG. 12 is a flowchart of host read system processing. The operation will be described below. Steps: S301 to S306 Steps S141 to S14 of the startup process in FIG.
When a read-related command is received by MPU 7 and startup processing is performed, the MPU 30 reads the area CA of the RAM 31b.
Subtract 1 from the number of look-ahead blocks CBSTK. The MPU 30 checks whether the drive control unit 2 is executing an instruction, and if it is stopped, performs drive activation processing, which will be described later with reference to FIG. The MPU 30 checks whether the number of instructions stored (preread block number) CBSTK in the area CA mentioned above is 0 or more, and
If it is a smaller negative value, the read data has not been transferred to the data buffer 34, so the CBSTK
It waits until 0 or more, that is, one or more blocks of read data from the drive 1 have been transferred to the data buffer 34. When the number of look-ahead blocks CBSTK becomes 0 or more,
MPU30 is host interface circuit 32b
Turn on data busy DBY via , and notify the host controller that execution has started. Since the read data should have been transferred from the drive 1 to the data buffer 34, the MPU 30
The read execution result, the start address RADR of the read data in the data buffer 34, and the number of read bytes RBC are read from the instruction buffer CBUF of the RAM 31b. Steps: S307 to S311 The MPU 30 checks the read direction, and in the case of forward, checks whether the load point LDP was detected when the drive processed the block based on the read execution result read from the instruction buffer CBUF of the RAM 31b in the step described above. investigate. If the load point LDP had been detected, the first block would have been read from the load point LDP, so the recording density is checked from the read execution result. The recording density of the read execution result indicates the recording density of the magnetic tape read. And the recording density
If it is 1600rpi, the final limit value CBE of the instruction buffer management area CA of the RAM 31b is set to 8, and if it is 6250rpi, the final limit value CBE is set to 16 at the same time. Steps: S311 to S313 When the magnetic tape hits the load point LDP during read operation in the reverse direction, that is, when the magnetic tape reaches the starting point, the MPU 30 performs S311 to S313.
311, If the data cannot be transferred because there is no data block after reading, S312, Tape mark
If TM is detected (S313), the process moves to step S320 to report completion to the host controller. Steps: S314-S319 In cases other than those described in steps S311-S313, the MPU 30 determines whether the read-related command given from the host controller involves data transfer. Read commands that do not involve data transfer include Space, Backspace, and Space file.
File) Back Space
File). If it is a read-related command that involves data transfer, the data transfer to the host controller is executed. That is,
The MPU30 is the instruction buffer of the RAM31b.
First buffer address read from CBUF
RADR is set in the load address counter LCTR of the data transfer control circuit 33, the number of read bytes is set in the byte counter BCTR, and the data transfer control circuit 33 is activated. As a result, the data transfer control circuit 33 outputs the read strobe pulse RSTB (FIG. 6i) and the load address counter LCTR.
The read data in the data buffer 34 is transferred to the host controller according to the address. Load address counter LCTR stores read data as 1
Counts up every time a byte is transferred. When the data transfer control circuit 33 determines that data transfer for the number of read bytes has been completed, the MPU 30
is the data buffer management area DA of RAM31b
Add the used segment USEG to the free space FSEG and update it. On the other hand, since the read data is transferred to the data buffer 34 even in read instructions that do not involve data transfer, the free space in step S318 is
Update FSEG. Next, the MPU 30 checks whether the aforementioned read-related command is a file search-related command, such as a space file or a backspace file, and if it is a file search-related command, the process returns to step S301.
In other words, file search instructions are divided into read instructions. Steps: S320 to S321 If the instruction is not a file search type command, or if the read direction is forward and the load point LDP has not been detected in step S308, if the load point is reached during a read operation in the reverse direction, there is no data block. or tape mark detection, the MPU 30 reports normal completion or error completion to the host controller from the host interface circuit 32b, turns off the data busy DBY signal, and
Return to the startup wait routine. (e) Description of drive processing operation FIG. 13 is a flowchart of drive activation processing. The details of the processing will be described below. Steps: S401 to S405 The MPU 30 determines whether the instruction to be executed is a write type or a read type depending on whether the transfer direction mode of the data transfer control circuit 33 is a write mode or a read mode. If it is in read mode, it is determined to be a read-related command,
The MPU 30 checks whether the number of pre-read blocks CBSTK in the area CA of the RAM 31b is a negative value smaller than zero. If CBSTK is greater than or equal to zero, it has already read ahead, so check whether it is okay to start it. Returns if startup is not possible (stopped due to an error detected during pre-reading). On the other hand, if it is possible to start, the number of read-ahead blocks CBSTK in the instruction buffer management area CA of RAM31b
Check whether is less than 63. If it is not smaller than 63, the instruction buffer CBUF in the RAM 31b is full, and the process returns. On the other hand, if the number of read-ahead blocks is less than 63, it is checked whether the free space FSEG is 64KB or more, and if it is less than 64KB, it is returned as data transfer is not possible. Step: Free space FSEG is 64KB in S406
If the above is the case, data can be transferred from drive 1, so MPU 30 uses the starting address of RAM 31b.
BADR is set in the store address counter SCTR of the data transfer control circuit 33, and the data transfer control circuit 33 is placed in a standby state. Next, the MPU 30 turns off the distance counting valid flag, and when the read direction is reverse, turns off the LEOT flag. After turning off, the MPU 30 starts up via the drive interface circuit 32a.
Issue the GO signal and the relevant read-related command to drive 1, and return. A high speed driving instruction is added to the command issued at this time. Steps: S421 to S426 If the command is in write mode in step S401, it is determined that it is a write-related command, and preparations are made for automatic transfer to the drive. That is, the MPU 30 reads the write-related instruction from the instruction buffer CBUF of the RAM 31b, and checks whether this instruction involves data transfer. If the instruction involves data transfer, the MPU30 will use the RAM31
Start address from instruction buffer CBUF of b
WADR and byte number WBC are detected and set in the load address counter LCTR and byte counter BCTR of the data transfer control circuit 33, respectively. Furthermore, the data transfer control circuit 33 is put into a standby state. Steps: S427 to S429 After this standby state, or if it is a write command (erase, write tape mark, etc.) that does not involve the aforementioned data transfer, the MPU 30 determines whether the EWA signal is on or off from the drive interface circuit 32a. Find out. If the EWA signal is off, the magnetic tape is not in the EWA area, so
In order to initialize the end of the magnetic tape, turn on the distance counting valid flag and clear the redused flag and EOT counter ECTR. Thereafter, the MPU 30 issues the activation GO signal and the write-related command via the drive interface circuit 32a, and returns. FIG. 14 is a flow diagram of the drive write process. The processing will be described below. Steps: S501 to S511 When the MPU 30 receives the completion report from the drive,
It is checked whether the completed instruction type is read type or write type, and the process proceeds from read type to drive read processing shown in FIG. 15. If the completed instruction type is write type, MPU30
checks the write recording density of area EA of RAM 31b. Depending on whether the recording density is 6250rpi or 1600rpi, the write tape mark length WTM and erase length in the following travel counter increments and LEOT detection point detection processing
The only difference is the ERS, IBG length, and judgment value EPTR, and the processing itself is completely the same. The MPU 30 checks whether the instruction in the instruction buffer CBUF is a write instruction, erase variable instruction, write tape mark instruction, or fixed erase instruction. If the instruction is a write instruction or an erase variable instruction, the number of bytes read from the instruction buffer CBUF.
Convert WBC to the used segment USEG and set it as a temporary value L. Also, if the command is a write tape mark command, the write tape mark length is a fixed value.
WTM is similarly set to a temporary value L. Furthermore, if the instruction is a fixed erase instruction, the fixed erase length ERS is similarly set to a temporary value L. Then, the IBG length is further updated by adding it to the temporary value L. Step: S512 to S518 Magnetic tape is in early warning area EWA
If it is not within the EWA, there is no need to count the distance, so the process moves to step S519. If it is within EWA, check whether the distance counting valid flag is on or not, and if it is not on, proceed to step S518.
If the distance counting valid flag is on, the above-mentioned temporary value L is added and updated to the travel count value ECTR. Next, it is determined whether the travel count value ECTR is 50 feet or more, and if it is less than 50 feet, there is no need to change the instruction preemption control, so the process moves to step S519. If it is 50 feet or more, check the ET processing mode, and if it is physical ET mode, proceed to step S518 and turn on the redused flag, and if it is not physical ET mode, turn on the LET flag and redused flag from S517 to
S518. Steps: S519 to S522 If the instruction involves data transfer, add the used segment USEG to the free segment FSEG,
Update free segment FSEG. Next, subtract 1 from the instruction stack CBSTK,
Returns if CBSTK is zero. Otherwise, the process moves to the aforementioned write-related processing continuation processing shown in FIG. 13. FIG. 15 shows a flowchart of the drive read process. The processing will be described below. Steps: S551 to S561 When the MPU 30 reaches the load point LDP during a read operation in the reverse direction, when no data block is detected during a read operation in the forward direction, when a tape mark is detected, the MPU 30 reads the read data from the drive. Since no transfer was performed, the process moves to step S561, stores the read execution result in the command buffer CBUF, and then returns. In cases other than the above, calculate the byte count BC and store the buffer address BADR and byte count BC in the command buffer CBUF.
Furthermore, the used segment is changed from the free segment FSEG.
Update free segment FSEG by subtracting USEG,
Segment USEG used for buffer address BADR
is added to update the buffer address BADR. Next, if the read direction is forward and EOT is detected, the process moves to step S561, stores the read execution result in the command buffer area CBUF, and returns. If the read direction is reverse or forward and EOT is not detected, the read execution result is stored in the command buffer area CBUF, and then the command stack number CBSTK is checked. If the command stack number CBSTK is 63 or more, the command buffer area CBUF has not been fully prefetched, so the process returns. If the command stack number CBSTK is less than 63, pre-reading is possible, so read processing continues and the process moves to FIG. 13. [Effects of the Invention] As described above, according to the present invention, magnetic tape termination processing specified from the operator panel can be performed according to either the physical EOT mode or the logical EOT mode. target
Regarding EOT mode, processing in buffered mode or non-buffered mode is also possible. Particularly in the non-buffered mode, the operation is the same as in the conventional system in which access is made for each instruction, and the physical EOT and logical EOT match. Even in this case, except for the end of the magnetic tape,
Needless to say, instruction prefetch processing is performed. In addition, since the running speed of the magnetic tape is kept low in the non-buffered mode, performance deterioration due to frequent repositioning can be prevented.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the principle of the present invention, FIG. 3 is an overall block diagram of an embodiment of the present invention, and FIGS. 4 and 5 are block diagrams of the block diagram of FIG. 3.
6a-j and 7a-e are operation timing diagrams of the device in FIG. 3, FIGS. 8-10 are startup processing flowcharts of one embodiment, and FIGS.
The figure is a flowchart of an example of host processing,
13 to 15 are flowcharts of one embodiment of paired drive processing, FIG. 16 is an explanatory diagram of instruction preemption control of a magnetic tape device, and FIGS. 7A and 7B are explanatory diagrams of the prior art. Explanation of symbols, 1...Magnetic tape drive section, 2...
Drive control unit, 3...Instruction/data prefetch control unit, CBUF...Instruction buffer, 34...Data buffer.

Claims (1)

[Scope of Claims] 1. A magnetic tape drive section 1 having a magnetic tape drive mechanism that drives a magnetic head 14 and a magnetic tape 16 wound on reels 11 and 12; an access command to the magnetic tape given from a higher level; buffer control means 3 for preemptively storing a plurality of data and transmitting the results of access to the magnetic tape to the upper layer; Magnetic tape control means 2, 2 that controls the drive section and performs operations in response to the access command.
0, 21, wherein the buffer control means operates based on a predetermined physical termination processing mode or logical termination processing mode, and preemptive access mode or normal access mode. ) In the case of the physical termination processing mode, in the preemption access mode, the number of preemption instructions in the area before the end area of the magnetic tape is reduced to a predetermined value, and when the magnetic tape reaches the end area, the number of prefetch instructions is reduced to zero. (b) In the case of the logical termination processing mode, when the area before the end area of the magnetic tape is reached, the number of prefetch instructions is zero. If so, the magnetic tape device is configured to notify the upper level of the termination area, reduce the number of preemption instructions to zero, and access the magnetic tape according to the termination processing mode and the access mode.