JP2546074B2 - Disk unit usage rate collection method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk control device having a cache memory, and in particular, when the data on the cache memory does not hit and the disk device is used, the usage rate is collected and reported to a host device. The present invention relates to a usage rate collecting method of a disk device that enables the operation.

Since a disk device used as an external storage device of a computer system needs a mechanical operation for positioning a head at a specified address in order to read data from an address specified by a host device, it is accessed. Time will increase.

In order to shorten the access time, a disk controller provided with a cache memory is provided so that frequently accessed data is stored in the cache memory and hit data is transferred from the cache memory. There is.

If there is no data required by the host device in the cache memory and there is a mishit, the disk controller reads the specified data from the disk device and transfers it to the host device, and at the same time, the cache memory. However, if the usage rate of the disk device exceeds a certain value, the response from the disk control device to the input / output command sent by the host device becomes slow.

Therefore, the higher-level device needs to adjust the issuance of the I / O command according to the usage rate of the disk device, but for this purpose, it is necessary to recognize the usage rate of the disk device.

[0006]

2. Description of the Related Art FIG. 4 is a block diagram for explaining an example of a conventional technique, and FIG. 5 is a detailed block diagram of each functional unit.

The disk controller 3 is composed of a plurality of functional units and is a channel adapter (hereinafter abbreviated as CA).
6 to 9 have a configuration as shown in FIG.
Is operated by reading the program stored in the control memory 22 and is transmitted via the interface circuit 19 to the central processing unit 1 or 2 via a channel (not shown).
/ O command is received and data is transferred to and from the central processing unit 1 or 2, and the common bus control circuit 20 is controlled to transfer data to and from another functional unit via the common bus 17 or 18. I do.

Device adapter (abbreviated as DA hereinafter) 10
5 to 13 have a configuration as shown in FIG.
Reads out the program stored in the control memory 22 to operate, sends a command to the disk device 4 or the disk device 5 via the interface circuit 19, performs data transfer with the disk device 4 or 5, and The bus control circuit 20 is controlled to transfer data with another functional unit via the common bus 17 or 18.

Resource manager (hereinafter abbreviated as RM) 1
Reference numeral 4 denotes a configuration as shown in FIG. 5 (B), in which the processor 24 reads a program stored in the control memory 23 to operate and controls the common bus control circuit 25 to pass through the common bus 17 or 18. All the start I / O commands from the central processing unit 1 or 2 are received and stored in the RAM 26, and these start I / O commands are centrally managed, and each start I / O command is received.
For each / O command, the CA 5-9 and DA 10-13 are instructed to perform data transfer processing.

The control information for each received start I / O command, the control information for each channel path, and the control information for the disk devices 4 and 5 are stored in the RAM 26, and the other functional units are the RAM access control circuit 27. Via RAM26
Can be accessed and the above information can be read, and this information is centrally managed.

The cache control circuit 15 has a configuration as shown in FIG. 5C, and the processor 29 operates by reading the program stored in the control memory 28, and controls the common bus control circuit 30 to perform the common bus control. The data entered via 17 or 18 is written to the cache memory 16, and the data read from the cache memory 16 is shared bus 17 or 1.
The data written in the cache memory 16 is periodically written to the disk device 4 or 5 according to the instruction from the RM 14.

Then, the data stored in the cache memory 16 is managed, it is checked whether or not the data requested to be transferred by the CAs 6 to 9 exists, and it is determined whether it is a hit or a mishit.

For example, if the central processing unit 1 is CA6,
When a start I / O command is sent, the address of the disk device 4, that is, the cylinder address, the head address, and the record address are designated and the data reading is instructed,
The CA 6 requests the RM 14 to use the common bus 17, and when permitted, sends out the address of the cache control circuit 15 and couples it.

When this coupling is completed, the CA 6 causes the cache control circuit 15 to check whether the data at the address designated by the central processing unit 1 exists in the cache memory 16.

If the cache memory 16 exists, that is, if there is a hit, the cache memory 16
The data hit from is read out and transferred to the central processing unit 1.

However, if the data at the specified address does not exist in the cache memory 16 and a mishit occurs,
When the address of the DA 10 is transmitted and combined, the DA 10 is instructed to position the head at the specified address of the disk device 4, and when the data read from the disk device 4 is received via the DA 10, it is transferred to the central processing unit 1. To do.

At this time, the cache control circuit 15 uses the DA
The data sent by the 10 to the common bus 17 is written in the cache memory 16. The same applies when the central processing unit 1 accesses the disk device 5 via CA8.
In the case of a mishit, the data is read from the disk device 5 via the DA 12.

The same is true when the central processing unit 2 accesses the disk device 4 via the CA 7. If a mishit occurs, the data is read from the disk device 4 via the DA 11.

The same applies when the central processing unit 2 accesses the disk unit 5 via the CA 9.
In the case of a mishit, the data is read from the disk device 5 via the DA 13.

[0020]

As described above, conventionally, when the central processing unit 1 or 2 reads data from the disk unit 4 or 5, the central processing unit 1 or 2 accesses the disk control unit 3 by using the cache. It is the same regardless of whether the data existing in the memory 16 hits or misses, and the access frequency is not adjusted depending on the usage rates of the disk devices 4 and 5.

Therefore, the hit rate of the data existing in the cache memory 16 is good, and even if the disk devices 4 and 5 are hardly accessed, the frequency of sending the I / O command is not increased, and a miss occurs. The number of hits is high and the usage rates of the disk devices 4 and 5 increase, and the disk control device 3 responds to an I / O command sent when the disk capacity exceeds a certain value.
It does not reduce the frequency of sending and receiving I / O commands even if the response from the device is delayed.

Therefore, the processing efficiency of the disk control device 3 is poor, and therefore the processing efficiency of the computer system is lowered. In view of such a problem, the present invention notifies the central processing units 1 and 2 of the usage rates of the disk devices 4 and 5 to correspond to the usage rates of the disk devices 4 and 5 and to the disk control device 3. The purpose is to be able to adjust the access frequency.

[0023]

FIG. 1 is a block diagram for explaining the principle of the present invention. The disk control device 31 controls data transfer between the higher-level device 32 and the disk device 4, and also stores the higher-level device 32 in the cache memory 16.
Data having a high access frequency is stored and the hit data is transferred from the cache memory 16.

Then, the counting means 33 for counting the time when the disk device 4 and the disk control device 31 are coupled to each other and the counting means 33 are allowed to operate for a predetermined time based on a request from the host device 32. And a control means 34 for controlling the total number of hours when the disk device 4 and the disk control device 31 are combined within the predetermined time.
3 is counted, and the count result of the counting means 33 is divided by the predetermined time to calculate the usage rate of the disk device 4.

[0025]

With the above configuration, the disk control device 31 can calculate the usage rate of the disk device 4 within a predetermined time, and therefore notifies the host device 32 of the usage rate of the disk device 4. You can

Therefore, the upper device 32 is the disk device 4
If the usage rate of the disk device is less than a certain value, the frequency of sending the input / output command to the disk device 4 can be increased and the load on the disk device 4 can be increased.

When the value exceeds the fixed value, the processing efficiency of the disk controller 31 can be always maximized by waiting for the output of the input / output command.

[0028]

2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of FIG.

The same reference numerals as those in FIG. 4 denote the same functions.
The RM 35 of the disk control device 31 has a built-in counter 36, and when the central processing unit 1 or 2 issues an instruction to collect performance information via CA 6-9, the measurement time T of FIG.
As shown in, the counter 36 is controlled to be enabled for a predetermined time, that is, T time.

When notified from the DAs 10 to 13 that the disk device 4 and / or the disk device 5 is connected, the counter 36 is activated to count the time as shown in S ₁ of FIG. When the connection is released, the counter 36
The counting operation of is stopped.

That is, the time during which the transfer of commands and the transfer of data between the DAs 10 to 13 and the disk device 4 and / or the disk device 5 is performed is counted. Therefore, within this counting time S ₁ , the counting time is the same whether the disk devices 4 and 5 operate independently or simultaneously.

When the DAs 10 to 13 notify the disk device 4 and / or the disk device 5 again, the counter 36 is activated to count the time as shown in S ₂ of FIG. When the connection is released, the counting operation of the counter 36 is stopped, and the disk device 4 and / or
Alternatively, when it is notified that the disk device 5 is connected, the counter 36 is activated to count the time as shown in S ₃ of FIG. 3, and when the connection is released, the counting operation of the counter 36 is stopped.

The RM 35, when a predetermined time T has passed,
With the counter 36 disabled, the count value S ₁ +
S ₂ + S ₃ is read and the usage rate of the disk device is calculated as shown in the usage rate of FIG.

That is, (S ₁ + S ₂ + S ₃ ) / T is calculated and notified to the central processing unit 1 or 2.

[0035]

As described above, according to the present invention, since the usage rate of the disk device can be calculated and notified to the higher-level device, the higher-level device responds to the usage rate of the disk device by inputting / outputting data. The frequency of issuing commands can be adjusted.

Therefore, it is possible to improve the processing efficiency of the disk control device, which in turn can improve the processing efficiency of the computer system.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of FIG.

FIG. 4 is a block diagram illustrating an example of a conventional technique.

FIG. 5: Detailed block diagram of each functional unit

[Explanation of symbols]

 1, 2 Central processing unit 3, 31 Disk control unit 4, 5 Disk unit 6-9 Channel adapter 10-13 Device adapter 14, 35 Resource manager 15 Cache control circuit 16 Cache memory 17, 18 Common bus 19 Interface circuit 20, 25 , 30 Common bus control circuits 21, 24, 29 Processors 22, 23, 28 Control memory 26 RAM 27 RAM access control circuit 32 Upper device 33 Counting means 34 Control means 36 Counter

Claims (1)

(57) [Claims] 1. A cache memory (16) for controlling data transfer between a host device (32) and a disk device (4).
Data frequently accessed from the upper device (32) is stored on the upper side, and hit data is stored in the cache memory (16).
In the disk control device (31) to be transferred from And a control means (34) for permitting the counting means (33) to operate during the period of time, and the disk device (4) and the disk control device (31) are combined within the predetermined time. The counting means (33) counts the total number of hours, and the counting means (3
A usage rate collecting method for a disk device, wherein the usage rate of the disk device (4) is calculated by dividing the counting result of 3) by the predetermined time.