JP3442099B2 - Data transfer storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer storage device for storing data transferred from a host device in accordance with a command from the host device or reading the stored data and transferring the data to the host device.

[0002]

2. Description of the Related Art A conventional data transfer storage device performs data transfer by DMA transfer between a host device and a buffer memory and between a buffer memory and an I / O device.

[0003]

However, since the conventional data transfer storage device has a circuit for performing the DMA transfer on both the upper side and the lower side via the buffer memory, the circuit of the hardware is Ri is Na large scale, on which device is expensive, Oh is difficult to reduce the size of the device
And the amount of data transferred from the host to the host
There was a problem that it was necessary to notify in advance .

The present invention solves such a conventional problem, simplifies the device configuration by controlling software, and performs the handshake procedure with, for example, the host side.
Therefore, the data transfer amount is obtained in advance from the upper side.
An object of the present invention is to provide a data transfer storage device that can perform high-speed processing equivalent to a DMA operation even if it is not possible .

[0005]

In order to achieve the above-mentioned object, the present invention firstly, receives an instruction from a host device and transfers data to the host device in n bits (where n is 2).
Upper device processing means for transmitting each of the above natural numbers, first storage means for temporarily storing the data, at least one second storage means for storing the data, and the first storage Control means for performing DMA transfer of data according to a predetermined transfer instruction between the means and the second storage means, and a command for interpreting the command received by the host device processing means and giving the transfer instruction to the transfer processing means. In the data transfer storage device, the upper device processing means is capable of reading and writing n × m bits ( however, by the control means).
However , m is a natural number of 2 or more) , a plurality of data registers, a status register for displaying the presence / absence of data in the plurality of data registers, and when data is written in the plurality of data registers, n × m bit
Divide the data into n-bit data, and divide the divided n-bit data.
The Ttodeta divided into m times a data transfer control means for transferring to the host system, wherein the control means includes a command recognition means for reading the instruction from the host system, said command recognition unit, the second And a transfer instruction means for instructing the transfer processing means to perform DAM transfer from the second storage means to the first storage means, Data writing means for writing data in the means to the plurality of data registers in units of n × m bits , wherein data of one data register among the plurality of data registers is used as the data during the transfer control means transfers, among the plurality of data registers, read the status of the other data registers from the status register, the state of the status register is "data Mu" Noto Data writing means for writing the data in the first storage means to the other data register,
Secondly, it receives the command from the higher-level device and transfers n bits (however,
Where n is a natural number of 2 or more), a host device processing means for receiving data for each, a first storage means for temporarily storing the data, and at least one second storage means for storing the data.
Storage means, transfer processing means for performing DMA transfer of data between the first storage means and the second storage means in accordance with a predetermined transfer instruction, and the instruction received by the host device processing means, In a data transfer storage device comprising a transfer processing means and a control means for giving the transfer instruction, the host device processing means is a data reception control means for receiving data from the host device, and the control means is readable and writable. Constructed from n × m bits (where m is a natural number of 2 or more)
A plurality of data registers and the n-bit data received by the data reception control means are divided into m times,
Serial data transfer control means for transferring to the data register, and a status register indicates whether the state of the data in said plurality of data registers, said control means, command recognition means for reading said instructions from said host device And when the command recognition means recognizes a transfer command from the host device to the second storage means, the data transferred to the plurality of data registers is read as n × m bit data, This was a data transfer means for writing in said first memory means in n × m bits among the plurality of data registers, n × m bits of one data register
The door data during transfer said data transfer control means, among the plurality of data registers, the other data register state
Read from the status register
When the status of the register is “with data”, the data transfer means for reading n × m bit data in the other data register and the transfer processing means from the first storage means to the second storage means DAM. And a transfer instruction means for giving a transfer instruction.

[0006]

According to the present invention, by the instruction from the host device,
The data write operation from the host device to the first storage means at the time of writing, and the operation of reading data from the first storage means at the time of read to the upper apparatus, the upper
Informs the amount of data transfer required by the host device from the device in advance
Even if you can not use DMA transfer without being asked,
It can be processed at high speed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the data transfer storage device 8 is connected to the host device 1 by a signal line 9. The data transfer storage device 8 is internally connected to the CPU 2 serving as a control unit via the CPU 2 and the CPU bus 10, receives commands from the host device, and transmits / receives data to / from the host device. It has a higher-level device processing unit 3 for performing the operation. Also,
A buffer memory 6 that is a first storage unit that temporarily stores data and a buffer memory processing unit 4 that controls the buffer memory 6.
have. In addition, SCSI (Small Com
a plurality of I / O devices 7 (7a, 7) that are second storage means conforming to the computer system interface.
b, 7c), the buffer memory processing unit 4 and the I / O device 7 are provided with a SCSI processing unit 5 as a transfer processing unit that performs DMA transfer of data according to a transfer instruction of the CPU 2.

The SCSI processing unit 5 and the buffer memory processing unit 4 are connected via a signal line 11a, and the SCSI processing unit 5 and the I / O device 7 are connected via a SCSI bus 12. Up to seven I / O devices 7 can be connected.

Next, the operation of the data transfer storage device 8 will be described.

The interface of the signal line 9 connecting the higher-level device 1 and the higher-level device processing section 3 has an 8-bit data line and a control line of up and down, operates in a handshake procedure, and activates and transfers commands. , Transitions in three stages of reporting. The maximum transfer rate of the signal line 9 is 500 KByte / sec due to the restriction of the host device 1.

First, the operation (write operation) of writing data from the host device 1 to the I / O device 7a will be described.
In the command activation sequence from the host device 1, a command, that is, an instruction, is sent via the signal line 9 to the host device processing unit 3
To receive. The reception completion is notified to the CPU 2 by an interrupt signal, and the CPU 2 reads the command from the higher-level device processing section 3. In response to the command, the CPU 2 issues a data transfer request to the host device processing unit 3. The host device processing unit 3 requests the transfer sequence from the host device 1.

When in the transfer sequence state, the host device 1
8 bits of data from the
When the data for bytes is accumulated, the CPU 2 reads it as 32-bit data from the higher-level device processing unit 3 and writes it in the buffer memory 6 via the buffer memory processing unit 4. The process of writing data from the host device 1 to the buffer memory 6 is repeated until the transfer amount requested by the host device 1.

When the transfer to the buffer memory 6 is completed,
The CPU 2 instructs the buffer memory processing unit 4 and the SCSI processing unit 5 to perform a DMA (direct memory access) operation, converts the 32-bit data in the buffer memory 6 into 8 bits in the buffer memory processing unit 4, and causes the SCSI processing unit 5 to operate. Then, DMA transfer is performed to the I / O device 7a. When this transfer sequence ends, the CPU 2 sends a report request to the higher-level device processing unit 3, and the higher-level device processing unit 3 requests the higher-level device 1 for the report sequence. In the report sequence state, the CPU 2 writes the status information indicating the normal writing operation end to the higher-level device processing unit 3, and this status information is transferred from the higher-level device processing unit 3 to the higher-level device 1.
The write operation ends.

Next, the operation (read operation) of reading data from the I / O device 7a to the host device 1 will be described.
Similar to the write operation, in the command activation sequence, the command is received by the host device processing unit 3 from the host device 1 via the signal line 9. When the reception is completed, the CPU sends an interrupt signal
2 is notified, and the CPU 2 reads the command from the higher-level device processing unit 3. In response to the command, the CPU 2 instructs the buffer memory processing unit 5 and the SCSI processing unit 5 to perform a DMA operation, and the 8-bit data read from the I / O device 7a is processed by the buffer memory processing unit 4 via the SCSI processing unit 5. Three
It is converted into 2 bits and DMA-transferred to the buffer memory 6. When the DMA transfer is completed, the CPU 2 issues a data transfer request to the host device processing unit 3. The host device processing unit 3 requests the transfer sequence from the host device 1. In the transfer sequence, the CPU 2 reads the 32-bit data from the buffer memory 6 via the buffer memory processing unit 4 and writes the 32-bit data to the higher-level device processing unit 3. The written data is transmitted to the higher-level device 1 as 8-bit data and 4
When the transmission of the data of bytes is completed, the CPU 2 repeats the process of transferring from the buffer memory 6 to the higher-level device 1 up to the transfer amount requested by the higher-level device 1. When the transfer sequence ends, the CPU 2 issues a report request to the higher-level device processing unit 3.

The host device processing unit 3 requests the report sequence from the host device 1.

In the report sequence state, the CPU 2
Writes status information indicating the end of the normal reading operation in the higher-level device processing unit 3. This status information is transferred from the host device processing unit 3 to the host device 1, and the read operation is completed.

Next, the high speed processing in this embodiment will be described with reference to FIGS. 2, 3 and 4. FIG. 2 is a block diagram showing the operation of the higher-level device processing section 3. FIG. 3 is a flowchart of the read transfer process. FIG. 4 is a flowchart of the write transfer process.

In FIG. 2, the host device processing section 3 is the same as that of FIG.
As shown in FIG. 3, the CPU 2 and the host device 1 are connected, and the internal configuration is as follows. That is, the control register 13 that is a register for controlling the higher-level device processing unit 3 from the CPU 2, the status register 14 that is a register for reading the status information of the higher-level device processing unit 3 from the CPU 2, and the read / write data are held. A data register A15 and a data register B16, a register selector 17 for selecting a register to be specified from these registers by the CPU 2, and an I / O sequence controller 18 for controlling a transfer sequence with the higher-level device 1. , A data transfer control unit 19 for controlling data transfer in a transfer sequence with the host device 1, an output signal buffer 20 for sending to the host device 1, and an input signal buffer 21 for receiving from the host device 1. To be done.

First, the read operation will be described based on FIG. 3 with reference to the block diagram showing the operation of the host device processing section 3 in FIG.

In the transfer sequence, the CPU 2 of FIG. 2 sets the settings required for the read operation in the control register 1
Write to 3. Then buffer to data register A15
Read from the buffer memory 6 via the memory processing unit 4
The 32-bit data is written (step S1), and then the buffer memory processing unit 4 is loaded into the data register B16.
The 32-bit data read from the buffer memory 6 via the via is written (step S2). As a result, the 32-bit data first written to the data register A15 is divided into 8-bit data by the data transfer control unit 19, and the higher-level device 1 is passed through the I / O sequence control unit 18 and the output signal buffer 20. 4 bytes for each 1 byte, and then 3 written to the data register B16
Similarly to the data register A15, 2-bit data is transferred to the higher-level device 1 by 4 bytes one byte at a time.

Data register A15 and data register B
After writing to 16, the CPU 2 sets the status register 14
Is read, and it is checked whether or not the data register A15 is empty, that is, whether or not the transfer of 32-bit data is completed (step S3). If it is empty, the buffer memory processing unit 4 is transferred to the data register A15. Via buff
The next new 32-bit data read from the memory 6 is written (step S4). After that, the status register 14 is read and it is checked whether or not the data register B16 is empty (step S5). If the data register B16 is empty, the data register B16 is passed to the buffer memory processing unit 4.
Then, the next 32-bit data read from the buffer memory 6 is written (step S6). Then, it is checked whether or not the transfer is completed (step S7). If the transfer is not completed, the process returns to step S3, and if the transfer is completed, the process is completed.

As described above, during the read operation, while the data in the B-side register is being transferred to the host device 1, the data is written in the A-side register, and the data in the A-side register is transferred to the host device. High-speed processing can be performed by writing data to the B-side register while transferring to 1.

Next, the write operation will be described based on FIG. 4 with reference to the block diagram showing the operation of the host device processing section 3 in FIG.

In the transfer sequence, the CPU 2 of FIG. 2 sets the settings necessary for the write operation in the control register 1
Write to 3. Then, the status register 14 is read to determine whether the data register A15 is full,
That is, it is checked whether or not all the 32-bit data is stored in the data register A15 (step S8). If the 32-bit data is full, the 32-bit data is read from the data register A15 and the buffer memory processor 4 is used to read the data.
Write to the far memory 6 (step S9). After that, the status register 14 is read and the data register B1
6 is checked to see if it is full (step S10). If it is full, 32-bit data is read from the data register B16 and passed through the buffer memory processing unit 4.
Write to the buffer memory 6 (step S11). Then, it is checked whether or not the transfer is completed (step S12). If the transfer is not completed, the process returns to step S8, and if the transfer is completed,
The process ends.

In the above-described write operation processing, the data of 1 byte transferred from the host device 1 is transferred to the data transfer control unit 19 via the input signal buffer 21 and the I / O sequence control unit 18 of FIG. The data is combined into byte data and written as 32-bit data in the data register A15 or the data register B16.

As described above, during the write operation, while the data is being transferred from the higher-level device 1 to the register on the B side, A
Data is read from the register on the screen, and the host device 1
While transferring data to the register A plane from, it can be a high-speed processing by reading the more data registers B surface.

In this case, since the transfer rate between the host device 1 and the data transfer storage device 8 is 500 KByte / sec, the transfer time of 32-bit data, that is, 4 bytes is 8 microseconds. Further, since the time for which the CPU 2 sets the 32-bit data in the data register A or B is 1 microsecond or less, one of the data registers is vacant until the transfer of the 32-bit data is completed. The time to set 32-bit data in the data register can be almost ignored.

Although the I / O device is a device conforming to SCSI in the above embodiment, the present invention can be applied to other data transmission interfaces.

[0030]

As described above, according to the present invention, the host device
Even if the data transfer amount required by the device is not recognized in advance, the data from the host device is written to the I / O device at the time of writing and the data from the I / O device to the host device at the time of reading according to the command of the host device. Since the reading process can be performed at high speed and the hardware configuration for the DMA transfer process can be simplified, the cost of the device can be reduced and the device can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer storage device of the present invention.

FIG. 2 is a block diagram of a host device processing unit shown in FIG.

FIG. 3 is a flowchart showing a read transfer process of FIG.

FIG. 4 is a flowchart showing a write transfer process of FIG.

[Explanation of symbols]

1 Upper device 2 CPU (control means) 3 Upper device processing unit 4 Buffer memory processing unit 5 SCSI processing unit (transfer processing means) 6 Buffer memory (first storage means) 7a to 7c I / O device (second storage means) 8 Data transfer storage device 9, 11, 11a signal line 10 CPU bus 12 SCSI bus 13 Control register 14 Status register 15 Data register A 16 Data register B 17 register selector 18 I / O sequence controller 19 Data transfer control unit 20 output signal buffer 21 Input signal buffer

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References JP-A-2-284251 (JP, A)                 Japanese Patent Laid-Open No. 63-271563 (JP, A)                 JP 63-137358 (JP, A)                 JP-A-4-148268 (JP, A)                 JP-A-3-14157 (JP, A)                 JP-A-1-123318 (JP, A)

Claims (2)

(57) [Claims] 1. An n-bit data (where n is 2 or more) data which is received from a higher-level device and is transferred to the higher-level device.
Host device processing means for transmitting every natural number), first storage means for temporarily storing the data, at least one second storage means for storing the data, and the first storage means.
Transfer processing means for performing DMA transfer of data according to a predetermined transfer instruction between the storage means and the second storage means, and the instruction received by the higher-level device processing means, and read the transfer instruction to the transfer processing means. In the data transfer storage device having a control means for giving, the higher-order device processing means can read and write n × m bits (however, m
Is a natural number of 2 or more), a status register that indicates the presence / absence of data in the plurality of data registers, and data is written to the plurality of data registers.
Divide n × m bit data into n bit data,
Data transfer control means for dividing the divided n-bit data into m times and transferring the data to the upper device, the control means comprising: an instruction recognizing means for reading and understanding the instruction from the upper device; and the instruction recognizing means. Recognizes a transfer command from the second storage means to the higher-level device, transfer instruction means for instructing the transfer processing means to perform DAM transfer from the second storage means to the first storage means, Data writing means for writing data in the first storage means to the plurality of data registers in units of n × m bits , wherein data of one data register of the plurality of data registers is transferred to the data transfer means. control means during the transfer
To, among the plurality of data registers, read the status of the other data register from said status register, when the state of the status register is "Data Mu", the first of said other data the data in the storage means A data transfer storage device comprising: a data writing unit that writes data to a register. 2. An n- bit (where n is a natural number of 2 or more) received from a higher-level device and transferred from the higher-level device.
Host device processing means for receiving data for each number, first storage means for temporarily storing the data, at least one second storage means for storing the data, and the first storage means And a transfer processing means for performing DMA transfer of data between the second storage means and a predetermined transfer instruction, and a control means for interpreting the command received by the host device processing means and giving the transfer instruction to the transfer processing means. In the data transfer storage device, the upper device processing means includes a data reception control means for receiving data from the upper device, and n × m bits (where m is readable / writable by the control means ).
Is a natural number of 2 or more), and the n-bit data received by the data reception control means.
Data transfer control means for transferring the data to the data register in m times, and a status register for displaying the presence / absence state of data in the plurality of data registers, the control means comprising: When the command recognition means for reading the command and the command recognition means recognize the transfer command from the higher-level device to the second storage means, the data transferred to the plurality of data registers is n × m bit data. age
Te read, which a data transfer means for writing in said first memory means in n × m bits among the plurality of data registers, n × m-bi of one data register
The Tsu Miyako data during transfer said data transfer control means, among the plurality of data registers, read the status of the other data registers from the status register, the stay
When the status of the status register is “with data”, data transfer means for reading n × m bit data in the other data register, and the transfer processing means from the first storage means to the second storage means. A data transfer storage device, comprising: a transfer instruction means for issuing a DAM transfer instruction.