JPS6019023B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in electronic computer systems, and more particularly to a data processing device that enables periodic data transfer between peripheral devices that do not exclusively occupy a CPU.

In conventional data processing devices, when data is transferred between comparatively low-speed peripheral devices, it is necessary for the CPU to perform the above control and to use the main memory as a data transfer path. Therefore, when using the above-mentioned device to transfer a large amount of data between peripheral devices, the CPU must be used exclusively for a long period of time. In order to eliminate the above-mentioned disadvantages, various improvements have been made to data transfer paths and the like.
FIG. 1 is a block diagram of a conventional data processing device, in which 1 is a main memory, 2 is a CPU, 3 and 4 are peripheral devices, and 5 is a block diagram of a conventional data processing device.
is a data transmission channel that enables data transfer between peripheral device 3 and peripheral device 4. The data transmission channel 5 is connected to the peripheral device 3 and the peripheral device 4 and to the CPU 2.
It is activated by a command from U2 and starts data transfer. Once activated by the CPU 2, the data channel 5 controls data transfer between the peripheral device 3 and the peripheral device 4 without passing through the main storage device 1 without a command from the CPU 2. However, even in the data processing apparatus as described above, in order to perform data transfer at a fixed period (for example, one hour is one day), the CPU 2 has to issue a data transfer request to the channel at a fixed period.

The present invention provides a data transmission channel with a built-in timer between peripheral devices whose input/output operations are controlled by the CPU, and enables periodic data transfer between the peripheral devices without monopolizing the CPU. The purpose is to obtain a processing device.

The invention relates to an improvement of the data transmission channel 5 of FIG.

FIG. 2 shows its block diagram. 6 is a buffer memory for temporarily storing information input from the peripheral devices 3 and 4; 7 is a data line connecting the peripheral devices 3 and 4 and the buffer memory; and 8 is a status and control line.

11 holds the address to retrieve information from the buffer memory,
This is a designated output address register, and 12 is a write address register that holds and designates an address at which information is stored in the buffer memory.

A comparison circuit 10 compares the contents of the address register 11 and the address register 12 to determine the magnitude relationship.

9 controls the buffer memory, determines the status of the peripheral devices 3 and 4 through the status line 8, sends the status of the channel itself to the peripheral devices 3 and 4, and also uses the address when information is stored in the buffer memory 6. It is a control circuit that functions to update the contents of the register 12 and, when outputting information from the buffer memory 6, to update the contents of the address register 11.

22 is a timer that adds at a constant cycle, for example, adds 1 bit every second; 23 is a cycle time register that sets the cycle time T when data is transferred at a constant cycle; is set by the CPU 2 through the input/output bus 13.

25, when data is set in the period time register 23, the contents of the period time register (period time T) and the contents of the timer 22 (current time at that time)' are added by the adder 24, and the added result is obtained. (Time after time T has elapsed)
is a timer register in which is stored.

A comparison circuit 26 compares the contents of the timer 22 (the current time, which changes from moment to moment) with the contents of the timer register 25, and when they match, sends a signal to the control circuit 9 to start data transfer.

FIG. 3 shows a block diagram of the control circuit 9 of FIG.

14 is a first interface unit that checks the status of the peripheral device 3 that is about to input information to the channel and requests information; 15 is a buffer memory control unit that controls the input/output of information to the buffer memory 6; 16 is a second interface unit that checks the status of the peripheral device 4 that receives the information output from the channel and requests the transfer of the information, and 17 is the second interface unit that receives the information output from the channel through the input/output bus 13. In response to the activation command received and the activation signal sent from the comparator circuit 26 via the transfer start line 27, a data transfer start command is issued to the buffer memory control unit 15, and a data transfer start command is issued to the buffer memory control unit 15.
This is a control section that functions to update the contents of 1 and write address register 12, and to instruct the interface sections 14 and 16 to issue a status request.

Now, a case in which data is to be transferred between the peripheral devices 3 and 4 at one hour intervals will be explained with reference to FIG. First, the CPU 2 sets a cycle time, in this case 1 hour, in the cycle time register 23 via the input/output line 13, and then sends a start command to the control unit 17. When data is set in the period time register 23, the timer 2
2 and the contents of the period time register 23 are added, and the result is set in the timer register 25. The contents of the timer register 25 indicate the time for the next data transfer. Then, the contents of the timer 22 and the timer register 25 are compared, and if they match, an activation signal is sent to the control section 17. When the control unit 17 receives the start command from the CPU 2, it clears the contents of the address registers 11 and 12 to 0, and
A signal is sent to the first interface unit 14 to check the status of the peripheral device 3 to which information is to be output.

The first interface unit 14 uses this signal to connect the peripheral device 3.
sends a status request signal to The peripheral device 3 that has received the request signal sends the status to the first interface section 14, and the first interface section 14 checks the status. If the status is ready, a signal to start output operation is sent to the peripheral device 3, and the write address register 12 is
One block of information sent from the peripheral device 3 is stored at the address specified by the buffer memory write signal. After the storage is completed, the contents of the write address register 12 are updated by the control unit 17 to become the address to be written next.
Next, a signal is sent to the second interface unit 16 to check the status of the peripheral device 4 to which information is to be input.

The first interface section 14 then issues a status request signal to the peripheral device 4 based on this signal. The peripheral device 4 that has received the request signal sends the status to the first interface section 14, and the first interface section 14 checks the status. If the status is ready, the contents of the address specified by the logical address register 11 are outputted to the peripheral device 4 for one block by the buffer memory read signal.
The contents of the output address register 11 are updated by 17 and become the address to be read next. By repeating the above operation, the comparison circuit 10 compares the contents of the address registers 11 and 12, and sends an address match signal to the control section 17 when the contents become equal.

When the signal 17 receives this signal, it sends a channel busy signal to the peripheral device 4, instructing it to temporarily stop inputting information. The end of the data transfer is when the end signal is received from the peripheral device 3 that outputs the information. When the end signal is received, the end signal 16 sends the end signal to the peripheral device 4. Next, after a certain period of time (currently one hour) after the start of the data transfer, when the contents of the timer match the contents of the timer register that was set during the previous transfer, the comparison circuit 26 transfers the data to the control section 17. Send a start signal, add the contents of the period time register and the contents of the timer, and store the result in the timer register. When the control unit 17 receives the data transfer start signal sent from the comparison circuit 26, it sets the address registers 11 and 12 to 0 in the same way as when it received the startup command from the CPU last time.
A signal is sent to the first interface unit 14 to check the status of the peripheral device 3 that is to be cleared and output information, and the data transfer is thereafter controlled in the same manner as the previous time. By repeating this series of operations, data is transferred between peripheral devices at regular intervals. A data transmission channel is provided between the peripheral devices to enable periodic data transmission between the peripheral devices independent of the CPU.

The input/output control of the peripheral devices is performed by the data transmission channel, and the CPU can perform arithmetic processing in parallel, increasing the processing capacity of the data processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a subordinate data processing device, FIG. 2 is a block diagram of a data transmission channel 5 showing an embodiment of the present invention, and FIG. 3 is a block diagram of a control circuit 9 shown in FIG. , FIG. 4 is a timing diagram showing the operation of the data transmission channel 5. In FIG. 1...Main storage device, 2...CPU, 3, 4
... Peripheral device, 5 ... Data transmission channel, 6 ... Buffer memory, 7 ... Data line, 8 ... Status line, 9 ...・・・
・Control circuit, 10... Comparison circuit, 11...
...Proposal address register, 12. ．．・．． ．．・Write address register, 13...I/O line, 14・
... Peripheral device interface 1 section, 15 ... Buffer memory control section, 16 ... Peripheral device interface 2 section, 17 ... Control section, 18 ...
・Proposal address register control line, 19・
...Write address register control line, 20...Buffer memory control line, 21...
...Timer match line, 22... Timer, 23
. . . Period time register, 24 . . . Adder, 25 . . . Timer register, 26.・・・・
Comparison circuit, 27...Transfer start line. Figure 3 Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] 1. A data processing device that transfers data between multiple peripheral devices via a data transmission channel,
The data transmission channel includes a buffer memory that receives data to be transferred from a peripheral device on the data transmission side among the plurality of peripheral devices and temporarily stores the data, a timer that counts at a constant cycle and indicates the current time, and the peripheral device. a timer register for holding the time to start data transfer between the buffer memory, a write address register for specifying the address for storing the data in the buffer memory, and a write address register for specifying the address for retrieving the data stored in the buffer memory. A read address register for specifying a read address register, and when the contents of the timer and the contents of the timer register match, data input from a peripheral device on the data transmitting side is stored at an address in the buffer memory indicated by the write address register. A data processing device comprising: a control circuit that reads the content stored at the address of the buffer memory indicated by the read address register and outputs the read content to a peripheral device on the data receiving side.