JPH04176226A - Spread spectrum communication equipment - Google Patents

Abstract

PURPOSE:To attain data transmission at a high speed by synchronizing a PN code for spread spectrum modulation with a digital data to be sent. CONSTITUTION:An A/D converter 3 samples a voice signal according to a prescribed sampling clock, converts a sampled analog amplitude into a digital data and outputs serially bit by bit according to a prescribed data transmission clock. An FSK modulation signal is fed to one input terminal of a double balanced modulator 7. A prescribed PN code signal is fed from a PN code generator 9 to the other input terminal of the double balanced modulator 7. Thus, an output signal of the FSK modulator 5 is subject to spread spectrum modulation, an undesired band component is eliminated by a filter 11, then the resulting signal is sent from a transmission antenna 23.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a spread spectrum communication device for transmitting digital data, and particularly to a spread spectrum communication device that enables higher-speed data transmission.

[Prior art]

Conventionally, a so-called spread spectrum (SS) communication device has been used as a highly confidential communication device. Such a spread spectrum communication device, for example, uses a PN (pseudo-noise) code to spread the information to be transmitted over a wide frequency band (i.e., spread modulation) and transmits the information. The original signal can be obtained by performing despreading or the like using an image PN code that has an image relationship with the side PN code. This despreading is performed using, for example, a SAW device such as a SAW convolver or a matched filter.

[The invention tries to solve i! l! By the way, in conventional spread spectrum communication equipment, when performing digital data transmission, the period per data hit or PN
When the code period is very long, as shown in FIG. 8, a number of SAW device outputs (convolution outputs) can be obtained, so data reproduction is easy. However, data speeds have become faster and data 1
When the period (hit length) per hit approaches the PN code period, the number of convolution outputs per one bit length of data decreases, making it difficult to reproduce the data. In particular, the length of the data or the PN
If the period is almost equal to the code period, the convolution output may not be obtained as shown in Figure 8 (■).
The data cannot be played back, resulting in a transmission error. The present invention has been made in view of the problems of the conventional devices described above, and an object of the present invention is to provide a spread spectrum communication device that enables higher-speed data transmission.

[;8! Means for Solving the Problem] In order to achieve the above object, the spread spectrum communication device of the present invention synchronizes the PN code for spread spectrum modulation and the digital data to be transmitted! l! It is a sign. In the present invention, the receiver is preferably one that reproduces the data using the output of the SAW device. As the synchronization method, the transmission data may be synchronized with the PN code, or the PN code may be synchronized with the transmission data.

[Effect]

According to the above configuration, the PN code and the transmission data are synchronized. Therefore, the correlation between the transmitted PN code and the image PN code on the receiving side is high, and a reproduction output such as a convolution output can be stably obtained. Incidentally, PN
If the code and transmission data are not synchronized, the transmission data may change in the middle of one cycle of the PN code.
Since the N code also changes, the correlation between the PN code and the image PN code in one cycle becomes low, and convolution output or the like may not be obtained.

[Effect]

Therefore, according to the spread spectrum communication device of the present invention that synchronizes the PN code and the transmitted data, the data 1
This enables high-speed data transmission in which the period per bit is approximately equal to the period of the PN code.

【Example】

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIGS. 1A and 1B show configuration examples of a transmitter and a receiver, respectively, of a spread spectrum communication device according to an embodiment of the present invention. The transmitter shown in FIG. 1A includes a microphone 1 for transmission, A
/D converter 3, FSX modulator (frequency shift modulator) 5,
S with double balanced modulator 7 and PN code generator 9
It includes an S modulator (spread spectrum modulator), a filter 11, a transmitting antenna 13, and a synchronization circuit 15, which is a feature of the present invention. Note that if the transmission signal is a signal or data other than audio, appropriate input circuits are used in place of the microphone 1 or the microphone 1 and the A/D converter 3. As shown in FIG. 1B, the receiver includes a receiving antenna 21,
A frequency conversion section including a mixer 27 and a local oscillator 29, which are composed of a filter 23, a reception amplifier 25, a double-balanced modulator, etc., an SS demodulation section 33, which is composed of an intermediate frequency amplifier 31, a correlator, etc., and an FSX signal amplifier 35. ,
Detector (FSK demodulator) 37, waveform shaper 39, D/A
A converter 41, an amplifier 43, and a speaker 45 are provided. As a correlator, a SAW convolver, a matched filter, etc. can be used. The detector 37 is configured by, for example, a tie-auto and a capacitor, and performs envelope detection of the signal (FSX signal) despread in the SS demodulator 33. Next, the operation of the spread spectrum communication device having the above configuration will be explained. First, in the transmitter of FIG. 1A, an audio signal input manually from the microphone 1 is input to the A/D converter 3. A
The /D converter 3 samples this audio signal according to a predetermined sampling clock (for example, a frequency of 32 kHz), and converts the sampled analog amplitude value into digital data (for example, one hit according to a predetermined data transmission clock (for example, a frequency of 512 kHz)). The A/D converter 3 converts the audio signal, which is an analog signal, into PCM data, which is digital data.The FSX modulator 5 outputs the signal serially from the A/D converter 3. A signal with a different frequency is generated depending on the level of the binary signal.The FSX output in FIG.
An example of an FSX modulation signal when the SK modulator 5 is a voltage-controlled sine wave generating circuit that generates a 2 MHz sine wave signal when the binary signal is at the IMHz level and "L" level. shows. Such FSX modulated signal is then applied to one input terminal of the double balanced modulator 7. A predetermined PN code signal is applied from a PN coco generator 9 to the other input terminal of the double-balanced modulator 7. As a result, the output signal of the FSX modulator 5 is spread spectrum (SS) modulated, and the output signal of the FSX modulator 5 is spread spectrum (SS) modulated.
After unnecessary band components are removed by 1, the transmitting antenna 2
Sent from 3. The transmitted signal had, for example, a center frequency of 285 MHz and a spreading bandwidth of 66 MHz. Further, the clock of the PN code was set to 33 MHz. Next, in the receiver shown in FIG. Applied to one input terminal. Further, a local oscillator 29 generates a local oscillator signal of, for example, 85 MHz and is applied to the other input terminal of the mixer 27 . As a result, the received signal with a center frequency of 285 MHz is frequency-converted into an intermediate frequency signal with a center frequency of 200 MHz. Such an intermediate frequency signal is input to the SS demodulator 33 after being amplified via the intermediate frequency amplifier 31. The SS demodulation unit 33 uses, for example, a SAW convolver that functions as a correlator and a bandpass filter, and generates an image PN that has an image relationship with the PN code generated by the PN code generator 9 on the transmitter side. Detecting the correlation between the code and the intermediate frequency signal as shown in FIG.
In addition to generating convolution outputs as shown in .about.-■, the intermediate frequency signal is despread (SS demodulated) to generate FSK signals as shown in FIG. 8 . This F
The SX signal is demodulated and waveform-shaped via a detector 37 and a waveform shaper 39. Thereby, the PCM data transmitted from the transmitter is reproduced as received data. This received data (PCM data) is converted into an audio signal which is an analog signal via the D/A converter 41, and is outputted as audio by the power amplifier 43 and the speaker 45. Note that the AGC circuit 47 controls the reception amplifiers 25, 31 .
35 gain controls. As a result, an AGC operation is performed to keep the level of the received signal constant. The above is a common operation with the conventional technology. The tree embodiment is characterized in that the transmitter is provided with a synchronization circuit 15 for synchronizing the transmission data and the PN code. The synchronization circuit 15 may be one that synchronizes the PN code with the transmission data or one that synchronizes the transmission data with the PN code. FIG. 2 shows a configuration example (15a) of a synchronization circuit that synchronizes a PN code with transmission data. In this figure, the FSX signal generator 5 and the PN code generator 9 are the same as those shown in FIG. 1A. Synchronous circuit 15a in FIG.
consists of an edge detection circuit that detects edges, that is, rising and falling edges, of data sent from the A/D converter 3 and outputs the detection output as a reset and initialization signal for the PN code generator 9. FIG. 3 shows a more specific circuit example of the synchronous circuit 15a and PN coco generator 9 portions of FIG. 2. In FIG. 3A, a DFF (day-late flip-flop) circuit 5
1 and 53 respectively set the level applied to the data input terminal to 1 of the clock applied to the clock input terminal (in this case, the PN code clock for PN code generation).
Output is delayed by the clock time. Q is a non-inverting output terminal, and Q is an inverting output terminal. Sending data is “L”
When rising from ° level to “H” level, DFF5
The output Q of 1 rises at the timing of the PN code clock immediately after that, but the output Q of DFF53 rises at the timing of the next PN code clock.
It will stand up after the code clock timing has arrived. Ant gate 55 outputs the first P after the output data rises.
DFF51 during one clock from the timing of the N code clock to the timing of the second PN code clock
The output Q of is "H'" level and the output Q of DFF53
or L”° level (therefore, the inverted output Q of DFF53
is at "H" level), it outputs a rising detection signal at "L" level. On the other hand, when the sending data falls from the "L" level l\, the D
The outputs Q of FFs 51 and 53 fall after one clock. The Nant gate 56 detects the fall of the sending data based on the fact that both the inverted output Q of the DFF 51 and the non-inverted output Q of the DFF 53 are "H" level, and outputs a detection signal of "L" level. Nando Kate 55
and 56's 'L'° level output is output from antenna 57.
After passing through the data selector 93 of the PN coco generator 9
is applied to the initial data setting signal input terminal X of . Also,
The L" level output of the ant gate 57 is inverted again by the inverter 59, and is output as an "L" level to the PN code reset signal input terminal Y of the data selector 93.
is applied to This PN coco generator 9 uses a six-stage shift register 91 that sequentially shifts the data applied to the first stage data input terminal to the subsequent stage in accordance with the PN code clock applied to the PN code clock input terminal Z. Exclusive OR (EXC) of the output data of the first stage and the output data of the sixth stage
-OR) output is applied to the data input terminal of the first stage, and the repetition period is 2''-1=6313, which is the maximum repetition period of the 6-stage PN code generator.
- to [
Generates a PN code with a clock cycle. The data selector 93 of the PN coco generator 9 inhibits the shift operation of the shift 1 register 91 when the output of the ant gate 57 of the synchronization circuit 15a is at "L" level, and also inhibits the shift operation of the shift 1 register 91. The initial data set by each switch is set in the shift register 91. As a result, each time the level of the sending data is reversed,
The PN coco generator 9 is initially set and generates a predetermined pattern of P
Start generating N code. That is, the PN code generator 9 generates a PN code that is synchronized with the transmission data. FIG. 4 shows the timing relationship among the sending data, the data sending clock, the edge detection signal (output of the inverter gate 59), and the generated PN code. In the figure, the edge (rising or falling, in the case of Fig. 4, rising) of the sending data is detected (point A) and the initial value pattern of the PN code is set (point 0, initial value pattern point). and detect the rising edge of the data sending clock (point B)
It is shown that the initial value pattern of the PN code is set (0 point). Note that the sending data is always sent at one of the rising and falling timings of the data sending clock. Therefore, instead of detecting the edge of the transmission data, as shown by the dotted line in FIG. 2, the PN code is synchronized by detecting the rising or falling edge (data transmission timing) of the data transmission clock. You can. FIG. 3B shows an example of a circuit (15b) for detecting the edge of the data sending clock when data is sent at the rising edge of the data sending clock. In Figure 3B, Figure 3A
The same reference numerals are used to denote parts that are common to the above, and common explanations will be omitted. In FIG. 3B, the sending data is output at both "H" level and "L° level" at the rising edge of the data sending clock. Therefore, the edge detection only detects the rising edge of the data sending clock, and the AND gates 56 and 57 can be omitted from the circuit of FIG. 3A. FIG. 5 shows a configuration example (15c) of a synchronization circuit that synchronizes transmission data with a PN code. In this figure, the FSK modulator 5 and PN code generator 9 are common to those shown in FIGS. 1A and 2. The synchronization circuit 15c in FIG. 5 detects the reference point of repetition of the PN code sent from the PN code generator 9, for example, the start point of the repetition period (initial value pattern point), and uses the detection signal as the data transmission clock. or the PN output as its synchronization signal
Consists of a code synchronization detection circuit. FIG. 6 shows a more specific circuit example of the synchronous circuit 15c and PN coco generator 9 portions of FIG. 5. In FIG. 6, the PN code generator 9 has the same structure as that in FIG. In the synchronization circuit 15c, 61 is a 63-decimal counter, and each time the PN code clock is divided by 63,
Generates a carrier output RC of H” level.This H°
The carrier output RC of the “level” and the level of the “L” level obtained by inverting this carrier output are applied to the initial data setting signal input terminal X and the PN code reset signal input terminal Y of the PN code generator 9, respectively. In addition, the PN code clock is applied to the PN code clock input terminal Z.Thereby, the PN code generator 9 generates the PN code at a repetition period such that the initial state is reached at the timing when the carrier output is generated. On the other hand, the output QF of the most significant bit of the 63-decimal counter 61 is supplied as a data sending clock (or sampling clock) to a data sending circuit, for example, an A/D converter. The count value output is r6
In the state of 3J (QF=゛″H°°), one more P
When the N code clock is generated, the count value output is 'IJ'.
(QF="L"), a carrier output is generated, and this carrier output causes the PN code generator 9
or initialized. Then, when 31 PN code clocks are generated, the 63-decimal counter 61 outputs a count value of "32", and the output of the most significant bit becomes QF or "H" level. In the data sending circuit, data is sent out using this "H°°" level signal as a data sending clock. In this way, data is sent every time 63 PN code clocks are generated.
That is, it is executed in synchronization with the repetition period of the PN code. FIG. 7 shows the timing relationship among the sending data, the data sending clock, the edge detection signal (output of the inverter gate 63), and the generated PN code. As shown in the figure, the PN code clock is divided (point A), the PN code period is detected, and the data transmission clock is created or synchronized (
B point) and sends data (0 point),
It is possible to synchronize the sending data with the PN code (0 point). As explained above, by synchronizing the PN code and the transmitted data, the data speed becomes high, and even if the data hit length is close to the PN code period, a stable component can be achieved as shown in Figure 8. It is possible to obtain a fusion output and perform stable data transmission. Also, in the case of low-speed data transmission, the data speed length (data bit length) is approximately an integral multiple of the PN code period,
Data reproduction becomes easier (see Figure 8 ■).

[Brief explanation of the drawing]

1A and 1B are block circuit diagrams showing a transmitter and a receiver, respectively, constituting a spread spectrum communication device according to an embodiment of the present invention, and FIG. 2 is a synchronous circuit in the transmitter of FIG. 1A. A block circuit diagram showing an example; FIGS. 3A and 3B are circuit diagrams each more specifically representing the synchronous circuit in FIG. 2; FIG. 4 is a circuit diagram showing the circuit shown in FIGS. 2 and 3A. The timing chart of each signal in □Figure 5 is as follows:
A block circuit diagram showing another example of the synchronization circuit in the transmitter shown in FIG. 1, FIG. 6 is a circuit diagram more specifically representing the synchronization circuit in FIG. 5, and FIG. The timing chart of each signal in the circuit shown in FIG. 6, and the timing chart 1 to FIG.
It is. 1 Microphone 3: A/D converter 5/FSX modulator 7.27 Double balanced modulator 9 PN code generator 11.23.23a/filter 13 Transmission antenna 15.15a, 15b, 15c Synchronization circuit 21/reception antenna 25.31, 35.43 Amplifier 29 Local oscillator 33 - Correlator 37/Detector 39 Waveform shaper 41: D/A converter 45 Speaker 47/AGC circuit Patent applicant Mitsui Mining Mining Co., Ltd. Agent Patent attorney Ito Tatsuo Agent Patent Attorney Tetsuya Ito Kuboha

Claims (4)

[Claims] (1) In a spread spectrum communication device comprising a transmitter that spread spectrum modulates digital transmission data and transmits the data, and a receiver that reproduces the data from the spread spectrum signal, the transmitter receives the transmission data and spread spectrum modulation. 1. A spread spectrum communication device comprising a synchronization means for synchronizing a PN code for a spread spectrum communication device. (2) the SA by which the receiver despreads the PN code;
2. The spread spectrum communication apparatus according to claim 1, wherein said data is reproduced using an output of a W device. (3) The spread spectrum communication device according to claim 1, wherein the synchronization means synchronizes the transmission data with the PN code. (4) The spread spectrum communication device according to claim 1, wherein the synchronization means synchronizes the PN code with the transmission data.