JP2775038B2 - Spread spectrum communication equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication apparatus for performing digital data transmission, and more particularly, to a spread spectrum communication apparatus which enables higher-speed data transmission.

[Prior art]

Conventionally, a so-called spread spectrum (SS) communication device has been used as a highly confidential communication device. Such a spread spectrum communication apparatus, for example, performs primary modulation on information to be transmitted by a method known as a data modulation method such as FSK modulation, and spreads the information over a wide frequency band using a PN (pseudo noise) code. In other words, the original signal can be obtained by performing despreading or the like on the receiver side using an image PN code having an image relationship with the PN code on the transmission side. This despreading is performed, for example, by using an SW convolver or a matched filter.
This is performed using an AW device.

[Problems to be solved by the invention]

By the way, in the conventional spread spectrum communication apparatus, when digital data transmission is performed, if the period per data bit is much longer than the period of the PN code, as shown in FIG. (Convolution output) is obtained, so that data reproduction is easy. However, when the data speed increases and the period (bit length) per data bit approaches the PN code period, the number of convolution outputs for the data 1 bit length decreases, and data reproduction becomes difficult. There was an inconvenience. In particular, when the bit length of the data is substantially equal to the period of the PN code, a convolution output may not be obtained as shown in FIG. 8, and the data cannot be reproduced, resulting in a transmission error. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the conventional device, and has as its object to provide a spread spectrum communication device capable of higher-speed data transmission.

[Means for Solving the Problems]

In order to achieve the above object, the present invention firstly modulates digital transmission data firstly, and then spreads and modulates the primary modulation signal with a transmitter, and reverses the spread spectrum modulation signal using a SAW device. In a spread spectrum communication apparatus comprising a receiver for detecting the despread output asynchronously, shaping the waveform of the detected output and regenerating the data, the transmitter, the transmitter, the transmission data and the spread spectrum modulation. And a synchronizing means for synchronizing with the repetition period of the PN code. As the primary modulation, a method known as a digital data modulation method such as FSK modulation can be used.
An envelope detector can be used as the detector that performs asynchronous detection. As the synchronization method, the transmission data may be synchronized with the PN code, or the PN code may be synchronized with the transmission data.

According to the above configuration, the PN code and the transmission data are synchronized. For this reason, the correlation between the transmitted PN code and the image PN code on the receiving side is high, and a reproduction output such as a convolution output can be stably obtained. If the PN code and the transmission data are not synchronized, the PN code changes due to the change in the transmission data during one period of the PN code.
Correlation with the PN code may be low, and convolution output or the like may not be obtained. Therefore, according to the spread spectrum communication apparatus of the present invention in which the PN code and the transmission data are synchronized, the data 1
High-speed data transmission in which the cycle per bit is almost equal to the cycle of the PN code becomes possible.

【Example】

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIGS. 1A and 1B show an example of the configuration of a transmitter and a receiver of a spread spectrum communication apparatus according to an embodiment of the present invention. The transmitter shown in FIG. 1A includes a microphone 1 for transmitting,
A / D converter 3, FSK modulator (frequency shift modulator) 5, double balance modulator 7, SS modulator (spread spectrum modulator) having PN code generator 9, filter 11, transmission antenna
13 and a synchronization circuit 15 which is a feature of the present invention. When the transmission signal is a signal or data other than voice, an appropriate input circuit is used instead of the microphone 1 or the microphone 1 and the A / D converter 3. The receiving unit includes, as shown in FIG.
A frequency conversion unit having a mixer 27 and a local oscillator 29 including a filter 23, a reception amplifier 25, a double balanced modulator, and the like, an intermediate frequency amplifier 31, an SS demodulation unit 33 including a SAW convolver, and an FSK signal amplifier 35. , Detector 37,
It includes a waveform shaper 39, a D / A converter 41, an amplifier 43, and a speaker 45. The detector 37 is composed of, for example, a diode and a capacitor, and performs an envelope detection of the signal (FSK signal) despread in the SS demodulation unit 33. Next, the operation of the spread spectrum communication apparatus having the above configuration will be described. First, in the transmitter of FIG. 1A, an audio signal input from the microphone 1 is input to the A / D converter 3. A / D
The converter 3 samples this audio signal in accordance with a predetermined sampling clock (for example, a frequency of 32 kHz), converts the sampled analog amplitude value into digital data (for example, 16 bits), and converts the digital data into a predetermined data transmission clock (for example, 16 bits). For example, the data is serially output one bit at a time according to a frequency of 512 kHz. That is, the A / D converter 3 converts the audio signal, which is an analog signal, into PCM data, which is digital data. The FSK modulator 5 generates a signal having a different frequency according to the level of a binary signal serially output from the A / D converter 3. The FSK output shown in FIG. 8 is 1 MHz and "L" when the binary signal is at "H" level as the FSK modulator 5.
An example of an FSK modulation signal when a voltage-controlled sine wave generation circuit that generates a sine wave signal of 0.2 MHz at the level is shown. Such an FSK modulated signal is then applied to one input terminal of a double balanced modulator 7. A predetermined PN code signal is applied from a PN code generator 9 to the other input terminal of the double balanced modulator 7. As a result, the output signal of the FSK modulator 5 is subjected to spectrum extension (SS) modulation, and unnecessary band components are removed by the filter 11, and then transmitted from the transmitting antenna 23. As an example, the transmission signal has a center frequency of 285 MHz,
The spreading bandwidth was 66 MHz. The clock of the PN code was set to 33 MHz. Next, in the receiver shown in FIG. 1B, the signal transmitted as described above is received by the receiving antenna 21 and is selected and amplified via the filter 23 and the receiving amplifier 25. Applied to one input terminal. Further, a local oscillator signal of, for example, 85 MHz is generated from the local oscillator 29 and applied to the other input terminal of the mixer 27. As a result, a received signal having a center frequency of 285 MHz
The frequency is converted to an intermediate frequency signal of Hz. Such an intermediate frequency signal is amplified via the intermediate frequency amplifier 31 and then input to the SS demodulation unit 33. The SS demodulation unit 33 uses a SAW convolver having both functions as a correlator and a bandpass filter, and includes an image PN code having an image relationship with the PN code generated by the PN code generator 9 on the transmitter side. , And detects the correlation with the intermediate frequency signal to generate a convolution output as shown in FIGS. This convolution output is demodulated and waveform-shaped via a detector 37 and a waveform shaper 39. Thereby, the PCM data transmitted from the transmitter is reproduced as received data. This received data (PCM data) is converted to an audio signal which is an analog signal via a D / A converter 41,
And voice output by the speaker 45. Note that the AGC circuit 47 controls the gain of the receiving amplifiers 25, 31, and 35 according to the level of the audio signal output from the D / A converter 41. Thereby, the AGC operation for keeping the level of the received signal constant is performed. The above is the operation common to the prior art. The present embodiment is characterized in that a periodic circuit 15 for synchronizing transmission data and a PN code is provided in a transmitter. As the synchronizing circuit 15, a circuit that synchronizes the PN code with the transmission data and a circuit that synchronizes the transmission data with the PN code can be considered. FIG. 2 shows a configuration example (15a) of a synchronization circuit that synchronizes a PN code with transmission data. In the figure, an FSK signal generator 5 and a PN code generator 9 are the same as those shown in FIG. 1A. 2 detects an edge of data sent from the A / D converter 3, that is, a rising edge and a falling edge, and outputs a detection output as a reset and initialization signal of the PN code generator 9. It consists of an edge detection circuit. FIG. 3 shows a more specific circuit example of the synchronization circuit 15a and the PN code generator 9 shown in FIG. In FIG. 3A, DFF (delayed flip-flop) circuits 51 and 5
3 indicates the level applied to the data input terminal D,
The clock applied to the clock input terminal (here, PN
PN code clock for code generation) is output with a delay of one clock time. Q is a non-inverted output terminal, and is an inverted output terminal. When the transmission data rises from the "L" level to the "H" level, the output Q of DFF51 rises at the timing of the PN code clock immediately thereafter, but the output Q of DFF53 rises.
Rises when the timing of the next PN code clock comes. After the transmission data rises, the AND gate 55 outputs the second PN code from the timing of the first PN code clock.
DF for one clock up to the timing of the code clock
The output Q of F51 is at "H" level and the output Q of DFF53 is at "L"
When the signal is at the level (the inverted output of the DFF 53 is at the “H” level), it outputs a “L” level rising detection signal. On the other hand, when the transmission data falls from the "H" level to the "L" level, the outputs Q of DFFs 51 and 53 fall with one clock delay. The NAND gate 56 detects the fall of the transmission data based on the fact that both the inverted output of the DFF 51 and the non-inverted output Q of the DFF 53 are at the “H” level, and outputs a “L” level detection signal. Nandgate 55
The "L" level output of the PN code generator 9 is applied to the initial data setting signal input terminal X of the data selector 93 after passing through the AND gate 57. The "L" level output of the AND gate 57 is again inverted by the inverter 59 and applied to the PN code reset signal input terminal Y of the data selector 93 as "L" level. The PN code generator 9 uses a six-stage shift register 91 for sequentially shifting data applied to the first-stage data input terminal to the subsequent stage according to the PN code clock applied to the PN code clock input terminal Z. An exclusive OR (EXC-OR) output of the output data of the first stage and the output data of the sixth stage is applied to the data input terminal of the first stage. generating a maximum repetition is the period 2 ⁶ -1 = 63 [clock] cycle of PN code in the code generator. The data selector 93 of the PN code generator 9
When the output of the AND gate 57 of “a” is at “L” level, the shift operation of the shift register 91 is prohibited,
The initial data set by each switch of the initial data setting circuit 95 is set in the shift register 91. Thus, each time the level of the transmission data is inverted, the PN code generator 9 is initialized and a predetermined pattern
Start generating the PN code. That is, the PN code generator 9 generates a PN code synchronized with the transmission data. 4th
The figure shows the timing relationship between the transmission data, the data transmission clock, the edge detection signal (output of the inverter gate 59), and the generated PN code. The figure shows that the edge (rising or falling, in the case of FIG. 4, rising) of the transmitted data is detected (point A) and the initial value pattern of the PN code is set (point C: initial value pattern point). , And the rising edge of the data transmission clock is detected (point B) and the initial value pattern of the PN code is set (point C). The transmission data is always transmitted at one of the rising edge and the falling edge of the data transmission clock. Therefore, instead of detecting the edge of the transmission data, the rising or falling edge (data transmission timing) of the data transmission clock may be detected to synchronize the PN code, as shown by the dotted line in FIG. . FIG. 3B shows a circuit example (15b) for detecting the edge of the data transmission clock when data is transmitted at the rising edge of the data transmission clock. In FIG. 3B, FIG.
The same reference numerals are given to the same parts as those described above, and the common description will be omitted. In FIG. 3B, the transmission data is output at both the "H" level and the "L" level at the rising edge of the data transmission clock. Therefore, the edge detection only needs to detect the rising of the data transmission clock, and the AND gates 56 and 57 can be omitted from the circuit of FIG. 3A. FIG. 5 shows a configuration example (15c) of a synchronization circuit for synchronizing transmission data with a PN code. In the figure, the FSK modulator 5
The PN code generator 9 is the same as that shown in FIGS. 1A and 2. Synchronous circuit 15c in FIG.
Detects a reference point of repetition of the PN code transmitted from the PN code generator 9, for example, a start point (initial value pattern point) of a repetition period, and outputs a detection signal as a data transmission clock or a synchronization signal thereof. It consists of a PN code synchronization detection circuit. FIG. 6 shows a more specific circuit example of the synchronization circuit 15c and the PN code generator 9 shown in FIG. 6, the PN code generator 9 has the same configuration as that of FIG. In the synchronous circuit 15c, 61 is a 63-ary counter, P
Each time 63 N code clocks are counted, an "H" level carrier output RC is generated. The "H" level carrier output RC and the "L" level signal obtained by inverting the carrier output are supplied to the initial data setting signal input terminal X and the PN code reset signal input terminal Y of the PN code generator 9, respectively. Applied. The PN code clock is applied to a PN code clock input terminal Z. As a result, this PN
The code generator 9 generates a PN code at a repetition cycle such that the code generator 9 becomes an initial state at the timing when the carrier output occurs. On the other hand, the output QF of the most significant bit of the 63-base counter 61 is supplied as a data transmission clock (or sampling clock) to a data transmission circuit, for example, an A / D converter. That is, the 63-base counter 61 outputs a count value of “63” (QF =
When one more PN code clock is generated in the state of “H”, the count value output becomes “1” (QF = “L”) and a carrier output is generated, and the PN code is generated by the carrier output. The vessel 9 is initialized. And more
When 31 PN code clocks are generated, the 63-ary counter 61
Indicates that the count value output is “32” and the output of the most significant bit is
QF becomes “H” level. In the data transmission circuit, data transmission is performed using this "H" level signal as a data transmission clock. As described above, data transmission is executed every time 63 PN code clocks are generated, that is, in synchronization with the repetition period of the PN code. FIG. 7 shows the timing relationship between the transmission data, the data transmission clock, the edge detection signal (output of the inverter gate 63), and the generated PN code. As shown in the figure, the PN code clock is frequency-divided (point A), the period of the PN code is detected, and a data transmission clock is created or synchronized (B
(Point C) to transmit the data (point C), the transmitted data can be synchronized with the PN code (point C). As described above, by synchronizing the PN code and the transmission data, even if the data rate is increased and the data bit length approaches the PN code cycle, as shown in FIG. And stable data transmission can be performed. Also in the case of low-speed data transmission, the data rate length (data bit length) becomes almost an integral multiple of the PN code period, and data reproduction becomes easier (see FIG. 8).

[Brief description of the drawings]

1A and 1B are block circuit diagrams showing a transmitter and a receiver constituting a spread spectrum communication apparatus according to an embodiment of the present invention, respectively. FIG. 2 is a synchronizing circuit in the transmitter of FIG. 1A. FIGS. 3A and 3B are circuit diagrams more specifically showing the synchronous circuit of FIG. 2, respectively. FIG. 4 is a circuit diagram of the circuit shown in FIGS. 2 and 3A. 5 is a block circuit diagram showing another example of the synchronization circuit in the transmitter of FIG. 1A, and FIG. 6 shows the synchronization circuit of FIG. 5 more specifically. FIG. 7 is a timing chart of each signal in the circuits shown in FIGS. 5 and 6, and FIG. 8 compares the timing relationship of each signal in the present invention and the conventional spread spectrum communication apparatus. Show timing It is a chart. 1: Microphone 3: A / D converter 5: FSK modulator 7, 27: Double balanced modulator 9: PN code generator 11, 23, 23a: Filter 13: Transmission antenna 15, 15a, 15b, 15c: Synchronization Circuit 21: Receiving antenna 25, 31, 35, 43: Amplifier 29: Local oscillator 33: Correlator 37: Detector 39: Waveform shaper 41: D / A converter 45: Speaker 47: AGC circuit

Claims (5)

(57) [Claims] A digital transmission data is firstly modulated first.
Next, a transmitter for transmitting the primary modulated signal by spread spectrum modulation, and a despreading of the spread spectrum modulated signal using a SAW device, detecting the despread output asynchronously, and shaping the waveform of the detected output. A spread spectrum communication apparatus comprising a receiver for reproducing the data, wherein the transmitter is provided with synchronization means for synchronizing the transmission data with a repetition period of a PN code for spread spectrum modulation. Spread spectrum communication equipment. 2. The spread spectrum communication apparatus according to claim 1, wherein said primary modulation is FSK modulation, and said asynchronous detection is envelope detection. 3. The spread spectrum communication apparatus according to claim 1, wherein the synchronization means synchronizes the transmission data with the PN code. 4. The spread spectrum communication apparatus according to claim 1, wherein said synchronization means synchronizes the PN code with the transmission data. 5. The spread spectrum communication apparatus according to claim 1, wherein one bit of the transmission data corresponds to a repetition period of the PN code on a 1: 1 basis.