JP2785009B2 - Spread spectrum reception method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving system in spread spectrum (hereinafter, referred to as SS) communication.

[0002]

2. Description of the Related Art In a conventional SS receiving system of this type, a demodulation circuit using a digital matched filter as disclosed in Japanese Patent Application Laid-Open No. 5-252142 is used.
For example, as shown in FIG. 9, after a carrier reproduced by a VCO is applied to an SS signal to make data including a spreading code,
Despreading is performed through the digital matched filter, and further, a frequency error is detected from this output, and negative feedback is applied to the VCO.

[0003]

In the above-mentioned prior art SS receiving system, a separate circuit for reproducing a carrier is required, and the input SS signal has an AGC having a wide dynamic range. Therefore, there is a disadvantage that the circuit configuration becomes complicated.

[0004] Further, if the above-mentioned faulty example is expanded and described, the carrier recovery circuit is a DC loop, so that temperature compensation is difficult, and a 90 ° phase shifter for detecting a frequency error is required. Two circuits related to the phase shifter after the 90 ° phase shifter are required.

Accordingly, the present invention eliminates the need for an AGC circuit for applying AGC, a carrier recovery circuit (including an A / D converter) and a 90 ° phase shifter, and at the same time reduces the number of gates in each circuit. Accordingly, it is an object of the present invention to obtain an SS receiving system in which the entire circuit configuration is simplified.

[0006]

The construction of the present invention will be described with reference to FIG. 1. The carrier frequency of the SS signal input is frequency-converted by the mixer 1 and the local oscillator 2 to an integral multiple of the chip rate, and the amplitude is limited. The saturation output of the amplifier 3;
Sampling is performed by the clock output of the clock generator 4.

The shift register 5 which delays the sampled SS signal by two chip rates has a PN signal.
(Pseudorandom Noise). The output signals are passed through the multiplier 6 from the MSB to the LSB of the PN code, and all of the output signals are added to the adders 7 and 8.

Next, data are output by further inputting the despread SS signals of two series output from the adders 7 and 8 to the multiplier 10.

The digital matched filter 9 includes the shift register 5 and the multiplier 6 and the adders 7 and 8 which are continuous.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the spread spectrum receiving system of the present invention will be described in detail with reference to the drawings.
Rate and the sampling clock is eight times the chip rate.

The PN code has 7 bits "000101".
1 "and the carrier frequency of the SS signal and the chip rate are made equal to differentiatedly.
This operation will be described with reference to Binary PSK (hereinafter, referred to as DBPSK).
8 to FIG. 8, and each clock (CLK) input is supplied simultaneously by the clock generator 4.

In FIG. 9, the conventional SS receiving system using a digital matched filter delays reproduced data and further applies a PN code to perform despreading. In the present invention, as shown in FIG. After delaying the PSK waveform,
Further, despreading is performed by applying a PN code, and the configuration is shown in FIGS.

The SS signal to be transmitted is of the direct spreading type, and the spreading is performed by BPSK. The data is synchronized with one cycle of the PN code, but the carrier of the SS signal is always synchronized. No need.

In FIG. 1, an input SS signal is frequency-converted by a mixer 1 and a local oscillator 2 to an integral multiple of a chip rate.
To the limiting level (see FIG. 8).

Next, sampling is performed by the saturation output of the amplitude limiting amplifier 3 and the clock output of the clock generator 4 ((a) of FIG. 3 shows an example of sampling data of data O, and (b) of FIG. 1 shows an example of sampling data).

Although the sampling clock is asynchronous with the SS signal, since the carrier frequency and the chip rate are equal, the sampling at a certain point in time and the sampling eight clocks later than the sampling clock are shown in FIG. ,
As shown in (b), the PN code is shifted by one bit, and the phase difference is 0 ° or 180 °.

As described above, according to the SS receiving method of the present invention, since the frequency difference is used, the signal may be asynchronous and the waveform may be saturated. Regarding the frequency shift, for example, even if the PN length is 13 bits and the shift is 10 PPM,
13 × 8 × 10 × 10-6 × 360 ° = 0.37 °, which is not a problem.

Next, the digital matched filter 9 shown in FIG.
In FIG. 3, the sampling data (1) to (6) shown in FIG.
Assuming that 4) is in the shift register 5 as shown in FIG. 4A, (A) is (1), (B) is (9),
(C) is (17), (D) is-(25), (E) is (33), (F) is-(41), and (G) is-(4).
The data of 9) is output by the multiplier 6, and all the data are added by the adders 7 and 8, (H) is (1) + (9) + (17)-(25) + (3)
3)-(41)-(49).

FIG. 4 shows a shift from this state by one.
(H) is (2) + (10) +
(18)-(26) + (34)-(42)-(50).

Next, waveforms (A) to (G) and (H) expressed on the time axis are shown in FIGS. 5 (a) and 5 (b), respectively.

(H) obtained by adding all of (A) to (G) becomes 7 times (PN length times) between 8 clocks when the PN code given to the shift register 5 and the PN code of the SS signal coincide. Further, (H) is delayed by one period of the PN code (I), and the product of (H) and (I) is taken (J) to demodulate the data. The output waveform of the multiplier 10 to be described is shown in FIG.

For reference, FIG. 7 shows a waveform simulated by DBPSK using an AGC amplifier (not shown), and FIG. 8 shows an amplitude limiting (limiter) amplifier (FIG. 1).
2) shows a waveform simulated by DBPSK.

[0023]

Since the present invention is constructed as described above, it has the following effects.

Since the AGC is not required for the input amplifier, a conventional FM limiter amplifier or the like can be used as it is, so that the size and cost of the device can be reduced.

Further, since an A / D converter is not required, the influence of noise at the input stage can be reduced, so that higher quality data output can be achieved, and the size and cost of the device can be reduced. .

Further, since a carrier reproducing circuit and a 90 ° phase shifter are not required, the apparatus operates stably with respect to a temperature change and the like, and can reduce the size and cost of the apparatus.

[0027] Since all circuits can be constituted by digital circuits, a gate array can be formed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram for explaining the present invention.

FIG. 2 is an explanatory diagram of SS-DBPSK of the present invention.

FIG. 3 is a diagram showing an example of sampling data.

FIG. 4 is a diagram showing a shift state of sampling data.

FIG. 5 is a waveform diagram showing sampling data on a time axis.

FIG. 6 is a waveform diagram showing a multiplier (detection) output in a PN code.

FIG. 7 is a waveform chart by a DBPSK (AGC amplifier).

FIG. 8 is a waveform chart by a DBPSK (limiter amplifier) of the present invention.

FIG. 9 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Mixer (MIX) 2 Local oscillator (OSC) 3 Amplitude limiting amplifier (limiter) 4 Clock generator (CLK) 5 Shift register (D: delay) 6,10 Multiplier 7,8 Adder ($ 1, $ 2) 9 Digital matched filter

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 1/707

Claims (1)

(57) [Claims] In a wireless communication system for performing direct spread spectrum, a received spread spectrum signal is frequency-converted by a frequency conversion unit to an integral multiple of a chip rate.
The output of the frequency conversion means is
Ri amplified, further, this was oversampling saturation output of the amplitude limiting amplifier means with a clock output of the click <br/> locking generating means, the over-sampled output, diffusion delay means 1 chip rate min Doubled the number of code bids
Input to the delay device and output of each stage of the arranged delay means
The spreading code for two systems corresponding to each stage of the delay means.
Are multiplied by multiplication means, and
Each multiplication output for one system is divided into two systems by two addition means.
Are added, and the addition outputs of the two systems are multiplied by
A spread spectrum receiving system comprising means for multiplying and demodulating by a stage .