JPH0758669A - Digital matched filter - Google Patents

Abstract

PURPOSE:To make a circuit scale small by successively obtaining the correlation between partial spectrum spreading codes for which spectrum spreading codes are divided and reception spread spectrum signals. CONSTITUTION:A reception shift register 11 serially inputs the chips of the reception spread spectrum signals and a multiplier 12 multiplies the number of the chips outputted by the respective stages of the register 11 by coefficients for the respective chips. Coefficient registers 13a and 13b respectively hold values corresponding to the first half and second half parts of the spreading codes of the chip and output them as multiplication coefficients based on changeover control signals CNT from a control part 17 to the multiplier 12. An adder 14 obtains the sum of the output of the multiplier 12 and outputs it as a partial correlation coefficient, an absolute value calculation part 15 generates a partial correlation absolute value and a comparison part 16 detects a chip timing when the partial correlation absolute value exceeds a threshold value THI. The control part 17 performs control so as to let the desired partial spreading codes be held in the registers 13a and 14b at the chip timing and partial correlation coefficient adding means 18-20 fetch the output of the adder 14 and cumulatively add and output the output for one chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital matched filter used in a receiver of a spectrum direct spread communication system or the like.

In a so-called spread spectrum communication system in which an information signal is transmitted after being multiplied by a wide band spreading code and is despread at the receiving side to return to a narrow band signal, the C / N (carrier noise ratio) of the received radio wave is poor. However, because it can detect information signals, space communication and CDMA (Code Division Multiple Acc
ess: Code division multiple access), and the cost reduction of the device is desired. Reducing the hardware scale by configuring a matched filter that performs despreading with a digital circuit is an effective means for this purpose.

[0003]

2. Description of the Related Art FIG. 4 shows a spread spectrum direct communication system to which a digital matched filter of the present invention is applied.

On the transmitting side, each bit of the transmission data is multiplied by a spreading code. Below, the information “1” of the transmission data is −
1, the information "0" will be described as having a standardized signal level of +1. The output of the multiplication result is (-1) × (-
1) = (+ 1) × (+1) = + 1 (that is, “1” + as the information value
"1" = "0" + "0" = "0"), and (-1) x (+1) =
(+1) x (-1) = -1 (Information value is "1" + "0" =
Since “0” + “1” = “1”), the multiplier operates in the same way as the EX-OR circuit for information values. When the transmission information bit is "1", the bit pattern of the spread code is inverted, and when the transmission information bit is "0", the spread bit pattern is generated as it is as the baseband signal of the spread spectrum transmission signal. . Normally, the spreading code is a pseudo-random code (PN code) with a specific phase, but in the following explanation, ABCDEFGHIJ
Spreading code “1111010110” of KLMNOP bit length 16 (hereinafter each chip of spreading code is called chip because it is called chip)
010001 "is used. For original transmission data at an information rate of 9.6 Kbit / s, 1-bit information" 0 "is the 16-chip-long spreading code pattern, and 1-bit information" 1 "is the spreading code. Is converted into a 16-bit bit string “0000101001101110” which is inverted, so that the original transmission data string has a baseband spread spectrum signal (chip bit rate (spread code bit rate) of 9.6 × 16 = 153.6 Kbit / s). SS signal).

The transmitting side sends out a radio signal in which the carrier is modulated in a predetermined manner by PSK modulation or the like with the transmission baseband spread spectrum signal. As a result, the spectrum of the transmitted signal is 16 times smaller than that when modulated at the original information rate.
Spread in double the band.

On the receiving side, the received radio signal is subjected to predetermined frequency conversion and PSK demodulation to obtain a received baseband spread spectrum signal which is an analog signal having a frequency of 153.6 KHz. This analog received spread spectrum signal is sampled at a chip clock frequency of 153.6 KHz and AD
It is converted into a digitized received spread spectrum signal. The digitized received spread spectrum signal is input to the digital matched filter. The digital matched filter performs spectrum despreading by calculating the correlation between this input signal and the built-in spreading code pattern, and the repetition frequency 9.6 equal to the information rate.
The maximum correlation value is output at K Hz.

The configuration and operation of the conventional digital matched filter will be described with reference to FIG. The baseband reception spread spectrum signal digitized at the chip clock frequency is sequentially input to the reception shift register 31 having a depth of 16 steps equal to the chip length. On the other hand, the coefficient register 33 uses the spreading code “1111” having the same pattern as the spreading code used on the transmitting side.
010110010001 "is fixedly held and output in parallel. The 16 multipliers 32 provided corresponding to the chip length of the spread code are chips that are parallel outputs of the spread code and the reception shift register 31. The chip clock period is compared by multiplying each chip by the match / mismatch with the received spread signal corresponding to the length.The comparison result is that 16 chips are constantly added by the adder 34 and output as an autocorrelation value. When the pattern of the received signal matches the pattern of the spread code, the multiplication results are all 1 and the maximum correlation value 16 is obtained from the adder 34, and when the received signal pattern is the inverse of the spread code pattern, all the multiplication results are obtained. Since it is -1, the negative maximum correlation value -16 is output from the adder 34. At other chip clock timings, a value of about 16/2 is output.

The absolute value calculator 35 converts this correlation value into a positive correlation absolute value. The comparator 36 compares the absolute value of the correlation with a preset threshold value between 8 and 16, detects a chip timing exceeding the threshold value, and outputs a detection pulse DET.

The detection pulse DET and the absolute value of the correlation value are used as a control signal for pulling in the carrier recovery at the start of reception and as an identification timing pulse in the identification section in the subsequent stage. In FIG. 4, the data identification section subsequent to the matched filter regenerates the original transmission data by identifying the value of the correlation value at the chip timing of the detection pulse DET.

In the above, as the spreading code chip length increases, the number of types of spreading code patterns increases, so the peak of the correlation value increases, and it is possible to satisfactorily receive low-CN received signals, and in the case of multiple access. Will have more channels.

[0011]

The above-mentioned conventional digital matched filter requires a shift register having a depth equal to the chip length of the spread code and a multiplier having the same number as the chip length. Therefore, if the chip length is increased, the circuit becomes longer. There was a problem that the scale increased.

As described above, the circuit scale of the matched filter increases in accordance with the chip length of the spread code, so that the length of the spread code required for the communication system is within a range in which the matched filter can be configured by one LSI. L is exceeded
The SI was cascade-connected to form a matched filter. In addition, there is a problem that the chip length of the spread code is limited when the matched filter is configured with one LSI.

The present invention was created in view of the above problems, and an object thereof is to reduce the circuit scale of a digital matched filter.

[0014]

FIG. 1 is a block diagram of a first embodiment of a digital matched filter according to the present invention. In order to solve the above problems, the digital matched filter of the present invention is a digital matched filter that despreads an original signal by despreading a received spread spectrum signal that has been spread spectrum using a spreading code of a predetermined chip length on the original signal. In the filter, a spread code of a predetermined chip length is divided into a plurality of partial spread codes having substantially the same chip length, partial correlation values between the received spread spectrum code and each of the plurality of partial spread codes are sequentially obtained, and all the partial spread codes are obtained. The sum of the maximum partial correlation values for the spread code is output as a correlation value between the spread code having the predetermined chip length and the received spread spectrum code. Further, as shown in FIG. 1, the reception shift register means 11 having the depth of the chip length of the partial spread code and serially input by the chip of the receive spread spectrum code.
A multiplication means 12 for multiplying the output of each stage of the reception shift register means 11 by a coefficient respectively, and each partial spreading code is switched and held based on a control signal, and the held value is multiplied by the multiplication means. Partial spreading code supply means 13
a, 13b, the sum of the outputs of the multiplying means, an adding means 14 for outputting as a partial correlation value, an absolute value calculating means 15 for generating a partial correlation absolute value which is an absolute value of the partial correlation value,
The comparison means 16 for detecting the chip timing at which the partial correlation absolute value exceeds the predetermined threshold TH1, and the maximum partial correlation value between the subsequent partial spread code and the received spread spectrum signal with reference to the first chip timing at the start of reception. And a control means 17 for generating a control signal for controlling so that a desired partial spread code is held in the partial spread code supply means at the timing, and the adder means outputs at the chip timing. Partial correlation value adding means 18, 19, 20 for taking in the partial correlation value and cumulatively adding one chip length and outputting it.

[0015]

Since the number of chips for correlation decreases due to the division, the number of the reception shift register for holding the chip of the reception spread spectrum code and the number of multipliers for calculating the correlation in the matched filter to obtain the correlation value is set to the partial spread code. It is sufficient to provide the same number of chips. Therefore, the circuit scale of the matched filter can be reduced. The number of divisions is
CN ratio of the target communication system (carrier / noise
The ratio can be appropriately determined. By appropriately determining the number of divisions according to the CN of the communication system, an efficient circuit configuration can be achieved.

When the number of divisions is increased, the number of chips of the partial spread code is reduced and the maximum value of the partial correlation value is reduced. Therefore, although the division is at most two in a space communication system or the like with a small CN, CDMA mobile communication or wireless communication. For LAN etc., CN
Is relatively good, the desired control can be performed with the partial correlation value, and the number of divisions can be increased.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a block diagram of the second embodiment. The same reference numerals denote the same objects throughout the drawings.

In the following embodiment, the spreading code has a chip length of 16
And from front to back ABCDEFGHIJKLMNOP (value is 111101011001
0001), and a case where each of these two divided chips is used as a partial spread code will be described.

In the first embodiment, a plurality of coefficient registers for fixedly holding each partial spread code are provided as the partial spread code supply means, and the coefficient supply source is appropriately switched.

In FIG. 1, reference numeral 11 denotes an 8-stage reception shift register, and digital data obtained by sampling a reception spread spectrum signal demodulated into a baseband signal with a chip clock are sequentially input to a chip serial. This digital data has positive and negative values corresponding to the information values "0" and "1" of the transmitting side chip. 12 is a multiplier,
Eight are provided corresponding to each stage of the reception shift register,
The chip value output from each stage of the shift register and the coefficient are multiplied for each chip. 13a and 13b are two coefficient registers, 13a is 8 chips in the first half of the 16-chip spreading code,
That is, ABCDEFGH "11110101" holds, and 13b holds the values corresponding to the 8-chip IJKLMNOP "10010001" in the latter half part. , And is supplied to the multiplier 12 as a multiplication coefficient. The relationship between the information of the partial spreading code and the signal level of the coefficient actually supplied to the multiplier is that "0" is +
It is assumed that 1 and "1" correspond to signal levels with a polarity of -1. For example, when the switching control signal CNT is "H", "-1," which corresponds to the second partial spread code "10010001"
"1, -1, -1,1,1,1, -1" is from the coefficient register 13b, and when it is "L", it corresponds to "11110101" in the first half, "-1, -1, -1, -1,1 , -1,1,
1 "is supplied from the coefficient register 13a to each multiplier as a multiplication coefficient.

Reference numeral 14 denotes an adder, which performs arithmetic addition of the multiplication results output from the eight multipliers 12 and outputs the result as a partial correlation value. Reference numeral 6 denotes an absolute value calculation unit which, when the partial correlation value output by the adder 14 is a positive value, remains as it is, and when it is a negative value, converts it into a positive value by inverting the polarity sign and always has a positive value. Output the partial correlation absolute value. Reference numeral 16 is a comparator for detecting the chip clock timing at which the partial correlation absolute value has a peak within one partial spreading code period (that is, autocorrelation is obtained), and is 1/4 of the maximum correlation value from the outside. For example, when the spreading code length is 16 as in the present embodiment, an appropriate numerical value between 4 and 8 is set as the threshold TH1, and the value output by the absolute value calculation unit 15 exceeds this threshold. Outputs detection pulse DET1 at clock timing. Reference numeral 18 denotes a partial correlation value holding register, which takes in the partial correlation value output from the adder 14 at the timing of the latch pulse LP from the control unit 17, and holds / outputs it.

A control unit 17 receives the detection pulse DET1 and generates various control signals. The switching control signal CNT is
Immediately after the operation starts, it becomes "H", and when the first detection pulse DET1 is input, it becomes "L" and the next detection pulse DET1 is input.
It becomes "H". After that, each time the detection pulse DET1 is input, "L",
"H" is output alternately. This switching control signal causes DET1
Each time a pulse is generated, the multiplication coefficient supplied to the multiplier alternates between the latter half partial spreading code and the first half partial spreading code. Further, the control unit 17 supplies the latch pulse LA to the partial correlation value holding register 18 every other detection pulse from the detection pulse following the first detection pulse, and the output control pulse is output at the detection pulse timing in the middle of the two latch pulses. Output OUTCNT. An adder 19 constantly adds the output of the partial correlation value holding register 18 and the output of the first adder 14 and outputs the result. Reference numeral 20 denotes an output gate formed of, for example, a 3-state gate, which outputs the output of the second adder 19 to the subsequent stage as a correlation value only when the output control pulse OUTCNT is applied.

Reference numeral 21 is a second absolute value calculation unit, which converts the addition result from the second adder 19 which is always input into a positive value and outputs it. Reference numeral 22 is a comparison circuit, and a second threshold value TH2 for detecting a value equal to or more than 1/2 of the maximum correlation value in one chip pattern cycle, for example, a numerical value 8 is set from the outside, and when the input exceeds the threshold value, Detection pulse DE
Output T.

Next, the operation will be described with reference to FIG. It is assumed that the original signal to be transmitted is a sequence of data "0" and is spread over 16 chips by the spreading code and transmitted.

In FIG. 2, the time axis is the vertical direction, the upper stage for each chip clock timing is the information value of the received spread spectrum signal held in the receive shift register, and the lower stage is the coefficient supplied by the coefficient register. It is the corresponding information value. First, in the initial state, the switching control signal CNT is "H", and IJKLMNOP "10010001" of the partial spread code pattern of the latter half of the spread code is read from the coefficient register 13b.
The multiplication coefficient "-1,1,1, -1,1,1,1, -1" corresponding to is supplied. The received spread signal is input to the receive shift register one chip at a time, and at the chip clock timing 0 when the eight chips corresponding to the latter half of the spread code are input, the parallel output of eight chips of the receive shift register 11 becomes "10010001". Since the corresponding values are "-1,1,1, -1,1,1,1, -1", the outputs of the eight multipliers are all +1 and the partial correlation absolute value is 8 and is maximum. As a result, the first detection pulse DET1-1 is output, and the control unit 17 starts operation. First detection pulse DET1
Since the control unit 17 sets the switching control signal CNT to "L" by -1, the coefficient supply source is switched to the coefficient register 13a, and "-1, -1,-" corresponding to the first-half partial spreading code ABCDEFGH "11110101"
1, -1,1, -1,1,1 "is fed to the multiplier. After the first switch
At timing 9 after 8 chip clocks, the first half of the next received spread spectrum signal is input and held in the receive shift register, so the partial correlation value and its absolute value become maximum again, and the second detection pulse DET1- 2 occurs. As a result, the partial correlation value a at that time is taken into the correlation value holding register 18, the switching control signal CNT becomes "H", and the multiplication coefficient is switched to the latter partial spreading code.
As a result, the received signal is awaited by the latter spreading code, and the partial correlation value becomes maximum again at the chip timing 16 of the eighth chip clock after switching. At this time, the value obtained by adding the maximum partial correlation value a in the first half and the maximum partial correlation value b in the latter half by the second adder 19 is output to the subsequent stage as the output of the matched filter and is set to a predetermined value. The data is decrypted and the data is extracted. The absolute value is the second threshold TH
Since the comparator 22 detects that the value exceeds 2, the detection pulse DET and the maximum correlation value are output once in one chip pattern cycle.

When the transmission information is "1", the sign of the received signal pattern is inverted, so the sign of the correlation output before the absolute value is "-" and the correlation value takes the absolute value. Is positive. "1" and "0" of the transmission information are detected by discriminating the positive or negative of the correlation output at the timing of the detection pulse. The correlation value is also used for controlling a local oscillator for converting the received radio frequency number signal into an IF signal. The detection pulse is used as a timing signal for identifying data and generating a chip clock.

FIG. 3 shows a second embodiment in which a shift register is used as the coefficient register of the partial spread code supplying means. The coefficient register is composed of a current coefficient holding register 23a holding an 8-chip length partial spread code and a standby coefficient register 23b holding the remaining 8-chip length. A spreading code pattern for one chip pattern period of 16 chips long is divided and held in both, and the multiplication coefficient is supplied to the multiplier 12 from the current coefficient holding register 23a. The output from the final stage of one coefficient holding register is connected to the input of the first stage of the other coefficient register, and counterclockwise by the shift pulse SP synchronized with the chip pattern clock from the control unit 17 '.
Shift one chip at a time. Therefore, the working coefficient register
23a outputs the coefficient corresponding to 8 chips of the spread code pattern in succession, and shifts in the leading digit direction every 1 chip clock.
Shift one chip at a time. Then, the control unit 17 ′ outputs the shift pulse SP at the cycle of the chip clock when the first detection pulse DET1 is input. In the initial state, the current register
23a shows partial spreading codes I, J, K, L, M, N, which are the latter half of the spreading code.
The pattern of 8 chips of O and P is held so that the last chip I corresponds to the first stage of the shift register, and the waiting coefficient register 23b stores the first-half partial spread codes A, B, C, D, E, F, A pattern for 8 chips of G and H is stored. Since no shift pulse is generated at this point, the current coefficient register
The output of 23a is fixed. The reception spread signals input to the reception shift register 11 are successively shifted, and the partial correlation value from the adder 14 becomes maximum at the chip timing when its parallel output coincides with the latter half. Since the absolute value at that time exceeds the threshold value of the comparator 16, the first detection pulse DET1 is output. As a result, the control unit 17 'starts supplying the shift pulse, the contents of the current coefficient register are shifted in the leading digit direction by one chip, and the coefficient corresponding to the first half partial spread code is output at the eighth chip clock. To do. At this time, since the first half of the next reception spread code has been input to the reception shift register 11, the partial correlation value at the chip clock timing becomes maximum. Since the control unit 17 'generates the latch pulse LP and the output control pulse OUTCNT at the same chip timing as in the first embodiment with reference to the first detection pulse DET1, the peak of the partial correlation value in the first half is obtained. a is held in the partial correlation value register 18. At the next 8-chip clock, the correlation value between I, J, K, L, M, N, O, P in the latter half of the spreading code and the input spread signal peaks, so the maximum correlation value b in the latter half is the threshold value. After that, the third detection pulse DET1 is output. At this time, the addition result of the first-half maximum correlation values a and b held in the partial correlation value register is output to the data identification unit in the subsequent stage. Further, since the absolute value of this correlation value exceeds the second threshold value, the detection pulse DET is output.

In the above embodiment, the spreading code having a chip length of 16 is divided into two partial spreading codes having a length of 8 chips. If the chip length of this spreading code is an odd number and the spreading code cannot be divided into two parts with the same chip length, the reception shift register and the multiplier may be provided according to the larger chip length.

When the number of divisions is set to 3 or more, the partial correlation value registers corresponding to the number of divisions are provided, and the control section sets the partial correlation value corresponding to each partial spread code at an appropriate timing. By holding the maximum value and outputting one total correlation value for each one spread code frame, or by cumulatively adding three or more maximum partial correlation values sequentially obtained for each chip length unit after division. , One maximum correlation value for all chip lengths may be output.

This chip division number is the CN of the communication system.
Depending on the combination of the ratio, the required number of channels, the spreading code length, etc., it is possible to appropriately determine the optimum characteristics.

[0031]

As described above, according to the present invention, since the correlation between the partial spread code obtained by dividing the spread code and the received spread spectrum signal is sequentially obtained, the multiplier for receiving the correlation and the received spread signal are held. The number of shift registers can be reduced, and the digital matched filter can be realized with a small circuit scale.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a digital matched filter of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a block diagram of a second embodiment of the digital matched filter of the present invention.

FIG. 4 is a diagram showing a direct spectrum spread spectrum communication system to which the digital matched filter of the present invention is applied.

FIG. 5 is a block diagram of a conventional digital matched filter.

[Explanation of symbols]

11 ... Reception shift register, 12 ... Multiplier, 13a, 13b, 23a, 23
b ... Coefficient holding register, 14 ... Adder, 15 ... Absolute value calculation unit, 16 ... Comparison unit, 17, 17 '... Control unit

Claims (2)

[Claims] 1. A digital matched filter for despreading an original signal by despreading a spread spectrum signal of a received signal, which is spread spectrum of the original signal using a spreading code of a predetermined chip length, and divides the spreading code of a predetermined chip length. Then, a plurality of partial spread codes having substantially equal chip lengths are obtained, partial correlation values of the received spread spectrum code and each of the plurality of partial spread codes are sequentially obtained, and the sum of the maximum partial correlation values for all partial spread codes is calculated. A digital matched filter, wherein the digital matched filter is configured to output as a correlation value between a spread code having the predetermined chip length and a received spread spectrum code. 2. A reception shift register means (11) having a depth of a chip length of a partial spread code and serially input by a chip of a spread spectrum code, and an output of each stage of the reception shift register means (11). Multiplying means for multiplying each coefficient (12), and each partial spreading code is switched and held based on the control signal,
Partial spreading code supply means (13a, 13b) for supplying the held value to the multiplication means as a multiplication coefficient, and addition means (14) for obtaining the sum of the outputs of the multiplication means and outputting it as a partial correlation value, Absolute value calculation means (15) for generating a partial correlation absolute value which is the absolute value of the partial correlation value, and comparison means (16) for detecting a chip timing at which the partial correlation absolute value exceeds a predetermined threshold TH1, and at the start of reception. Based on the first chip timing of, the chip timing that maximizes the partial correlation value between the subsequent partial spread code and the received spread spectrum signal is obtained, and at this timing the desired partial spread code is the partial spread code supply means (13a). , 13b) and a control means (17) for generating a control signal for controlling so as to hold the partial correlation value output by the adding means (14) at the chip timing and cumulatively add one chip length. Output The digital matched filter according to claim 1, further comprising: partial correlation value adding means (18, 19, 20) for