KR950007434B1 - Dial early-late tracking loop circuit - Google Patents

Abstract

In the spread spectrum communication system, the digital early-late tracking loop circuit enhances the synchronous tracking performance. This digital ELL(Early-Late tracking Loop) matches easily early loop and late loop, and the size of ELL circuit is minimized. The ELL circuit consists of a sampler(22) that samples analogue received signal (21), an analogue/digital converter(24), a PN symbol generator that outputs early PN symbol(216) and late PN symbol(217), multipliers(25, 26) and a voltage-controlled clock generator(213). This ELL circuit deals with effects of fading and noise actively.

Description

Digital Early-rate Tracking Loop Circuit

1 is a block diagram of a conventional digital early-rate tracking loop circuit.

2 is a block diagram of a digital early-rate tracking loop circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

22: sampler 23: analog / digital conversion unit

25,26: multiplier 27,28: accumulator

29,210: Square detector 211: Subtractor

212 loop filter 214 PN code generator

215: voltage control clock generator

The present invention relates to a synchronous tracking loop circuit for demodulating a received signal in a spread spectrum communication system, and in particular, to provide a digital early tracking loop call for digitally improving the synchronous tracking performance. have.

In general, a band conversion communication system is a communication system in which a designer or a user wants to protect information from interference or detection of a communication, and a frequency system of a transmission signal has a wider bandwidth than that of a message signal. In the field of spread spectrum communication, synchronization tracking is one of the important problems that affect the performance of a system. Previously, synchronous tracking was mainly performed using analog early-late tracking loops (ELLs) and Tau-Dither loops (TDLs). The explanation is as follows.

When the signal γ (t + τ) (1) delayed by τ with respect to the transmission signal in FIG. 1 is input to the ELL, it is detected by the phase detector 14 and then generated by the PN (Pseudo Noise) code generator 11. As fast as half cycle of Signal 13 and half cycle only big slow The signal 12 is multiplied by two correlators 2 and 3, respectively. Where τ represents a phase difference. In this case, the outputs of the two correlators 2 and 3 become autocorrelation values between the reference signal and the phase shifted signal. The correlation is a value for a reference PN code that is earlier or slower by half a period.

The outputs of the two correlators 2 and 3 are respectively detected only the bands restored through the band pass filters 4 and 5, and only the magnitude of the correlation values is output through the square detectors 6 and 7. The correlation value is input to the subtractor 8. Therefore, the process of multiplying the slow sign by filtering and square detection is called a late loop (LL) and the process of multiplying the fast sign by filtering and square detection is called an early loop (EL). ) Is the difference between the early loop EL and the rate loop LL. The difference means a phase difference between the phase of the currently input signal 1 and the reference PN code. By adjusting the phase of the reference PN code generator 11 by this phase error, an accurate synchronization is achieved. A predetermined DC value is generated in the loop filter 9 and then the DC value is controlled in the voltage controlled oscillator 10. By inputting and oscillating to generate a clock corresponding to the phase error, the PN code output speed can be adjusted.

However, in the conventional analog ELL circuit, it is impossible to match the early loop and the late loop in hardware, so that the decriminator characteristics are distorted, and there is no way to establish the correlator characteristics for fading and noise. . On the other hand, analog TDL has the disadvantage of easy hardware matching but severe distortion of thermal noise.

It is therefore an object of the present invention to provide a digital ELL circuit that facilitates matching between early loops and rate loops, thereby improving system performance and miniaturization.

The digital early-rate tracking loop circuit for achieving the above object comprises a sampling means for sampling an analog received signal a predetermined number of times in a synchronous tracking circuit of a spread spectrum communication system, and converting the sampling signal into a digital form. An analog / digital conversion means, pien code generating means for outputting an early phi code and a rate phi code in binary code form having a unique autocorrelation characteristic and having a predetermined period, and a signal converted into the digital form A first multiplier for despreading by multiplying the early P & I code, a second multiply for despreading by multiplying the signal converted into the digital form and the rate pien code, and outputs of the first and second multipliers Each of the first and second cumulative replication means that accumulatively add during each symbol duration, and the output of the first and second cumulative replication means, respectively, Generating a predetermined clock in response to the detected phase difference; and means for detecting a phase difference between the received signal and the reference PEN code by calculating the difference between the first and second square detection means; And a voltage control clock generating means for providing the clock to the PEN code generating means and controlling the phase of the reference PEN code to be in phase with the received signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. Common knowledge in the field will be obvious to the Gazaan. In the following description of the present invention, detailed descriptions of related well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention.

2 is a configuration diagram of a digital ELL circuit according to the present invention, which includes a sampler 22 for sampling an analog received signal 21 by a predetermined number of times, and an analog / digital converter 24 for converting the sampling signal into a digital form. And a PN code generator 214 for outputting an early PN code 216 and a rate PN code 217 of binary code form having a unique autocorrelation characteristic and having a predetermined period, and the digital reception signal 24 and Two multipliers 25 and 26 for logically multiplying the early PN code 216 and the rate PN code 217, two accumulators 27 and 28 for cumulative addition of the two logical products, and the two additions. Two square detectors 29 and 210 for square-computing a result, a subtractor 31 for detecting a difference between the two squared detector results, and a clock controlled by the detected difference signal to adjust the phase of the PN code with an input signal. Voltage-controlled clock generator controls to be in phase It consists of the living part 213.

The present invention will be described in detail based on the above configuration.

The sampler 22 samples the analog signal 21 received from the transmitting side for a predetermined number of times. The analog / digital converter 24 converts the sampling signal into a digital form. The received signal r (k + τ _s ) 24 converted into the digital form is an early PN code r (t + τ _s ) 216 and a rate PN code outputted from the PN code generator 214. (217) and two multipliers (25, 26) are respectively multiplied and inversely converted. The despread signal is input to two accumulators 27 and 28, respectively. The two accumulators 27 and 28 are known Accumulator & Dump circuits, which accumulate and add a despread signal transmitted from the multipliers 25 and 26 for one symbol duration, respectively, and then use two square detectors 29 and 210 respectively. To pass). The two square detectors 29 and 210 square-operate the outputs of the first and second cumulative replicators 27 and 28, respectively, and provide them to the subtractor 31, and the two square detectors 29 and 210 in the subtractor 31. The phase difference between the early loop and the rate loop is detected from the The detected phase difference signal is input to the loop filter 212 to extract only necessary components. The clock of the voltage control clock generator 213 is adjusted using the extracted signal to adjust the phase of the reference PN code output from the PN code generator 214 to be in phase with the received signal.

The multiplier 25 and the accumulator 27 and the multiplier 26 and the accumulator 28 are digital matched filters. Unlike the analog type, the characteristics of the tracking loop can be improved by considering channel characteristics and fading. The two square detectors 29 and 210 can maintain tracking regardless of whether the data of the input signal is 1 or -1.

As described above, by implementing the digital ELL circuit, it is easy to digitalize the spread spectrum system, has a good matching between the early loop and the rate loop, and has the advantage of actively coping with the effects of fading and noise, and digitalize the system. As a result, there is a miniaturization and lightening effect.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (1)

A synchronous tracking circuit of a spread spectrum communication system, comprising: sampling means for sampling an analog received signal a predetermined number of times, analog / digital conversion means for converting the sampling signal into a digital form, and unique autocorrelation characteristics, and having a predetermined period A pien code generating means for outputting an aliphaene code and a rate pien code having a binary code form, a first multiplier for despreading by multiplying the digitally converted signal and the early pien code, and A second multiplier for logically inversely multiplying the signal converted into a digital form by the rate pien code, and first and second cumulative replication means for accumulating and adding the outputs of the first and second multipliers for one symbol duration, respectively; And calculating first and second square detection means for squared operation of the outputs of the first and second cumulative replication means, and the difference between the two square detection results. Means for detecting a phase difference between the received signal and the reference PEN code, and generating a predetermined clock in response to the detected phase difference, and providing the clock to the PEN code generating means so that the phase of the reference PEN code is set to the received signal. A digital early-rate tracking loop circuit, comprising: a voltage controlled clock generating means for controlling to be in phase with the same.