JP2596988B2 - Spread spectrum communication system and apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a spread spectrum (SS) communication system, particularly to a direct spread system.

[Conventional technology]

The SS communication method has been widely applied to power line communication in addition to satellite communication and mobile communication. The conventional method will be described with reference to FIG. On the transmitting side, the output of a PN (pseudo noise) code sequence generator 1 is subjected to an EX-OR operation by the transmission data and an EX-OR circuit 2, and then, as a transmission signal by an amplifier 3,
Send to the transmission path. On the receiving side, the received signal is amplified by the amplifier 4 and then correlated with the output of the synchronous PN code sequence generator 5 by the correlator 6, and the correlation value is discriminated by the comparator 7 between “1” and “0”. None, demodulation is performed by associating these “1” and “0” with “1” and “0” of transmission data. FIG. 17 shows signal waveforms at various points in the circuit of FIG.

Transmission paths include wireless, wired, and others, and are widely considered as transmission media. Therefore, in many cases, the transmission signal is not only sent directly to the transmission medium, but also converted into a signal suitable for transmitting the transmission medium and sent. Also, power line communication requires an interface that is separated from commercial power. In the following, a connection portion with a transmission medium that performs such a signal conversion / separation operation is referred to as a reception interface / transmission interface.

[Problems to be solved by the invention]

In the conventional method, the synchronous PN code sequence generator 5 on the receiving side is a generator synchronized with the transmission PN sequence. To synchronize, first, a synchronization point is searched. If there is no problem with the transmission characteristic of the transmission line, a peak is detected at the synchronization point as shown in FIG. However, in the case of a transmission line having extremely poor transmission characteristics such as power line communication and having a dip point in the transmission band, the correlation waveform further deteriorates as shown in FIG. Of the data may be reversed, resulting in data "1" or "0" error. Further, there is a disadvantage that synchronization cannot be maintained due to deterioration of the waveform.

An object of the present invention is to provide a new SS communication system that eliminates the above-mentioned disadvantages by using two PN code sequences.

[Means for solving the problem]

The present invention relates to a modulation signal composed of a PN code sequence keyed by transmission data by associating two PN code sequences having the same code length with low cross-correlation with bit values “1” and “0” of a digital signal, respectively. As it is or as a converted transmission wave, it is transmitted to the transmission medium and transmitted to the receiving side, and between the modulated signal extracted from the receiving wave at the receiving side and the same two PN code sequences as the transmitting side PN code sequence. Simultaneous correlation calculations are performed, and when one of the correlation outputs exceeds the reference value,
The transmission data is determined to be "1" or "0" and restored, and when none of them exceeds the reference value, it is determined that there is no carrier.

[Action]

According to the present invention, two sequences of the PN code sequence are modulated by transmission data, and the transmission signal associates the first sequence and the second sequence with bit values “1” and “0” of the transmission data. The received modulation signal has two PN code sequences for each PN code cycle;
1, one of the second series. If the received modulated signal is guided to, for example, two parallel paths, the first path of the PN code sequence is correlated with the first sequence of the PN code sequence on one path, and the second sequence is correlated on the other path. The correlation peak output appears on either path. Depending on which path shows the correlation peak output, the data “1”,
"0" can be determined.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the entire basic configuration for implementing the present invention, and FIG. 2 shows a block diagram of a two-sequence demodulator on the receiving side. FIG. 3 shows the signal waveform of the signal at each point in FIG. 1 and FIG.

In FIG. 1, a transmission data a is input to a two-sequence modulator 11 and one of two PN code sequences is output as an output b. The transmission data is a binary signal of "1" and "0".
As shown in FIG. 3, the two-sequence modulator 11 selects and outputs the first sequence PN1 for "0" and the second sequence PN2 for "1", for example. This output is sent to the transmission line via the transmission interface 12. The transmission interface 12 is a connection part in a broad sense, as shown in the related art, and is a part including modulation of a carrier or mixing into a power line. The receiving interface 13 also demodulates the carrier or separates the carrier from the power line.
14 and receive data "1",
“0” is obtained. Whether or not a carrier is received is indicated by a carrier detection signal f.

FIG. 2 shows a block diagram of the two-sequence demodulator 14. The reception modulation signal c is branched into two paths and divided into two paths.
Correlation calculation is performed by a correlator 141 that correlates with PN1 of the first series and a correlator 142 that correlates with PN2 of the second series.
The correlation output comparator 143 and exceeds the threshold V _R "1"
A pulse is output. Outputs of comparators 143 and 144 are R
The signal is input to the R terminal and the S terminal of the S flip-flop 145. The setting of this input terminal is such that the first sequence corresponds to the transmission data “0”, so that the reception modulation signal c is the first sequence PN1
In this case, the RS flip-flop 145 is reset and the output becomes "0", and in the case of the second series PN2, the RS flip-flop 145 is set and the output becomes "1". Therefore, the correlation outputs d ₁ , d ₂ and R
The signal waveform of the demodulated data e by the S flip-flop 145 is as shown in FIG. Note that the correlation peak appears at the end of each cycle.

When there is no carrier, the output f of the carrier detection circuit 15
Is detected by The carrier detection circuit 15 includes a comparator 143,
The output of 144 is input to the timer circuit 15B via the OR circuit 15A. The timer circuit 15B is set by the output pulse of the OR circuit 15A, and sets the output f to "1" for a certain period of time, and to "0" after this period. This fixed time is PN
It is longer than the code period T. If there is any correlation output within this time T, f always indicates “1”, and if there is no correlation output beyond this time T, it becomes “0”. Can be detected.

In the method of the present invention described above, unlike the conventional method, the receiving side simply detects the synchronization and drives the RS flip-flop to “1” or “0”.
It does not form “1” or “0” as a correlation waveform from the waveform of the received modulation signal as shown in the figure. Therefore, the phase synchronization of the PN code on the receiving side that correlates with the received modulation signal need not be strict as compared with the conventional example. Further, if an absolute value is taken as the output of the correlator, no error occurs even in the case of a transmission line having characteristic deterioration such that the transmission peak value is negative.

Next, various circuit configurations used for each component of the transmission device and the reception device will be described.

A. Transmitter An example of a two-sequence modulator used in a transmitter will be described.

(1) In FIG. 4, two M-sequence generators are provided and their outputs are switched and output. FIG. 5 shows signal waveforms of each part. The M-sequence generators 22 and 24 differ from each other in the feedback loop of the three-stage shift register, and operate on the output clock of the oscillator 21. NAND that the bits of the shift register of the M-sequence generator 22 become "1" so that the M-sequence generator 24 always has a constant phase at a specific phase with respect to the output of the M-sequence generator 22 The detection is performed by the circuit 23. At this time, each bit of the shift register of the M-sequence generator 24 is loaded with a specific bit value by the initial value setting connection 25. In the example shown, FF ₂₁ , FF ₂₂ and FF ₂₃ are 1, 0, 1 respectively
I have to.

The switching circuit 26 switches the outputs of the M-sequence generators 22 and 24 in each cycle according to “1” and “0” of the transmission data TXD. In the figure, the output PN1 of the M-sequence generator 22 is output when it is "0", and the output PN2 of the M-sequence generator 24 when it is "1". Note that N
When the output 23a of the AND circuit 23 is sent to a transmission data processing unit (not shown) as a transmission request signal, the transmission data
TXD is sent periodically.

(2) FIG. 6 shows the transmission of two series of codes by switching the connection of the feedback loop of one shift register by "1" and "0". FIG. 7 shows signal waveforms at various parts of the circuit.

The three-stage shift register 32A is driven by the output clock of the oscillator 31, and the EX-OR circuits 32B and 32C
A feedback loop is formed via the switching circuit 33. The feedback loop is switched by the switching circuit 33 every cycle of the M-sequence generator. When switching to D1, the first stream (corresponding to "0" data)
When switching to the D2 side, a second stream (corresponding to "1" data) is generated. The NAND circuit 34 detects that each bit of the shift register 32A has become "1", enables the D flip-flop 35, takes in the transmission data TXD, and outputs its output SW
To set the switching circuit 33 to the "1" side or the "0" side. The modulation output is taken out from the last stage of the shift register 32A and sent out.

B. Receiver (1) An example of a two-sequence demodulator used for the receiver will be described. The two-sequence demodulator is basically composed of the received signal and the output of two built-in PN code generators as described in FIG.
It comprises a correlator for obtaining a correlation with PN1 and PN2, a data reconstructor for reconstructing data from two outputs of the correlator, and a carrier detection circuit. FIG. 8 shows a two-sequence demodulator using a surface acoustic wave (SAW) convolver to correlate the correlators. This circuit is exactly the same as that already described with reference to FIG. 2, and in the correlator, the PN code sequence assigned to the "0" bit of the transmission data; the PN code sequence assigned to the PN1 and "1" bits
The PN code sequence; PN2 is correlated with the SAW convolvers 41 and 42, respectively. In this example, the received signal c is processed as an analog signal. FIG. 9 is a signal waveform diagram of each part. In this case, it indicates 4-bit transmission data. The output f of the carrier detection circuit 15 is output f after a time t> T (data 1-bit time point) after the timer circuit 15B is set.
Is set to zero, indicating that the data has ended.

Hereinafter, a case will be described in which the configuration of the correlation unit is variously modified and realized as the receiving device. The input to the correlator may be an analog signal or a digital signal obtained by A / D conversion of the analog signal.

(2) FIG. 10 shows a case where the received signal is a digital signal, and the received signal is transmitted to the correlators 50 (1) and 50 (1) having the same configuration.
(2), and correlates with the first sequence PN1 and the second sequence PN2, respectively. The configuration is illustrated for the correlator 50 (1). The first series PN1 correlated with the received signal stores one state pattern in the register 51 in a fixed manner. Therefore, the number of stages is equal to the code length N. This pattern data is defined as PN1-1, PN1-2,... PN1-n. On the other hand, the received signal is input to the shift register 52, and the fixed pattern data PN1-1 to PN1-
n and EX-OR circuit group 53 and EX-OR are taken, and the sum is summed.
So that sell correlation output d ₁ by taking 54.
In order to improve the accuracy of the correlation calculation, the shift register 52 has n = N × m stages so that one bit of the fixed pattern is correlated with m data. The shift clock is also set to m times.

The circuit shown in FIG. 10 is for a case where the received signal is a digital signal.
As a delay line having (N × m) taps, the EX-OR circuit group 53 is a multiplier group, and the sum circuit 54 is an analog adder.

(3) FIG. 11 shows a case where the circuit is simplified by sharing the shift register of the circuit of FIG. 10 with the first and second systems. The storage registers 611 and 612 are the first series P
N1, N-stage registers for storing fixed patterns of N1 and second series PN2. An n = N × m-stage shift register 610 for inputting a reception signal is common to both streams. And for each series, EX-OR circuit group 612, summing circuits 613 and EX-OR circuit group 622, no correlation calculation in the sum circuit 623, and outputs the correlation output d _1, d _2.

The circuit shown in FIG. 11 is a case where the received signal is a digital signal, but if the received signal is an analog signal, the shift register 610 is a tapped delay line, the EX-OR circuit groups 612 and 622 are a multiplier group, and a sum circuit.
613 and 623 are analog adders.

(4) FIG. 12 is a circuit designed to reduce the scale of the circuit of FIG. 10 for digital reception signals. The details of this circuit are described in Japanese Patent Application No. 63-160954 by the present applicant, and will be described briefly. In FIG. 10, since the EX-OR of one bit of the fixed pattern is taken by m EX-OR circuits, the EX-OR circuit has n = N ×
m, and this sum is taken. To obtain a digital sum, first, a primary adder that takes the sum of two adjacent EX-OR circuits, a secondary adder that takes the sum of the outputs of the adjacent primary adders, and add Therefore, the number of adders becomes extremely large. By the way, in the circuit of FIG. 12 (exemplifying the case of an M-sequence code having a code length of 7 bits), the correlator 70 includes a plurality of correlation measuring circuits.
Each of the correlation measuring circuits 71 includes one fixed pattern bit and m pieces of data of the input received data N × m (for example, SF _{1 to} SF _{m in} FIG. 10). ), The sum of the correlation values for m data at once from the up-down counter using the relationship between the input value and the output value of the m-stage shift register. Things. In the figure, first, a first sequence PN1 having a code length of 7 is input to the register 72, and its bit values M1 to M7 are stored. The received signal is input to the correlation unit 70, and the data is shifted to the correlation measurement circuits 71 (1) to 71 (7), and the correlation is obtained for each block. As shown in FIG. 13 (a), the correlation measuring circuit 71 includes an eight-stage shift register 71A, two EX-OR circuits 71B and 71C, and an up / down counter 71D. The correlation between the signal Di and the bit value M of PN1 is counted.
Since details are described in Japanese Patent Application No. 63-160954, the correlation count is performed by the operation shown in the operation table of FIG. When the respective bits M1~M7 of PN1 adding the correlation measurement circuit 71 (1) to 71 addition section 73 the calculated correlation counted in (7), it is possible to sell a correlation signal d _1.

Sell a correlation signal d ₂ by the same circuit configuration also PN2. In the above configuration, there are advantages that the number of adders forming the adder 73 is significantly reduced, the circuit scale is reduced, and the position delay is reduced.

(5) In FIG. 12, the correlation unit 70 is provided separately for PN1 and PN2, but the shift register 71A of the correlation measurement circuit 71 can be shared for PN1 and PN2. No.
FIG. 14 shows an overall configuration diagram, and FIG. 15 shows a correlation measuring circuit.

〔The invention's effect〕

As described above, the transmission data “1”,
For “0”, the first series and the second series with low cross-correlation of the PN code
A sequence is assigned, the transmission data is modulated, and transmitted as it is or as a converted transmission wave to the transmission medium. On the receiving side, a modulated signal is extracted from the received wave transmitted via the transmission medium, and the same as the transmitting side. Is synchronized with the first and second sequences of the PN code, and when a synchronization peak is obtained, the first synchronization is performed.
The transmission data "1" or "0" is determined depending on whether the stream is the series or the second series, and is restored.

Unlike the conventional example, transmission data is not directly reproduced from the correlation signal waveform, but only the correlation peak is detected. Therefore, the PN code on the receiving side must be strictly synchronized with the PN code on the transmitting side. Absent. Also, such as inverting the synchronization waveform,
Even if the transmission characteristic is poor in the transmission path, the present invention only needs to detect the presence or absence of the synchronization peak, so that no error occurs. Note that the two-sequence modulator and the two-sequence demodulator of the present invention can be realized with various configurations as shown in the embodiments.

[Brief description of the drawings]

1 to 15 relate to an embodiment of the present invention, FIG. 1 is a diagram showing a communication system, FIG. 2 is a block diagram of a two-sequence demodulator of a receiver, and FIG. 3 is transmission data in a transmission example. Between the two-sequence and the two-sequence and the demodulation waveform diagram by the two-sequence demodulator on the receiving side
FIGS. 4 and 5 are illustrations of a two-sequence modulator of the transmitting apparatus and signal waveform diagrams of respective parts thereof, and FIGS. 6 and 7 are other examples of the two-sequence modulator and signal waveform diagrams of respective parts thereof. . FIG. 8 is a diagram using a surface acoustic wave convolver as a correlator as a two-sequence demodulator of a receiving device, FIG. 9 is a demodulation waveform diagram when transmission data is short, and FIGS. It is a block diagram of various correlators used. 16 to 18 relate to a conventional example, and FIG.
FIG. 17 is a diagram showing a demodulated waveform of the conventional example, and FIG. 18 is a diagram for explaining the problems of the conventional example. 11 ... 2 sequence modulator, 12 ... transmission interface, 13 ... reception interface, 14 ... 2 sequence demodulator, 15 ... carrier detection circuit, 141, 142 ... correlator, 143, 144 ... comparator, 145 ... Flip-flop, 21,31 oscillator, 22,24 M-sequence generator, 26,33 switching circuit, 32A shift register, 32B, 32C EX-OR circuit, 41,42 SAW Convolver, 50 (1), 50 (2) ... correlator, 51 ... (memory) register, 52 ... shift register, 53 ... EX-OR circuit group, 54 ... summation circuit, 610 ... shift register , 611,621 ... (memory) register, 612,622 ... EX-OR circuit group, 613,623 ... summation circuit, 71 (1) to 71 (7) ... correlation measurement circuit, 70 ... correlation section, 72 ... (memory) ) Register 73 ... Addition unit.

Claims (13)

(57) [Claims] 1. A modulation signal comprising a PN code sequence keyed with transmission data by associating two PN code sequences having the same code length with low cross-correlation with bit values "1" and "0" of a digital signal, respectively. , Transmitted as it is or as a converted transmission wave, transmitted to the transmission medium and transmitted to the receiving side, and between the modulated signal extracted from the received wave at the receiving side and the two PN code sequences identical to the PN code sequence on the transmitting side. At the same time, and when any correlation output exceeds the reference value,
A spread-spectrum communication system characterized in that transmission data is determined as "1" or "0" and restored, and when neither exceeds a reference value, it is determined that there is no carrier. 2. The spread spectrum communication system according to claim 1, wherein the transmission data is input, and two different PN code sequences; the first sequence and the second sequence are each set to "1" of the transmission data.
Alternatively, a transmission device including a two-sequence modulator that selectively outputs the signal in accordance with “0”, and a transmission interface that inputs a modulation signal of the two-sequence modulator and transmits the signal to a transmission medium as a transmission wave. 3. A spread-spectrum communication system according to claim 1, wherein a reception interface for inputting a reception wave from a transmission medium and extracting a modulation signal, and two different PN codes identical to those on the transmission side for inputting the modulation signal and receiving the modulation signal. First and second correlators, each of which correlates with a sequence, and outputs of the first and second correlators, each of which is compared with a reference value and outputs a "1" when the output exceeds the reference value. A second comparator; and an RS flip-flop in which outputs of the first comparator and the second comparator are led to a set terminal and a reset terminal. The output of the RS flip-flop is used as demodulated signal data. When the output of either the comparator or the second comparator becomes "1", the timer is set to "1", and a carrier detection circuit for resetting the timer when there is no input from the comparator within the timer measurement time is provided. Having a receiving device. 4. A spread-spectrum communication device comprising the transmitting device according to claim 2 and the receiving device according to claim 3. 5. The transmitting apparatus according to claim 2, wherein the two-sequence modulator comprises two M-sequence generators driven by a common clock and outputs the bit values of transmission data "1" and "0".
And a switch for selecting and outputting the switching by means of detecting the periodic point in time when the first M-sequence generator enters a specific state, and having means for initializing the second M-sequence generator based on the detection signal. A transmission device characterized by the above-mentioned. 6. A transmitter according to claim 2, wherein the two-sequence modulator converts a feedback loop connection of one shift register by a switch, and generates two M-sequences as an output of the shift register. , A circuit for periodically detecting a specific state of the shift register, and a latch circuit for receiving transmission data based on the detection signal. Characterized in that the transmission device performs a selection switch. 7. The receiving apparatus according to claim 3, wherein the first and second correlators are surface acoustic wave convolvers that correlate the analog reception modulation signal with the first and second PN code sequences, respectively. A receiving device. 8. The receiving apparatus according to claim 3, wherein the first and second correlators have the same configuration and have a first sequence (second sequence).
And a register for storing an N-bit PN pattern in a specific state, and a mf clock (f
Has a shift register that operates at the clock frequency of the PN code), and EX-ORs each of the N bits of the PN pattern with the bit of every m stages of the shift register, and performs the EX-OR operation of all the EX-OR circuits. Output is summed up to 1st series (2nd series)
A receiving device for providing a correlation output of: 9. A receiving apparatus according to claim 8, wherein the first and second correlators are each configured as an EX-OR circuit as a multiplying circuit, and the sum is replaced with an analog addition to process an analog reception modulation signal. 10. The first and second correlators in the receiving apparatus according to claim 3, wherein each of the first and second correlators is a first or second correlator.
Two first and second registers for storing a specific state of an N-bit PN pattern of a sequence, and N × m for inputting a received modulation signal
And one shift register that operates at the mf clock (f is the clock frequency of the PN code) at each stage. For each of the N bits of the PN pattern of the first register and the second register,
EX with bits for every m stages of one common shift register
A receiving apparatus, wherein -OR is taken, the outputs of the EX-OR circuit are summed by a summing circuit for each of a first stream and a second stream, and a correlation output of the first stream and the second stream is obtained. 11. The receiving apparatus according to claim 10, wherein the shift register is a delay line with a tap, the EX-OR circuit is a multiplier, and the summation circuit is replaced with an adder, and the analog receiving modulation signal is processed. . 12. The receiving apparatus according to claim 3, wherein the correlator includes a register for storing a PN pattern having a code length of N bits in a specific state, output bits of each stage of the register, and a serial bit pattern. A correlation unit composed of a plurality of correlation measurement circuits for performing a correlation measurement for each bit stage with respect to an input signal sequentially input, and a measurement value of a correlation measurement circuit at each stage of the correlation unit are added and output as a correlation output. The correlation measuring circuit includes an m-stage shift register that operates with an mf clock (f is a clock frequency of a PN code), and a counter that counts the clock of the frequency mf. Operates only when the input value of the correlation measurement circuit is different from its output value, and matches or does not match the output bit of the register with the input bit of the correlation measurement circuit. A first correlator in which a PN pattern stored in a register of the correlator is a first series pattern, and a second correlator in which a PN pattern stored in a register of the correlator is a second series pattern. A receiving device comprising: 13. The receiving apparatus according to claim 12, wherein the shift register of the correlation measuring circuit of the correlator is a first correlator and a second correlator.
A receiving device commonly used with correlators.