JPH01251833A - Timing compensating circuit - Google Patents

Abstract

PURPOSE:To realize the synchronism between data and the PN code cycle without using a buffer memory nor jitter absorbing circuit by absorbing the phase difference between the clock of a data terminal and a pseudo noise PN code of a modulator within a data duration time. CONSTITUTION:A pseudo noise code generating circuit 4 produces a PN code and also transmits an epoch signal (epoch pulse) serving as a sampling command signal for each cycle of the PN code. An exclusive logical arithmetic circuit 6 performs the exclusive logic arithmetic between the output data received from a D flip-flop serving as a sampling means and the PN code received from the circuit 4 and sends said arithmetic result to a secondary modulation system as a primary modulation signal. In such a constitution, the phase difference between the clock of a data terminal so far absorbed by a buffer memory and the PN code cycle of a modulator can be absorbed within a data duration time. Thus it is possible to secure the synchronism between data and the PN code without using a buffer memory nor jitter absorbing circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a spread spectrum communication system, and in particular, to timing compensation that can compensate for phase errors between a data terminal and a modulator when data transmission between the two is asynchronous. Regarding circuits.

[Conventional technology]

This type of spread spectrum communication method is a communication method in which data is spread by a pseudo-noise code and sent out onto a transmission path, and data is extracted from a signal from the transmission path using the same pseudo-noise code as the above-mentioned pseudo-noise code. , it has been used because of its confidentiality and ability to maintain identity. Various spread spectrum communication systems have been proposed depending on the spreading method. In the direct spread spectrum communication system (hereinafter referred to as 5S-DS system), if one bit of data and the period of the pseudo-noise code (PN code) are synchronized, the demodulation system can synchronize the PN code. It is often used because it has many advantages, such as being able to obtain the data timing as is, eliminating the need for a data timing extraction circuit, and being able to obtain initial synchronization without a preamble. However, in reality, in the 5S-DS system described above, the data terminal cannot necessarily operate in synchronization with one cycle of the PN code of the modulator, so conventionally, a buffer memory is prepared on the modulator side. This buffer memory allows the clock of the data terminal and the PN of the above-mentioned modulator to be
It absorbed the difference with the code period. Further, in order to absorb data jitter, the conventional 5S-DS system is provided with a circuit such as a shift register.

[Problem to be solved by the invention]

The conventional 5S-DS system described above uses modulated data and P,
In order to synchronize the period of the N code, a buffer memory was provided, so in addition to the buffer memory,
A control circuit is required to control this buffer memory.
The disadvantage is that the number of circuit components increases. Furthermore, the conventional 5S-DS system has the disadvantage that signal delay occurs due to the presence of a buffer memory.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a timing compensation circuit that can synchronize data and a PN code with a reduced number of circuit components. .

[Means for Solving the Problems] In order to achieve the above object, the timing compensation circuit of the present invention includes a sampling means for sampling data, a pseudo noise code, and the aforementioned pseudo noise code in a spread spectrum communication system. A pseudo-noise code generation circuit outputs a sampling command signal every cycle of the noise code, and a logical operation is performed on the output data from the sampling means and the pseudo-noise code from the pseudo-noise code generation circuit to generate a primary modulation signal. It is equipped with a logic operation circuit that outputs.

The present invention makes it possible to absorb the discrepancy between the clock of the data terminal and the PN code of the modulator within the data duration, thereby eliminating the need for a conventional buffer memory and jitter absorption circuit. data and PN without
It can be synchronized with the code period.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of an embodiment of a timing compensation circuit for spread spectrum communication according to the present invention.

The embodiment shown in FIG. 1 includes a D flip-flop 2 as a sampling means for sampling human data DT, a PN code, and an epoch signal (e
poch pulse), output data from the D flip-flop 2 which is the sampling means mentioned above, and P from the pseudo noise code generation circuit 4.
It is provided with an exclusive logic operation circuit 6 which performs an exclusive logic operation with the N code and outputs it to the secondary modulation system as a primary modulation signal. In addition, the embodiment includes a clock generation circuit 8 that outputs a clock that provides the original oscillation of the PN code to the pseudo-noise code generation circuit 4, and a clock generation circuit 8 that generates the pseudo-noise code generation circuit 4 based on the clock CK synchronized with the middle of the data. A D flip-flop 10 is provided to form a star (5 tart) signal for operation.

The operation of the timing compensation circuit of such an embodiment will be explained.

FIG. 2 is a timing chart for explaining the operation of the embodiment. In FIG. 2, the horizontal axis indicates time t, (a) is the input data DT, (b) is the epoch pulse of the pseudo noise code generation circuit 4, and (,C) is the output from the Q output terminal of the D flip-flop 2. signal, (d) is the PN code of the pseudo noise code generation circuit 4, (e) is the exclusive logic operation circuit 6
This is the output of

First, the D flip-flop IO is set by a clock OK synchronized with the center of input data, and at this timing, the pseudo noise code generation circuit 4 starts operating. At the same time, an epoch pulse is applied from the pseudo noise code generation circuit 4 to the D flip 70 tube 2. As a result, the D flip-flop 2 is activated by the epoch pulse shown in FIG. 2(b).
The human power data DT is sampled as shown in FIG. 2(C). The output of FIG. 2(C) from the D flip-flop 2 is the output of FIG. 2(d) from the pseudo noise code generation circuit 4.
An exclusive OR operation is performed in the exclusive logic operation circuit 6 using the PN code of , and the output is outputted to the secondary modulation system as a primary modulation output as shown in FIG. 2(e).

- When the cycle modulation is completed and the next cycle is started, the pseudo-noise code generation circuit 4 outputs epoch < /res again, so the manual data DT based on this epoch pulse is transferred to the D flip-flop 2. to sample.

Then, the operations described above are repeated.

FIG. 3 is a time chart showing the relationship between the output and the human power of the exclusive logic operation circuit 6, where the horizontal axis shows time t,
The signal shows the relationship between the input power and the output of the exclusive logic operation circuit 6, and the shaded area indicates that it is subjected to primary modulation.
It is.

Here, FIG. 3(a) shows the normal state in the initial state.

Even if the position of the human data DT shifts over time due to the difference in the original oscillation between the human data DT and the PN code, data O jitter, etc., as long as it stays within 172 bits, the -order change All the modulations are performed correctly, and the output of the -order modulation is one in which the data and the PN code are completely synchronized (see FIG. 3(b)).

As time passes, the deviation of the human data DT is reduced to 1/2.
When the number of bits or more is exceeded, a cycle slip occurs, as shown in FIG. 3(C), and one-bit data dropout occurs in the -order modulation output. The timing shown in FIG. 3(C) occurs when the clock of the input data DT is earlier than the period of the PN code, and vice versa, when it is slower than the period of the PN code, erroneous data will be inserted.

〔Effect of the invention〕

As described above, the present invention is capable of absorbing the phase difference between the clock of the data terminal and the period of the PN code of the modulator, which was conventionally absorbed by the buffer memory, within the data duration. It is possible to synchronize the data and the PN code without any trouble. In addition, in the present invention, the difference in absorbability is 172, which is the data duration.
Therefore, it is particularly effective when the clock stability of the human data DT is relatively good and the transmission rate is low.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing charts shown to explain the operation of the embodiment. 2...D flip-flop (sampling means), 4...Pseudo noise code generation circuit, 6...
Exclusive logic operation circuit (logic operation circuit). Applicant NEC Corporation Agent Patent Attorney Isao Yamauchi +6 ) (b) (C)

Claims (1)

[Claims] In a spread spectrum communication system, a sampling means for sampling data, a pseudo-noise code generation circuit for generating a pseudo-noise code and outputting a sampling command signal every cycle of the pseudo-noise code, and an output from the sampling means. 1. A timing compensation circuit comprising a logic operation circuit that performs a logic operation on data and a pseudo-noise code from a pseudo-noise code generation circuit and outputs the result as a primary modulation signal.