JPH02303056A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH02303056A JPH02303056A JP12331989A JP12331989A JPH02303056A JP H02303056 A JPH02303056 A JP H02303056A JP 12331989 A JP12331989 A JP 12331989A JP 12331989 A JP12331989 A JP 12331989A JP H02303056 A JPH02303056 A JP H02303056A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- electrode
- package
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 20
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 238000000465 moulding Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はカード用ＩＣモジュール等の薄型半導体集積回
路の製造方法に関し、特にそのパッケージの製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a thin semiconductor integrated circuit such as an IC module for a card, and particularly to a method of manufacturing a package thereof.
従来、この種の薄型半導体集積回路を製造するには、裏
面に外部接続用電極を有しかつ半導体集積回路が装着さ
れる収納部を有するパッケージを予め形成しておき、こ
のパ、ツケージ内に半導体集積回路を装着させ、金属細
線等によって半導体集積回路とパッケージの内部電極と
を接続した後、半導体集積回路をボッティング樹脂等に
よって封止していた。これを第５図ないし第７図によっ
て説明する。Conventionally, in order to manufacture this type of thin semiconductor integrated circuit, a package is formed in advance, which has electrodes for external connection on the back side and a housing section into which the semiconductor integrated circuit is mounted, and a package is placed inside the package. After mounting the semiconductor integrated circuit and connecting the semiconductor integrated circuit to the internal electrodes of the package using thin metal wires or the like, the semiconductor integrated circuit is sealed with a potting resin or the like. This will be explained with reference to FIGS. 5 to 7.
第５図（ａ）〜（ｃ）は従来の薄型半導体集積回路用パ
ッケージを示す図で、同図（ａ）は平面図、同図（ｂ）
は（ａ）図中ｖ −ｖ ｖＡ断面図、同図（ｃ）は裏面
図゛を示す。第６図（ａ） 、 （ｂ）は従来のパッケ
ージに半導体集積回路チップが装着された状態を示す図
で、同図（ａ）は平面図、同図（ｂ）は（ａ）図中■−
■線断面図を示す、第７図は樹脂封止後の従来の薄型半
導体集積回路を示す断面図である。これらの図において
、１は薄型パッケージで、この薄型パンケージ１は基板
１ａを３枚、断面略階段状に積み重ねて形成され、幅方
向中央部には厚みが薄く形成されたダイパッド部２が設
けられ、かつ外側部には前記ダイパッド部２より厚みが
厚く形成された外枠部３が設けられている。４は後述す
る半導体集積回路チップに接続される内部電極、５は外
部装置（図示せず）に接続される外部電極で、この外部
電極５は前記薄型パッケージｌの裏面に形成され、薄型
パッケージ１に設けられたスルーホール（図示せず）等
によって前記内部電極４に接続されている。７は半導体
集積回路チップで、この半導体集積回路チップ７は上面
に電極７ａが形成され、前記薄型パッケージ１のグイパ
ッド部２に接着材８を介して装着されている。９は前記
半導体集積回路チップ７の電極７ａと薄型パフケージ１
の内部電極４とを接続するための金属細線、１０は半導
体集積回路チンブ７および金属細線９等を封止するため
の封止樹脂である。FIGS. 5(a) to 5(c) are diagrams showing a conventional thin semiconductor integrated circuit package, in which FIG. 5(a) is a plan view and FIG. 5(b) is a plan view.
(a) is a sectional view along v-vvA in the figure, and (c) is a back view. 6(a) and 6(b) are diagrams showing a state in which a semiconductor integrated circuit chip is mounted in a conventional package, where (a) is a plan view and FIG. 6(b) is a −
FIG. 7, which shows a cross-sectional view along the line (2), is a cross-sectional view showing a conventional thin semiconductor integrated circuit after resin sealing. In these figures, reference numeral 1 denotes a thin package, and this thin pancage 1 is formed by stacking three substrates 1a with a substantially stepped cross section, and a thin die pad portion 2 is provided at the center in the width direction. , and an outer frame portion 3 formed to be thicker than the die pad portion 2 is provided on the outer side. 4 is an internal electrode connected to a semiconductor integrated circuit chip, which will be described later; 5 is an external electrode connected to an external device (not shown); this external electrode 5 is formed on the back surface of the thin package 1; It is connected to the internal electrode 4 through a through hole (not shown) provided in the internal electrode 4 . Reference numeral 7 denotes a semiconductor integrated circuit chip, and this semiconductor integrated circuit chip 7 has an electrode 7a formed on its upper surface, and is attached to the pad portion 2 of the thin package 1 via an adhesive 8. Reference numeral 9 indicates the electrode 7a of the semiconductor integrated circuit chip 7 and the thin puff cage 1.
10 is a sealing resin for sealing the semiconductor integrated circuit chip 7, the metal thin wire 9, etc.
次に、上述したように構成された従来の半導体集積回路
を製造する方法について説明する。従来の半導体集積回
路を組立てるには、先ず、薄型パフケージｌに半導体集
積回路チップ７を装着させる。この際には上述したよう
に接着材８が使用される。次いで、第６図（ａ）および
第６図（ｂ）に示すように、半導体集積回路チップ７上
の電極７ａと薄型パッケージ１の内部電極４とを金属細
線９によって接続する。これによって半導体集積回路チ
ップ７上の電極４と外部電極５とが金属細線９゜内部電
極４を介して電気的に接続されることになる。このよう
にして配線した後、第７図に示すように、薄型パッケー
ジｌにおける外枠部３によって囲まれた部分に封止樹脂
１０をポツティング等によって充填する。上述したよう
に封止樹脂１０を充填して半導体集積回路チフプ７．金
属細線９等を封止することによって半導体集積回路の製
造工程が終了されることになる。Next, a method for manufacturing the conventional semiconductor integrated circuit configured as described above will be described. To assemble a conventional semiconductor integrated circuit, first, a semiconductor integrated circuit chip 7 is mounted on a thin puff cage l. At this time, the adhesive 8 is used as described above. Next, as shown in FIGS. 6(a) and 6(b), the electrodes 7a on the semiconductor integrated circuit chip 7 and the internal electrodes 4 of the thin package 1 are connected by thin metal wires 9. As a result, the electrode 4 on the semiconductor integrated circuit chip 7 and the external electrode 5 are electrically connected via the thin metal wire 9° inner electrode 4. After wiring in this manner, as shown in FIG. 7, a portion of the thin package I surrounded by the outer frame portion 3 is filled with sealing resin 10 by potting or the like. As described above, the semiconductor integrated circuit chip 7 is filled with the sealing resin 10. By sealing the thin metal wires 9 and the like, the manufacturing process of the semiconductor integrated circuit is completed.
しかるに、従来の製造方法によって製造される半導体集
積回路においては、薄型パフケージ１が複雑な構造であ
るために高価であり、この高価な薄型パッケージ１を使
用して製造されるために製造コストが高（なるという問
題があった。However, in semiconductor integrated circuits manufactured by conventional manufacturing methods, the thin puff cage 1 is expensive due to its complicated structure, and the manufacturing cost is high because the thin puff cage 1 is manufactured using this expensive thin package 1. (There was a problem.
本発明に係る半導体集積回路の製造方法は、インナーリ
ードの先端部に外部接続用電極バンドがリードフレーム
の裏面側へ段差をもって下げて一体に形成され、かつこ
の電極パッド上に半導体集積回路チップの電極と接合さ
れる突起電極が設けられたリードフレーム上に半導体集
積回路チップを接合させ、次いで、封止樹脂を、前記電
極パッドの裏面を外部に露出させてモールド成形するも
のである。In the method of manufacturing a semiconductor integrated circuit according to the present invention, an electrode band for external connection is integrally formed at the tip of the inner lead with a step down to the back side of the lead frame, and a semiconductor integrated circuit chip is formed on the electrode pad. A semiconductor integrated circuit chip is bonded onto a lead frame provided with protruding electrodes to be bonded to electrodes, and then a sealing resin is molded with the back surfaces of the electrode pads exposed to the outside.
本発明に係る半導体集積回路の製造方法によれば、外部
接続用電極パッドに半導体集積回路チップを接合させた
状態で封止樹脂をモールド成形することによってパッケ
ージが形成されるから、パッケージを予め形成しておく
ことなく半導体集積回路を製造することができる。According to the method for manufacturing a semiconductor integrated circuit according to the present invention, the package is formed by molding the sealing resin with the semiconductor integrated circuit chip bonded to the external connection electrode pad, so the package is formed in advance. Semiconductor integrated circuits can be manufactured without any pre-existing conditions.
以下、本発明の一実施例を第１図ないし第４図によって
詳細に説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.
第１図（ａ） 、 （ｂ）は本発明に係る半導体集積回
路の製造方法に使用されるリードフレームを示す図で、
同図（ａ）は平面図、同図（ｂ）は（ａ）図中Ｉ−１線
断面図を示す。第２＠はリードフレームに半導体集積回
路チップが接合された状態を示す平面図、第３図（ａ）
、 （ｂ）は樹脂封止後のリードフＬ、 −ムを示す
図で、同図（ａ）は平面図、同図（ｂ）は（ａ）図中ｍ
−ｍ線断面図を示す。第４図（ａ）〜（ｃ）はリードフ
レームから分断された半導体集積回路を示す図で、同図
（ａ）は平面図、同図（ｂ）は側面図、同図（ｃ）は裏
面図を示す。これらの図において前記第５図ないし第７
図で説明したものと同一もしくは同等部材については同
一符号を付し、ここにおいて詳細な説明は省略する。第
１図ないし第４図において、１１は本発明の半導体集積
回路の製造方法を実施する際に使用するリードフレーム
を示し、このリードフレーム１１はフレーム枠部１２と
、このフレーム枠部１２に複数本一体に設けられ、後述
する分断工程で切断される外部リード１３と、これらの
各外部リード１３に一連に設けられ、半導体集積回路チ
ップ７に接合される電極パッド１４が先端部に設けられ
たインナーリード１５と、各インナ−リード１５を連結
させて補強するタイバー１６とから構成されている。ま
た、前記インナーリード１５の電極バッド１４は、第１
図（ｂ）に示すように、リードフレーム１１の裏面側へ
段差をもって下げて形成され、半導体集積回路７の電極
７ａに接合される突起電極１４ａが上方へ向けて突設さ
れている。このように段差をもって形成されかつ突起電
極１４ａが形成された電極パッド１４をリードフレーム
１１に一体に形成するには、先ず、レジストマスクを使
用して板材を両面側からエツチングし、リードフレーム
１１の外形形状と等しい形状をもった同一厚のリードフ
レームを形成する。そして、突起電極１４ａとなる部分
を残して電極パッド１４の上面側にハーフエツチングを
施すと共に、電極バッド１４を残してリードフレームの
裏面側にハーフエツチングを施す。このハーフエツチン
グを施すことによって、第１図（ｂ）に示すようなリー
ドフレーム１１が得られる。すなわち、電極バッド１４
が突起電極１４ａとなる部位を残して薄く形成されるこ
とによって、突起電極１４ａが相対的に高く形成される
ことになり、また、リードフレームが電極バッド１４を
残して薄く形成されるこ、とによって、電極バッド１４
が段差をもって下げて形成されることになる。FIGS. 1(a) and 1(b) are diagrams showing a lead frame used in the method for manufacturing a semiconductor integrated circuit according to the present invention,
3(a) is a plan view, and FIG. 2(b) is a sectional view taken along line I-1 in FIG. 1(a). 2nd @ is a plan view showing a state in which a semiconductor integrated circuit chip is bonded to a lead frame, FIG. 3(a)
, (b) is a diagram showing the lead frame L after resin sealing, (a) is a plan view, and (b) is a diagram showing m
-m line sectional view is shown. FIGS. 4(a) to 4(c) are diagrams showing a semiconductor integrated circuit separated from a lead frame, in which FIG. 4(a) is a plan view, FIG. 4(b) is a side view, and FIG. 4(c) is a back side. Show the diagram. In these figures, the above-mentioned figures 5 to 7
The same or equivalent members as those explained in the figures are given the same reference numerals, and detailed explanations are omitted here. 1 to 4, reference numeral 11 indicates a lead frame used when carrying out the method of manufacturing a semiconductor integrated circuit of the present invention, and this lead frame 11 has a frame portion 12 and a plurality of External leads 13 are provided integrally with the main body and are to be cut in a cutting process to be described later, and electrode pads 14 are provided in series on each of these external leads 13 and bonded to the semiconductor integrated circuit chip 7 at the tip. It is composed of inner leads 15 and tie bars 16 that connect and reinforce each inner lead 15. Further, the electrode pad 14 of the inner lead 15 is
As shown in FIG. 2B, a protruding electrode 14a is formed to be lowered with a step toward the back side of the lead frame 11 and is connected to the electrode 7a of the semiconductor integrated circuit 7, protruding upward. In order to integrally form the electrode pad 14, which is formed with steps and has the protruding electrode 14a formed thereon, on the lead frame 11, first, the plate material is etched from both sides using a resist mask. A lead frame having the same shape as the outer shape and the same thickness is formed. Then, half-etching is performed on the top surface of the electrode pad 14, leaving a portion that will become the protruding electrode 14a, and half-etching is performed on the back surface of the lead frame, leaving the electrode pad 14. By performing this half etching, a lead frame 11 as shown in FIG. 1(b) is obtained. That is, the electrode pad 14
By forming the lead frame thinly leaving a portion that will become the protruding electrode 14a, the protruding electrode 14a is formed relatively high, and the lead frame is formed thinly leaving the electrode pad 14. According to the electrode pad 14
is formed by lowering it with a step.
なお、１７はモールド成形された封止樹脂である。Note that 17 is a molded sealing resin.
次に、上述したように構成されたリードフレーム１１を
使用して本発明の半導体集積回路の製造方法を説明する
。先ず、第２図に示すように、リードフレームｌｌ上に
半導体集積回路チップ７を接合する。この半導体集積回
路チップ７の接合にあたっては、半導体集積回路チップ
７の電極７ａをリードフレーム１１の突起電極１４ａに
半田等の専電性材によって接着して行われる。次いで、
半導体集積回路チップ７が接合されたリードフレーム１
１をモールド金型（図示せず）内に装着させ、第３図（
ａ）および第３図（ｂ）に示すように、封止樹脂１７を
モールド成形してパッケージを形成する。この際、電極
バッド１４の裏面が封止樹脂１７で覆われずに外部に露
出されるようにしてモールド成形が行われる。樹脂封止
後、第４図（ａ）ないし第４図（ｃ）に示すように、リ
ードフレーム１１のタイバー１６および外部リード１３
を切断し半導体集積回路をリードフレーム１１から分断
させて半導体集積回路の製造工程が終了される。このよ
うにして形成された半導体集積回路は、パッケージの裏
面に露出された電極バッド１４を外部装置（図示せず）
に接続して作動される。また、上述した半導体集積回路
の特性検査あるいは性能測定等を実施するには、パッケ
ージの側部に突設された外部リード１３に測定装置（図
示せず）を接続して行われる。Next, a method of manufacturing a semiconductor integrated circuit according to the present invention will be described using the lead frame 11 configured as described above. First, as shown in FIG. 2, the semiconductor integrated circuit chip 7 is bonded onto the lead frame 11. The semiconductor integrated circuit chip 7 is bonded by bonding the electrodes 7a of the semiconductor integrated circuit chip 7 to the protruding electrodes 14a of the lead frame 11 using a proprietary material such as solder. Then,
Lead frame 1 to which semiconductor integrated circuit chip 7 is bonded
1 into a mold (not shown), and as shown in Fig. 3 (
As shown in a) and FIG. 3(b), the sealing resin 17 is molded to form a package. At this time, molding is performed such that the back surface of the electrode pad 14 is not covered with the sealing resin 17 and is exposed to the outside. After resin sealing, as shown in FIGS. 4(a) to 4(c), the tie bars 16 of the lead frame 11 and the external leads 13
The lead frame 11 is cut to separate the semiconductor integrated circuit from the lead frame 11, and the manufacturing process of the semiconductor integrated circuit is completed. The semiconductor integrated circuit thus formed can be connected to the electrode pad 14 exposed on the back surface of the package by an external device (not shown).
It is operated by connecting to. Further, in order to perform the characteristic inspection or performance measurement of the semiconductor integrated circuit described above, a measuring device (not shown) is connected to the external lead 13 protruding from the side of the package.
したがって、本発明に係る半導体集積回路の製造方法に
よれば、電極バッド１４に半導体集積回路チップ７を接
合させた状態で封止樹脂１７をモールド成形することに
よってパッケージが形成されるから、パッケージを予め
形成しておくことなく半導体集積回路を製造することが
できる。Therefore, according to the method for manufacturing a semiconductor integrated circuit according to the present invention, the package is formed by molding the sealing resin 17 with the semiconductor integrated circuit chip 7 bonded to the electrode pad 14. A semiconductor integrated circuit can be manufactured without being formed in advance.
以上説明したように本発明に係る半導体集積回路の製造
方法は、インナーリードの先端部に外部接続用電極パッ
ドがリードフレームの裏面側へ段差をもって下げて一体
に形成され、かつこの電極バンド上に半導体集積回路チ
ップの電極と接合される突起電極が設けられたリードフ
レーム上に半導体集積回路チップを接合させ、次いで、
封止樹脂を、前記電極バンドの裏面を外部に露出させて
モールド成形するため、外部接続用電極パッドに半導体
集積回路チップを接合させた状態で封止樹脂をモールド
成形することによってパッケージが形成されるから、パ
ッケージを予め形成しておくことなく半導体集積回路を
製造することができる。As explained above, in the method for manufacturing a semiconductor integrated circuit according to the present invention, an electrode pad for external connection is integrally formed at the tip of the inner lead with a step down to the back side of the lead frame, and on this electrode band. The semiconductor integrated circuit chip is bonded onto a lead frame provided with protruding electrodes to be bonded to the electrodes of the semiconductor integrated circuit chip, and then,
Since the sealing resin is molded with the back side of the electrode band exposed to the outside, the package is formed by molding the sealing resin with the semiconductor integrated circuit chip bonded to the external connection electrode pad. Therefore, semiconductor integrated circuits can be manufactured without forming a package in advance.
したがって、従来の高価な薄型パッケージを使用するこ
となく半導体集積回路を製造することができ、しかも、
ワイヤボンディング等が不要になり製造工程が簡略化さ
れるから、製造コストを低く抑えることができる。また
、外部接続用電極パッド上に半導体集積回路チップが直
接的に接合されるから、半導体集積回路の薄型化を図る
こともできる。さらにまた、リードフレームから半導体
集積回路を分断する際に、外部リードをパッケージの側
部に突出させた状態で切断することによって、この外部
リードを測定端子として使用することができるから、薄
型半導体集積回路を従来の樹脂封止パッケージ、例えば
、ＳＯＰ （スモール アウトライン パッケージ）型
半導体装置等と同様に取り扱うことができるという効果
もある。Therefore, semiconductor integrated circuits can be manufactured without using conventional expensive thin packages, and
Since wire bonding and the like are not required and the manufacturing process is simplified, manufacturing costs can be kept low. Furthermore, since the semiconductor integrated circuit chip is directly bonded onto the external connection electrode pad, it is possible to reduce the thickness of the semiconductor integrated circuit. Furthermore, when separating the semiconductor integrated circuit from the lead frame, by cutting the external leads with them protruding from the side of the package, the external leads can be used as measurement terminals. Another advantage is that the circuit can be handled in the same way as a conventional resin-sealed package, such as an SOP (Small Outline Package) type semiconductor device.
第１図（ａ） 、 （ｂ）は本発明に係る半導体集積回
路の製造方法に使用されるリードフレームを示す図で、
同図（ａ）は平面図、同図（ｂ）は（ａ）図中ｍ−ｍ線
断面図を示す。第２図はリードフレームに半導体集積回
路チップが接合された状態を示す平面図、第３図（ａ）
、 （ｂ）は樹脂封止後のリードフレームを示す図で
、同図（ａ）は平面図、同図（ｂ）は（ａ）図中ｍ−ｍ
線断面図を示す、第４図（ａ）〜（ｃ）はリードフレー
ムから分断された半導体集積回路を示す図で、同図（ａ
）は平面図、同図（ｂ）は側面図、同図（ｃ）は裏面図
を示す。第５図（ａ）〜（ｃ）は従来の薄型半導体集積
回路用パッケージを示す図で、同図（ａ）は平面図、同
図（ｂ）は（ａ）図中Ｖ−Ｖ線断面図、同図（ｃ）は裏
面図を示す。第６図（ａ） 、 （ｂ）は従来のパッケ
ージに半導体集積回路チップが装着された状態を示す図
で、同図（ａ）は平面図、同図（ｂ）は（ａ）図中ＶＴ
−ＶＩ線断面図を示す。第７図は樹脂封止後の従来の薄
型半導体集積回路を示す断面図である。
７・・・・半導体集積回路チップ、１１・・・・リード
フレーム、１３・・・・外部リード、１４・・・・電極
パッド、１４ａ・・・・突起電極、１５・・・・インナ
ーリード、１７・・・・封止樹脂。FIGS. 1(a) and 1(b) are diagrams showing a lead frame used in the method for manufacturing a semiconductor integrated circuit according to the present invention,
3(a) is a plan view, and FIG. 2(b) is a sectional view taken along the line mm in FIG. 1(a). Figure 2 is a plan view showing a semiconductor integrated circuit chip bonded to a lead frame, Figure 3 (a)
, (b) is a diagram showing the lead frame after resin sealing, where (a) is a plan view, and (b) is a line taken along m-m in the figure (a).
4(a) to 4(c), which show line cross-sectional views, are diagrams showing a semiconductor integrated circuit separated from a lead frame.
) shows a plan view, (b) a side view, and (c) a back view. FIGS. 5(a) to 5(c) are diagrams showing a conventional thin semiconductor integrated circuit package, in which FIG. 5(a) is a plan view and FIG. 5(b) is a sectional view taken along the line V-V in FIG. 5(a). , the same figure (c) shows a back view. 6(a) and 6(b) are diagrams showing a state in which a semiconductor integrated circuit chip is mounted in a conventional package, in which FIG. 6(a) is a plan view and FIG. 6(b) is a VT
-VI line sectional view is shown. FIG. 7 is a sectional view showing a conventional thin semiconductor integrated circuit after resin sealing. 7... Semiconductor integrated circuit chip, 11... Lead frame, 13... External lead, 14... Electrode pad, 14a... Projection electrode, 15... Inner lead, 17...Sealing resin.
Claims (1)
ドフレームの裏面側へ段差をもって下げて一体に形成さ
れ、かつこの電極パッド上に半導体集積回路チップの電
極と接合される突起電極が設けられたリードフレーム上
に半導体集積回路チップを接合させ、次いで、封止樹脂
を、前記電極パッドの裏面を外部に露出させてモールド
成形することを特徴とする半導体集積回路の製造方法。A lead in which an electrode pad for external connection is integrally formed at the tip of the inner lead with a step lowered to the back side of the lead frame, and a protruding electrode that is connected to the electrode of the semiconductor integrated circuit chip is provided on the electrode pad. 1. A method of manufacturing a semiconductor integrated circuit, comprising: bonding a semiconductor integrated circuit chip onto a frame, and then molding a sealing resin with the back surfaces of the electrode pads exposed to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12331989A JPH02303056A (en) | 1989-05-17 | 1989-05-17 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12331989A JPH02303056A (en) | 1989-05-17 | 1989-05-17 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02303056A true JPH02303056A (en) | 1990-12-17 |
Family
ID=14857614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12331989A Pending JPH02303056A (en) | 1989-05-17 | 1989-05-17 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02303056A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19745648A1 (en) * | 1997-10-15 | 1998-11-26 | Siemens Ag | Carrier element for contactless semiconductor chip-card |
| DE10147376A1 (en) * | 2001-09-26 | 2003-04-24 | Infineon Technologies Ag | Electronic component used in electronic devices comprises a plastic housing and a metallic support arranged in the housing with a semiconductor chip arranged on the metallic support using Flip-Chip technology |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63239852A (en) * | 1987-12-03 | 1988-10-05 | Mitsui Haitetsuku:Kk | Semiconductor device |
| JPS63258050A (en) * | 1987-04-15 | 1988-10-25 | Mitsubishi Electric Corp | Semiconductor device |
| JPS63310150A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Cable Ltd | Lead frame for plastic-sealed ic and package for plastic-sealed ic |
-
1989
- 1989-05-17 JP JP12331989A patent/JPH02303056A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63258050A (en) * | 1987-04-15 | 1988-10-25 | Mitsubishi Electric Corp | Semiconductor device |
| JPS63310150A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Cable Ltd | Lead frame for plastic-sealed ic and package for plastic-sealed ic |
| JPS63239852A (en) * | 1987-12-03 | 1988-10-05 | Mitsui Haitetsuku:Kk | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19745648A1 (en) * | 1997-10-15 | 1998-11-26 | Siemens Ag | Carrier element for contactless semiconductor chip-card |
| US6719205B1 (en) | 1997-10-15 | 2004-04-13 | Infineon Technologies Ag | Carrier element for a semiconductor chip for incorporation into smart cards |
| DE10147376A1 (en) * | 2001-09-26 | 2003-04-24 | Infineon Technologies Ag | Electronic component used in electronic devices comprises a plastic housing and a metallic support arranged in the housing with a semiconductor chip arranged on the metallic support using Flip-Chip technology |
| DE10147376B4 (en) * | 2001-09-26 | 2009-01-15 | Infineon Technologies Ag | Electronic component and leadframe and method for producing the same |
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