JPH0621305A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0621305A JPH0621305A JP17242192A JP17242192A JPH0621305A JP H0621305 A JPH0621305 A JP H0621305A JP 17242192 A JP17242192 A JP 17242192A JP 17242192 A JP17242192 A JP 17242192A JP H0621305 A JPH0621305 A JP H0621305A
- Authority
- JP
- Japan
- Prior art keywords
- internal terminals
- semiconductor device
- hollows
- semiconductor chip
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止形半導体装置
を機械的衝撃等に耐えうるようにリードフレームの内部
端子の構造に改良を加えた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a resin-sealed semiconductor device is improved in structure of internal terminals of a lead frame so as to withstand mechanical shock and the like.
【０００２】[0002]
【従来の技術】近年、半導体装置において半導体ウエハ
表面に写真彫刻技術を使用し、ウエハ表面上に適宜不純
物の拡散又、層間膜の形成、電極蒸着、保護膜等の工程
技術を用いて集積回路を形成してウエハを製造してい
る。ウエハ内に形成された半導体素子は、次工程である
組立工程で分離し、リードフレーム上のダイパッドに接
着して半導体チップ上のＡｌ電極と内部端子を金線で電
気的接合を行い樹脂封止工程を経て所定の半導体装置が
完成する。ここで半導体装置に使用されているパッケー
ジの種類は数多くあるが中でもエポキシ樹脂で封止され
るパッケージは低コストの民生用として大量に使用され
ている。以下、従来の半導体装置について説明する。2. Description of the Related Art Recently, in a semiconductor device, a photolithography technique has been used on the surface of a semiconductor wafer to appropriately diffuse impurities on the surface of the wafer and process technology such as formation of an interlayer film, electrode deposition, and a protective film. To form a wafer. The semiconductor element formed on the wafer is separated in the assembly process, which is the next step, and adhered to the die pad on the lead frame to electrically connect the Al electrode on the semiconductor chip and the internal terminal with a gold wire for resin sealing. A predetermined semiconductor device is completed through the steps. Here, there are many types of packages used for semiconductor devices, but among them, a large number of packages sealed with epoxy resin are used for low-cost consumer use. The conventional semiconductor device will be described below.
【０００３】図３は上記のような半導体装置を示すもの
であり、半導体チップ１はダイパッド２に固定するもの
で半導体チップ１とダイパッド２は接着材もしくは銀ペ
ーストによって接着されている。また、図４は図３で示
した半導体装置の断面構造を示すものである。以上のよ
うに構成された半導体装置について以下その動作につい
て説明する。まず半導体チップ１に対する複数の内部端
子３ａ，３ｂ……と外部端子４ａ，４ｂ……は対応し連
結しているものでダイパッド２と同一平面上に設置され
て、このダイパッド２の各辺に沿って等間隔で外方向に
向け配置されている。そして、半導体チップ１上の回路
端子に対して設置したＡｌ電極（図示せず）をそれぞれ
金線５と順次接続しこの金線５を内部端子３ａ，３ｂ…
…と対応して順次接着する。このように形成したものを
外部端子をエポキシ樹脂６等の合成樹脂でモールディン
グする。すなわち、エポキシ樹脂６で封止された樹脂封
止金型で半導体装置７が構成されるものである。このよ
うに構成される樹脂封止型パッケージの半導体装置７は
近年、機能の増大等にもかかわらずパッケージサイズが
小型化、薄型化の傾向が著しく要求されている。FIG. 3 shows such a semiconductor device as described above. The semiconductor chip 1 is fixed to the die pad 2, and the semiconductor chip 1 and the die pad 2 are adhered by an adhesive material or a silver paste. Further, FIG. 4 shows a sectional structure of the semiconductor device shown in FIG. The operation of the semiconductor device configured as described above will be described below. First, a plurality of internal terminals 3a, 3b ... And external terminals 4a, 4b ... corresponding to the semiconductor chip 1 are connected correspondingly and are installed on the same plane as the die pad 2 and along each side of the die pad 2. Are evenly spaced outwards. Then, Al electrodes (not shown) installed on the circuit terminals on the semiconductor chip 1 are sequentially connected to the gold wires 5, and the gold wires 5 are connected to the internal terminals 3a, 3b ...
Corresponding to ... and adhere sequentially. The external terminal thus formed is molded with a synthetic resin such as epoxy resin 6. That is, the semiconductor device 7 is configured by a resin-sealing die sealed with the epoxy resin 6. In recent years, the resin-encapsulated package semiconductor device 7 having such a structure has been required to have a smaller package size and a thinner package despite the increase in functions.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、小型化、薄型化していく樹脂封止型パッケ
ージの半導体装置において半導体チップサイズがパッケ
ージサイズのほぼ７０％を占める半導体装置（メモリ
ー）になると内部端子の占める割合が小さくなり、内部
端子の機械的強度等が低下して、半導体装置の信頼性も
低下するという問題を有してくると考えられる。そこで
本発明は、上記従来の課題を解決するもので、小型化、
薄型化する半導体装置において内部端子とエポキシ樹脂
との密着性を向上させ、高信頼性の半導体装置を提供す
ることを目的とする。However, in the above-mentioned conventional configuration, in a semiconductor device of a resin-encapsulated package which is becoming smaller and thinner, the semiconductor chip size occupies almost 70% of the package size (memory). In that case, it is considered that there is a problem that the ratio of the internal terminals is reduced, the mechanical strength of the internal terminals is reduced, and the reliability of the semiconductor device is also reduced. Therefore, the present invention is to solve the above-mentioned conventional problems, downsizing,
An object of the present invention is to provide a highly reliable semiconductor device by improving the adhesion between internal terminals and an epoxy resin in a thin semiconductor device.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に本発明の半導体装置は、リードフレームの内部端子の
表裏面に複数の窪みを形成する構成を有している。In order to solve the above problems, the semiconductor device of the present invention has a structure in which a plurality of depressions are formed on the front and back surfaces of the internal terminals of the lead frame.
【０００６】[0006]
【作用】この構成である内部端子に複数の窪みを形成す
ることにより、半導体装置に使用しているエポキシ樹脂
と複数の窪みがパッケージ形成時に入り込むことによ
り、内部端子とエポキシ樹脂の密着を更に向上させ、高
信頼性の半導体装置を実現することが可能になる。By forming a plurality of dents in the internal terminal having this structure, the epoxy resin used in the semiconductor device and the plurality of dents enter during package formation, further improving the adhesion between the internal terminal and the epoxy resin. As a result, a highly reliable semiconductor device can be realized.
【０００７】[0007]
【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。図１は、半導体リードフレームを示
すもので製造される半導体装置７を囲む充分の大きさの
正方形の枠体１０が連続して一体的に構成されている。
この半導体リードフレーム９は後、切断する部材と共に
例えば、銅等の薄板を打ち抜き等の手段で形成したもの
で枠体１０の対向する一対の辺１０ａ，１０ｂより中心
部に向け支持腕１１を突出形成し、この支持腕１１で四
角形状のダイパッド２を支持する。このダイパッド２の
各辺に沿って複数の内部端子３の先端が等間隔で配置さ
れるものでこの各内部端子３は放射状に延び、枠体１０
にそれぞれ直角に連続される。これら内部端子３は、そ
の中程のタイバー１２で保持されている。このように半
導体リードフレーム９で一体的に形成される内部端子３
は、図２の断面に示すように複数の内部端子３の表裏面
を凹部である窪み８ａ，８ｂ……を散在形状にする。例
えば、窪みはハーフエッチ等の技術によって凹部を形成
し、その残余の部分が一つの平面を形成するようにす
る。そして、半導体チップ１をダイボンディングした
後、金線５により半導体チップ１上のＡｌ電極（図示せ
ず）と内部端子３をワイヤボンディングする。しかし、
内部端子３で金線５を接着する部分においては窪みは形
成しない。次に図中の鎖線で示す範囲内を合成樹脂でモ
ールドし、パッケージを形成する。このタイバー１２内
部に沿ってその囲まれる範囲を切り離して半導体装置７
を形成する。このように構成される半導体装置７におい
て、樹脂封止された後に内部端子３はエポキシ樹脂６と
接合する面積が少ないため機械的強度を保持する必要が
あり、窪みを形成することにより、エポキシ樹脂と内部
端子の密着性が向上し、機械的強度が増し、信頼性が向
上する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor lead frame, and a square frame body 10 of a sufficient size surrounding a semiconductor device 7 to be manufactured is continuously and integrally configured.
The semiconductor lead frame 9 is formed by punching a thin plate of copper or the like together with a member to be cut, and the supporting arm 11 is projected toward the center from a pair of opposite sides 10a and 10b of the frame body 10. The square die pad 2 is supported by the support arm 11. The tips of a plurality of internal terminals 3 are arranged at equal intervals along each side of the die pad 2. The internal terminals 3 extend radially and the frame 10
Are continued at right angles. These internal terminals 3 are held by the tie bar 12 in the middle thereof. The internal terminal 3 integrally formed with the semiconductor lead frame 9 in this way
As shown in the cross-section of FIG. 2, the front and back surfaces of the plurality of internal terminals 3 are formed with the recesses 8a, 8b ... For example, the depression is formed by a technique such as half etching so that the remaining portion forms one plane. Then, after the semiconductor chip 1 is die-bonded, an Al electrode (not shown) on the semiconductor chip 1 and the internal terminal 3 are wire-bonded by the gold wire 5. But,
No recess is formed in the portion of the internal terminal 3 where the gold wire 5 is bonded. Next, the area shown by the chain line in the figure is molded with a synthetic resin to form a package. The semiconductor device 7 is separated along the inside of the tie bar 12 by separating the enclosed area.
To form. In the semiconductor device 7 having such a structure, since the internal terminal 3 has a small area to be bonded to the epoxy resin 6 after being resin-sealed, it is necessary to maintain mechanical strength. And the internal terminal adhesion is improved, the mechanical strength is increased, and the reliability is improved.
【０００８】なお、実施例において窪みは半円状の凹形
状を使用したがこの凹部は実質的に窪みになるものであ
ればよく内部端子に窪みを用いることで密着性が向上さ
れる機能を備えたものであればよい。In the embodiment, the recess has a semi-circular recessed shape, but it is sufficient that the recess be substantially a recess, and the function of improving the adhesion by using the recess for the internal terminal is provided. Anything can be used as long as it is provided.
【０００９】[0009]
【発明の効果】以上のように本発明は、リードフレーム
の内部端子の表裏面に窪みを設けることにより、エポキ
シ樹脂と内部端子との密着性を向上させ、機械的強度が
増し、高信頼性の半導体装置を実現することができるも
のである。As described above, the present invention improves the adhesion between the epoxy resin and the internal terminals by providing the depressions on the front and back surfaces of the internal terminals of the lead frame, increases the mechanical strength, and has high reliability. The semiconductor device can be realized.
【図１】本発明の一実施例にかかわる半導体装置を構成
するリードフレーム等の部材を示す平面図FIG. 1 is a plan view showing members such as a lead frame constituting a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例を示す半導体装置の断面図FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the present invention.
【図３】従来の半導体装置の斜視図FIG. 3 is a perspective view of a conventional semiconductor device.
【図４】従来の半導体装置の断面図FIG. 4 is a sectional view of a conventional semiconductor device.
１ 半導体チップ ２ ダイパッド ３ 内部端子 ４ 外部端子 ５ 金線 ６ エポキシ樹脂 ７ 半導体装置 ８ 窪み ９ 半導体リードフレーム １０ 枠体 １１ 支持腕 １２ タイバー 1 Semiconductor Chip 2 Die Pad 3 Internal Terminal 4 External Terminal 5 Gold Wire 6 Epoxy Resin 7 Semiconductor Device 8 Dimple 9 Semiconductor Lead Frame 10 Frame 11 Support Arm 12 Tie Bar
Claims (1)
のＡｌ電極と金線で電気的接合した複数の窪みを有した
リードフレームの内部端子とを有し、前記複数の内部端
子が樹脂で一体的にモールドされたことを特徴とする半
導体装置。1. A semiconductor chip and an internal terminal of a lead frame having a plurality of recesses electrically connected to a plurality of Al electrodes of the semiconductor chip with a gold wire, wherein the plurality of internal terminals are made of resin. A semiconductor device characterized by being mechanically molded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17242192A JPH0621305A (en) | 1992-06-30 | 1992-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17242192A JPH0621305A (en) | 1992-06-30 | 1992-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0621305A true JPH0621305A (en) | 1994-01-28 |
Family
ID=15941659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17242192A Pending JPH0621305A (en) | 1992-06-30 | 1992-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621305A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996029778A1 (en) * | 1995-03-19 | 1996-09-26 | Hugo Lucca | Method and device for electrically controlling low-resistance loads |
| US5973388A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe |
| US6197615B1 (en) * | 1997-04-04 | 2001-03-06 | Samsung Electronics Co., Ltd. | Method of producing lead frame having uneven surfaces |
| US6252306B1 (en) | 1998-05-12 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Method of producing semiconductor device and configuration thereof, and lead frame used in said method |
| US6483178B1 (en) * | 2000-07-14 | 2002-11-19 | Siliconware Precision Industries Co., Ltd. | Semiconductor device package structure |
-
1992
- 1992-06-30 JP JP17242192A patent/JPH0621305A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996029778A1 (en) * | 1995-03-19 | 1996-09-26 | Hugo Lucca | Method and device for electrically controlling low-resistance loads |
| US6197615B1 (en) * | 1997-04-04 | 2001-03-06 | Samsung Electronics Co., Ltd. | Method of producing lead frame having uneven surfaces |
| US5973388A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe |
| US6252306B1 (en) | 1998-05-12 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Method of producing semiconductor device and configuration thereof, and lead frame used in said method |
| US6483178B1 (en) * | 2000-07-14 | 2002-11-19 | Siliconware Precision Industries Co., Ltd. | Semiconductor device package structure |
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