JPH09129798A - Electronic component and fabrication thereof - Google Patents
Electronic component and fabrication thereofInfo
- Publication number
- JPH09129798A JPH09129798A JP28043395A JP28043395A JPH09129798A JP H09129798 A JPH09129798 A JP H09129798A JP 28043395 A JP28043395 A JP 28043395A JP 28043395 A JP28043395 A JP 28043395A JP H09129798 A JPH09129798 A JP H09129798A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- lead
- component chip
- leads
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はワイヤボンディング
をしないでリードの先端を電子部品チップのバンプ電極
に直接接続する面実装に適した電子部品およびその製法
に関する。さらに詳しくは、バンプ電極と接続するリー
ドが複数個ある場合にも、リードとバンプ電極との接続
を確実にして信頼性を向上させた電子部品およびその製
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component suitable for surface mounting in which a tip of a lead is directly connected to a bump electrode of an electronic component chip without wire bonding, and a manufacturing method thereof. More specifically, the present invention relates to an electronic component having a reliable connection between the lead and the bump electrode and improved reliability even when there are a plurality of leads connected to the bump electrode, and a method for manufacturing the same.
【０００２】ここにバンプ電極とは、他のリードと接続
される電極でリードが直接接続され得るように突起状に
形成された電極を意味する。Here, the bump electrode means an electrode formed in a projection shape so that the lead can be directly connected with an electrode connected to another lead.
【０００３】[0003]
【従来の技術】ダイオードなどの半導体装置で、ワイヤ
ボンディングをしないで直接リードの先端をバンプ電極
などに電気的に接続し、パッケージ外部に導出されるリ
ードを実質的に同一面に形成する、いわゆるワイボンレ
ス面実装型半導体装置は、たとえばつぎのように製造さ
れる。2. Description of the Related Art In a semiconductor device such as a diode, the tip of the lead is directly electrically connected to a bump electrode or the like without wire bonding, and the lead led out to the outside of the package is formed on substantially the same surface. The Wybonless surface mount semiconductor device is manufactured, for example, as follows.
【０００４】たとえば３端子型ダイオードは、図４また
は図５（ａ）に断面図が示されるように、ダイパッド部
１ａがリードフレームの面Ａと同じか、それより僅かに
高く形成されたリードフレームのダイパッド部１ａに半
導体チップ４をダイボンディングし、ついでバンプ電極
４ａと接続するリード端部２ａをもちあげるフォーミン
グ加工をし、横ずらしをしてハンダづけなどにより電気
的に接続し、そののちエポキシ樹脂などによりモールド
してパッケージ７を形成し、各リード１、２をリードフ
レームから切り離して半導体装置を形成している。For example, in a three-terminal type diode, as shown in the sectional view of FIG. 4 or FIG. 5 (a), the lead frame in which the die pad portion 1a is formed to be the same as the surface A of the lead frame or slightly higher than it. The semiconductor chip 4 is die-bonded to the die pad portion 1a of the above, then the lead end portion 2a connected to the bump electrode 4a is subjected to a forming process, and the lead end portion 2a is laterally shifted and electrically connected by soldering or the like. A package 7 is formed by molding with a mold such as the above, and the leads 1 and 2 are separated from the lead frame to form a semiconductor device.
【０００５】図４に示される構造の半導体装置では、各
リード１、２を切り離したのち、図４に示されるように
リード１、２のフォーミング加工をして面実装をするこ
とができるようにされたり、基板のスルーホールに各リ
ードを差し込んでハンダづけできるように延ばすなどの
種々のフォーミング加工が施される。なお、図４〜５に
おいて、５は半導体チップをダイボンディングするプリ
フォーム材、６はバンプ電極４ａとリード端部２ａとを
電気的に接続するハンダである。In the semiconductor device having the structure shown in FIG. 4, after separating the leads 1 and 2 from each other, the leads 1 and 2 are formed as shown in FIG. 4 so that they can be surface-mounted. Or various forming processes such as inserting the leads into the through holes of the substrate and extending the leads so that they can be soldered. 4 to 5, 5 is a preform material for die-bonding a semiconductor chip, and 6 is a solder for electrically connecting the bump electrode 4a and the lead end portion 2a.
【０００６】図４または図５（ａ）に示される構造の半
導体装置は、樹脂の外部に導出されるリード１、２の先
端ががすべてパッケージ７の底面と実質的に同一面とな
り、このままプリント基板などに面実装をすることがで
きる。なお、図５（ａ）に示される構造の半導体装置で
は、リードフレームの状態でダイパッド部１ａが少しも
ちあげられているが、ダイパッド部１ａの下側もパッケ
ージ７用の樹脂で被覆して水分の侵入を防止するもの
で、この高さは０．１〜０．２ｍｍ程度である。そのた
め、リードフレームをロール状に巻いてもつぶれること
がなく、リードフレームの形成の際に同時にフォーミン
グされる。In the semiconductor device having the structure shown in FIG. 4 or FIG. 5A, the tips of the leads 1 and 2 led out of the resin are substantially flush with the bottom surface of the package 7, and printing is performed as it is. It can be surface-mounted on a board or the like. In the semiconductor device having the structure shown in FIG. 5A, the die pad portion 1a is slightly lifted up in the state of the lead frame, but the lower side of the die pad portion 1a is also covered with the resin for the package 7 to prevent moisture. It prevents intrusion, and this height is about 0.1 to 0.2 mm. Therefore, even if the lead frame is wound in a roll shape, the lead frame is not crushed and is simultaneously formed when the lead frame is formed.
【０００７】一方、バンプ電極４ａと接続される側のリ
ードは、さらに半導体チップの厚さとバンプ電極の高さ
分高くもちあげられるとともに、半導体チップ側に横ず
らしをして重ねるため、ダイボンディングをしたのちに
さらに半導体チップの厚さ分以上の高さだけもちあげら
れ、そののち押し下げるフォーミング加工がなされてい
る。On the other hand, the lead on the side connected to the bump electrode 4a is further lifted by the thickness of the semiconductor chip and the height of the bump electrode, and is die-bonded so as to be stacked side by side on the semiconductor chip side. Later, the semiconductor chip is lifted up by a height equal to or more than the thickness of the semiconductor chip, and then the forming process is performed by pushing it down.
【０００８】[0008]
【発明が解決しようとする課題】半導体チップ４の一面
に形成されるバンプ電極が複数個存在する電子部品チッ
プの場合、前述の方法で製造すると、もちあげるリード
の数も複数個となる。そのため、図５（ｂ）に示される
ように、もちあげられるリード端部２ａ、３ａの電子部
品チップ（半導体チップ）４に対する高さがばらつくと
いう問題がある。このような高さのばらつきが発生する
と、バンプ電極と接触しないリード端部３ａが発生し、
信頼性が低下するという問題がある。In the case of an electronic component chip having a plurality of bump electrodes formed on one surface of the semiconductor chip 4, when it is manufactured by the above method, the number of leads to be lifted becomes plural. Therefore, as shown in FIG. 5B, there is a problem that the height of the lifted lead ends 2a and 3a with respect to the electronic component chip (semiconductor chip) 4 varies. When such height variations occur, lead end portions 3a that do not contact the bump electrodes are generated,
There is a problem that reliability is reduced.
【０００９】本発明はこのような問題を解決し、ワイボ
ンレスで面実装に適した電子部品であっても、バンプ電
極とリード端部との電気的接続の信頼性を向上させた電
子部品およびその製法を提供することを目的とする。The present invention solves such a problem, and even an electronic component which is suitable for surface mounting without a wipe-on, has improved reliability of electrical connection between the bump electrode and the end of the lead, and the electronic component. The purpose is to provide a manufacturing method.
【００１０】[0010]
【課題を解決するための手段】本発明による電子部品
は、一面に複数個のバンプ電極を有する電子部品チップ
と、該複数個のバンプ電極および前記電子部品チップの
他面にそれぞれ電気的に接続されるリードと、前記電子
部品チップの周囲を被覆するパッケージとからなり、前
記電子部品チップの他面と接続される前記リードの端部
において大きなフォーミング加工が施されている。An electronic component according to the present invention is an electronic component chip having a plurality of bump electrodes on one surface, and electrically connected to the plurality of bump electrodes and the other surface of the electronic component chip, respectively. And a package that covers the periphery of the electronic component chip, and a large forming process is performed on an end portion of the lead that is connected to the other surface of the electronic component chip.
【００１１】前記バンプ電極および前記他面にそれぞれ
接続され前記パッケージから外部に導出される前記リー
ドの先端部が前記パッケージの底面と実質的に同一面に
形成されている場合に、リードの先端部において大きな
フォーミング加工が施されやすいため、とくに効果が大
きい。When the tip of the lead, which is connected to the bump electrode and the other surface and is led out to the outside of the package, is formed on the same plane as the bottom surface of the package, the tip of the lead is formed. In particular, the large forming process is easily performed, so that the effect is particularly large.
【００１２】ここに実質的に同一面とは、モールドパッ
ケージから導出される各リードの先端が該パッケージの
底面とほぼ平行な面に形成され、さらなる特別なリード
フォーミングをしなくても容易にプリンと基板などに面
実装できる程度であることを意味する。Here, "substantially the same surface" means that the tips of the leads led out from the mold package are formed in a surface substantially parallel to the bottom surface of the package, and the printing can be easily performed without further special lead forming. It means that it can be surface-mounted on a board.
【００１３】本発明の電子部品の製法は、（ａ）リード
フレームにおける電子部品チップをボンディングするダ
イパッドを該リードフレームの面より押し下げ、（ｂ）
前記ダイパッドに電子部品チップをボンディングし、
（ｃ）前記リードフレームのダイパッド部と前記電子部
品チップのバンプ電極と接続されるリードとを相対的に
横方向にずらせて位置合わせをし、（ｄ）前記電子部品
チップの各電極と前記リードの各々とを電気的に接続し
たのちパッケージ用樹脂でモールドすることを特徴とす
る。According to the method of manufacturing an electronic component of the present invention, (a) the die pad for bonding the electronic component chip in the lead frame is pushed down from the surface of the lead frame, (b)
Bonding an electronic component chip to the die pad,
(C) The die pad portion of the lead frame and the lead connected to the bump electrode of the electronic component chip are relatively laterally displaced and aligned, and (d) each electrode of the electronic component chip and the lead. Each of them is electrically connected and then molded with a resin for packaging.
【００１４】[0014]
【発明の実施の形態】つぎに、本発明の電子部品および
その製法について図面を参照しながら説明をする。BEST MODE FOR CARRYING OUT THE INVENTION Next, an electronic component of the present invention and a manufacturing method thereof will be described with reference to the drawings.
【００１５】図１（ａ）は、本発明の電子部品の一実施
形態である３端子型ダイオードの断面説明図、図１
（ｂ）および図１（ｃ）はそれぞれ図１（ａ）のＢ−Ｂ
線断面説明図および底面図、図２は他の構造の３端子型
ダイオードの断面説明図、図３は図１の３端子型ダイオ
ードの製造工程を説明する図である。FIG. 1A is a sectional explanatory view of a three-terminal type diode which is an embodiment of an electronic component of the present invention, and FIG.
(B) and FIG. 1 (c) are respectively BB of FIG. 1 (a).
2 is a cross-sectional explanatory view and a bottom view, FIG. 2 is a cross-sectional explanatory view of a three-terminal diode having another structure, and FIG. 3 is a diagram illustrating a manufacturing process of the three-terminal diode of FIG.
【００１６】図１〜２に示される本実施形態の３端子型
ダイオードは、電子部品チップである半導体チップ４が
２個の直列ダイオードを内蔵し、その両端の端子が半導
体チップ４の一面である表面にバンプ電極４ａ、４ｂで
２個形成され、２個のダイオードの接続点の端子が半導
体チップ４の他面である裏面に形成され、表面に２個、
裏面に１個の３端子ダイオードが形成されている。この
２個のバンプ電極４ａ、４ｂにそれぞれリードフレーム
の各リード２、３の端部２ａ、３ａが電気的に接続さ
れ、半導体チップ４の他面側はリードフレームのダイパ
ッド１ａと電気的に接続されている。In the three-terminal type diode of this embodiment shown in FIGS. 1 and 2, a semiconductor chip 4 which is an electronic component chip contains two series diodes, and terminals at both ends are one surface of the semiconductor chip 4. Two bump electrodes 4a and 4b are formed on the front surface, terminals at the connection points of the two diodes are formed on the back surface which is the other surface of the semiconductor chip 4, and two are formed on the front surface.
One 3-terminal diode is formed on the back surface. The ends 2a and 3a of the leads 2 and 3 of the lead frame are electrically connected to the two bump electrodes 4a and 4b, respectively, and the other surface side of the semiconductor chip 4 is electrically connected to the die pad 1a of the lead frame. Has been done.
【００１７】すなわち、半導体チップ４の各電極端子と
リードとの間を金線などのワイヤボンディングで連結し
ない、いわゆるワイボンレスタイプにおいて、本発明で
は半導体チップ４の１端子側の面である他面側と接続さ
れるリードの端部（ダイパッド１ａ）が大きくフォーミ
ング加工されていることに特徴がある。なお、各符号は
図４〜５と同じ部分を示し、その説明を省略する。That is, in the so-called Wybonless type in which each electrode terminal of the semiconductor chip 4 and the lead are not connected by wire bonding such as a gold wire, in the present invention, the other surface which is the one-terminal side of the semiconductor chip 4 is used. It is characterized in that the ends (die pad 1a) of the leads connected to the side are largely formed. The reference numerals indicate the same parts as those in FIGS. 4 to 5, and the description thereof will be omitted.
【００１８】この種のワイボンレスタイプの電子部品で
は、電子部品チップの電極端子（バンプ電極）との電気
的接続のため、およびリードを横ずらしして重ねるた
め、電子部品チップの厚さ分の２倍程度リードフレーム
の一方のリードまたはそのリードと接続される仲介リー
ドをもちあげ、そののち上下戻しをする大きなフォーミ
ング加工をしなければならない。In this type of Wybonless type electronic component, the thickness of the electronic component chip is equal to the thickness of the electronic component chip because it is electrically connected to the electrode terminals (bump electrodes) of the electronic component chip and the leads are laid side by side. It is necessary to lift one lead of the lead frame or the intermediary lead connected to the lead about twice, and then to perform a large forming process in which the lead is vertically returned.
【００１９】本発明では電子部品チップと接続のため、
上下に移動させるリードの加工を大きなフォーミング加
工とよび、この大きなフォーミング加工を施すリードを
電子部品チップの１端子側と接続するリード側にしたも
のである。このようにすることにより、複数のリードを
同時に大きくフォーミング加工をする必要がないため、
リード間で高さのばらつきが生じることがなく、電子部
品チップの電極端子とリードとの接続不良などが発生せ
ず信頼性の高い電子部品が得られる。In the present invention, since the electronic component chip is connected,
The processing of the lead that is moved up and down is called large forming processing, and the lead to which this large forming processing is performed is the lead side that is connected to one terminal side of the electronic component chip. By doing this, it is not necessary to form a large number of leads at the same time,
There is no variation in height between the leads, a defective connection between the electrode terminals of the electronic component chip and the leads does not occur, and a highly reliable electronic component can be obtained.
【００２０】図１に示される例では、多端子側のリード
２、３の端部２ａ、３ａにも若干の段差が設けられてい
るが、これは半導体チップ４のバンプ電極４ａ、４ｂと
ボンディングされるリード端部２ａ、３ａを完全にパッ
ケージ用樹脂で被覆するためのもので、電子部品チップ
の両面にリードを配置するための加工ではない。そのた
め、段差の高さも０．１〜０．２ｍｍ程度で、リードフ
レームの製造時に同時に形成され、高さがばらつくこと
無く一定に形成される。一方、１端子側のリードはこの
高さと、電子部品チップの厚さおよびバンプ電極の高さ
と、さらにずらせ重ねのためにもちあげられる高さの合
計分の大きなフォーミング加工が施される。In the example shown in FIG. 1, the steps 2a and 3a of the leads 2 and 3 on the multi-terminal side are also provided with slight steps, which are bonded to the bump electrodes 4a and 4b of the semiconductor chip 4. This is for completely covering the lead end portions 2a, 3a to be formed with the resin for packaging, and is not a process for disposing the leads on both sides of the electronic component chip. Therefore, the height of the step is about 0.1 to 0.2 mm, and it is formed at the same time when the lead frame is manufactured, and the height is constant without variation. On the other hand, the lead on the side of one terminal is subjected to a large forming process by the total of this height, the thickness of the electronic component chip and the height of the bump electrode, and the height which is lifted up for shifting and stacking.
【００２１】本発明で、大きなフォーミング加工を施す
という意味は、電子部品チップとの電気的接続の際に電
子部品チップの両面と接続するため、リードフレームの
一方のリードを電子部品チップの厚さ以上の寸法で電子
部品チップの一面側または他面側に加工することを意味
する。In the present invention, a large forming process means that one lead of the lead frame is connected to both sides of the electronic component chip when electrically connected to the electronic component chip. The above dimensions mean that the electronic component chip is processed on one surface side or the other surface side.
【００２２】つぎに、図１に示される３端子型ダイオー
ドの製法について図３を参照しながら説明する。Next, a method of manufacturing the three-terminal type diode shown in FIG. 1 will be described with reference to FIG.
【００２３】まず、図３（ａ）に示されるようなリード
フレーム１０をその長手方向に沿って供給する。このリ
ードフレーム１０は、前述のように、半導体チップのバ
ンプ電極と接続されるリード２、３の端部２ａ、３ａが
パッケージ用樹脂で被覆されるように、０．１〜０．２
ｍｍ程度リードフレーム１０の面より低くなるようにフ
ォーミング加工が施されているが、これはリードフレー
ム１０の製造時に形成されているもので、この状態でロ
ール状に巻きつけられ、変形することなく供給される。
なお、図３（ａ）において、１１はセクションバーで、
リード１とリード２、３とをずらせ重ねする際の変形を
吸収する部材であり、１２、１３はそれぞれフレーム枠
である。First, the lead frame 10 as shown in FIG. 3A is supplied along its longitudinal direction. As described above, the lead frame 10 has a thickness of 0.1 to 0.2 so that the ends 2a of the leads 2 and 3 connected to the bump electrodes of the semiconductor chip are covered with the packaging resin.
Forming processing is performed so that it is lower than the surface of the lead frame 10 by about mm, but this is formed when the lead frame 10 is manufactured. In this state, it is wound into a roll shape and is not deformed. Supplied.
In FIG. 3A, 11 is a section bar,
Reference numerals 12 and 13 denote frame frames, which are members that absorb the deformation when the leads 1 and the leads 2 and 3 are displaced and overlapped.
【００２４】つぎに、半導体チップ４をボンディングす
るダイパッド１ａに半導体チップ４を通常の方法でダイ
ボンディングしたのち、またはダイパッド１ａを一部押
し下げたのち半導体チップ４をダイボンディングし、さ
らにダイパッド１ａを押し下げてフォーミング加工をす
る。この押し下げる全体の高さは、半導体チップ４の厚
さとバンプ電極４ａの高さおよびリード２、３の端部２
ａ、３ａの段差分、ならびにずらせ重ねのための段差の
和程度で、たとえば０．４〜０．６ｍｍ程度である（図
３（ｂ）参照）。Next, after the semiconductor chip 4 is die-bonded to the die pad 1a for bonding the semiconductor chip 4 by a usual method, or the die pad 1a is partially pushed down, the semiconductor chip 4 is die-bonded, and the die pad 1a is further pushed down. Forming process. The overall height of the push-down is the thickness of the semiconductor chip 4, the height of the bump electrode 4a, and the end portions 2 of the leads 2 and 3.
The sum of the steps a, 3a and the steps for shifting and overlapping is, for example, about 0.4 to 0.6 mm (see FIG. 3B).
【００２５】つぎに、図３（ｃ）に示されるように、リ
ードフレーム１０のフレーム枠１２と１３の相対移動を
行い、半導体チップ４のバンプ電極４ａ、４ｂとリード
端部２ａ、３ａとの位置合わせを行い、上下戻しをし、
バンプ電極４ａ、４ｂとリード端部２ａ、３ａとをハン
ダづけする。ついで、エポキシ樹脂などの合成樹脂でモ
ールドをし、リードフレームから各リード１、２、３を
切り離し、図３（ｄ）に断面図で示されるような半導体
装置が形成される。なお、他の符号は図１と同じ部分を
示す。Next, as shown in FIG. 3C, the frame frames 12 and 13 of the lead frame 10 are moved relative to each other so that the bump electrodes 4a and 4b of the semiconductor chip 4 and the lead end portions 2a and 3a are separated from each other. Align it, put it back up and down,
The bump electrodes 4a, 4b and the lead end portions 2a, 3a are soldered. Then, molding is performed with a synthetic resin such as an epoxy resin, and the leads 1, 2, and 3 are separated from the lead frame, and a semiconductor device as shown in a sectional view in FIG. 3D is formed. The other reference numerals indicate the same parts as in FIG.
【００２６】前記各実施形態のリード形状は面実装構造
に適した形状であったが、面実装構造の場合にリードの
大きなフォーミング加工が行われる場合が多く、本発明
を適用するのに好ましい。しかし、本発明は面実装構造
に限定されることなく、パッケージから導出される外部
リードの形状はどのようにフォーミング加工が施されて
いてもよい。Although the lead shape of each of the above-described embodiments is a shape suitable for the surface mounting structure, in the case of the surface mounting structure, a large lead forming process is often performed, which is preferable for applying the present invention. However, the present invention is not limited to the surface mounting structure, and the shape of the external lead derived from the package may be subjected to any forming process.
【００２７】以上の実施形態では、３端子型ダイオード
の例であったが、３端子に限らず、４端子以上の多端子
の場合にも適用でき、さらにダイオード以外のトランジ
スタなどの半導体装置や、コンデンサなど、一面が１端
子で他面が多端子の電子部品をリードで直接接続する電
子部品に適用できる。In the above embodiment, the example of the three-terminal type diode has been described, but the present invention is not limited to three terminals and can be applied to a case of multiple terminals of four terminals or more, and further semiconductor devices such as transistors other than diodes, It can be applied to an electronic component such as a capacitor in which one side has one terminal and the other side has multiple terminals and is directly connected by a lead.
【００２８】[0028]
【発明の効果】以上説明したように、本発明によれば、
電子部品チップをボンディングしたのち、リードとの電
気的接続のためのリードのフォーミング加工を電子部品
チップの一面側に設けられるバンプ電極と接続するリー
ド側ではなく、電子部品チップの他面側で接続されるリ
ードで行っているため、多端子側のリードの高さにばら
つきが生じることなく安定した接続が得られ、信頼性の
高い電子部品が得られる。As described above, according to the present invention,
After bonding the electronic component chip, the forming process of the lead for electrical connection with the lead is connected not on the lead side that connects to the bump electrode provided on the one side of the electronic component chip, but on the other side of the electronic component chip. Since the lead is made by a common lead, stable connection can be obtained without variations in the height of the lead on the multi-terminal side, and a highly reliable electronic component can be obtained.
【図１】本発明の電子部品の一実施形態の説明図であ
る。FIG. 1 is an explanatory diagram of an embodiment of an electronic component of the present invention.
【図２】本発明の電子部品の一実施形態の他の構造の説
明図である。FIG. 2 is an explanatory diagram of another structure of the embodiment of the electronic component of the present invention.
【図３】図１の電子部品の製法の説明図である。FIG. 3 is an explanatory diagram of a method for manufacturing the electronic component of FIG.
【図４】従来の３端子ダイオードの断面説明図である。FIG. 4 is a cross-sectional explanatory view of a conventional 3-terminal diode.
【図５】従来の３端子ダイオードの断面説明図である。FIG. 5 is a cross-sectional explanatory view of a conventional 3-terminal diode.
１ リード １ａ ダイパッド（リード端部） ２、３ リード ２ａ、３ａ リード端部 ４ 半導体チップ ４ａ、４ｂ バンプ電極 ７ パッケージ 1 Lead 1a Die Pad (Lead End) 2, 3 Leads 2a, 3a Lead End 4 Semiconductor Chips 4a, 4b Bump Electrode 7 Package
Claims (3)
部品チップと、該複数個のバンプ電極および前記電子部
品チップの他面にそれぞれ電気的に接続されるリード
と、前記電子部品チップの周囲を被覆するパッケージと
からなり、前記電子部品チップの他面と接続される前記
リードの端部において大きなフォーミング加工が施され
てなる電子部品。1. An electronic component chip having a plurality of bump electrodes on one surface, leads electrically connected to the plurality of bump electrodes and the other surface of the electronic component chip, and a periphery of the electronic component chip. An electronic component, which is formed of a package that covers the surface of the electronic component chip and is subjected to a large forming process at an end of the lead connected to the other surface of the electronic component chip.
れ接続され前記パッケージから外部に導出される前記リ
ードの先端部が前記パッケージの底面と実質的に同一面
に形成されてなる請求項１記載の電子部品。2. The tip of the lead, which is respectively connected to the bump electrode and the other surface and is led out from the package, is formed on the same surface as the bottom surface of the package. Electronic components.
チップをボンディングするダイパッドを該リードフレー
ムの面より押し下げ、（ｂ）前記ダイパッドに電子部品
チップをボンディングし、（ｃ）前記リードフレームの
ダイパッド部と前記電子部品チップのバンプ電極と接続
されるリードとを相対的に横方向にずらせて位置合わせ
をし、（ｄ）前記電子部品チップの各電極と前記リード
の各々とを電気的に接続したのちパッケージ用樹脂でモ
ールドすることを特徴とする電子部品の製法。3. A die pad for bonding an electronic component chip in a lead frame is pressed down from the surface of the lead frame, (b) an electronic component chip is bonded to the die pad, and (c) a die pad portion of the lead frame. After the bump electrodes of the electronic component chip and the leads connected to each other are laterally displaced and aligned, (d) each electrode of the electronic component chip and each of the leads are electrically connected. A method of manufacturing electronic parts, characterized by molding with a packaging resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28043395A JPH09129798A (en) | 1995-10-27 | 1995-10-27 | Electronic component and fabrication thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28043395A JPH09129798A (en) | 1995-10-27 | 1995-10-27 | Electronic component and fabrication thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09129798A true JPH09129798A (en) | 1997-05-16 |
Family
ID=17624993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28043395A Pending JPH09129798A (en) | 1995-10-27 | 1995-10-27 | Electronic component and fabrication thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09129798A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223634A (en) * | 1999-01-28 | 2000-08-11 | Hitachi Ltd | Semiconductor device |
| US6479888B1 (en) | 1999-02-17 | 2002-11-12 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US6573119B1 (en) | 1999-02-17 | 2003-06-03 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| US7332757B2 (en) | 1999-01-28 | 2008-02-19 | Renesas Technology Corp. | MOSFET package |
| JP2009021630A (en) * | 2008-09-24 | 2009-01-29 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
-
1995
- 1995-10-27 JP JP28043395A patent/JPH09129798A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7985991B2 (en) | 1999-01-28 | 2011-07-26 | Renesas Electronics Corporation | MOSFET package |
| US7342267B2 (en) | 1999-01-28 | 2008-03-11 | Renesas Technology Corp. | MOSFET package |
| US8816411B2 (en) | 1999-01-28 | 2014-08-26 | Renesas Electronics Corporation | Mosfet package |
| US8455986B2 (en) | 1999-01-28 | 2013-06-04 | Renesas Electronics Corporation | Mosfet package |
| US7394146B2 (en) | 1999-01-28 | 2008-07-01 | Renesas Tehcnology Corp. | MOSFET package |
| US7332757B2 (en) | 1999-01-28 | 2008-02-19 | Renesas Technology Corp. | MOSFET package |
| US8183607B2 (en) | 1999-01-28 | 2012-05-22 | Renesas Electronics Corporation | Semiconductor device |
| JP2000223634A (en) * | 1999-01-28 | 2000-08-11 | Hitachi Ltd | Semiconductor device |
| US7400002B2 (en) | 1999-01-28 | 2008-07-15 | Renesas Technology Corp. | MOSFET package |
| US7160760B2 (en) | 1999-02-17 | 2007-01-09 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7812464B2 (en) | 1999-02-17 | 2010-10-12 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing for high output MOSFET |
| US7385279B2 (en) | 1999-02-17 | 2008-06-10 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US6479888B1 (en) | 1999-02-17 | 2002-11-12 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US6812554B2 (en) | 1999-02-17 | 2004-11-02 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US6573119B1 (en) | 1999-02-17 | 2003-06-03 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| JP2009021630A (en) * | 2008-09-24 | 2009-01-29 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
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