JP5282211B2 - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pinball game machine which reliably detects a power failure by providing a sufficient time lag between an input to a forced interrupt terminal and the verification of an input to a port. <P>SOLUTION: When a signal of detecting a power failure is input to a non-maskable interrupt (NMI) terminal of a game control CPU 30a, the pinball game machine is configured not to perform backup processing but to perform forced interrupt processing immediately. A step of making a determination (S210, S220) on whether the pinball game machine shifts to the backup processing or not is placed in a position before performing initial value random number updating processing (S240-S260) of residual processing. The effect of increasing accuracy of detecting the power failure is achieved by determining whether the signal of detecting a power failure is input to an input port or not. Consequently, a possibility of carrying out the backup processing due to the occurrence of a reduction in a voltage caused by a noise or an instantaneous reduction in a power supply voltage which is not the power failure is reduced. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention monitors a power supply voltage supplied from an external power supply or a power supply voltage supplied to a main controller, and when the power supply voltage drops below a predetermined voltage by the monitoring, a processing means for backing up the state of the main controller It is related with the game machine provided with.

  The gaming machine includes a power supply board connected to an external power supply, and supplies a power supply voltage to various control devices provided in the gaming machine. In the power supply board, a power supply voltage supplied from an external power supply or a main control device The power supply voltage supplied to is monitored, and when the power supply voltage drops below a predetermined voltage due to the monitoring, a power failure detection signal is output to the main control device.

This power failure detection signal is input to a forced interrupt (NMI) terminal of a CPU provided in the main controller.
In response to an input to the forced interrupt terminal of the CPU, the main controller prohibits writing to the RAM after saving the register at that time in a predetermined area of the RAM, and performs infinite loop processing until the power is turned off. It is configured to do.

Due to such a configuration, when noise or an instantaneous voltage drop occurs, a power failure detection signal may be output by monitoring the voltage on the power supply board.
In that case, the main controller determines that a power failure has occurred and enters the infinite loop process after performing the above process, so the game is played even though the power supply voltage has returned to the normal state. I can't do it.

  Therefore, when a power failure detection signal is input to the forced interrupt terminal, the register is immediately saved (backed up) in a predetermined area of the RAM, and then writing to the RAM is prohibited and input to the port. It is also possible to determine whether noise or an instantaneous voltage drop has occurred by repeatedly checking the above, and when the voltage is restored, the invention can be made to restore the register and play the original state as it is. ing.

However, even if the input to the port is confirmed repeatedly, there is almost no time difference between the input to the forced interrupt terminal and the input confirmation of the port. There was a possibility of judging as.
In addition, the timing at which the power failure detection signal is input to the forced interrupt terminal of the main controller cannot be predicted, and when the power failure detection signal is input, the progress of the program progresses by saving the register immediately. Also, there is a problem that the processing at the time of power failure becomes complicated.
Further, if there is an input to the forced interrupt terminal, there is a problem that there is a lot of useless processing because it is necessary to save and restore the register even when the voltage is restored immediately after that.

JP 2001-204947 A

  The present invention has been made in view of the above-described problems, and an object of the present invention is not to have a configuration in which a register is immediately saved (backed up) by an input to a forced interrupt terminal, and a preset process is performed. A configuration that starts backup processing sometimes simplifies processing and suppresses wasteful processing, ensuring a sufficient time difference between the input to the forced interrupt terminal and the input confirmation to the port to ensure a reliable power outage An object of the present invention is to provide a gaming machine capable of performing detection.

  The gaming machine according to claim 1, wherein a main control device having a CPU, timer interrupt means for outputting a timer interrupt signal at predetermined time intervals, a power supply voltage supplied from the outside, or a power supply supplied to the main control device Voltage monitoring means for outputting a power failure detection signal when the voltage becomes equal to or lower than a predetermined voltage, the timer interrupt signal to the INT terminal of the CPU, and the power failure detection signal to the NMI terminal and input port of the CPU. In addition, in each gaming machine configured to input, the CPU executes an INT process based on a timer interrupt to the INT terminal, and performs a remaining process until the next timer interrupt occurs after the completion of the INT process. And executing the power failure detection signal input to the NMI terminal to interrupt the INT process or the remaining process being executed and set a power failure flag indicating that a power failure may have occurred. The INT processing or the residual processing is resumed from the position where it was interrupted after the NMI processing is executed, and the final processing of the INT processing and the first processing of the residual processing are performed. , A power failure confirmation process for confirming whether or not to perform a backup process including a register saving process is performed between any of the INT process and the remaining process. If the flag is set, it is determined whether or not a power failure detection signal is input to the input port. If it is input, backup processing is executed. If it is not input, the power failure flag is reset. It is characterized by having constituted so.

Here, the timing at which the timer interrupt means outputs the timer interrupt signal may be 2 ms or 4 ms, which is generally used. However, if there is no problem in control, there is no problem as long as it has periodic periodicity. Absent.
Further, the voltage monitoring means may be configured to monitor any of a power supply voltage (AC24V) supplied from the outside and a power supply voltage (DC32V, NDC24V, DC12V, DC5V) supplied to the main controller.
Further, the predetermined voltage only needs to ensure at least the CPU drive voltage before the end of the backup process, and can be any value as long as it is set in consideration of the voltage decay and the time required to complete the backup process.

  Whether or not the power failure detection signal is input to the input port before executing the processing for setting the power failure flag in the NMI processing of the gaming machine according to claim 1. If it is input, the process for setting the power failure flag is executed. If not, the process for setting the power failure flag is not executed.

  The gaming machine according to claim 3 is characterized in that, in the gaming machine according to claim 1 or 2, a delay circuit for delaying an input to the NMI terminal after branching the power failure detection signal is provided.

  According to a fourth aspect of the present invention, the gaming machine according to the first or second aspect is configured to execute a delay process for delaying the determination as to whether or not the power failure detection signal is input to the input port. It is characterized by that.

  According to the gaming machine of the first aspect, even when the power failure detection signal is input to the NMI terminal, the backup processing is not immediately performed, and the predetermined position (here, the INT processing is completed). In addition, since the power failure confirmation processing is performed before the residual processing starts, it is not necessary to store the processing position on the program in the RAM when saving the register, and it is sufficient to start from the residual processing at the time of return. In addition, the process at the time of power recovery can be simplified.

  Even if a power failure detection signal is input to the NMI terminal due to a voltage drop when noise or an instantaneous power supply voltage drop occurs, INT processing 1 is performed at the maximum after the input to the NMI terminal. Since there is time for the batch, when determining input to the input port, there is a high possibility that power has already been restored. By determining whether or not a power failure detection signal is input to the input port in the previous stage, it is possible to suppress the possibility of performing a meaningless register saving process or register restoring process.

  According to the gaming machine of the second aspect, the same effect as the gaming machine of the first aspect is achieved, and the condition for setting the power failure flag is strict (a power failure detection signal is input to the NMI terminal, and the input port is If the power failure detection signal is input, it is possible to improve the certainty regarding the setting of the power failure flag.

  According to the gaming machine of the third aspect, the same effect as that of the gaming machine according to the first aspect can be obtained, and the input of the power failure detection signal to the NMI terminal can be made more effective than the power failure detection signal input to the input port by the delay circuit. It is possible to delay the time, and it is possible to provide a sufficient time difference between the input determination to the NMI terminal and the input determination to the input port, and there is a possibility of performing meaningless register saving processing and register restoring processing. It can be suppressed more.

  In addition, the same effect as the gaming machine according to claim 2 can be obtained, and the above-described effect can be achieved. Further, the certainty relating to the setting of the power failure flag can be further increased.

  According to the gaming machine of the fourth aspect, the same effect as the gaming machine of the first aspect is obtained, and the input of the power failure detection signal to the input port is made to be more delayed than the input of the power failure detection signal to the NMI terminal by delay processing. It is possible to delay the time, and it is possible to provide a sufficient time difference between the input determination to the NMI terminal and the input determination to the input port, and there is a possibility of performing meaningless register saving processing and register restoring processing. It can be suppressed more.

  In addition, the same effect as the gaming machine according to claim 2 can be obtained, and the above-described effect can be achieved. Further, the certainty relating to the setting of the power failure flag can be further increased.

  Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings relating to a ball game machine 1 included in the game machine. The embodiments of the present invention are not limited to the following examples, and various forms belonging to the technical scope of the present invention can be adopted. Differences in contents described in the respective examples are possible. Needless to say, the portions can be appropriately combined.

As shown in FIG. 1, the ball game machine 1 includes a large rectangular outer frame 2 and a front frame 3, and a CR prepaid card unit (hereinafter referred to as a CR unit) 4 is provided on the left side of the outer frame 2.
The front frame 3 is provided with an upper plate 5 having a ball storage section below the front frame 3 and includes a discharge port (not shown) and a ball removal button for winning balls or rental balls.

The upper plate 5 and the lower plate 6 are connected to each other so that the game ball is guided to the lower plate 6 when the upper plate 5 is full of game balls.
A firing handle 7 is attached to the right side of the lower plate 6.
The firing handle 7 includes a firing stop switch 7a, an operation detector 7b, a touch sensor 7c, and a rotating ring 7d (see FIG. 3).
A game button 8 is provided at an appropriate position on the front frame 3 to perform a push-down operation regarding the game.

The game board 9 will be described with reference to FIG.
The outer shape of the game board 9 is substantially rectangular, and a substantially circular game area 11 surrounded by an outer rail (not shown) and an inner rail 10 is formed on the front surface of the game board 9.
On the condition that the hand touches the touch sensor 7c, when the rotation ring 7d is rotated clockwise, the game ball is placed on the game board 9 with a firing strength corresponding to the operation amount (rotation angle) of the operation of the rotation ring 7d. To fire.
Note that game nails (not shown) are implanted at various locations in the game area 11 formed on the surface of the game board 9.

On the game board 9, a character display device 12 composed of an LCD panel unit 12 a for displaying effect symbols and an effect control device 33 for controlling the display of the LCD panel unit 12 a, a special symbol is displayed in the center of the game area 11. Special symbol display device 13 composed of 7 segment LEDs, normal symbol display device 14 composed of 7 segment LEDs for displaying normal symbols, special symbol hold indicator 15 having a plurality of LEDs, normal symbol hold having a plurality of LEDs A display 16 and a liquid crystal frame decoration 17 are arranged (see FIG. 3).
In the present embodiment, the special symbol display device 13 and the normal symbol display device 14 are directly controlled by the main control device 30 (see FIG. 3).

A normal symbol start gate 18 having a normal symbol start switch 18 a is provided on the left side of the liquid crystal frame ornament 17, and a dummy is disposed on the right side of the liquid crystal frame ornament 17 in order to improve the left-right balance.
Detection of a game ball by the normal symbol start switch 18a causes the normal symbol of the normal symbol display device 14 to start to change, and stops display after a predetermined time.
In the present embodiment, even if a game ball is detected by the normal symbol start switch 18a of the normal symbol start gate 18, the prize ball is not discharged to the player.

A normal electric accessory 19 having a special symbol start switch 19 a is provided below the liquid crystal frame decoration 17.
The special symbol on the special symbol display device 13 starts to fluctuate upon detection of the game ball by the special symbol start switch 19a, and is stopped and displayed after a predetermined time.

The ordinary electric accessory 19 is configured to change between an easy winning state and a difficult winning state by opening and closing the blade member 19c by the ordinary electric solenoid 19b. Is possible.
In the present embodiment, when a game ball is detected by the special symbol start switch 19a of the ordinary electric accessory 19, three prize balls are discharged to the player.

A large winning opening 20 is provided below the ordinary electric accessory 19, and a count switch 20 a for detecting all the game balls that have entered the large winning opening 20 is provided.
The big prize opening 20 is configured to change between a state where a prize can be won and a state where a prize cannot be won by opening and closing the lid member 20c by the big prize opening solenoid 20b. A game ball passes through the front of.

On the other hand, in a state where the lid member 20c is open and the winning is impossible, the lid member 20c projects from the surface of the game board 9 at the lower end of the big prize opening 20, and the game ball is guided into the big prize opening 20 by the lid member 20c. .
In the present embodiment, when a game ball is detected by the count switch 20a of the special winning opening 20, 15 player balls are discharged to the player.

The character display device 12 synchronizes the special symbol display by the special symbol display device 13 and displays the effect symbol in a variable manner, and stops the display in a manner informing the player whether to shift to the jackpot gaming state.
When the special symbol is stopped and displayed in the jackpot display mode on the special symbol display device 13, the effect symbol is stopped and displayed in the jackpot display mode on the LCD panel unit 12a of the character display device 12.
The player recognizes whether or not to shift to the jackpot gaming state by visually recognizing the display mode of the effect symbol displayed mainly on the LCD panel unit 12a of the character display device 12.

In the game area 11, a general winning port 21 including a general winning port switch 21 a is disposed along the inner rail 10, and an out hole 22 is opened at a portion corresponding to the lowermost portion of the inner rail 10.
Also, a CR payment display device provided with a ball lending button 23a for requesting lending of a lending ball to the upper plate 5, a payment button 23b for determining card discharge, and a balance display device 23c for displaying an effective balance of the card. 23.

The electric circuit of the ball game machine 1 will be described with reference to the block diagram of FIG.
The electric circuit of the ball game machine 1 includes a main control device 30, a prize ball control device 31, a launch control device 32, an effect control device 33, a sub integration device 34, and the like, as shown in the figure.

  The main control device 30 is configured as a logical operation circuit centered on an 8-bit one-chip microcomputer incorporating a ROM storing a game control program, a CPU for performing calculations, a RAM serving as a work area for operations, and the like. In addition, an external input / output circuit for performing input / output with each device or various switches and various actuators is also provided.

A normal symbol start switch 18a, a special symbol start switch 19a, a count switch 20a, a general prize opening switch 21a, and the like are connected to the input side of the main controller 30.
On the output side of the main controller 30, a special symbol display device 13, a normal symbol display device 14, a special symbol hold indicator 15, a normal symbol hold indicator 16, a normal electric role solenoid 19b, a big prize opening solenoid 20b, an external connection The terminal device 35 and the like are connected.

As shown in FIG. 2, the main control device 30, the production control device 33, and the sub integration device 34 are arranged directly or indirectly on the back side of the game board 9 of the ball game machine 1, and the frame of the ball game machine 1 A prize ball control device 31, a launch control device 32, and a power supply board 36 are arranged on the back side.
The power supply board 36 includes a power supply detection circuit 36a, a power failure detection circuit 36b, a power switch 36c, a RAM clear switch 36d, and the like.

The power switch 36c is a switch for switching between a state in which the power supply voltage supplied via the power cord 38 and the power relay board 37 is not supplied to various devices in the gaming machine.
The RAM clear switch 36d is operated for a predetermined time when the power switch 36c is turned on (when the power supply voltage is switched to a state where the power supply voltage is supplied), so that the power supply board 36 outputs a RAM clear signal. This signal is input to the main controller 30 and the prize ball controller.

  Although not shown in detail here, the power switch 36c and the RAM clear switch 36d are provided at positions where it is difficult or impossible to operate simultaneously with one hand, and the RAM clear switch 36d is intended to be operated. It is desirable that the RAM clear switch 36d is not accidentally operated when the power switch 36c is not turned on.

  The power supply detection circuit 36a and the power failure detection circuit 36b are circuits that monitor any one of NDC24V, DC32V, DC18V, DC12V, and DC5V generated by rectifying the AC24V supplied to the power supply board 36. Here, the voltage of DC32V is monitored. It is configured to monitor, and is output to a control device (main control device 30 and prize ball control device 31 in this embodiment) that needs at least backup.

When the DC 32V exceeds the power failure detection voltage (here, 17V to 20V), the power supply detection circuit 36a switches the power failure detection signal from Low indicating the power failure state to Hi indicating the power supply state.
The power failure detection circuit 36b switches the power failure detection signal from Hi indicating the power supply state to Low indicating the power failure state when DC32V falls below the power failure detection voltage (here, 17V to 20V).
Based on the state of the power failure detection signal (Hi or Low), the main control device 30 and the prize ball control device 31 can determine whether or not backup is necessary.

In addition, the power cord is connected to the power relay board 37, the power cord 38 is connected to the power relay board 37, and the power cord 39 is connected to the CR unit 4. Power is directly or indirectly supplied to various control devices such as solenoids and motors.
The power supply detection circuit 36 a and the power failure detection circuit 36 b may be provided on a board other than the power supply board 36, or may be configured to be provided on the main controller 30. In that case, since the power supply detection circuit 36a and the power failure detection circuit 36b and the circuit configuration are complicated for each control device, the power failure detection signal may be transmitted from the main control device 30 to another control device.
The supply of the power supply voltage from the power supply board 36 to the prize ball control device 31 may be performed via the main control device 30. Similarly, the power failure detection signal may be given to the prize ball control device 31 via the main control device 30.

The special symbol start switch 19a is in the normal electric accessory 19, the normal symbol start switch 18a is in the normal symbol start gate 18, the general winning port switch 21a is in the general winning port 21, and the count switch 20a is in the big winning port 20. Install.
The normal symbol start switch 18a indicates that the game ball has passed through the normal symbol start gate 18, the special symbol start switch 19a indicates that the game ball has entered the normal electric accessory 19, and the count switch 20a indicates that the game winning ball 20 The general winning opening switch 21a detects that the gaming balls have entered the general winning opening 21, respectively.

  The ordinary electric solenoid 19b connected to the output side of the main controller 30 is mounted in the ordinary electric accessory 19 and used to open and close the wing member 19c of the ordinary electric accessory 19, and is a big prize opening solenoid. 20b is attached in the big prize opening 20, and is used in order to open and close the cover member 20c.

The special symbol display device 13 displays a special symbol indicating whether or not the jackpot that will open the lid member 20c of the special winning opening 20 is displayed, and the normal symbol display device 14 opens and closes the blade member 19c of the ordinary electric accessory 19 A normal symbol indicating whether or not the win is true is displayed.
The special symbol hold indicator 15 and the normal symbol hold indicator 16 respectively display the number of normal symbols held and the number of special symbols held.
The external connection terminal device 35 outputs data from the main control device 30 and the prize ball control device 31 to the outside (hall computer).

The prize ball control device 31 connects the CR unit 4, the prize ball motor 31b and the external connection terminal device 35 to the output side, and connects the main control device 30, the CR unit 4 and the prize ball payout switch 31c to the input side.
The main control device 30 and the prize ball control device 31, and the CR unit 4 and the prize ball control device 31 are connected so as to be capable of bidirectional communication.
The prize ball control device 31 controls the prize ball motor 31b in accordance with a prize ball command transmitted from the main control device 30 when a game ball is detected by the special symbol start switch 19a, the general prize opening switch 21a or the count switch 20a. Drive control is performed, and the number of game balls set as prize balls is paid out to the player.

In addition, when the ball lending button 23a of the CR settlement display device 23 is operated, the award ball motor 31b is driven and controlled in accordance with a ball lending request command transmitted from the CR unit 4, and the game ball set as a lending ball Pay the number to the player.
The prize ball control device 31 determines whether or not the number of game balls set as a prize ball has been paid out by detecting the game balls by the prize ball payout switch 31c, but the game ball is detected by the prize ball payout switch 31c. It is good also as a structure input into the main controller 30, and it is good also as a structure input into both the main controller 30 and the prize ball control apparatus 31.

The firing control device 32 connects the firing motor 24 and the touch lamp 7e on the output side, and connects the firing stop switch 7a, the operation detector 7b, and the touch sensor 7c on the input side.
While driving and controlling the firing motor 24, the firing strength is changed according to the amount of operation of the rotating ring 7d operated by the player.
When the player presses the firing stop switch 7a, the firing is stopped, and when the touch sensor 7c provided in the vicinity of the rotating ring 7d is in the on state, the touch lamp 7e is turned on.

The character display device 12 drives and controls the LCD panel unit 12a including a TFT substrate, a CF substrate, a liquid crystal panel including a controller that applies a predetermined voltage according to an image signal, a backlight, and the like, and the LCD panel unit 12a. The effect control device 33 is configured.
The effect control device 33 is configured as a logical operation circuit centered on a 32-bit one-chip microcomputer.

The sub-integrating device 34 receives the effect command transmitted from the main control device 30, sends a detailed command to the effect control device 33, and the effect control device 33 controls the LCD panel unit 12a based on the detailed command.
Further, the sub-integrating device 34 turns on and notifies various lamps 25, various LEDs 26, and the like that perform payout and rental ball payout display, winning display, ball shortage display, and error display, and further controls driving of the speaker 27. is there.
A detection signal of the game button 8 is input and a signal is transmitted to the effect control device 33.

Transmission of various commands from the main control device 30 to the external connection terminal device 35 and the sub integration device 34 is configured by a one-way communication circuit that transmits only from the main control device 30.
This one-way communication circuit is provided on the output side of the main control device 30, and even if any command is input from the external connection terminal device 35 and the sub integration device 34, the main control device 30 is not affected at all.
Naturally, the one-way communication circuit can be provided on the input side of the external connection terminal device 35 and the sub-integrating device 34, or can be provided on both sides. If it is in a state to be done, there is no problem.

Next, an electric circuit showing how the power failure detection signal output from the power supply board 36 is input to the 8-bit one-chip microcomputer (hereinafter referred to as “game control CPU”) 30a of the main controller 30 is shown in FIG. FIG. 5 and FIG. 6 show timing charts showing timings at which signals output to the main control device 30 by the power supply detection circuit 36a and the power failure detection circuit 36b are input to the game control CPU 30a. This will be described in detail.
The signals that are largely related in the present embodiment are POW-DN1 and POW-DN2, and the description of other signals is omitted here.

Various signals, power supply voltages, and the like are input to the main control device 30 provided in the main control device via a harness connected to the power supply board 36.
Here, the connection connector 30 b is a connector provided on the main control device 30 side of the harness that connects the power supply board 36 and the main control device 30.

When the power is turned on, as shown in FIG. 5, when the DC 32V generated from the AC 24V supplied to the power supply board 36 exceeds the power failure detection voltage, the power failure detection signal, that is, the POW-DN1 is set in the power failure state. It switches from Low indicating Hi to Hi indicating the power supply state.
When the power is shut off, as shown in FIG. 6, when the DC 32V generated from the AC 24V supplied to the power supply board 36 falls below the power failure detection voltage (here, 17V to 20V), the power failure detection circuit 36b POW-DN1 is switched from Hi indicating the power supply state to Low indicating the power failure state.

POW-DN1 branches before being input to game control CPU 30a, one is input to P0 (input port) of game control CPU 30a, and the other is input to X4 / XNMI (NMI terminal) via delay circuit 30c. Yes.
The delay circuit 30c is configured as an analog method using a time constant of a capacitor and a resistor as a delay time (may be configured by using one or a plurality of ICs), and is input to P0 and input to X4 / XNMI. Means a time difference of a predetermined time (3 μs in this embodiment).

This time difference is provided to reduce the possibility that the game control CPU 30a malfunctions when the signal input to the POW-DN1 is disturbed by electrostatic noise.
Specifically, it will be described in detail with reference to FIG. 10 (forced interrupt processing) described later.

The processing executed by the game control CPU 30a provided in the main control device 30 of the ball game machine 1 having the circuit configuration described above will be described according to the flowcharts shown in FIGS. 7, 8, 9 and 10. “Step” is abbreviated as S.
Hereinafter, the operation of the game control CPU 30a of the main controller 30 will be described in detail.
First, when the power supply voltage is supplied to the game control CPU 30a, the game control CPU 30a executes the power-on process shown in FIG.

  Here, whether or not the RAM clear signal output when the RAM clear switch 36d is operated at a predetermined timing after the power switch 36c is turned on after the RAM initial setting process (S100) is input, That is, it is determined whether or not the RAM is erased (S110), and if it is input (S110: yes), RAM erase (S150) for erasing game information stored in the RAM is performed. S110: no), it is determined whether or not the RAM guarantee value set in FIG. 9 to be described later is 1 indicating that the backup has been normally completed when the power was last cut (S120).

If the RAM guarantee value is not 1 (S120: no), the backup is not completed normally, and even if the register is restored, it cannot be returned to the gaming state before power-off. )I do.
If the RAM guarantee value is 1 (S120: yes), the backup has been completed normally. Therefore, the value stored in the RAM is calculated to create a SUM value (S130). It is determined whether it is 0 indicating that it is not damaged (S140).

If the SUM value is not 0 (S140: no), the RAM is erased (S150) because an abnormality is found in the backup data.
If the SUM value is 0 (S140: yes), a power-return process (S160) is performed to restore the register and return to the gaming state before power-off.
Execution of S150 or S160 ends the power-on process, and the remaining process shown in FIG. 8 starts.

  The process shown in FIG. 8 is a process executed by the game control CPU 30a provided in the main controller 30, and is a normal interrupt process (shown in FIG. 8) executed every 2ms timer interrupt (INT interrupt). When the (INT process) is completed in less than 2 ms, it is a residual process that is repeatedly executed at the remaining time in the next INT interrupt.

First, INT interruption is prohibited (S200), and it is determined whether or not the NMI flag set in FIG. 10 described later is 0 indicating that no power failure detection signal is input to the NMI terminal of the game control CPU 30a ( S210).
If the NMI flag is not 0 (S210: no), it is determined whether a power failure detection signal is input to the input port of the game control CPU 30a (S220). If not (S220: yes), the game It is determined that the power failure detection signal input to the NMI terminal of the control CPU 30a is noise or an instantaneous power supply voltage drop, the NMI flag is set to 0 (S230), and initial value random number update processing 1 (S240) is performed.
If the NMI flag is 0 (S210: yes), initial value random number update processing 1 (S240) is performed.

Subsequent to the initial value random number update process 1 (S240), the initial value random number update process 2 (S250) and the initial value random number update process 3 (S260) are executed to release the prohibition of interrupt (S270).
If a power failure detection signal is input to the input port of the game control CPU 30a (S220: no), the register is saved (S280), and the RAM guarantee value is set to 1 indicating that the backup is normally completed (S290). A RAM write protection process for prohibiting writing to the RAM is executed (S295), and a loop is performed without performing other processes until the power is turned off.
If there is an INT interrupt during this remaining process, the interrupt prohibition is canceled (S270), and then the routine proceeds to the normal interrupt process (INT process) shown in FIG.

When the backup process is performed without any problem as described above and there is no problem such as bit corruption in the RAM (a phenomenon in which a part of the BIT stored in the RAM changes from 0 to 1 to 1 to 0), When power is restored, a power supply detection signal is input from the power supply detection circuit 36a, and processing at power-on is performed. Even if power is restored during the loop, P0, X4 / XNMI, and XSRST change to Hi from the power supply board 36, so that power-on processing is performed.
At this time, since the RAM clear switch is not operated in the power-on process of FIG. 7 (S110: no) and the RAM guarantee value is 1 (S120: yes), the above-described S130 is executed, and the SUM value is set. Since it is not 0 (S140: yes), a process for restoring the register (S160) is performed, and the game is resumed in the same game state as when the power is turned off.

  Here, if the INT process takes 2 ms or longer, the next INT process may be performed without performing the remaining process, but even in such a case, backup or fraud prevention is possible. From this point of view, it is desirable to perform the residual processing at least once.

  In the normal interrupt process (INT process) shown in FIG. 9, various random numbers used for special symbol success / failure determination are updated (S300), the count of the timer is updated (S310), and installed in a winning opening or the like. Input processing such as a game ball detection signal from the detection switch and a signal from the switches provided in the frame device (S320), special symbol game processing (S330) related to execution of the success / failure notification and jackpot game, normal symbol success / failure Normal design game processing (S340) related to determination and control of the ordinary electric accessory 19 (S350), production control command transmission processing to the sub-integrating device 34 for controlling the display of the production image, illumination, voice output, etc. (S350), special design The data output process (S360) for the display control of the display device 13 and the opening / closing control of the variable winning opening (ordinary electric accessory 19 and large winning opening 20) is performed and the process returns, as shown in FIG. It was to shift to interrupt prohibition of residual processing (S200).

In the forced interrupt process (NMI process) shown in FIG. 10, the power failure detection circuit 36 b provided on the power supply board 36 detects a decrease in power supply voltage and outputs a power failure detection signal, which is used for game control of the main controller 30. This process is executed when input to the NMI terminal of the CPU 30a. If there is an input to the NMI terminal during the normal interrupt process (INT process) shown in FIG. 9 or the remaining process shown in FIG. Is executed automatically.
If a negative determination is made in S210 of FIG. 8, the forced interrupt process is not executed until S270 in the remaining process of that time ends.

The input of the power failure detection signal to the NMI terminal is four times of the internal system clock of the game control CPU 30a (here, the CPU of LE4280 is assumed, and if the input clock is 15.36 MHz, the internal system clock is 7.68 MHz. 1 The clock time is 130.2 ns), and it is configured to determine that the input is made on condition that the input of the power failure detection signal to the NMI terminal is continued.
That is, since the clock for 4 times is 520.8 ns, when the noise having a width of 520.8 ns or more or the voltage drop of the power failure detection level occurs, it is detected that the power is cut off by the game control CPU 30a, NMI processing is executed.

  Under the circumstances as described above, when it is detected that the power supply is cut off by the NMI terminal of the game control CPU 30a, the saving of the register indicating the position of the program before the execution of the forced interrupt process (S400) is executed, and the game control It is determined whether the input port (P0) of the CPU 30a is Low indicating a power failure state (S410).

  If it is determined in S410 that the input to the input port is Low (S410: yes), the NMI flag is set to 1 indicating that a power failure has been detected (S420), and the program before the execution of the forced interrupt process is executed. In order to return, the register is restored (S430), the process returns to return, and the process returns to the process before the forced interrupt (remaining process and each step of the normal interrupt process).

If it is determined in S420 that the input to the input port is Hi (S410: no), the register is restored to return to the program before the execution of the forced interrupt processing without setting the NMI flag to 1 (S430). ) Is executed to return to the process before returning to the process before the forced interrupt (remaining process and each step of the normal interrupt process).
Here, only the NMI flag is set to 1, and no substantial backup processing is performed.

  As described above, when the game control CPU 30a performs each process as shown in FIGS. 7 to 10, when there is an input to the INT terminal of the game control CPU 30a during the remaining process (when there is an INT interrupt) ), The initial value random number update process (S240 to 260) is always finished, and the normal interrupt process is performed after the interrupt is permitted (S270). Therefore, the interrupt is always prohibited after the normal interrupt process is finished (S200). It will be good if we return to.

  In addition, when a power failure detection signal is input to the NMI terminal of the game control CPU 30a, a forced backup process is performed immediately, but a substantial backup process (saving a register or generating a SUM value) is not performed. By placing the determination (S210, S220) regarding whether or not to shift to the backup process at a position to be executed before the initial value random number update process (S240 to S260) of the residual process, the normal interrupt process and the residual process are performed. There is an effect that the backup process is executed after executing the entire process without being halfway, and it is not necessary to store the progress of the program when the register is saved.

  Here, the determination (S210, S220) regarding whether or not to proceed to the backup process is arranged at a position to be executed before the initial value random number update process (S240 to S260) of the residual process, but the initial value of the residual process Even if it is arranged after the random number update process (S240 to S260) (between S260 and S270), the backup process is executed after the initial value random number update process (S240 to S260) is executed. The same effect is obtained that it is not necessary to store the progress of the program when the register is saved.

  In addition, since the process is shifted to the remaining process after the power-on process is completed, the program should be restored when the register is restored to the state before the power supply voltage drops when the power supply voltage is restored. The position can also be the same.

  Also, in the forced interrupt process, the process of setting the NMI flag to 1 on condition that a power failure detection signal is input to the input port is executed, so that at least after the forced interrupt process occurs, the process Since 5 clocks are required for transition, 11 clocks are required for saving the AF flag, and 11 clocks are required for port reading, the power failure detection signal is really low to the input port after a total of 27 clocks (130.2 ns × 27 = 3.5154 μs). It will be judged.

Since it is very unlikely that a voltage drop due to noise or an instantaneous power supply voltage drop will continue for 3.5154 μs instead of a power failure, the judgment is made only by inputting a power failure detection signal to the NMI terminal (520.8 ns In comparison with the input of the power failure detection signal to the NMI terminal and the input of the power failure detection signal to the input port (3.5154 μs), the power failure detection accuracy is improved.
Further, the chance of setting the NMI flag to 1 due to the occurrence of a voltage drop due to noise or a drop in the power supply voltage is reduced, and the possibility of executing the backup process can be reduced.
However, since it is very unlikely that the voltage drop due to the occurrence of a noise that is not a power failure or a momentary drop in the power supply voltage will continue for 3.5154 μs, it cannot be absolutely stated that the input port and the NMI terminal The input time difference (see FIGS. 4 and 6) is effective.

  Specifically, the input to the input port becomes Low 3 μs earlier than the input to the NMI terminal becomes Low, and similarly, the input to the input port 3 μs earlier than the input to the NMI terminal becomes Hi. Becomes Hi, and at the time when the clock to the NMI terminal is Low for 4 times, the power failure detection signal output from the power supply board 36 has already changed from Hi to Low for 3 μs (main control from the power supply board 36). (Excluding the time required for propagation to the device 30) has elapsed, and when the time required for determining the input of the power failure detection signal to the input port is added, noise with a noise width of 6.5154 μs or more or instantaneous When the voltage drop due to the occurrence of the power supply voltage drop occurs, the NMI flag is set to 1, and the resistance to noise and instantaneous interruption can be greatly enhanced.

  However, even when noise with a noise width of 6.5154 μs or more does not occur, four times of clock detection to the NMI terminal of the game control CPU 30a (NMI processing execution condition) and low detection of the input port (see FIG. Assuming the extremely rare case where another noise is generated in S410 of FIG. 10, confirmation of input to the input port (see FIG. 8) is effective before the shift to the backup processing.

Specifically, while the NMI flag is set to 1 by detecting Low for four clocks to the NMI terminal of the game control CPU 30a and detecting Low at the input port thereafter, the NMI flag to be executed in the remaining processing thereafter When it is 1, it is configured to determine whether or not a power failure detection signal is input to the input port again.
Although it depends on the processing contents in the normal interrupt processing, if the average required time is 1.2 ms, the power failure detection signal is really low to the input port about several μs to 1.2 ms after the NMI flag is set to 1. It will be judged.

  The possibility of a voltage drop due to noise that continues for about several μs to 1.2 ms or an instantaneous power supply voltage drop is extremely low, and when four low clocks to the NMI terminal of the game control CPU 30a are detected (NMI It is unthinkable that another noise is generated when the processing execution condition), Low detection at the input port (S410 in FIG. 10), and Low detection again at the input port (S220 in FIG. 8) are possible. Not a probability).

  Therefore, compared to the case where the NMI flag set in the forced interrupt process is determined to be only 1 (520.8 ns to 6.5154 μs), a power failure detection signal is sent to the input port in a process different from the forced interrupt process. Is determined by whether or not the power is input (approximately several μs to 1.2 ms), the effect that the detection accuracy of the power outage becomes higher is achieved, and it is due to the occurrence of noise that is not a power outage and an instantaneous power supply voltage drop. The possibility that the backup process is executed due to the occurrence of the voltage drop can be reduced.

  If the input to the input port is Hi in the determination in S220 of the remaining process, the power is being supplied. Therefore, the NMI flag is set to 0 in S230 without proceeding to the backup process. Therefore, it is not necessary for the employee of the gaming facility to perform a resetting operation (power ON / OFF in this embodiment), and the gaming facility employee is not bothered by noise or instantaneous interruption.

  In this embodiment, the delay circuit 30c is provided so that the input to the X4 / XNMI is delayed by 3 μs as compared with the input to the P0. However, the delay time is not limited to this and the delay time is changed by the circuit design. It is desirable that the length be long enough to prevent backup processing.

Here, the configuration is such that the input to the input port is confirmed at two places, S220 of the residual process shown in FIG. 8 and S410 of the forced interrupt process shown in FIG. 10, but the delay circuit 30c is not provided. When only one of them is adopted, it is desirable to adopt S220 of the residual process in FIG.
The delay circuit 30c is not provided, and the forced interrupt processing S410 shown in FIG. 10 is not adopted (only the residual processing S220 shown in FIG. 8 is adopted), so that four clocks to the NMI terminal are low. The interval between the detection (execution condition of NMI processing) and the input confirmation to the input port (S220 in FIG. 8) is sufficient, and it is possible to accurately determine the power failure (power cut-off). The possibility that backup processing is executed due to the occurrence of a voltage drop due to the occurrence of a significant power supply voltage drop can be reduced.

Further, when the delay circuit 30c is provided and only one of the residual processing S220 shown in FIG. 8 and the forced interrupt processing S410 shown in FIG. 10 is employed, the residual processing shown in FIG. The effect can be expected by adopting the forced interrupt processing S410 shown in FIG.
Even if the delay circuit 30c is provided and the residual processing S220 shown in FIG. 8 is not adopted (even if S410 in FIG. 10 is adopted), the interval between the input to the NMI terminal and the input port in the NMI processing is sufficient. It is possible to accurately determine a power failure (power shutdown), and to reduce the possibility that backup processing is executed due to the occurrence of a voltage drop due to noise that is not a power failure or an instantaneous power supply voltage drop.

  In this embodiment, it is confirmed whether the input to the input port is not Low (Hi) when the power is shut off. However, the same processing may be performed when the power is turned on. There is no problem even if it is performed only at the time of interruption.

In the first embodiment, the delay circuit 30c is configured to delay the input to the X4 / XNMI by a predetermined time (3 μs) as compared to the input to the P0. However, in the second embodiment, the game control CPU 30a It is configured so as to be delayed by control, and is changed from dealing with hardware to dealing with software.
For this reason, the description of the first embodiment is used for the description other than the above-described portions, and here, the description will be made in detail focusing on the differences.
Note that FIG. 4 used in the description of the first embodiment is different in that the delay circuit 30c is deleted, and the power failure detection signals in FIGS. 5 and 6 are simultaneously transmitted to P0 and X4 / XNMI according to the difference. This is input, and illustration and description here are omitted.

First, FIG. 11 corresponding to FIG. 10 of Example 1 will be shown and described in detail.
In the forced interrupt process 2 (NMI process 2) shown in FIG. 11, the power failure detection circuit 36b provided on the power supply board 36 detects a decrease in the power supply voltage and outputs a power failure detection signal. This process is executed when input to the NMI terminal of the game control CPU 30a. If there is an input to the NMI terminal during the normal interrupt process (INT process) shown in FIG. 9 or the remaining process shown in FIG. Is to be executed forcibly.
If a negative determination is made in S210 of FIG. 8, the forced interrupt process is not executed until S270 in the remaining process of that time ends.

Here, the input of the power failure detection signal to the NMI terminal is four times of the internal system clock of the game control CPU 30a (in this case, the CPU LE4280 is assumed. If the input clock is 15.36 MHz, the internal system clock is 7. 68 MHz. The time of one clock is 130.2 ns), and the power failure detection signal to the NMI terminal is determined to be input on the condition that the input is continued.
In other words, since 4 clocks are 520.8 ns, a power failure detection signal is input to the NMI terminal of the game control CPU 30a when noise having a width of 520.8 ns or more or a voltage drop of the power failure detection level occurs. become.

  Under the circumstances as described above, when a power failure detection signal is input to the NMI terminal of the game control CPU 30a, the saving of the register indicating the position of the program before the execution of the forced interrupt process (S500) is executed, and the determination of S510 Then, it is determined whether or not a predetermined time has elapsed since the start of the NMI processing (S510). If it has not elapsed (S510: no), the timer is incremented (S520), and the determination is made again in S510. Processing is executed (S510, S520).

When the loop process is repeatedly executed and the predetermined time has elapsed in S510 (S510: yes), the timer is reset (S530), and the input port (P0) of the game control CPU 30a indicates a power failure state. It is determined whether it is Low (S540).
If it is determined in S540 that the input to the input port is Low (S540: yes), the NMI flag is set to 1 indicating that a power failure has been detected (S550), and the program before execution of the forced interrupt process is executed. In order to return, the register is restored (S560), the process returns to return, and the process returns to the process before the forced interrupt (remaining process and each step of the normal interrupt process).

If it is determined in S540 that the input to the input port is Hi (S540: no), the register is restored to return to the program before execution of the forced interrupt processing without setting the NMI flag to 1 (S560). ) Is executed to return to the process before returning to the process before the forced interrupt (remaining process and each step of the normal interrupt process).
Here, only the NMI flag is set to 1, and no substantial backup processing is performed.

  By arranging the loop processing (S510, S520) in the forced interrupt as described above, the input to the input port (P0) is detected after the detection of Low for 4 clocks to the NMI terminal (X4 / XNMI). It is possible to earn time until it is determined whether it is Low or not, and the possibility that backup processing will be executed due to the occurrence of a voltage drop due to noise that is not a power outage or an instantaneous power supply voltage drop is reduced. The same effects as in Example 1 are obtained.

Since the delay time is set by the program, the number of components mounted on the main controller 30 can be reduced as compared with the configuration of the first embodiment in which the delay circuit 30c is mounted.
In addition, when designing a new ball game machine, if the occurrence of noise or instantaneous power supply voltage drop is likely to occur, the problem can be solved by setting a long delay time in the program without changing the hardware. It can be solved and easily dealt with when problems arise.

  Since the frequency of noise and instantaneous power supply voltage drop varies depending on the installation environment (game facility equipment, etc.) of the ball game machine 1, a switch or the like that can be operated by an employee installed in the ball game machine 1 ( There is no problem even if one can be selected from the delay times set in a plurality of stages by a switch or the like disposed on the back side of the gaming machine.

  Although the delay circuit 30c is mounted in the first embodiment and the delay processing (S510, S520) is mounted in the second embodiment, both may be mounted, and basically a delay time to be set is set. There is no problem even if a delay circuit 30c is provided and a delay process is mounted so as to cope with a change in the environment, and the time is adjusted by the delay process when a problem occurs in the delay time in the delay circuit 30c.

  In the first embodiment, the main control device 30 includes the delay circuit 30c. In the second embodiment, the game control CPU 30a of the main control device 30 executes the delay process. However, the control device having a backup function ( Basically, it may be used for the award ball control device 31 and / or the sub-integration device), and the timing for executing the backup by being mounted on all the control devices having a backup function provided in the ball game machine 1 Are almost synchronized and can be restored to the gaming state when the power is shut off after the power is restored.

1 is a front view of a ball game machine 1 according to the present invention. It is a rear view of the ball game machine 1 which concerns on this invention. It is an electric wiring block diagram which shows the transmission path of the signal of the ball game machine 1 which concerns on this invention. FIG. 3 is an electrical wiring block diagram showing a signal transmission path from the power supply board 36 to the game control CPU 30a of the main control device 30 according to the first embodiment. 6 is a timing chart showing a relationship between a voltage change at power-on and a signal output from the power supply board 36 according to the first embodiment. 4 is a timing chart showing a relationship between a voltage change at the time of power-off and a signal output from a power supply board according to the first embodiment. It is a flowchart which shows the process at the time of power-on performed by the game control CPU30a of the main controller 30 which concerns on this invention. It is a flowchart which shows the residual process (a backup process is included) performed by the game control CPU30a of the main controller 30 which concerns on this invention. It is a flowchart which shows the normal interruption process (INT process) performed by the game control CPU30a of the main controller 30 which concerns on this invention. 7 is a flowchart illustrating a forced interrupt process (NMI process) executed by the game control CPU 30a of the main control device 30 according to the first embodiment. 10 is a flowchart showing a forced interrupt process 2 (NMI process 2) executed by the game control CPU 30a of the main control device 30 according to the second embodiment.

Explanation of symbols

1: Ball game machine 2: Outer frame 3: Front frame 4: CR unit 5: Upper plate 6: Lower plate 7: Launch handle 7a: Launch stop switch 7b: Operation detector 7c: Touch sensor 7d: Rotating ring 7e : Touch lamp 8: Game button 9: Game board 10: Inner rail 11: Game area 12: Character display device 12a: LCD panel unit 13: Special symbol display device 14: Normal symbol display device 15: Special symbol hold indicator 16: Normal symbol hold indicator 17: Liquid crystal frame decoration 18: Normal symbol start gate 18a: Normal symbol start switch 19: Normal electric accessory 19a: Special symbol start switch 19b: Normal electric role solenoid 19c: Blade member 20: Large prize opening 20a : Count switch 20b: Large prize opening solenoid 20c: Lid member 21: General prize 21a: General winning opening switch 22: Out hole 23: CR payment display device 23a: Ball rental button 23b: Payment button 23c: Balance display device 24: Launch motor 25: Various lamps 26: Various LEDs 27: Speaker 30: Main control device 30a: Game control CPU
30b: Connector 30c: Delay circuit 31: Prize ball control device 31a: Prize ball control CPU
31b: Prize ball motor 31c: Prize ball payout switch 32: Launch control device 33: Production control device 34: Sub-integration device 35: External connection terminal device 36: Power supply board 36a: Power supply detection circuit 36b: Power failure detection circuit 36c: Power switch 36d: RAM clear switch 37: Power relay board 38: Power cord 39: Power cord

Claims (4)

A main control unit having a CPU;
Timer interrupt means for outputting a timer interrupt signal every predetermined time;
Voltage monitoring means for outputting a power failure detection signal when the power supply voltage supplied from the outside or the power supply voltage supplied to the main control device is equal to or lower than a predetermined voltage;
With
In the gaming machine configured to input the timer interrupt signal to the INT terminal of the CPU and the power failure detection signal to the NMI terminal and input port of the CPU, respectively.
The CPU executes an INT process based on a timer interrupt to the INT terminal, and executes a remaining process until the next timer interrupt occurs after the completion of the INT process,
Based on the input of the power failure detection signal to the NMI terminal, the NMI processing including the processing of interrupting the INT processing or the remaining processing being executed and setting a power failure flag indicating that a power failure may have occurred is executed. And the INT process or the residual process is resumed from the position where it was interrupted after execution of the NMI process,
A power failure that confirms whether backup processing including register saving processing is executed at any one of the final processing of the INT processing, the first processing of the residual processing, and the INT processing and the residual processing. It is configured to execute the confirmation process,
In the power failure confirmation process, it is determined whether or not a power failure detection signal is input to the input port on the condition that the power failure flag is set. If not, the game machine is configured to reset the power failure flag. Before executing the process of setting the power outage flag in the NMI process, it is determined whether or not the power outage detection signal is input to the input port,
If it is input, execute the process to set the power outage flag,
The gaming machine according to claim 1, wherein if it is not inputted, the processing for setting the power failure flag is not executed. The gaming machine according to claim 1, further comprising a delay circuit that delays input to the NMI terminal after branching the power failure detection signal. The gaming machine according to claim 1 or 2, wherein a delay process for delaying a determination as to whether or not the power failure detection signal is input to the NMI terminal is executed.

Images