JP2009000241A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of preventing a fraudulent game even when a storage circuit is fraudulently initialized. <P>SOLUTION: A main control circuit 31 successively updates a count value 33a for winning determination over one cycle within a first range from a first initial value within a first range, and also successively updates a count value 33b for winning initial value within a second range from the second initial value within a second range within the first range. A random number generation circuit 34 generates a random number on the basis of intrinsic identification information intrinsic to each game machine. The main control circuit 31 sets the first initial value using a value determined on the basis of the random number generated in the random number generation circuit 34 in the updating of the first cycle of the count value 33a for the winning determination after the initialization of a RAM 33, and sets the first initial value using the count value 33b for the winning initial value in the second and succeeding cycles. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a gaming machine, and more particularly, to a gaming machine having a storage circuit that stores gaming information that changes with gaming.

A gaming machine, for example, a pachinko machine, is provided with various gaming devices and a control circuit for controlling each gaming device. For example, a start winning opening / closing member, a large winning opening / closing member, a payout device, and the like are provided as gaming machines, and a main control circuit, a payout control circuit, and the like are provided as control circuits. In addition, a power supply circuit that supplies power to the control circuit and the gaming machine is provided. As the power supply circuit, for example, an AC / DC conversion circuit that converts AC commercial power into DC power is used.
In such a pachinko machine, when the player is playing a game and the supply of DC power from the power supply circuit is stopped due to a power failure, the processing of the control circuit and the gaming machine is interrupted. For example, if the supply of DC power from the power supply circuit is stopped while award balls are being paid out from the payout device, the payout device stops in the middle of paying out the prize balls. At this time, since the main control circuit and the payout control circuit also stop operating, the information on the number of unpaid prize balls is also deleted.
Therefore, the game information at the time when the power failure occurs is stored in a storage circuit (RAM), and the game is resumed from the gaming state interrupted by the occurrence of the power failure when the power failure is restored. For example, when a power failure occurs, the control circuit executes a power failure process. In the power failure process, determination information is created based on the game information stored in the memory circuit (RAM) at the time when the power failure occurs, and stored in the memory circuit (RAM). During a power failure, game information and determination information stored in a storage circuit (RAM) are held by backup power supplied from a backup power source. Then, when the power failure is restored (power is restored), the control circuit executes a restoration process. In the return processing, the determination information is created based on the game information stored in the storage circuit (RAM), and the generated determination information is compared with the determination information stored in the storage circuit (RAM). It is determined whether or not the game information stored in (RAM) is normal (whether or not it has changed during a power failure). When it is determined that the game information stored in the memory circuit (RAM) is normal (when it is not changed during a power failure), the memory circuit (RAM) is not initialized. Thereby, based on the game information at the time of the power failure occurrence, that is, the game is resumed from the gaming state interrupted by the occurrence of the power failure. On the other hand, when it is determined that the game information stored in the memory circuit (RAM) is abnormal (when there is a possibility that it has changed during a power failure), the memory circuit (RAM) is initialized. Thus, the game is started based on the initial value of the game information, that is, from the initial game state.
In a conventional gaming machine, a backup power supply for supplying backup power to a memory circuit (RAM) is provided on a power supply board together with the power supply circuit (see Patent Document 1).
JP 2000-279579 A

In the pachinko machine, when a start winning ball signal indicating that a game ball has entered the start winning opening is input, a lottery is performed to determine whether or not to generate a winning gaming state advantageous to the player. . For example, the jackpot determination count value for determining whether or not to generate a jackpot gaming state (open control or open / close control of the bonus winning opening / closing member that opens / closes the winning prize opening) is acquired, and the acquired jackpot determination It is determined whether or not the count value matches the set value (winning value). As the jackpot determination count value, for example, a count value that is incremented by “1” from the initial value within the range of “0” to “299” is used. Here, when the jackpot determination count value is always repeatedly added within the range of “0” and “299”, the timing at which the jackpot determination count value matches the set value occurs at equal intervals. For this reason, a fraud board using a sensory device that informs the timing when the jackpot determination count value matches the set value, or an illegal board that illegally inputs the start winning ball signal at the timing when the jackpot determination count value matches the set value is used. There is a risk of fraud being used.
Therefore, the initial update type jackpot determination count value is used as the jackpot determination count value. For example, a jackpot initial value count value that is repeatedly updated (added) with a shorter update cycle than the jackpot determination count value by “1” within a range of “0” and “299” is provided, and the jackpot initial value count value is set. A process of updating (adding) the big hit determination count value by “1” over one period within the range of “0” and “299” is performed for each period. The initial value update type jackpot determination count value is updated as shown in FIG. 8, for example. When the memory circuit (RAM) is initialized at time t21, the jackpot determination count value and the jackpot initial value count value stored in the RAM are both initialized to “0”. For this reason, the big hit determination count value is updated from the initial value “0” of the big hit initial value count value in the first cycle (first cycle) after the storage circuit (RAM) is initialized. . When the jackpot determination count value reaches “299” (the last value in one cycle with “0” as an initial value) at time t22, the update in the first cycle is completed. Then, the initial value of the second period (second cycle) of the jackpot determination count value is set using the jackpot initial value count value. In FIG. 8, the jackpot initial value count value “60” is set as the initial value of the second period of the jackpot determination count value. When the jackpot determination count value reaches “299” at time t23, the update in the second cycle has not been completed, and thus the update returns to “0” and is continued. At time t24, when the big hit determination count value reaches “59” (the last value in one cycle with “60” as an initial value), the update in the second cycle ends. Thereafter, in the same manner, the jackpot determination count value is set within the range of “0” and “299” from the initial value set (updated) using the jackpot initial value count value for each cycle. It is updated (added) by “1” over a period (one cycle).
In this way, by using the initial value update type jackpot determination count value as the jackpot determination count value, the timing at which the jackpot determination count value matches the set value (winning value) is prevented from occurring at equal intervals. can do.
However, even when the initial value update type jackpot determination count value is used, the jackpot initial value count value immediately after the memory circuit (RAM) is initialized is initialized to “0”. The count value is updated from “0”. For this reason, if the update interval of the jackpot determination count value and the set value (winning value) are known, the memory circuit (RAM) is initialized (the jackpot determination count value and the jackpot initial value count value are initialized). From this point on, it is possible to predict a period until the jackpot determination count value reaches the set value (win value) (timing when the jackpot determination count value matches the set value).

Here, in the conventional gaming machine, since the backup power supply is provided on the power supply board, a power line for supplying backup power to the control board is connected between the power supply board and the control board. In this case, if a fraud in which the supply of DC power to the control board is stopped for a certain period while the power line for supplying backup power is short-circuited or disconnected, the supply of DC power to the control board is stopped. During this time, backup power is not supplied from the backup power source to the control board, so that the game information stored in the storage circuit is erased. For this reason, in the return processing in the control circuit after the supply of DC power to the control circuit is resumed, the memory circuit is initialized and the jackpot determination count value starts to be updated (counted) from the initial value “0”. Is done.
In order to prevent such fraud, it is conceivable to provide a backup power supply on the control board. However, if a backup power supply is provided on the control board, the control board may be illegally removed from the gaming machine, and game information stored in the storage circuit may be illegally rewritten. For example, if the main control board is removed from the gaming machine and the start winning ball signal is input to the main control circuit until the probability fluctuation state (the probability that the lottery result is a hit is higher than normal) is entered, Done. In this case, the game is played in an illegally set probability variation state. For this reason, it is difficult to employ a method of providing a backup power source on the control board.
The present invention has been made in view of these points, and an object of the present invention is to provide a technique capable of preventing an illegal game due to an illegal initialization of a memory circuit.

The gaming machine of the present invention has a control board and a power supply board.
A power supply circuit for supplying power to the control board is provided on the power supply board. As the power supply circuit, for example, an AC-DC conversion circuit that converts AC24V power into DC34V power and DC12V power is used. The voltage of DC power supplied from the power supply circuit from the viewpoint of preventing the influence of noise mixing on the power lines that supply drive power to the control circuit and memory circuit provided on the control board and fraud to the power lines. It is preferable to provide a voltage conversion circuit (for example, a voltage conversion circuit that converts DC12V power to DC5V power) for converting the voltage into a drive power voltage such as a control circuit or a memory circuit provided on the control board.
The control board is provided with a control circuit, a storage circuit, and a random number generation circuit.
The memory circuit includes game information that changes with the game, a count value for hit determination that is sequentially updated within the first range, and an initial value that is sequentially updated within the second range within the first range. Count value, unique identification information unique to each gaming machine, and the like are stored. The first range is set by the first value and the second value, and the second range is set by the third value and the fourth value. The second range may be the same as the first range (for example, [first value = third value] and [second value = fourth value]). As game information stored in the memory circuit, for example, in a pachinko machine, the number of start winning ball signals indicating that a game ball (game medium) has entered the start winning opening, a winning game state (a jackpot gaming state or a probable game) Game information indicating the occurrence of a state, etc., prize ball information indicating the number of prize balls to be paid out from the payout device, and the like are used. The unique identification information unique to each gaming machine typically includes identification information (manufacturing information) of a circuit or element provided in the gaming machine, for example, a control circuit IC chip in which a control circuit and a memory circuit are integrally formed. Number). A ROM or RAM is used as the memory circuit. Typically, the storage circuit stores a ROM that stores information that does not change (for example, unique identification information) and information that changes (for example, game information, a count value for hit determination, or a count value for hit initial value). It is composed of RAM.
The random number generation circuit generates a random number based on the unique identification information stored in the storage circuit. As the random number generation circuit, a random number generation circuit that generates a known random number such as an M-sequence random number can be used.
The control circuit executes the following processing.
When the drive power is supplied, the main process and the timer interrupt process are executed after the return process is executed. The timer interrupt process is executed, for example, every 4 ms in the timer interrupt period in the main process.
In the return process, it is determined whether or not the game information and the like stored in the storage circuit is normal (whether or not the game information and the like are changed during a power failure). In the present invention, as a method for determining whether or not the game information or the like stored in the memory circuit is normal, the determination information calculated based on the game information or the like stored in the memory circuit and the memory information stored in the memory circuit are stored. The determination information (determination information calculated at the time of the previous power failure process) is compared. As the determination information, for example, a checksum value such as game information stored in the storage circuit, parity data, or the like can be used. If the calculated determination information and the determination information stored in the storage circuit do not match, the game information stored in the storage circuit is not normal, that is, abnormal (there may be a change during a power failure). And initialization processing for initializing the game information, the hit determination count value, and the hit initial value count value stored in the storage circuit is executed. When the game information is initialized, the game is started from the initial game state. As a method for initializing the game information, the hit determination count value, and the hit initial value count value stored in the storage circuit, typically, the game information, the hit determination count value, and the hit initial value count value A method for initializing the RAM for storing the data is used. On the other hand, if the calculated determination information matches the determination information stored in the storage circuit, the game information stored in the storage circuit is normal (not changed during a power failure). Determine and do not execute the initialization process. In this case, the game is resumed from the game state corresponding to the game information stored in the storage circuit, that is, the game state at the time of the previous power failure.
In the main process, a power failure detection signal input determination process and a hit initial value count value update process are executed.
In the power failure detection signal input determination process, it is determined whether or not a power failure detection signal indicating that a power failure has occurred is input. If it is determined that a power failure detection signal has been input, determination information used in the return process (for example, checksum value or parity data such as game information stored in the storage circuit) is calculated and stored in the storage circuit To do. The power failure detection signal is output from a power failure detection circuit that detects that a power failure has occurred. The power failure detection circuit is preferably provided on the control board, but can also be provided on the power supply board. For example, when the power failure detection circuit is provided on the control board, when it is detected that the voltage of DC12V power supplied to the control board is lower than the power failure detection set value, or when it is provided on the power supply board. Can be configured to output a power failure detection signal when it is detected that the voltage of DC 12V power converted by the power supply circuit has dropped below the power failure detection set value.
In the hit initial value count value update process, the hit initial value count value is sequentially updated from the second initial value within the second range by the second update value. The second update value and the update direction can be set as appropriate. When the gaming machine has a plurality of winning game states and uses a plurality of hit determination count values for determining whether or not to generate each of the plurality of winning game states, the initial value count value is updated. In the processing, the hit initial value count value corresponding to each of the plurality of hit determination count values is updated.
In the timer interrupt process, a hit determination count value update process and a lottery condition determination process are executed.
In the hit determination count value update process, the hit determination count value is updated for each first update value over one period in the first range from the first initial value in the first range. Here, in the present invention, in the first cycle of the hit determination count value after executing the initialization process, the first initial value is determined using a value determined based on the random number generated by the random number generation circuit. In each period after the second period of the hit determination count value after setting the value and executing the initialization process, the first initial value is set using the count value for hit initial value. The first update value and the update direction can be set as appropriate. “One period in the first range” is set in the first range by the first value and the second value, and the update direction of the count value for hit determination is the direction from the first value to the second value. If the first initial value is set to the first value, the range from the first value to the second value (first value to second value) When the first initial value is set to a value other than the first value, the range from the first initial value to the value immediately before the first value (the first initial value to the first value) 2 to the value immediately before the first initial value). When the gaming machine has a plurality of winning gaming states and uses a plurality of winning determination count values for determining whether or not to generate each winning gaming state, Each of the plurality of hit determination count values is updated.
In the lottery condition determination process, it is determined whether the lottery condition is satisfied. As a lottery condition, for example, in a pachinko machine, a condition in which a start winning ball signal indicating that a game ball has entered a start winning opening is used. When it is determined that the lottery condition is satisfied, the hit determination count value is compared with the set value. When the winning determination count value matches the set value, a control signal for generating a winning gaming state is output. For example, a command signal for effect display on the display device that the lottery result is winning or that a winning gaming state has occurred, driving for opening / closing or controlling the opening / closing member of the large winning opening that opens / closes the large winning opening Output a signal.
In the present invention, as a count value for hit determination (for performing a lottery) for determining whether or not to generate a win game state advantageous to the player, the first count is determined for each cycle of the count value for hit determination. While using the initial value update type hit determination count value for updating the hit determination count value over one period from the first initial value while updating the initial value, the game information stored in the storage circuit, In the first cycle update of the count value for hit determination after executing the initialization process for initializing the count value for determination and the count value for hit initial value, it is determined based on the random number generated by the random number generation circuit. In the update of each period after the second period of the count value for hit determination after executing the initialization process, the first initial value is set using And it sets the first initial value by using a preparative value. In the present invention, a random number generation circuit that generates a random number based on unique identification information unique to each gaming machine is used as the random number generation circuit. For this reason, even when the initialization process is executed improperly, the point when the hit determination count value matches the set value (win value) in the first cycle of the hit determination count value (the initialization process is executed) It is very difficult to predict the period until the count value for hit determination first matches the set value. In addition, the count value update process for hit initial value is executed in the main process, and the count value update process for hit determination is executed in the timer interrupt process in the main process. Change. Thereby, in each cycle after the second cycle of the hit determination count value, the first initial value of the hit determination count value updated using the hit initial value count value also randomly changes. It is very difficult to predict the point in time when the business count value matches the set value (winning value). Therefore, it is possible to reliably prevent an illegal game due to an illegal initialization of the memory circuit.
When the control circuit is provided with voltage conversion means for converting the voltage of the power supplied to the control board into a voltage corresponding to the drive power voltage of the control circuit or storage circuit provided on the control board. Since there is no need to connect a power line for supplying driving power (power having a voltage corresponding to driving power) to a control circuit or processing means provided on the control board, the control circuit or processing means Thus, it is possible to prevent the memory circuit from being illegally initialized due to the influence of noise mixed in the power line for supplying driving power or the like, or the unauthorized operation on the power line.
In addition, when the power failure detection circuit is provided on the control board, it is not necessary to connect the signal line for transmitting the power failure detection signal to the control board. It is possible to prevent the memory circuit from being illegally initialized.

  By using the present invention, illegal games due to illegal initialization of the memory circuit can be prevented.

Embodiments of the present invention will be described below with reference to the drawings.
The structure of the principal part of the 1st Embodiment of this invention is shown in FIG. In the present embodiment, the present invention is configured as a pachinko machine.
The present embodiment has a power supply board 10 and a main control board 20. Although not shown in FIG. 1, the pachinko machine according to the present embodiment has various boards other than the main control board 20 and gaming equipment.
The power supply board 10 corresponds to the “power supply board” of the present invention, and the main control board 20 corresponds to the “control board” of the present invention.
The power supply board 10 is provided with a power supply circuit 11 for supplying power to a control circuit in the gaming machine, gaming equipment, and the like. As the power supply circuit 11, an AC / DC conversion circuit that converts AC power into DC power is used. In the present embodiment, the power supply circuit 11 converts AC24V power supplied to the terminal 10a of the power supply board 10 into DC34V power and DC12V power.
The power supply circuit 11 corresponds to the “power supply circuit” of the present invention.
Here, in order to supply DC5V power, which is driving power of the control circuit and the memory circuit, from the power supply board 10 to each control board, it is necessary to connect a power line for supplying DC5V power to the power supply board 10 and each control board. . Since DC5V power has a low voltage, it is greatly affected by a voltage drop caused by the power line and noise mixed in the power line. In addition, when a power line for supplying DC 5V power connected to the power supply board 10 or each control board is short-circuited for a single period, the control circuit disposed on each control board operates without performing a power failure process. After stopping, return processing is performed. In this case, since the power failure process is not performed, the control circuit initializes the memory circuit. Thus, if a power line that supplies DC 5V power is connected to the power supply board 10 or each control board, an improper operation (an illegal operation on the power line) may be performed in which the power circuit is short-circuited for a single period to initialize the storage circuit. There is.
Therefore, in this embodiment, DC34V power and DC12V power that are less affected by voltage drop due to the power line and noise mixed in the power line and are difficult to perform unauthorized operations (when DC34V power and DC12V power are cut off, many games are used. Since the operation of the device stops, unauthorized operation is easily detected.) Is supplied from the power supply board 10 to each control board. For example, the DC 34V power converted by the power supply circuit 11 is supplied to the terminal 20a of the main control board 20 via the terminal 10b and the power line L1 of the power supply board 10, and the DC12V power is supplied to the terminal 10c and the power line L2 of the power supply board 10. To the terminal 20b of the main control board 20.

In addition, at the time of a power failure (when the supply of drive power to the main control circuit 31 or the like is interrupted), after the power failure is restored (after power recovery), the game can be resumed from the gaming state before the power failure. It is necessary to supply backup power for holding game information and the like stored in the RAM 33. In the present embodiment, the power supply substrate 10 is provided with a backup capacitor 12 for supplying backup power. In the state in which power is supplied from the power supply circuit 11 to the main control board 20, the backup capacitor 12 receives the DC5V power converted by the voltage conversion circuit 21 provided in the main control board 20 as a diode 24, a power line pattern m3, The battery is charged by being supplied via the terminal 20e of the main control board 20, the power line L3, and the terminal 10d of the power supply board.
The backup capacitor 12 corresponds to the “backup power supply” of the present invention.
As described above, when a backup power supply is provided on the control board, the control board is removed from the gaming machine, and the gaming information stored in the storage circuit provided on the control board is illegally rewritten, and then the gaming machine There is a risk of fraudulent attachment. In the present embodiment, a backup capacitor 12 that supplies backup power is provided on the power supply substrate 10. For this reason, for example, when the main control board 20 is removed from the gaming machine, the driving power is not supplied to the memory circuit (RAM 33), and it is possible to prevent such a fraud from being performed on the memory circuit (RAM 33). Can do.

The main control board 20 is provided with a voltage conversion circuit 21, a power failure detection circuit 22, a RAM clear switch 23, a diode 24, a main control circuit 31, a ROM 32, a RAM 33, a random number generation circuit 34, and the like. In the present embodiment, the main control circuit 31, the ROM 32, the RAM 33, and the random number generation circuit 34 are configured as an integrated (chip) main control circuit IC30. The main control board 20 is provided with other elements and circuits.
The main control board 20 is provided with terminals 20a to 20g. A DC34V power line L1 for supplying DC34V power and a DC12V power line L2 for supplying DC12V power are connected between the terminals 10b, 10c of the power supply board 10 and the terminals 20a, 20b of the main control board 20. A power line pattern m1 for supplying DC 34V power is provided between the terminal 20a and the terminal 20c, and a power line pattern m2 for supplying DC 12V power is provided between the terminal 20b and the terminal 20d. Yes. From the power line patterns m1 and m2, DC34V power and DC12V power are supplied to the DC34V load and DC12V load provided on the main control board 20. Various signals (for example, a start winning ball signal) are input to the terminal 20f of the main control board 10. The signal input to the terminal 20f is input to the main control circuit 31 via the terminal 30c of the main control circuit IC30. A control signal from the main control circuit 31 (for example, a main control signal such as a main command signal and a drive signal) is output via the terminal 30d of the main control circuit IC30 and the terminal 20g of the main control board 10.

The voltage conversion circuit 21 converts DC 12V power into DC 5V power used as drive power for the main control circuit 31, the RAM 33, and the like. For example, a switching regulator or a three-terminal regulator is used as the voltage conversion circuit 21.
The voltage conversion circuit 21 corresponds to the “voltage conversion circuit” of the present invention.
The DC5V power converted by the voltage conversion circuit 21 is supplied to the terminal 30b of the main control circuit IC30 via the diode 24 and the power line pattern m3. Further, it is also supplied to the backup capacitor 12 provided on the power supply board 10 through the power line L3 connected between the terminal 20e of the main control board 20 and the terminal 10d of the power supply board 10.

The power failure detection circuit 22 detects that the power supplied to the main control board 20 has decreased, and outputs a power failure detection signal (sometimes referred to as a “power failure warning signal”). In the present embodiment, a decrease in power is detected by a decrease in power voltage. For example, the power failure detection circuit 22 detects that the voltage of DC12V power supplied to the voltage conversion circuit 21 (control board 20) has dropped below the power failure detection set value, and the power supplied to the main control board 20 is detected. A power failure detection signal indicating that the voltage (that is, the voltage of the driving power supplied to the main control circuit 31 or the RAM 33) has decreased is output. The power failure detection signal is input to the main control circuit 31 via the terminal 30a of the main control circuit IC30.
The power failure detection circuit 22 corresponds to the “power failure detection circuit” of the present invention.
Here, as described above, when the supply of the drive power to the main control circuit 31 is stopped, it is necessary to cause the main control circuit 31 to execute a power failure process. For this reason, as the power failure detection set value, the DC 12V power supplied to the main control board 20 due to a power failure or the like decreases, and the power failure detection signal is output from the power failure detection circuit 22, and the main control circuit 31 executes the power failure process. The voltage of DC5V power supplied from the voltage conversion circuit 21 is a voltage at which the main control circuit 31 and the RAM 33 can operate (for example, 4.75V for the main control circuit 31 using 5V drive power). It is set to be held as described above.

The RAM clear switch 23 is used when the RAM 33 is initialized. When the RAM clear switch 23 is operated, an initialization instruction signal is input to the main control circuit 31 via the terminal 30e of the main control circuit IC30.
The RAM clear switch 23 corresponds to the “initialization instruction switch” of the present invention.
In this embodiment, when a power failure occurs and a power failure detection signal is input, backup power is supplied from the backup capacitor 12 to the main control circuit IC 30 and stored in the RAM 33 when the power failure occurs. Game information is held. Then, when the power failure is restored (at the time of power recovery), the game is resumed from the gaming state at the time of the power failure based on the game information stored in the RAM 33.
However, when the game store is opened, it may be necessary to initialize the RAM 33 provided on the control board of each gaming machine and start the game from the initialized game information. The RAM clear switch 23 is used when forcibly initializing the RAM 33 provided on the main control board 20 as described above. For example, when the RAM 33 is initialized, the power switch of the gaming machine is turned on while the RAM clear switch 23 is operated (ON). The main control circuit 31 (processing means 31a) forcibly initializes the RAM 33 when the driving power is supplied in a state where the RAM clear switch 23 is being operated (a state where the initialization instruction signal is input). Turn into.

The main control circuit 31 is constituted by a CPU. The main control circuit 31 operates based on an operation program stored in the ROM 32, game information stored in the RAM 33, and the like. The processing means 31a, the lottery means 31b, the hit determination count value update means 31c, and the hit initial value The processing of the count value updating means 31d and the initial value setting means 31d is executed.
The main control circuit 31 corresponds to the “control circuit” of the present invention.

The ROM 32 stores an operation program of the main control circuit 31 (each unit 31a to 31d), unique identification information (unique ID) 32a, and the like. As the unique identification information 32a, identification information unique to the gaming machine is used. For example, identification information of elements and circuits provided in the gaming machine is used. In the present embodiment, the main control circuit 31 provided on the main control board 30, the identification information of the main control circuit IC30 in which the ROM 32, the RAM 33, etc. are integrally formed (for example, the main control circuit IC30 given at the time of manufacture). Each serial number is used.
The unique identification information 32a stored in the ROM 32 corresponds to “unique identification information unique to each gaming machine” of the present invention.

The RAM 33 stores game information that changes with the game, operation information of each means of the main control circuit 31, a hit determination count value 33a, a hit initial value count value 33b, and the like. The hit determination count value 33a and the hit initial value count value 33b are stored in the hit determination count value storage area and the hit initial value count value storage area of the RAM 33, respectively.
The game information that changes with the game includes, for example, the number of start winning ball signals indicating that a game ball has entered the start winning port, and a winning ball signal indicating that the game ball has entered the winning port (for example, , The number of normal winning ball signals indicating that the player has entered the normal winning opening, the number of winning balls signal indicating that the player has entered the big winning gate, the number of winning balls instructed to pay out to the payout device, and the state of play per game The game information and the like indicating that the player is playing is stored.
The hit determination count value 33a is used to determine (lottery) whether or not to generate a win gaming state advantageous to the player. In the present embodiment, an initial value update type hit determination count value is used as the hit determination count value 33a. That is, the hit determination count value 33a is an initial value (hereinafter referred to as a “first initial value”) within a range between the first value and the second value (hereinafter referred to as “first range”). ) To the second value in the direction from the first value to the first value, and sequentially updated over one period (one cycle) within the first range, and the first initial value every period. The value is updated. The first update value and the update direction can be set as appropriate. For example, the count value for hit determination 33a is changed from the first initial value in the first range between the first value “0” and the second value “299” to one cycle in the first range. Over the first update value “1” is sequentially added (the update direction is the addition direction) and is represented by a count value. In this case, in one cycle (one cycle) in the first range, the process (update process) of adding the first update value “1” from the first initial value in the first range is “300”. It is the range until it performs. When the hit determination count value 33a reaches the second value “299” within one period (one cycle), the value returns to the first value “0” and the update (addition) is continued.
The hit initial value count value 33b is used to set a first initial value for each period (one cycle) of the hit determination count value 33a. The hit initial value count value 33b is an initial value (hereinafter referred to as "second initial value") within a range between the third value and the fourth value (hereinafter referred to as "second range"). From the third value to the fourth value, the second update value is sequentially updated over the second range. The second range is set so as to be included in the first range (so that the third value and the fourth value are values within the first range). Preferably, the second range is set to the same range as the first range ([third value = first value] and [fourth value = second value]). The second update value and the update direction can be set as appropriate. For example, the hit initial value count value 33b is a second range (= first value) between the third value “0” (= first value) and the fourth value “299” (= second value). Count value sequentially added by the second update value “1” (= first update value) over the second range from the second initial value in the range of 1) (the update direction is the addition direction). It is represented by When the hit initial value count value 33b reaches the fourth value “299”, the count value 33b returns to the third value “0” and the update (addition) is continued. The second initial value of the hit initial value count value 33b can be selected as appropriate. However, when the RAM 33 is initialized, a value set in the hit initial value count value storage area of the RAM 33 (for example, “0”) is preferably used.

If the pachinko machine has a plurality of hit gaming states, the RAM 33 stores a plurality of hit determination count values 33a. For example, the jackpot gaming state occurs depending on the jackpot gaming state that opens or closes the jackpot opening / closing member that opens / closes the jackpot and the winning symbol used when displaying that the jackpot gaming state occurs on the display device When a probability variation gaming state with a higher probability than normal is generated, a jackpot determination count value for determining whether or not to generate a jackpot gaming state (lottery) as the hit determination count value 33a The winning symbol determination count value for determining whether or not to generate the probability variation gaming state (lottery) is stored.
When a plurality of hit determination count values 33a are stored in the RAM 33, a plurality of hit initial value counts used for setting a first initial value for each cycle of each of the plurality of hit determination count values 33a. The value can also be stored in the RAM 33.
The count value for hit determination 33a corresponds to the “count value for hit determination” of the present invention, and the count value for hit initial value 33b corresponds to the “count value for hit initial value” of the present invention. The ROM 32 and the RAM 33 correspond to the “memory circuit” of the present invention.

The random number generation circuit 34 generates a random number based on the unique identification information 32a unique to each gaming machine stored in the ROM 32 (using the unique identification information 32a as an initial value). As the random number generation circuit 34, a random number generation circuit that generates a known random number such as an M-sequence random number can be used.
Here, as will be described later, the random number generated by the random number generation circuit 34 is the first initial value (start value S) of the first cycle hit determination count value 33a after the RAM 33 is initialized, or the RAM 33. Is used to set a period (start period T) from the initialization of the process until the start of the process of updating the hit determination count value 33a. Therefore, using the random number generated by the random number generation circuit 34, the start value S of the first cycle of the hit determination count value 33a and the start period T for starting the update processing of the hit determination count value 33a are easily set. It is preferable to be able to do so. For example, the change range of the random number generated by the random number generation circuit 34 can be made equal to the change range of the hit determination count value 33a (the first range set by the first value and the second value). Thus, it is configured to be settable. Alternatively, a method of converting the random number generated by the random number generation circuit 34 into the start value S of the first cycle of the hit determination count value 33a or the start period T for starting the update processing of the hit determination count value 33a is set. To do.
In the present embodiment, the first initial value (start value S) in the first cycle of the hit determination count value 33a after the RAM 33 is initialized using the random number generated by the random number generation circuit 34. Is set.
The random number generation cycle (random number update cycle) in the random number generation circuit 34 can be set as appropriate.

Each means of the main control circuit 31 will be described.
The hit determination count value updating means 31c sets the hit determination count value 33a stored in the RAM 33 to the first value from the first initial value within the first range in the direction from the first value to the second value. Are sequentially updated over one period (one cycle) within the first range.
The initial value setting means 31d sets a first initial value for each cycle of the count value for hit determination 33a. In the present embodiment, the initial value setting means 31d uses the random number 34a generated by the random number generation circuit 34 in the first cycle of the hit determination count value 33a after the RAM 33 is initialized by the processing means 31a. In each cycle after the second cycle of the count value 33a for hit determination after the RAM 33 is initialized, the first initial value is set using the value determined based on (start value S). A first initial value is set using the count value 33b for the hit initial value.
The hit determination count value update means 31c and the initial value setting means 31d constitute an initial value update type hit determination count value update means for updating the initial value update type hit determination count value 33a. In other words, in the present embodiment, the hit determination count value 33a uses a value determined based on the random number generated by the random number generation circuit 34 in the first cycle after the RAM 33 is initialized. From the first initial value to be updated (set), and in each cycle after the second cycle after the RAM 33 is initialized, the count value for the initial value 33b is updated (set). Are updated sequentially from the first initial value in the direction from the first value to the second value by the first updated value over one period within the first range.

  The hit initial value count value updating means 31d calculates the hit initial value count value 33b stored in the RAM 33 from the second initial value within the second range between the third value and the fourth value. The second update value is sequentially updated over the second range in the direction from the third value to the fourth value. The second range may coincide with the first range.

When the pachinko machine has a plurality of winning game states, a plurality of hit determination count values for updating a plurality of hit determination count values 33a for determining whether or not to generate each of the plurality of gaming states. Update unit 31c and a plurality of hit initial value count values update for updating a hit initial value count value 33b used for setting a first initial value for each period of each of the plurality of hit determination count values 33a. There can be provided means 31d and a plurality of initial value setting means 31d for setting a first initial value for each period of each of the plurality of hit determination count values 33a.
For example, the aforementioned jackpot determination count value for determining whether or not to generate a jackpot gaming state (lottery) and the winning symbol determination for determining (lottery) whether or not to generate a probable gaming state When the count value for use is used, the count value for jackpot determination count value updating means for updating the count value for jackpot determination and the count value for winning symbol determination for updating the count value for determination of the hit symbol are used as the count value update means 31c for winning determination. An update means is provided, and as a hit initial value count value update means 31d, a jackpot initial value count value update means for updating the jackpot initial value count value and a hit symbol initial value count for updating the hit symbol initial value count value A value updating unit is provided, and the initial value setting unit 31d is a first jackpot determination count value for each cycle. Providing an initial value for the initial value setting means per set the first set value for each cycle of the jackpot determining the initial value setting means and per symbol judgment count value for setting the set value.

  In the present embodiment, the process of updating the hit initial value count value 33b by the hit initial value count value updating means 31d is performed in the main process of the processing means 31a (main control circuit 31) and in the main process of the processing means 31a. This is performed in a timer interrupt process every timer interrupt cycle (for example, 4 ms). The hit determination count value 33a is updated by the hit determination count value updating means 31c in the main process of the processing means 31a (main control circuit 31). In this way, by updating the hit initial value count value 33b in the main process of the processing means 31 and the timer interrupt process in the main process, the timer interrupt process in the main process of the processing means 31a is performed. Compared to the case where only the initial count is performed, the count value for hit initial value 33b changes more randomly. As a result, the first initial value for each period of the count value for hit determination also changes more randomly. The hit initial value count value 33b can be updated only in the main process of the processing unit 31a. Even in this case, the hit initial value count value changes randomly.

The lottery means 31b performs a lottery process for determining whether or not to generate a winning gaming state advantageous to the player due to the establishment of the lottery conditions. As the lottery condition, the above-described condition that the start winning ball signal indicating that the game ball has entered the start winning opening is input.
In the lottery process, first, the winning determination count value 33a stored in the winning determination count value storage area of the RAM 33 is acquired (read). Then, the acquired hit determination count value 33a is compared with the set value (win value) stored in the ROM 32 (a lottery is performed), and a comparison result (lottery result) is output.
When the pachinko machine has a plurality of winning game states, the lottery means 31b executes a lottery process for each of the plurality of winning game states. For example, first, the jackpot determination count value is compared with a set value (jackpot set value). When the jackpot determination count value matches the jackpot set value (when the lottery game lottery result is a win), the winning symbol determination count value is compared with the set value (probability variation symbol set value). Then, a winning symbol lottery result (probability variation jackpot symbol or normal jackpot symbol) is output. When the jackpot determination count value does not coincide with the jackpot set value (when the lottery game lottery result is out of order), the losing symbol determination count value is acquired and the jackpot lottery result (missing symbol) is output.
Note that when the jackpot determination count value matches the jackpot set value, and when the hit symbol determination count value matches the probability variation symbol set value, the jackpot gaming state and the probability variation gaming state occur. The jackpot determination count value matches the jackpot set value, but if the hit symbol determination count value does not match the probability variation symbol set value, only the jackpot gaming state occurs. When the jackpot determination count value does not match the jackpot set value, the jackpot gaming state and the probability variation gaming state do not occur.
Various methods can be used as a method of executing the lottery process. For example, various count values such as a jackpot determination count value, a winning symbol determination count value, and a miss symbol determination count value are acquired in advance, and the lottery process is sequentially performed by appropriately selecting from the acquired count values. You can also

The processing unit 31a performs various processes.
When the voltage of DC5V power (driving power) supplied from the voltage conversion circuit 21 reaches an operating voltage at which the main control circuit 31 can operate, whether or not the RAM clear switch 23 is operated (an initialization instruction signal is input). Or not). When it is determined that the RAM clear switch 23 is operated, an initialization process for initializing the RAM 33 is executed, and when the RAM clear switch 23 is not operated, a return process is executed. Thereafter, main processing and timer interrupt processing are executed.
In the initialization process, the RAM 33 is initialized. Thereby, the game information, the hit determination count value 33a, and the hit initial value count value 33b stored in the RAM 33 are initialized. In the present embodiment, when the RAM 33 is initialized, the hit determination count value 33a and the hit initial value count value 33b are initialized to “0”.
The initialization process for initializing the RAM 33 corresponds to the “initialization process” of the present invention.

In the return process, it is determined whether or not the game information or the like stored in the RAM 33 is normal (whether or not it has changed during a power failure). For example, determination information such as a checksum value and parity data is calculated based on game information stored in the RAM 33, and the calculated determination information and determination information stored in the RAM 33 (calculated during the previous power failure process). Compare judgment information). When the calculated determination information matches the determination information stored in the RAM 33, it is determined that the game information stored in the RAM 33 is normal (not changed during a power failure). In this case, the initialization process for initializing the RAM 33 is not performed, whereby the game is resumed based on the game information and the like stored in the RAM 33 (resumed from the game state at the time of power failure). On the other hand, when the calculated determination information does not match the determination information stored in the RAM 33, it is determined that the game information stored in the RAM 33 is abnormal (there may be a change during a power failure). To do. In this case, an initialization process for initializing the RAM 33 is executed. Thereby, the game is started based on the initialized game information or the like (started from the initial game state).
In the recovery process, a backup flag determination process for determining whether or not the backup flag indicating whether or not the previous power failure process has ended normally indicates that the previous power failure process has ended normally. Do. If it is determined that the backup flag indicates that the previous power failure process has not ended normally, an unauthorized operation may be performed, and therefore an initialization process is executed.

In the main process, a power failure detection signal input determination process and a hit initial value count value update process are executed.
In the power failure detection signal input process, it is determined whether or not the power failure detection signal (power failure warning signal) output from the power failure detection circuit 22 is input. When it is determined that a power failure detection signal has been input, power failure processing is executed.
In the power failure process, determination information such as a checksum value and parity data used in the above-described return process is calculated and stored in the RAM 33. In the power failure processing, when the power failure processing is normally executed (when the determination information is stored in the RAM 33), the backup flag is set to a state (for example, “1”) indicating that the power failure processing has been completed normally. Set. When the power failure process does not end normally, the backup flag is maintained in a state (for example, “0”) indicating that the power failure process did not end normally. The backup flag is retained during a power failure.
The hit initial value count value update processing is executed by the hit initial value count value update means 31d.

In the timer interrupt process, a hit determination count value update process, a hit initial value count value update process, and a lottery condition determination process are executed.
The hit determination count value update processing is executed by the hit determination count value update means 31c and the initial value setting means 33d.
The hit initial value count value update processing is executed by the hit initial value count value update means 31d.
In the lottery condition determination process, it is determined whether the lottery condition is satisfied. When the lottery condition is satisfied, the lottery process is executed. The lottery process is executed by the lottery means 31b. Then, based on the lottery result, a control signal for generating a gaming state is output. For example, if the lottery result indicates that the count value for winning determination matches the set value, a command signal or a winning gaming state for effect display on the liquid crystal display device is generated. A command signal for effect display on the liquid crystal display device and the like, and a drive signal for opening / closing or controlling the opening / closing member of the large winning opening / closing member for opening / closing the large winning opening are output.
The processing unit 31a performs various other processes.

Next, the processing of the main control circuit 31 (processing means 31a, lottery means 31b, hit determination count value update means 31c, hit initial value count value update means 31d, initial value setting means 31d) of the present embodiment, This will be described with reference to the flowcharts shown in FIGS. 2 and 3 are flowcharts for explaining the outline of the power-on process and the main process of the main control circuit 31, and FIG. 4 is a flowchart for explaining the outline of the timer interrupt process of the main control circuit 31.
First, the power-on process and main process of the main control circuit 31 will be described. The power-on process shown in FIGS. 2 and 3 is such that the main control circuit 31 can operate with the voltage of DC5V power supplied from the voltage conversion circuit 21 provided on the main control board 20 when the power is turned on. It starts when the operating voltage is reached.

In step S1, a stack pointer is set. The stack pointer indicates, for example, the address of the stack that temporarily stores data, the address of the stack that temporarily stores the return address of the main routine when returning from the subroutine to the main routine, and the like. In step S1, the stack initial address is set in the stack pointer. Thereby, the data and the return address are sequentially stored in the stack from the initial address.
In step S2, output of a power failure clear signal is started. The output of the control signal from the main control circuit 31 is prohibited by the power failure clear signal.
In step S3, wait timer processing 1 is executed.
In step S4, it is determined whether or not a power failure detection signal (power failure notice signal) is input. When the power failure detection signal is input, the process returns to step S3, and when the power failure detection signal is not input, the process proceeds to step S5.
Here, since it takes time until the voltage of DC 12V power reaches the power failure detection set value set in the power failure voltage detection circuit 22 after the supply of DC 12V power is started by turning on the power or the like, the main control circuit 31 When it is in an operable state (when the voltage of DC5V power becomes equal to or higher than the operating voltage of the main control circuit 31), the voltage of DC12V power has not reached the power failure detection set value set in the power failure detection circuit 22. Sometimes. In this case, the main control circuit 31 may malfunction due to the power failure detection signal output from the power failure detection circuit 22. The processes in steps S3 and S4 are processes for waiting until the voltage of DC 12V power is stabilized (until the power failure detection set value or more) when the power is turned on. In the present embodiment, 200 ms is set as the wait time 1 of the wait timer process 1. If the DC 12V power voltage does not reach the power failure detection set value within the wait time 1, it is determined that an abnormality has occurred, and an abnormality process is executed. For example, a light emitting device, a speaker, a liquid crystal display device, or the like is used to notify that an abnormality has occurred.
In step S5, the output of the power failure clear signal is stopped. As a result, a control signal can be output from the main control circuit 31.

In step S6, it is determined whether or not the RAM clear switch 23 is operated. Whether or not the RAM clear switch 23 is operated is determined by whether or not an initialization instruction signal is input, for example. When the RAM clear switch 23 is operated, the process proceeds to step S7, and when the RAM clear switch 23 is not operated, the process proceeds to step S8.
In step S6, the “process for determining whether or not drive power is supplied in a state where the initialization instruction signal is input” of the present invention is executed.
In step S7, the RAM clear flag RCL is set to “1”.
In step S8, the RAM clear flag RCL is set to “0”.
In step S9, the wait timer process 2 is executed. Here, a period of time is required from when the power is turned on until image information can be displayed on the liquid crystal display device. The wait timer process 2 in step S9 is a process for waiting until image information can be displayed on the liquid crystal display device.

In step S10, it is determined whether or not the RAM clear flag RCL is set to “0”. When the RAM clear flag RCL is set to “0” (when the main control circuit 31 is in an operating state when the RAM clear switch 23 is not operated), the process proceeds to step S11, and the RAM clear flag RCL is set. When it is not set to “0”, that is, when it is set to “1” (when the main control circuit 31 is in an operating state with the RAM clear switch 23 being operated), the process proceeds to step S17. .
In step S11, determination information for determining whether or not the game information or the like stored in the RAM 33 is normal (whether or not the game information stored in the RAM 33 has changed during a power failure) is calculated. . In the present embodiment, a checksum value such as game information stored in the RAM 33 is calculated as determination information.
In step S12, the determination information calculated in step S11 is used to determine whether the information stored in RAM 33 is normal (whether game information, etc. stored in AM 33 has changed during a power failure). Determine. In the present embodiment, it is determined whether or not the checksum value calculated in step S11 matches the checksum value stored in the RAM 33 (the checksum value calculated during the previous power failure process). If the calculated checksum value matches the checksum value stored in the RAM 33, the process proceeds to step S14, and if not, the process proceeds to step S17.

In step S13, it is determined whether or not the backup flag BK is set to “1”. The backup flag BK is a flag indicating whether or not the power failure process has been normally completed during the previous power failure process. That is, “1” is set when the previous power failure process is normally completed, and “0” is set when it is not normally completed. When the backup flag BK is set to “1”, the process proceeds to step S14, and when it is set to “0”, the process proceeds to step S17.
In step S13, a process of “determining whether or not the previous power failure process ended normally” is executed.
In step S14, the main control circuit 31 is in the operating state when the RAM clear switch 23 is not operated (the initialization instruction signal is not input), and the game information stored in the RAM 33 is normal. In addition, it is determined that the previous power outage process has been completed normally, and the game is resumed based on the game information and the like stored in the RAM 33 (the game is resumed from the game state at the time of the power outage). That is, the work area of the RAM 33 is set at power recovery. For example, game information or the like stored in the save area of the RAM 33 is written in the work area of the RAM 33.
In step S15, power recovery processing is executed. In the power recovery process, for example, a control signal (main command signal or drive signal) corresponding to game information or the like stored in the RAM 33 is stored in a predetermined area of the RAM 33. When the process of step S15 ends, the process proceeds to step S16.

In step S17, the main control circuit 31 is in an operating state when the RAM clear switch 23 is being operated (a state where the initialization instruction signal is input), game information stored in the RAM 33, or the like. Is abnormal or it is determined that the previous power failure process has not ended normally, and the entire area of the RAM 33 is cleared (initialized). For example, an initial value “0” is set in the entire area of the RAM 33. A method of reading the initial value stored in the ROM 32 and setting it in the RAM 33 can also be used.
In step S18, the work area of the RAM 33 is initialized. In this initial setting, the initial value stored in the ROM 32 is read, and the read initial value is set in the work area of the RAM 33.
In step S <b> 19, the random number 34 a generated by the random number generation circuit 34 is acquired and stored in the RAM 33. As described above, the update processing of the first initial value (start value S) in the first cycle of the hit determination count value 33a after initialization of the RAM 33 and the hit determination count value 33a after initialization of the RAM 33 is started. It is used when setting the period (start period T) to be performed. In the present embodiment, the first initial value (start value S) of the first period of the hit determination count value 33a after initialization of the RAM 33 is set using the random number 34a acquired in step S19.
In step S20, RAM clear processing is executed. In the RAM clearing process, for example, a RAM clear notification command indicating that the RAM 33 has been initialized and a test command for inspecting each control circuit and gaming device are created and stored in the transmission area of the RAM 33. When a RAM clear notification command signal is output from the main control circuit 31, image information for notifying that the RAM 33 has been initialized is displayed on the liquid crystal display device. Further, when a test command is output from the main control circuit 31, each control circuit and each gaming device are inspected.
Note that, by the processing in steps S11, S12, S14, S17, and S18, the main control circuit 31 (processing unit 31a) performs a recovery process when the power is turned on.

In step S16, interrupt initialization is performed. In the interrupt initial setting, an interrupt cycle for performing timer interrupt processing in the main processing of the main control circuit 31 (processing means 31a) is set. In the present embodiment, 4 ms is set as the interrupt cycle. Of course, the main process is executed at a cycle shorter than the timer interrupt cycle.
In step S21, interrupt permission is set. Due to the interrupt permission setting, timer interrupt processing for each timer interrupt cycle set in step S16 is executed.

In step S22, “A” is set in the watchdog timer clear register WCL. When “A”, “B”, and “C” are sequentially set in the watchdog timer clear register WCL, the watchdog timer is cleared.
In step S23, it is determined whether or not a power failure detection signal (power failure notice signal) from the power failure detection circuit 22 is input. If a power failure detection signal is not input, the process proceeds to step S24. If a power failure detection signal is input, the process proceeds to step S25.
In step S24, a process for updating the count value for hit initial value 33b used for determining the first initial value for each cycle of the count value for hit determination 33a is performed. Here, when the RAM 33 is initialized, the count value for hit initial value 33b starts to be updated from the second initial value. As the second initial value, typically, when the RAM 33 is initialized, an initial value (for example, “0”) of the hit initial value count value 33b of the hit initial value count value storage area of the RAM 33 is used. It is done. In this case, when the update of the hit initial value count value 33b is started, it is only necessary to update the second update value from the initial value of the hit initial value count value 33b stored in the RAM 33.
In step S24, a non-hit determination count value other than the hit initial value count value (excluding the hit determination count value used in the lottery for determining whether or not to generate a win game state advantageous to the player). The update process can also be performed. For the non-winning determination count value, a reach display determination count value for determining whether or not to select a display mode including a reach display as a display mode for displaying the lottery result, and a variation display pattern of the lottery result are determined. For example, a count value for determining a variation display pattern is included. The non-hit determination count value is updated by the non-hit determination count value update means corresponding to each non-hit determination count value.
The hit initial value count value 33a is updated by the hit initial value count value updating unit 31d in step S24.
After finishing the process of step S24, it returns to step S22.
The main process of the main control circuit 31 (processing unit 31a) is executed by the processes of steps S22 to S24.
In this main process, the timer interrupt process shown in FIG. 4 is executed every timer interrupt period (for example, 4 ms).

In step S25, interrupt prohibition setting is performed. Due to the interrupt prohibition setting, subsequent timer interrupt processing is prohibited, and rewriting of game information and the like stored in the RAM 33 is prohibited.
In step S26, output of the power failure clear signal is started. Thereby, the output of the signal from the main control circuit 31 is stopped, and the driving of the gaming machine is stopped. When the driving of the gaming machine is stopped, power consumption is suppressed, and power for a stop process by the main control circuit 31 (processing unit 31a) is secured.
In step S27, whether or not the game information or the like stored in the RAM 33 is normal during the next restoration process of the main control circuit 32 (processing means 31a) (the game information or the like stored in the RAM 33 is being interrupted). Determination information for determining whether or not there is a change is created. In the present embodiment, determination information is calculated based on game information and the like stored in the RAM 33. In this embodiment, a checksum value such as game information stored in the RAM 33 is calculated. The game information stored in the RAM 33 and the calculated checksum value are stored in the save area of the RAM 33 as backup information. The determination information is not limited to the chuck sum value, and various determination information such as parity data can be used.
In step S28, when the processing of step S27 (processing for storing the game information and the like stored in the RAM 33 and the calculated checksum value in the save area of the RAM 33) is completed normally, the backup flag BK is set to the power failure processing. Set to “1” to indicate normal termination. When the process of step S27 is not normally completed, the backup flag BK is in a “0” state indicating that the power failure process has not been normally completed (a state when the RAM 33 is initialized). Retained.
In step S29, the watchdog timer is cleared. For example, “A”, “B”, and “C” are sequentially set in the watchdog timer clear register WCL. When the watchdog timer is cleared in step S29, the main control circuit 31 (processing unit 31a) causes the main control circuit 31 (processing unit 31a) to change the voltage of DC5V power supplied from the voltage conversion circuit 21 by turning on the power again. It waits until it becomes more than the operating voltage of 31a) (until power recovery).
In addition, the power failure process of the main control circuit 31 (processing means 31a) is performed by the process of step S25-step S29.

Next, timer interrupt processing of the main control side circuit 31 (processing means 31a) will be described. The timer interrupt process shown in FIG. 4 is executed every timer interrupt period (4 ms in the present embodiment) set in step S16 in the main process shown in FIG.
In step T1, “B” is set in the watchdog timer clear register WCL. At this time, the watchdog timer clear register WCL is set to “B” following the setting of “A” in step S22 (main processing) of FIG.
In step T2, the interrupt flag is cleared. When the interrupt flag is cleared, the timer interrupt cycle for determining the processing timing of the next timer interrupt process is started.
In step T3, various signals are input. The input signal is written in the input area of the RAM 33 as input information. As the input signal, for example, a start winning ball signal indicating that a game ball has entered the start winning port, a big winning ball signal indicating that a game ball has entered the big winning port, or the like is used.
In step T4, a timer subtraction process is performed. For example, when the symbols are variably displayed on the liquid crystal display device, the symbol variation display period is subtracted. In this case, when the variable display period becomes “0”, it is possible to determine when the variable display of the symbols on the liquid crystal display device ends. Alternatively, the input determination period of the ACK signal (response signal) after outputting the signal is subtracted. As a result, it is possible to determine that an abnormality has occurred because the ACK signal has not been input before the input determination period reaches “0”. In the present embodiment, since timer interrupt processing is executed every 4 ms, each period is subtracted by 4 ms.

In step T5, the hit determination count value 33a stored in the RAM 33 is updated. When a plurality of hit determination count values are used, the plurality of hit determination count values stored in the RAM 33 are updated.
In the present embodiment, in the first cycle update process of the hit determination count value 33a after initialization of the RAM 33, the start value S is determined using the random number 34a acquired in step S19, and the determined start value S is It is set as the first initial value of the first period of the hit determination count value 33a. On the other hand, in the update process in each cycle after the second cycle of the hit determination count value 33a after initialization of the RAM 33, the hit initial value count value 33b is changed to the first initial value in each cycle of the hit determination count value 33a. Set as a value. The process of setting the first initial value of each cycle of the hit determination count value 33a is executed by the initial value setting means 31d. The process of setting the first initial value of the first period of the hit determination count value 33a by the initial value setting means 31d can also be executed in step S19. In step T5, the hit determination count value 33a is sequentially updated from the first initial value set by the initial value setting means 31d. When the hit determination count value 33a reaches a value immediately before the first initial value of the cycle, the initial value setting means 31d sets the first initial value of the next cycle, and the set next cycle The update process of the next cycle is executed from the first initial value. When the hit determination count value 33a reaches the second value within the period, the updating process is continued from the first value.
In the present embodiment, the first initial value in the first period after the RAM 33 is initialized is generated based on the unique identification information 32a generated by the random number generation circuit 34 and unique to each gaming machine. Is set using random numbers. For this reason, the period until the count value 33a for hit determination reaches the set value (win value) for the first time (in the first cycle) after the RAM 33 is initialized differs for each gaming machine. Therefore, even if the RAM 33 is illegally initialized, it is difficult to predict when the hit determination count value 33a first matches the set value, thereby preventing illegal games due to the illegal initialization of the RAM 33. it can.
If the RAM 33 is not initialized when the main control circuit 31 (processing means 31a) starts operating, the game information, the hit determination count value 33a, and the hit initial value count value 33b are not initialized. . In this case, the hit determination count value 33a and the hit initial value count value 33b are updated from the values before the power failure.

  In step T5, an update process similar to the update process of the hit initial value count value 33b in step S24 is also performed. That is, update processing of the non-hit determination count value 33b is also performed. In this way, by performing the update process of the hit initial value count value in each of the main process and the timer interrupt process in the main process, the randomness of the hit initial value count value is further increased. The update process of the hit determination count value 33b in step T5 is executed by the hit determination count value update means 31c and the initial value setting means 31d, and the update process of the hit initial value count value 33b is performed by the hit initial value count. This is executed by the value updating means 31d.

In step T6, a prize ball control process is performed. In the winning ball control process, input information indicating that a game ball has entered a winning opening (general winning opening, starting winning opening, large winning opening, etc.) is read from the input area of the RAM 33 and corresponds to the read input information. A signal (prize ball command signal) indicating the number of prize balls (corresponding to a prize opening into which a game ball has entered) is stored in the transmission area of the RAM 33.
In step T7, fraud detection processing is performed. For example, the input information is read from the input area of the RAM 33, and the input information indicating that the jackpot gaming state in which the opening / closing control of the winning opening opening / closing member for opening / closing the winning opening is occurring is not input. Then, it is determined whether or not input information indicating that the game ball has entered the big winning opening is input. When fraud is detected, prize ball abnormality information is written in the transmission area of the RAM 33.

In step T8, a lottery process is performed. For example, input information is read from the input area of the RAM 33, and input information indicating a condition for performing a lottery to determine whether or not to generate a winning gaming state advantageous to the player is input (when the lottery condition is satisfied) ) Obtains (reads out) the hit determination count value 33a stored in the RAM 33. Then, the acquired winning determination count value 33a is compared with the set value (winning value) stored in the ROM 32 (lottery), and the comparison result is output (the lottery result is output). Or not).
For example, in the case of generating a jackpot gaming state and a probability variation gaming state, when a start winning port entry signal indicating that a game ball has entered the starting winning port is input, a jackpot determination count value is acquired, The acquired jackpot determination count value is compared with the set value (jackpot set value). When the acquired jackpot determination count value does not coincide with the jackpot set value, the lost symbol determination count value is acquired and output as a lottery result. When the acquired jackpot determination count value matches the jackpot setting value, the winning symbol determination count value is acquired, and the acquired winning symbol determination count value is compared with the set value (probability changing symbol setting value). When the acquired winning symbol determination count value does not coincide with the probability variation symbol set value, the winning symbol determination count value indicating the probability variation large symbol is output as a lottery result. When the acquired winning symbol determination count value does not coincide with the probability variation symbol setting value, the winning symbol determination count value indicating the normal jackpot symbol is output as the lottery result.
Next, output information is set based on the lottery result and written to the output area of the RAM 33. For example, if the lottery result indicates that the jackpot determination count value matches the jackpot setting value and the winning symbol determination count value matches the probability variation symbol setting value, the jackpot gaming state and the probability variation gaming state are Decide to generate. Also, if the lottery result indicates that the jackpot determination count value matches the jackpot set value, but the winning symbol determination count value does not match the probability variation symbol set value, the jackpot gaming state Decide to generate. The hit fluctuation display pattern is determined based on the hit fluctuation display pattern count value updated by the hit fluctuation display pattern count value updating means.
Then, the winning symbol information indicating the probability variation symbol or the normal jackpot symbol and the winning variation display pattern information indicating the winning variation display pattern are written in the output area of the RAM 33. In addition, information for generating a jackpot gaming state (for example, a driving signal for driving the big prize opening / closing member) and information for generating a probability changing gaming state (for example, high probability table selection information) are output to the output area of the RAM 33. Write.
On the other hand, when the jackpot determination count value does not coincide with the jackpot set value, the missing symbol is determined based on the missed symbol determination count value updated by the missing symbol determination count value updating means, and the variation variation display is performed. A deviation fluctuation display pattern is determined based on the deviation fluctuation display pattern count value updated by the pattern count value updating means. Then, the determined symbol information indicating the error symbol and the error variation display pattern information indicating the error variation display pattern are written in the output area of the RAM 33.
The lottery process at step T8 is executed by the lottery means 31b.

In step T9, signal output processing is performed. For example, the output information written in the output area of the RAM 33 is read, and various control signals (command signal and drive signal) are output based on the read output information.
In step T10, “C” is set in the watchdog timer clear register WCL. As a result, “A”, “B”, and “C” are sequentially set in the watchdog timer clear register WCL, so that the watchdog timer is cleared.
In step T11, the register is switched (returned). Here, when the timer interrupt process is started, the main control circuit 31 (processing unit 31a) saves the information stored in the register to the stack, and the information stored in the register used in the main process. Is prevented from being destroyed. In step T11, since the timer interrupt process is completed, the information saved in the stack is stored in the read register.

Next, the operation of the present embodiment will be described with reference to FIG. 5 showing the change state of the hit determination count value and the hit initial value count value. Hereinafter, a case where one hit determination count value 33a and one hit initial value count value 33b are used will be described. In addition, operations related to the change state of the hit determination count value 33a and the hit initial value count value 33b will be mainly described, and description of other operations will be omitted. In FIG. 5, the hit determination count value is indicated by a solid line, and the hit initial value count value is indicated by a broken line.
In the present embodiment, in the first cycle of the hit determination count value 33a after the RAM 33 is initialized, the start value S determined based on the random number 34a generated by the random number generation circuit 34 is changed to the first value S. The update is executed by setting the initial value to 1, and the update is executed by setting the count value 33b for the hit initial value to the first initial value of each cycle in each cycle after the second cycle. Has been.
The hit determination count value 33a is a first initial value in the first range “0” to “299” in which the reset value “0” is the first value and the turn-back value “299” is the second value. From the value, the first update value “1” is updated (added) in the direction (addition direction) from the reset value “0” to the return value “299”, and the count value 33b for the initial value is the reset value “0”. From the reset value “0” in the second range “0” to “299”, from the reset value “0” to the return value “299”, with the third value as the third value and the return value “299” as the fourth value. It is assumed that the second update value “1” is updated (added) in the direction (addition direction). In this case, one period (one cycle) of the hit determination count value 33a is a range from the first initial value being updated (added) by “1” “300” times. Further, when the count value for hit determination 33a and the count value for hit initial value 33b reach the return value “299”, the update (addition) is continued from the reset value “0”.

When the power of the pachinko machine is turned on and AC24V power is supplied to the power supply circuit 11 (power supply board 10), the power supply circuit 11 converts the AC24V power into DC34V power and DC12V power. The AC 24V power and the AC 12V power are supplied from the power supply board 10 to the main control board 20 via the power lines L1 and L2. The voltage conversion circuit 21 provided on the main control board 20 converts DC12V power supplied to the main control board 20 into DC5V power, and the main control circuit 31 and the RAM 33 are connected via the terminal 30b of the main control circuit IC30. Supply as drive power.
When the DC5V power voltage reaches the operating voltage, the main control circuit 31 (processing means 31a), based on the initialization instruction signal input from the RAM clear switch 23, the determination information stored in the RAM 33, or the backup data, It is determined whether or not the RAM 33 is to be initialized.

Consider a case where the main control circuit 31 initializes the RAM 33 at time t1. In the present embodiment, at the time point t1 when the RAM 33 is initialized, the count value for hit determination 33a and the count value for hit initial value 33b of the TAM 33 are set to “0” (= reset value). When the hit determination count value 33a is updated by the hit determination count value updating unit 31c immediately after the RAM 33 is initialized, the hit determination count value 33a starts to be updated from the reset value “0”. In this case, as described above, it is possible to predict a period from when the RAM 33 is initialized until the hit determination count value 33a first matches the set value (in FIG. 5, the hit value “140”).
In the present embodiment, the initial value setting means 31d has a random number (specific to each pachinko machine) generated by the random number generation circuit 34 in the first cycle of the determination count value 33a after the RAM 33 is initialized. The start value S determined based on the unique identification information 32a is set as the first initial value in the first period (step S19). Note that the random number generation circuit 34 is preferably configured such that the random number changes within the change range of the hit determination random number 33a. For example, change range information (for example, the fifth value and the sixth value indicating the change range of the start value S) indicating the change range of the random number is output from the main control circuit 31 (processing unit 31a) to the random number generation circuit 34. In addition, the change range of the random number generated by the random number generation circuit 34 can be set.

The hit determination count value 33a reaches the return value “299” at time t2 after the first period of update is started with the start value S determined based on the random number as the first initial value at time t1. However, the update from the reset value “0” is continued because the update in the first cycle is not completed. Then, at the time t3 when the update for one cycle (the update of “300” times) is performed from the initial value “S”, the hit determination count value 33a is set to a value immediately before the first initial value “S”. Reach. Thereby, the update (addition) of the first period of the hit determination count value 33a is completed.
The hit determination count value 33a is updated in the second cycle when the update in the first cycle is completed at time t3. Here, the initial value setting means 31d uses the hit initial value count value 33b in each cycle after the second cycle of the hit determination count value 33a after the RAM 33 is initialized. A first initial value 33a is set. In FIG. 5, at time t3, the hit initial value count value 33b is “120”, and “120” is set as the first initial value of the second cycle of the hit determination count value 33a. Update of the second cycle is started from the value “120”.
Thereafter, similarly, the hit determination count value 33a is updated within the first range while the first initial value is updated using the hit initial value count value 33b every cycle.

As described above, in the present embodiment, an initial value update type hit determination count value is used as the hit determination count value 33a, and one cycle of the hit determination count value 33a after the RAM 33 is initialized. In the eye, the start value S determined based on the random number generated by the random number generation circuit 34 is set as the first initial value in the first period, and in the second period and thereafter, the count value for the winning initial value is set. 33b is set as the first initial value of each period. Here, since the random number generation circuit 34 generates a random number based on the unique identification information 32a unique to each gaming machine, the start value S is different for each gaming machine.
Thus, a period from when the RAM 33 is initialized until the hit determination count value 33a first matches the set value (win value) (when the hit determination count value 33a matches the set value) is predicted. It becomes difficult. Also, in each cycle after the second cycle, the period from the start of each cycle until the hit determination count value 33a matches the set value (win value) (the hit determination count value 33a matches the set value) It is difficult to predict when to perform the operation. Therefore, an illegal game due to an illegal initialization of the RAM 33 can be prevented.

In the first embodiment, the first initial value of the first period of the hit determination count value 33a after the initialization of the RAM 33 is generated based on the unique identification information 32a unique to each gaming machine. Although the start value S determined based on the random number is set, the update process of the first period of the hit determination count value 33a after the initialization of the RAM 33 is performed based on the unique identification information 32a unique to each gaming machine. It can also be configured to start after the elapse of the start period T determined based on the generated random number.
In the following, a second embodiment will be described in which the timing for starting the update process of the hit determination count value 33a and the hit initial value count value 33b is delayed after the RAM 33 is initialized.
In the second embodiment, the hit initial value count value 33b is updated in step S24, the hit determination count value 33a is updated in step T5, and the hit initial value count value 33b is updated. However, only the process for updating the count value for hit initial value 33b and the process for updating the count value for hit determination 33a will be described below.

  In step S24 and step T5, the hit initial value count value 33b is updated. In the present embodiment, when the RAM 33 is initialized, when the period (start period T) determined based on the random number generated by the random number generation circuit 34 has elapsed since the RAM 33 was initialized, Update processing of the count value for determination 33a and the count value for hit initial value 33b is started. That is, when the RAM 33 is initialized, the start period T for starting the update of the count value for initial value 33b after the RAM 33 is initialized is determined using the random number obtained in step S19. Then, when the determined start period T elapses after the RAM 33 is initialized, the process for updating the hit initial value count value 33b is started. The hit initial value count value 33b is sequentially updated within the second range from the second value (“0” in the present embodiment) by the second update value.

In step T5, the hit determination count value 33b is updated. In this embodiment, when the RAM 33 is initialized, when the period (start period T) determined based on the random number generated by the random number generation circuit 34 has elapsed since the RAM 33 was initialized, Update processing of the count value for determination 33a and the count value for hit initial value 33b is started. That is, when the RAM 33 is initialized, the start period T for starting the update of the hit determination count value 33a after the RAM 33 is initialized is determined using the random number acquired in step S19. Then, the update of the hit determination count value 33a is started when the determined start period T has elapsed after the RAM 33 is initialized. Whether or not the start period T has elapsed since the start of the RAM 33 can be determined by the timer subtraction process in step T4.
The initial value setting unit 31d uses the first count value 33b for the first hit initial value in each cycle of the hit determination random number 33a when the start period T elapses after the RAM 33 is started. Set the initial value of. In step T5, the hit determination count value 33a is updated for each first update value from the first initial value set by the initial value setting means 31d.

The operation of the second embodiment will be described with reference to FIG. 6 showing the change state of the hit determination count value and the hit initial value count value. Each condition is the same as that described in FIG. In FIG. 6, the hit determination count value is indicated by a solid line, and the hit initial value count value is indicated by a broken line.
When the RM 33 is initialized at the time point t1, the start period T is determined based on the random number generated by the random number generation circuit 34.
Then, at the time t2 when the start period T has elapsed from the time t1, the hit determination count value 33a and the hit initial value count value 33b are updated. At time point t2, the count value for hit initial value 33b is the value “0” at the time when the RAM 33 is initialized. Therefore, the initial setting means 31d sets the first initial value in the first cycle of the count value for hit determination 33a. As the value, the value “0” of the count value 33b for hit initial value is set. Accordingly, the hit determination count value 33a and the hit initial value count value 33b are updated from “0” at time t2.
The count value for hit determination 33a is a return value at a time point t3 when updating for one cycle from the first initial value “0” (“300” times of updating) is performed after starting the updating process at the time point t2. Reach "299". Thereby, the update (count) of the first period of the count value for hit determination 33a is completed.
The hit determination count value 33a starts to be updated in the second cycle when the update in the first cycle is completed at time t3. Here, the initial value setting means 31d sets the hit initial value count value 33b as the first initial value in the second period. In FIG. 6, at the time t3, the hit initial value count value 33b is “130”, “130” is set as the first initial value of the second cycle of the hit determination count value 33a, and the first initial value is set. The update of the second cycle is started from “130”.
Thereafter, similarly, the hit determination count value 33a is updated within the first range while the first initial value is updated using the hit initial value count value 33b every cycle.

As described above, in the present embodiment, the initial value update type hit determination count value is used as the hit determination count value 33a, and when the RAM 33 is initialized, the hit determination count value 33a and the hit determination count value are determined. The update processing of the initial value count value 33b is started after the start period T determined based on the random number generated by the random number generation circuit 34 has elapsed. Here, since the random number generation circuit 34 is generated based on the unique identification information 32a unique to each gaming machine, the start period T is different for each gaming machine.
Thus, a period from when the RAM 33 is initialized until the hit determination count value 33a first matches the set value (win value) (when the hit determination count value 33a matches the set value) is predicted. It becomes difficult. Also, in each cycle after the second cycle, the period from the start of each cycle until the hit determination count value 33a matches the set value (win value) (the hit determination count value 33a matches the set value) It is difficult to predict when to perform the operation. Therefore, an illegal game due to an illegal initialization of the RAM 33 can be prevented.

In the second embodiment, when the RAM 33 is initialized, the hit determination is made after the start period T determined based on the random number generated by the random number generation circuit 34 has elapsed since the RAM 33 was initialized. Although the update process for the random number for random use 33a and the random number for random start value 33b is started, the update process for the random number for positive initial value 33b can be started before the update process for the random number for hit determination 33a.
Below, when the RAM 33 is initialized, the initial value random number update process is started, and the start period determined based on the random numbers generated by the random number generation circuit has elapsed since the RAM 33 was initialized. A third embodiment for starting the hit determination random number update process later will be described.
The gaming machine of the third embodiment can be configured similarly to FIG.
Since the process of the third embodiment executes the same process as the flowcharts shown in FIGS. 2 to 4 except for the update process of the hit determination random number 33a in step T5, Only the update processing of the determination count value 33a will be described.

In step T5, the hit determination count value 33b is updated. In the present embodiment, when the RAM 33 is initialized, when the period (start period T) determined based on the random number generated by the random number generation circuit 34 has elapsed since the RAM 33 was initialized, Update processing of the determination count value 33a is started. That is, when the RAM 33 is initialized, the start period T for starting the update of the hit determination count value 33a after the RAM 33 is initialized is determined using the random number acquired in step S19. When the determined start period T elapses after the RAM 33 is initialized, the initialization unit 31d sets the first initial value in the first cycle of the hit determination count value 33a to the hit initial value count value 33b. Set as a value.
Here, in the present embodiment, the update process of the hit initial value count value 33b is started from the time point t1 when the RAM 33 is initialized, as in the first embodiment. For this reason, at the time t2 when the start period T has elapsed since the RAM 33 was initialized, the hit initial value count value 33b is an arbitrary value. As a result, the first initial value of the first period of the hit determination count value 33a after the RAM 33 is initialized and when the update process of the hit determination count value 33a is started and after the RAM 33 is initialized are set. Randomly set.

The operation of the third embodiment will be described with reference to FIG. 7 showing the change state of the hit determination count value and the hit initial value count value. Each condition is the same as that described in FIG. In FIG. 7, the hit determination count value is indicated by a solid line, and the hit initial value count value is indicated by a broken line.
At the time point t1 when the RAM 33 is initialized, the count value for hit initial value 33b is started to be updated with the reset value “0” as the second initial value.
Then, at the time t2 when the start period T has elapsed since the initialization of the RAM 33, the update process of the hit determination count value 33a is started. At this time, the initial value setting means 31d sets the hit initial value count value 33b as the first initial value in the first cycle of the hit determination count value 33a. In FIG. 7, the hit initial value count value is “60” at time t2, and the hit determination count value 33a is the first count in the first cycle at the time t2. The initial value is set, and the first cycle update is started from the first initial value “60”.
The hit determination count value 33a reaches the return value “299” at the time point t3 after starting the update of the first cycle from the first initial value “60” at the time point t2, but the update of the first cycle is completed. Therefore, the update from the reset value “0” is continued. Then, at the time t4 when the update for one cycle from the initial value “60” (“300” update) is performed, the hit determination count value 33a is the first initial value “60” in the first cycle. The previous value “59” is reached. Thereby, the update (count) of the first period of the count value for hit determination 33a is completed.
When the update process for the first cycle is completed at time t4, the initial value setting unit 31d sets the count value 33b for winning initial value as the first initial value for the second cycle. In FIG. 7, the count value 33b for the hit initial value is “170” at the time point t4, “170” is set as the first initial value in the second cycle of the count value 33a for the hit determination, and the first initial value Updating of the second cycle starts from “170”.
Thereafter, similarly, the hit determination count value 33a is updated within the first range while the first initial value of each cycle is updated using the hit initial value count value 33b for each cycle. The
The hit initial value count value 33b may be updated before the start period T elapses from the initialization of the RAM 33, and may be started at an arbitrary point in the start period T.

As described above, in this embodiment, the initial value update type hit determination count value is used as the hit determination count value 33a, and the random number generated by the random number generation circuit 34 after the RAM 33 is initialized. After the start period T determined on the basis of elapses, update processing of the hit determination count value 33a is started. As described above, the start period T determined based on the random number generated by the random number generation circuit 34 is different for each gaming machine.
Further, the update process of the initial value count value 33b is started before the start period T elapses after the RAM 33 is initialized (including the time when the RAM 33 is initialized). Therefore, the hit initial value count value 33b at the time when the start period T has elapsed since the initialization of the RAM 33 is a random value, and the hit determination count value 33a is first set to the set value after the RAM 33 is initialized. It will be very difficult to predict the time until matching.
Therefore, an illegal game due to an illegal initialization of the RAM 33 can be prevented more reliably.

  In the first to third embodiments, the power line L3 is connected to the power supply board 10 and the main control board 20 in order to supply the backup power from the backup capacitor 12. For this reason, when the power line L2 is short-circuited in a state where the power line L3 is short-circuited or disconnected, the game information stored in the RAM 33 may be erased. In this case, when the short circuit of the power supply line L2 is canceled and the supply of DC 12V power is started, the RAM 33 is initialized by the return process of the main control circuit 31. Even in this case, as described above, since it is difficult to predict when the hit determination count value becomes equal to the set value, it is possible to prevent an illegal game from being performed.

  In the first to third embodiments, since the RAM clear switch 23 is provided on the main control board 20, the signal line for transmitting the operation signal (initialization instruction signal) of the RAM clear switch 23 is main-controlled. There is no need to connect to the substrate 20. Since the signal line for transmitting the initialization instruction signal is not connected to the main control board 20, the RAM 33 is illegally initialized by short-circuiting the power line L2 for a short time while the initialization instruction signal is illegally inserted into the signal line. Can be prevented.

The present invention is not limited to the configuration described in the embodiment, and various changes, additions, and deletions are possible.
The configuration of the power supply substrate 10 and the configuration of the main control substrate 20 are not limited to the configurations described in the embodiments.
The change range (first range or second range), update value (first update value or second update value), update direction, etc. of the hit determination count value 33a or the hit initial value count value 33b are as follows: It can be selected as appropriate.
The present invention can be configured by individually combining the configurations described in the embodiments individually or in combination.
The voltage value of the DC power supplied to the main control board 20 can be selected as appropriate.
Although the main control board 20 provided with the main control circuit 31 has been described, the present invention can also be applied to other control boards provided with other control circuits.
Although the case where it is configured as a pachinko machine has been described, the present invention can be configured as various gaming machines other than the pachinko machine.

The present invention can be configured as follows.
“(Aspect 1) A gaming machine that compares a count value for hit determination with a set value due to establishment of a lottery condition, and generates a hit gaming state when the count value for hit determination matches the set value,
A control circuit, a storage circuit, a random number generation circuit, a control board provided with the control circuit, the storage circuit and the random number generation circuit, a power supply circuit for supplying power to the control board, and the power supply circuit Provided with the power supply board provided,
The memory circuit includes game information that changes with the game, a count value for hit determination updated within the first range, and a hit initial value updated within the second range within the first range. Count value, unique identification information unique to each gaming machine is stored,
The random number generation circuit generates a random number based on the unique identification information stored in the storage circuit,
When the drive power is supplied, the control circuit executes a return process, and then executes a main process and a timer interrupt process.
In the restoration process, it is determined whether or not the information stored in the storage circuit is normal based on the determination information stored in the storage circuit, and the information stored in the storage circuit is not normal If it is determined, the game information stored in the storage circuit, a count value for hit determination and an initialization process for initializing the count value for hit initial value are executed,
In the main process, the power failure detection signal input determination process and the initial value count value update process are executed,
In the power failure detection signal input determination process, it is determined whether or not a power failure detection signal indicating that a power failure has occurred is input, and when it is determined that a power failure detection signal has been input, it is used in the return processing Determination information is calculated and stored in the storage circuit,
In the hit initial value count value update process, the hit initial value count value is updated by a second update value from the second initial value within the second range,
In the timer interruption process, a count value update process for winning determination and a lottery condition determination process are executed,
In the hit determination count value update process, the hit determination count value is updated from the first initial value by the first update value over one period within the first range, and for each period. When the first initial value is updated using the count value for the initial value and the initialization process is executed, the first random value is generated by the random number generation circuit after the initialization process is executed. After the start period determined based on a random number has elapsed, the hit determination count value is updated,
In the lottery condition determination process, it is determined whether or not the lottery condition is satisfied. When it is determined that the lottery condition is satisfied, the winning determination count value is compared with a set value, and the winning determination count is determined. When the value matches the set value, a control signal for generating a winning gaming state is output. Can be configured.

In this aspect, after the initialization process is executed, the hit determination count value is updated after a start period determined based on the random number generated by the random number generation circuit has elapsed.
In this aspect, after the initialization process is executed, the count value for hit determination is updated after a start period determined using a random number generated based on unique identification information that differs for each gaming machine has elapsed. Therefore, it is difficult to predict a period from when the initialization process is executed until the hit determination count value first matches the setting. Therefore, an illegal game due to an illegal initialization of the memory circuit can be prevented.

  In addition, “(Aspect 2) is a gaming machine according to Aspect 1, wherein in the hit initial value count value update process, when the initialization process is executed, the initialization process is executed and then the start is performed. The game machine is characterized by starting to update the count value for winning initial value before the period elapses. "

In this aspect, after the initialization process is executed, the update of the initial value count value is started before the start period determined based on the random number generated by the random number generation circuit elapses. The time to start updating the initial value count value may be before the hit determination random number update process is started, or may be the time when the initialization process is executed.
In this aspect, the first initial value of the first cycle of the hit determination count value after the initialization process is executed can be set at random. Therefore, an illegal game due to an illegal initialization of the memory circuit can be more effectively prevented.

  Further, “(Aspect 3) is the gaming machine according to any one of Claims 1, Aspects 1 and 2, wherein in the timer interruption process, the count value update process for winning determination, the lottery condition determination process, and the initial value for winning are determined. The game machine is characterized in that the count value update process is executed. ”

In this aspect, the hit initial value count value update process is executed in the main process of the control circuit and in the timer interrupt process in the main process.
In this aspect, the count value for the hit determination value, that is, the first initial value of each cycle of the count value for the hit determination can be changed more randomly. Is more difficult to predict.

  Further, “(Aspect 4) is a gaming machine according to any one of claims 1 and 1 to 3, wherein the control board is provided with a voltage conversion circuit and a power failure detection circuit. The voltage of power supplied from the power supply circuit is converted into a voltage corresponding to the voltage of drive power of the control circuit, and the power failure detection circuit detects that the power supplied from the power supply circuit is reduced. In some cases, the power failure detection signal is output.

In this aspect, the voltage conversion circuit and the power failure detection circuit are provided on the control board.
Thereby, it is not necessary to connect the power line for supplying the drive power of the control circuit provided in the control board to the control board. As a result, it is possible to prevent the influence of noise mixed in the power line for supplying the driving power for the control circuit, and it is possible to prevent the unauthorized operation on the power line for supplying the driving power for the control circuit. .
In addition, it is not necessary to connect a signal line for transmitting the initialization instruction signal to the control board, thereby preventing an unauthorized operation on the signal line for transmitting the initialization instruction signal.

  In addition, “(Aspect 5) is a gaming machine according to any one of claims 1 and 1, wherein the control board is provided with an initialization instruction means for outputting an initialization instruction signal. When the drive power is supplied, the circuit determines whether the drive power is supplied in a state where the initialization instruction signal is input, and the drive power is supplied in the state where the initialization instruction signal is input. If it is determined that the power is supplied, the main process and the timer interrupt process are executed after the initialization process, and the drive power is supplied in a state where the initialization instruction signal is not input. When the game machine is determined, the main process and the timer interrupt process are executed after the return process is executed.

In this embodiment, an initialization instruction switch for outputting an initialization instruction signal for instructing initialization of the memory circuit is provided on the control board. The control circuit initializes the storage means when operating in a state where the initialization instruction signal is output from the initialization instruction switch.
In this aspect, there is no need to connect a signal line for transmitting an initialization instruction signal from the initialization instruction switch to the control board. Thereby, an unauthorized operation on the signal line for transmitting the initialization instruction signal can be prevented.

  Further, “(Aspect 6) is a gaming machine according to any one of claims 1 and 1 to 5, wherein the power supply board is provided with a backup power supply for supplying backup power to the control board. Can be configured as a game machine.

In this aspect, a backup power supply for supplying backup power to the control board is provided on the power supply board.
As a result, as in the case where a backup power supply is provided on the control board, it is possible to prevent an illegal act of intentionally setting the game state by removing the control board.

1 is a diagram showing a schematic configuration of a first embodiment of the present invention. It is a flowchart explaining the outline of the power-on process (a main process is included) of the 1st Embodiment of this invention. It is a flowchart explaining the outline of the power-on process (a main process is included) of the 1st Embodiment of this invention. It is a flowchart explaining the outline of the timer interruption process of the 1st Embodiment of this invention. FIG. 6 is a diagram showing a change state of a hit determination count value and a hit initial value count value according to the first embodiment of the present invention. It is a figure which shows the change state of the count value for winning determination and the count value for winning initial value of the 2nd Embodiment of this invention. It is a figure which shows the change state of the count value for winning determination and the count value for winning initial value of the 3rd Embodiment of this invention. It is a figure which shows the change state of the count value for hit determination of a prior art example.

Explanation of symbols

10 Power Supply Board 11 Power Supply Circuit 12 Backup Capacitor (Backup Power Supply)
20 Main control board (control board)
21 Voltage conversion circuit 22 Power failure detection circuit 23 RAM clear switch (initialization instruction switch)
30 Main control circuit IC
31 main control circuit 31a processing means 31b lottery means 31c hit determination count value update means 31d hit value initial value count value update means 31e initial value setting means 32 ROM
32a Unique identification information 33 RAM
33a Count value for hit determination 33b Count value for initial value 34 Random number generation circuit (random number generation means)

Claims (1)

Due to the establishment of the lottery condition, a game machine that compares a count value for hit determination with a set value and generates a hit gaming state when the count value for hit determination matches the set value,
A control circuit, a storage circuit, a random number generation circuit, a control board provided with the control circuit, the storage circuit and the random number generation circuit, a power supply circuit for supplying power to the control board, and the power supply circuit Provided with the power supply board provided,
The memory circuit includes game information that changes with the game, a count value for hit determination updated within the first range, and a hit initial value updated within the second range within the first range. Count value, unique identification information unique to each gaming machine is stored,
The random number generation circuit generates a random number based on the unique identification information stored in the storage circuit,
When the drive power is supplied, the control circuit executes a return process, and then executes a main process and a timer interrupt process.
In the restoration process, it is determined whether or not the information stored in the storage circuit is normal based on the determination information stored in the storage circuit, and the information stored in the storage circuit is not normal If it is determined, the game information stored in the storage circuit, a count value for hit determination and an initialization process for initializing the count value for hit initial value are executed,
In the main process, the power failure detection signal input determination process and the initial value count value update process are executed,
In the power failure detection signal input determination process, it is determined whether or not a power failure detection signal indicating that a power failure has occurred is input, and when it is determined that a power failure detection signal has been input, it is used in the return processing Determination information is calculated and stored in the storage circuit,
In the hit initial value count value update process, the hit initial value count value is updated by a second update value from the second initial value within the second range,
In the timer interruption process, a count value update process for winning determination and a lottery condition determination process are executed,
In the hit determination count value update process, the hit determination count value is updated for each first update value from the first initial value over one period within the first range, and the initialization process is performed. In the first cycle after the first is executed, the first initial value is set using a value determined based on the random number generated by the random number generation circuit, and the initialization process is executed. In each of the subsequent cycles after the second cycle, the first initial value is set using the count value for the hit initial value,
In the lottery condition determination process, it is determined whether or not the lottery condition is satisfied. When it is determined that the lottery condition is satisfied, the winning determination count value is compared with a set value, and the winning determination count is determined. When the value matches the set value, a control signal for generating a winning gaming state is output.
A gaming machine characterized by that.

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