JP3811794B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gaming machine, and more particularly to a gaming machine that includes a main control board that controls the progress of the game and a sub-control board other than the main control board.
[0002]
[Prior art]
A gaming machine, such as a pachinko gaming machine, is configured to pay out a predetermined number of gaming balls as prize balls when the launched gaming balls win a prize opening. The game balls won in each winning opening on the game board surface are temporarily stopped in the safe ball tank, and the stopped game balls are detected one by one by a sensor, and a predetermined number of prize balls are driven by a motor or the like. After paying out to the player by the device, the detected game ball is discharged from the safe ball tank.
In this conventional pachinko machine, the winning game balls are stopped in the safe ball tank, and after the prize balls are paid out, they are discharged out of the machine. Since it was stopped in the ball tank, it had the effect of not giving a disadvantage to the player.
[0003]
However, the conventional pachinko gaming machine has the following problems.
(1) The configuration is bulky because it is necessary to have a safe ball tankRIt gets complicated.
(2) When a power outage or the like occurs, data on the number of prize balls to be paid out disappears, so that the maximum number of prize balls is paid out and an accurate prize ball is not paid out. For example, even if 5 or 10 premium balls are to be paid out for one winning ball, 15 premium balls are paid out.
(3) In the pachinko machine, noise is inherent in the AC voltage supplied from the 24V AC power supply, and noise accompanying the operation of the pachinko machine, for example, noise due to the prize ball discharge is supplied to the main control board and the sub control board. Since it is superimposed on a direct current power source, it may be difficult to accurately detect a power failure when a power failure is detected with a DC voltage.
[0004]
The gaming machine of the present invention is made for the purpose of stopping preparations for power failure by a safe ball tank, backing up with a battery, and reducing the influence of noise.
[0005]
[Means for Solving the Problems]
  That is, in order to solve the above-mentioned problem, the invention according to claim 1 is provided with a main control board that controls the progress of the game, a sub-control board that includes at least a prize payout control board for paying out a prize to the player, and an AC power supply. And a power supply board that converts the AC power supply into a DC power supply and supplies the converted DC power supply to the main control board and the sub control board.AC voltage waveformA power failure monitoring circuit for generating a power failure detection signal based on the power failure, and a power failure signal output means for simultaneously outputting the power failure detection signal generated by the power failure monitoring circuit to the main control board and the sub control board. When the power failure detection signal output by the power failure signal output means is input, the board stores and holds data indicating the progress of the game and also stops the operation. The prize payout control board has the power failure signal output means When a power failure detection signal to be output is input, unpaid premium payout data is stored and held, and the operation is stopped, and when the power failure is restored, the main control board is based on the stored and stored data indicating the progress of the game. It is determined whether or not a power failure occurs while the grand prize award is open, and it is determined whether or not the player is firing a game ball when the power failure is restored. If it is determined that no firing the ball is characterized in that a notification for prompting the firing to the player.
[0006]
In the gaming machine according to claim 1 having the above-described configuration, the power failure monitoring circuit detects the power failure based on the waveform of the AC voltage, and thus the above-described problem can be preferably solved. Compared to the case where a power failure is detected based on the waveform of the DC voltage, superiority is recognized in noise resistance, control accuracy, and speed.
[0007]
As for the power source of the gaming machine here, for example, in a pachinko machine, in general, a 24V AC power supply is supplied and used for various switches and lamps, and from a 24V AC, a 32V DC power source used for a solenoid or the like. 12V DC power source used for various switches and relays, various control boards, and 5V DC power source used for liquid crystal drive.
[0008]
The sub-control board includes at least a prize payout control board. In a pachinko gaming machine, the sub-control board may include a symbol control board or the like that displays symbols in a variable manner. The prize payout control board is a board that controls a drive device for paying out prizes, and in a pachinko machine, a motor or solenoid that pays out a prize ball (also referred to as “prize ball” or “prize ball”) as a prize. In a throttle gaming machine, a board that drives and controls a hopper that pays out coins as a prize.
[0009]
The power failure monitoring circuit generates a power failure detection signal based on the waveform of the AC voltage. As a generation mode, the power failure monitoring circuit monitors a waveform change exceeding a predetermined value, a voltage drop for a predetermined period, a lack of a predetermined cycle of voltage, and the like. Is. For example, provided with an AC voltage level detection circuit and a timer circuit, when the timer does not detect the rising or falling of the AC waveform within the time limit, or when the predetermined reference voltage is not output for a predetermined time or more based on the AC voltage, Examples include a circuit that determines a power failure.
[0010]
  The gaming machine according to claim 2 is:2. The gaming machine according to claim 1, wherein if a game ball is not fired even after a predetermined time has elapsed after the notification for prompting the launch, the stored power failure data is cleared.It is characterized by doing.
  As an additional configuration example 1 that can be added to the present invention,
  A symbol display means for confirming and displaying a stop symbol after the symbols are displayed in a variable manner due to the game ball entering the symbol operating port; a reserved memory count display means for displaying the number of reserved memories in the variable display;
  Due to the power-on generation signal of the power supply board, based on data relating to the game, recovery means for recovering the game,
  In accordance with the generation of the power-on generation signal, there is provided a configuration comprising display means for displaying a confirmed symbol immediately before a power failure stored in the storage holding means and the number of reserved storage.
[0011]
The operation stop means here executes the stop of the operation of the main control board and the sub control board all at once, and when the recovery means starts up the operation of the main control board and the sub control board, the sub control board is more than the main control board. Examples are those that control to start up quickly, and the means for stopping the operation and the means for starting the operation may be configured integrally or separately.
Furthermore, the operation of each sub-control board may be started all at once, or may be started with priority. In addition, as a configuration for starting up the operation of the sub control board earlier than the main control board, a configuration may be used in which a time difference is output from the reset circuit of the power supply board to output the start signal, or for one start-up. These signals may be transmitted, and a delay circuit may be provided on each substrate so that the operation start-up timing is different.
[0012]
  Having the above configurationAdditional configuration example 1InAffectThe gaming machine can suitably solve the above-mentioned problem, and, along with the generation of the power-on generation signal, displays the confirmed symbol immediately before the power failure stored in the memory holding means and the number of reserved storage, so that the player can The confirmed symbols and the number of reserved memories can be confirmed. Here, when a power failure occurs while the symbol is fluctuating, the number of reserved memories is preferably a value obtained by adding the variable being added as one reserved memory. For example, when a power failure occurs while the symbol is fluctuating in a state where the number of reserved storages is displayed as 2, the number of reserved storages is displayed as 3 when the power is restored from the power failure.
[0013]
  NaAs an additional configuration example 2 that can be added to the present invention,
  A symbol display means for confirming and displaying the stop symbol after the symbol is variably displayed due to the game ball entering the symbol operating port;
  After the stop symbol of the symbol display means is changed to a big hit symbol, the game shifts to a big hit control, and during the big hit period, the big prize opening is opened until a predetermined time or a predetermined number of prizes are opened so as to make it easy to win a game ball and then closed. A jackpot control means for repeating the operation a predetermined number of times,
  The main control board or the symbol control board stores the control up to the middle due to the timing when the power failure is detected when a power failure is detected while the big prize opening is open, and the big hit control is performed when the power failure is restored. The means includes a midway data display means for executing the control from the middle and displaying data relating to the remaining time of the predetermined time or the predetermined number of remaining winnings.
[0014]
  Having the above configurationAdditional configuration example 2InAffectThe gaming machine can suitably solve the above-mentioned problems, and displays the data related to the remaining time of the predetermined time or the predetermined number of remaining winnings at the time of restoration of a power failure, so that the operation of the big prize opening is accurately recovered. It can be confirmed whether or not.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The embodiments of the present invention are not limited to the following examples, and it goes without saying that various forms can be adopted as long as they belong to the technical scope of the present invention.
As shown in FIG. 1, the pachinko machine 10 according to the present embodiment includes a rectangular outer frame 11 and a front frame 12. A known card reader (prepaid card unit) 13 is provided on the left side of the outer frame 11. It has been. The front frame 12 is rotatably attached to the outer frame 11 by hinges 14 at the upper and lower left ends.
An upper plate 15 is provided below the front frame 12, and a lending button 16, a settlement button 17 and a balance display unit 18 are provided on the upper plate 15. When a prepaid card is inserted into the card slot 19 of the card reader 13, the stored balance is displayed on the balance display unit 18, and when the lending button 16 is pressed, the game balls are lent out and the game balls are drawn from the payout opening of the upper plate 15. Discharged.
[0016]
A window-shaped metal frame 20 is removably attached to the front frame 12 with respect to the front frame 12. A plate glass 21 is double fitted in the metal frame 20. A game board 22 is stored behind the plate glass 21.
A lower plate 23 is provided at the lower part of the front frame 12 of the upper plate 15, and a firing handle 24 is attached to the right side of the lower plate 23. A rotation ring (not shown) is held on the outer periphery of the launch handle 24, and the game ball can be launched onto the game board 22 by rotating clockwise.
The upper plate 15 and the lower plate 23 are connected to each other, and are configured to guide the game ball to the lower plate 23 when the upper plate 15 is full of game balls.
[0017]
FIG. 2 is a back view of the pachinko machine 10 viewed from the back side. As shown in the drawing, a mechanism board 26 to which the above-described game board 22 is detachably attached is housed in the above-described outer frame 11. The mechanism panel 26 is provided with a ball tank 27, a guide rod 28, and a payout device 29 from above. With this configuration, if there is a winning game ball at the winning opening on the game board 22, a predetermined number of gaming balls can be discharged from the ball tank 27 to the above-described upper plate 15 through the guide rod 28 by the payout device 29. .
In addition, the main control board 30 and the payout control board 31 can be attached to and detached from the mechanism board 26. The game board 22 has a special symbol display device 32, the launch control board 33 in the lower left part of the front frame, and the special symbol display device 32. External connection terminal boards 42 are respectively attached to the left side of each.
[0018]
Next, the game board 22 will be described with reference to FIG.
The game board 22 has an LCD panel unit (hereinafter referred to as “LCD”) 32a constituting a special symbol display device 32 at the center, a normal electric accessory 36 as a first type starting port at the lower part, and an ordinary upper part of the LCD 32a. The symbol display device 37, the normal symbol operation gates 38 and 39 on the left and right of the LCD 32a used to start the variation of the symbol displayed on the normal symbol display device 37, the large winning opening 40 below the normal electric accessory 36, and the bottom bottom out A mouth 41, other various winning holes, a windmill, a game nail (not shown), and the like are provided.
With this configuration, when the above-described launch handle 24 is rotated, the launch motor 33a (see FIG. 4) driven by the launch control board 33 is driven, and the game ball on the upper plate 15 is played through the guide rail 22 via the guide rail. Fired up. If the launched game ball wins each winning hole, the game ball is taken into the back of the board as a safe ball, and if not won, it is taken into the back of the board through the out port 41 as well.
[0019]
Next, the electrical configuration of the pachinko machine 10 described above will be described with reference to the block diagram of FIG.
As shown in the figure, the electric circuit of the pachinko machine 10 includes the main control board 30, the payout control board 31, the special symbol display device 32, the launch control board 33, the lamp control board 34, the sound control board 35, and the like. Yes. In this circuit diagram, a so-called relay board or the like is not shown in order to exchange signals.
[0020]
The main control board 30 is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer incorporating a ROM that stores a game control program and a RAM that serves as a work area for operations and the like. An external input / output circuit for inputting / outputting with various actuators is also provided.
On the input side of the main control board 30, there are a first type start port switch 36a, normal symbol operation switches 38a and 39a, an accessory continuous operation switch (hereinafter simply referred to as "V switch") 40a, a count switch 40b, a full tank A switch 43, a replenishment switch 44, a plurality of other prize opening switches 45, a ball removal switch 46, and the like are connected. On the output side, a big prize opening solenoid 40c, a V solenoid 40d, a normal accessory solenoid 36b, an external connection terminal board 42, and the like are connected.
[0021]
The first type start port switch 36a is in the above-described normal electric accessory 36 on the game board 22, the normal symbol operation switches 38a and 39a are in the normal symbol operation gates 38 and 39, respectively, and the V switch 40a is in the big prize opening 40. Within a specific area, the count switch 40b is also in the big prize opening 40, the full tank switch 43 is in the lower plate 23, the replenishment switch 44 is in the ball tank 27, and the other prize opening switch 45 is the ordinary electric accessory 36 and the big prize opening. Each winning opening and ball removal switch 46 on the board surface other than 40 are attached in the vicinity of the payout device 29. Here, the V switch 40a wins the prize winning opening 40 when the game ball that has won the prize winning opening 40 has passed the special device operating area (hereinafter referred to as "special area"). For all game balls, the full tank switch 43 indicates that the game ball is full in the lower plate 23, the replenishment switch 44 indicates that there is a game ball in the ball tank 27, and the other prize opening switch 45. Indicates that a game ball has won a prize on each of the prize holes on the board other than the ordinary electric accessory 36 and the big prize opening 40, and a ball removal switch 46 detects that the ball removal operation button has been pressed. It is.
The large winning opening solenoid 40c connected to the output side is used in the large winning opening 40, the V solenoid 40d is used in a special area in the large winning opening 40, and the ordinary accessory solenoid 36b is used for opening and closing the ordinary electric accessory 36. Is.
[0022]
The special symbol display device 32 includes the above-described LCD 32a and a symbol display device control board (hereinafter simply referred to as “design control board” (hereinafter also referred to as “image control board”)) 32b for driving and controlling the LCD 32a. The special symbol start memory display device 32c (see FIG. 3) for displaying the start memory number and the attached unit such as a backlight and an inverter board. Similar to the main control board 30 described above, the symbol control board 32b is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer.
[0023]
As with the main control board 30, the payout control board 31 is configured as a logical operation circuit using a microcomputer. The input circuit is connected with a prize ball payout switch 31a and a ball rental payout switch 31b, and the output circuit is cut into balls. A motor 31c and a ball lending motor 31d are connected. Further, the card reader 13 described above is bidirectionally connected to the payout control board 31, and a CR settlement display board 47 is connected to the card reader 13. The prize ball payout switch 31 a is also connected to the main control board 30.
The ball cutting motor 31c and the ball lending motor 31d are provided in the above-described payout device 29, and flow down a predetermined number of game balls supplied from the guide rod 28. A game ball paid out from the ball cutting motor 31c is detected by a prize ball payout switch 31a, and a game ball paid out from the ball rental motor 31d is detected by a ball rental payout switch 31b.
The CR adjustment display board 47 includes the lending button 16, the adjustment button 17, and the balance display unit 18 of the upper plate 15 described above. The CR adjustment display board 47 may be connected to the payout control board 31.
[0024]
When prize ball payout command data is transmitted from the main control board 30 with the above configuration, the payout control board 31 that has received this data adds the number of prize balls indicated by the transmitted data to the unpaid prize ball data. Are stored as new prize ball data, and after subtracting a predetermined number of game balls as prize balls, a subtraction process is executed from the prize ball data stored in the game balls detected by the prize ball payout switch 31a to obtain new prize balls. The payout process is executed until the value of the prize ball data becomes zero.
On the other hand, when the lending button 16 on the CR adjustment display board 47 is pressed, a 1-pulse signal is transmitted from the card reader 13 to the payout control board 31 in the case of 100 yen, and a 5-pulse signal is transmitted in the case of 500 yen. The The payout control board 31 executes a process of paying out the lending balls by drivingly controlling the ball lending motor 31d until 25 game balls are detected by the lending payout switch 31b for one pulse signal.
[0025]
The launch control board 33 drives and controls the launch motor 33a in accordance with the amount of rotation of the launch handle 24 operated by the player. When the player presses the launch stop switch 24b, the launch control board 33 stops firing or launches. When the touch switch 24a built in the handle 24 is in an ON state, the touch lamp 48 is turned on.
The touch switch 24 a is built in the firing handle 24 and detects that the player is touching the firing handle 24.
[0026]
The lamp control board 34 is mainly composed of a driving element such as a transistor. Upon receiving a command from the main control board 30, a normal symbol display device 37 having a normal symbol holding lamp and a normal symbol LED, a big hit lamp and an error lamp. Etc. and various lamps such as LEDs are lit and displayed.
[0027]
The sound control board 35 includes a sound source IC, an amplifier, and the like, and is used to drive and control the speaker 49 in response to a command from the main control board 30.
[0028]
Transmission to the special symbol display device 32, the payout control board 31, the launch control board 33, the lamp control board 34, and the sound control board 35 described above is a one-way communication circuit so that transmission can be performed only from the main control board 30. It is configured. This one-way communication circuit can be realized using an inverter circuit or a latch circuit.
[0029]
As shown in FIGS. 5 and 6, the main control board 30, the payout control board 31, the design control board 32b, the launch control board 33, the lamp control board 34, the sound control board 35, etc. Is supplied.
The power supply board 50 is connected to a 24V AC power supply 51, diode bridge circuits 52 and 53 connected to the 24V AC power supply 51, full wave 24V generation circuit 54 and DC32V generation circuit 55 connected to the diode bridge circuit 52, and diode bridge circuit 53. DC5V generation circuit 56 and DC5V generation circuit 57 that are connected to the DC5V, and a VBB power generation circuit 58 that is connected to the DC5V generation circuit 57 and generates a DC5V backup power supply by a capacitor, and supplies necessary power to each control board. It is configured as follows.
The VBB power supply generation circuit 58 is connected to the main control board 30 and the payout control board 31 and supplies backup power.
[0030]
Here, as shown in FIG. 6, the power supply substrate 50 includes a power-on reset circuit 61, an AC voltage monitoring circuit 62, a timer 1 circuit 63, a timer 2 circuit 64, and a power-down reset circuit 65.
The output side of the AC voltage monitoring circuit 62 is connected to the forced interrupt terminal NMI of the CPU 66 of the main control board 30 and the forced interrupt terminal NMI of the CPU 67 of the payout control board 31.
A power-down reset circuit 65 and a timer 2 circuit 64 are connected via an OR circuit 68 to the reset terminal RES of the CPU 66 of the main control board 30.
A power-down reset circuit 65 and a timer 1 circuit 63 are connected to a reset terminal RES of the CPU 67 of the payout control board 31 via an OR circuit 69.
A power-down reset circuit 65 and a power-on reset circuit 61 are connected via an OR circuit 71 to the reset terminal RES of the CPU 70 of the symbol control board 32b.
Similarly, a power-down reset circuit 65 and a power-on reset circuit 61 are also connected to the CPUs 72, 74, and 76 of the launch control board 33, the lamp control board 34, and the sound control board 35 via OR circuits 73, 75, and 77, respectively. It is connected.
The VBB power generation circuit 58 is connected to the backup terminal VBB of the CPU 66 of the main control board 30 and the backup terminal VBB of the CPU 67 of the payout control board 31.
[0031]
As shown in FIG. 7, the power-on reset circuit 61 includes a voltage monitoring IC 8, resistors R38, R39 and 40, bypass capacitors C22 and C23, and the like. The VS terminal that is the input terminal of the voltage monitoring IC 8 is supplied with a DC12V power source divided by the resistors R39 and R40, and the RESET terminal that is the output terminal is pulled up to DC5V by the resistor R38.
With the above configuration, the RESET terminal, which is the output terminal of the voltage monitoring IC 8, changes the reset signal 1 to be output from the high level to the low level when the voltage of the DC12V power supply decreases to 7.20-7.75V or less.
[0032]
The timer 1 circuit 63 changes the reset signal 1 output from the power-on reset circuit 61 from the high level to the low level, and the reset signal 2 output after a predetermined time (in this example, 100 ms) has elapsed from the high level. The delay circuit is changed to a low level.
The timer 2 circuit 64 changes the reset signal 1 output from the power-on reset circuit 61 from a high level to a low level after a predetermined time (in this example, 300 ms) has elapsed from when the reset signal 1 is changed from a high level to a low level. The delay circuit is changed to a low level.
[0033]
As shown in FIG. 8, the AC voltage monitoring circuit 62 has a level detection circuit 62a composed of a transistor and a resistor supplied with 24V AC power from the 24V AC power supply 51, and a level at which the reference voltage of the level detection circuit 62a can be changed. A timer circuit 62c composed of two monostable multivibrators connected to the adjustment circuit 62b and the output of the level detection circuit 62a, and a resistor for adjusting the timer operating time of the timer circuit 62c by changing the time constant And a time constant setting circuit 62d composed of a capacitor, and a power failure detection signal is output from the timer circuit 62c to the power-down reset circuit 65. That is, a power failure detection signal that is a timing for backing up data relating to the gaming state, that is, a signal for enabling NMI is output based on the AC waveform. Here, when one cycle of the 24V AC signal is lost, it is assumed that a power failure occurs.
The level detection circuit 62a compares the AC waveform with a reference level using a current switch or a trigger level, and generates a trigger signal B having a rectangular waveform.
By adjusting the variable resistance by the level adjustment circuit 62b, the power failure detection level of the AC 24V power supply can be converted into an arbitrarily adjusted digital waveform, and the power failure detection level can be set in a wide range.
[0034]
As shown in FIG. 9, when the digitized trigger signal B is input from the level detection circuit 62a to the timer circuit 62c, the timer circuit 62c is shorter than the pulse width of the trigger signal B set by the time constant setting circuit 62d. The power failure detection signal D longer than the pulse width of the time limit signal C and the trigger signal B set by the time constant setting circuit 62d appears. That is, since the time constant setting circuit 62d can be retriggered, if the trigger signal B is periodically input stably, the output side always outputs a triggered high level output signal. Become. On the other hand, if the trigger signal B is chipped as indicated by the dotted line in the figure (the AC power supply is missing for one cycle), the time limit signal C is in the non-trigger state, so its output also changes from high level to low level, and the power failure detection signal D Changes from high level to low level. As a result, it is possible to detect a missing period of the AC power source. Further, when the noise component N is present in the trigger signal B (when noise is superimposed on the 24 VAC power source), the noise component N can be retriggered to the timer circuit 62c. The output of the time signal C continues to be high level. As a result, there is an effect that the reset signal can be output until the noise of the AC power supply is removed and the AC power supply is stabilized.
Note that it is determined whether or not the elapsed time from the rising edge of the trigger signal B has occurred within the time limit, but for example, within an arbitrary set time of 1.5 to 1.9 times the AC voltage cycle If even one pulse does not come, a power failure may be used. More accurate than voltage monitoring. Further, the cycle of the AC voltage can be appropriately changed by a switch or the like according to either 50 Hz or 60 Hz. Further, the time limit signal C may be generated in response to the fall of the trigger signal B.
[0035]
The power-down reset circuit 65 sets the CPU reset signal 4 output after a predetermined time (in this example, 100 ms) from the time when the power failure detection signal output from the AC voltage monitoring circuit 62 is changed from high level to low level. The delay circuit is configured to change from a level to a low level.
[0036]
With the above configuration, the main control board 30, the payout control board 31, and other sub control boards other than the payout control board 31 when the power is supplied to the pachinko machine 10, that is, the symbol control board 32b, the launch control board 33, the lamp The operation of each CPU or the rising state of the control operation of each of the control board 34 and the sound control board 35 will be described with reference to the timing chart shown in FIG.
When the pachinko machine 10 is turned on, the power supply board 50 generates DC32V, DC12V, DC5V, and battery backup power supply (VBB). Each generated power supply is supplied to each control board. The sub-control board including the symbol control board 32b, the payout control board 31, and the power-on reset circuit 61, the timer 1 circuit 63, and the timer 2 circuit 64 The main control board 30 performs an operation start-up process as follows.
[0037]
As shown in FIG. 10, when power is supplied to the power supply board 50 (point P1), the voltages of the DC32V, DC12V, and DC5V power supplies gradually rise from 0V to 32V, 12V, and 5V in a parabolic manner. The NMI control signal is set after a predetermined time T1 has elapsed since the voltage of the DC12V power supply that gradually rises to the reference value LV2 (point P2) indicating the power-on reset voltage. In the meantime, DC32V reaches the gaming machine parts guaranteed voltage level, and then DC32V reaches the backup start voltage. The power-on reset circuit 61 does not immediately output a reset control signal even when the DC12V power supply reaches the reference value LV2, but in this specific example, the power-on reset time T2 rises after the backup start timing by the backup power supply VBB. = After about 100 ms, the reset control signal, which is the output signal of the power-on reset circuit 61, changes from the low level to the high level (point P3), and the CPU is applied to each sub-control board such as the symbol control board 32b excluding the payout control board 31. The reset signal 1 changes from the low level to the high level (point P3), the reset state is canceled, and the operation related to the control is started. That is, for all the sub-control boards except the payout control board 31, the reset signal from the power supply board 50 is directly input to the reset terminal of each CPU, and no delay time is set.
[0038]
In the timer 1 circuit 63, T3 = about 200 ms elapses after the DC12V power supply voltage becomes the reference value LV2, that is, 100 ms elapses after the CPU reset signal 1 output from the power-on reset circuit 61 changes from low level to high level. The CPU reset signal 2 to be output later is changed from the low level to the high level (point P4). This is set in consideration of the reset signal delay time and the security check time in the payout control board 31. The CPU 67 of the payout control board 31 to which the reset signal 2 is inputted executes a security check as to whether or not the program is a normal program over a period of about 320 ms after the CPU reset signal 2 becomes high level. Execute control related to payout. Accordingly, the CPU 67 of the payout control board 31 starts up the operation about 520 ms after the voltage of the DC 12V power supply becomes the reference value LV2.
[0039]
In the timer 2 circuit 64, T4 = 300 ms elapses after about 400 ms elapses after the voltage of the DC12V power supply becomes the reference value LV2, that is, the CPU reset signal 1 output from the power-on reset circuit 61 changes from low level to high level. The CPU reset signal 3 to be output later is changed from low level to high level (point P5). This is set in consideration of the reset signal delay time and the security check time in the main control board 30. The CPU 66 of the main control board 30 to which the CPU reset signal 3 is input executes a security check for whether it is a normal program over a period of about 200 ms from when the CPU reset signal 3 becomes high level. Later, control related to winning detection or the like is executed. Therefore, the CPU 66 of the main control board 30 starts up operation about 600 ms after the voltage of the DC 12V power supply reaches the reference value LV2.
[0040]
Thus, when the CPU 66 of the main control board 30 starts executing the game control according to the program written in the ROM, each sub-control board has already executed the game control. As a result, even if the CPU 66 of the main control board 30 transmits data to each sub-control board immediately after the power is turned on, each sub-control board is executing the original control, so that the data can be reliably received. .
[0041]
Next, an operation when power-on to the pachinko gaming machine 10 is interrupted by a power failure or the like will be described with reference to a timing chart shown in FIG.
When the power supply to the pachinko gaming machine 10 is interrupted by a power failure, the AC voltage A decreases and becomes zero, and the DC 32V, DC 12V, and DC 5V decrease as shown in FIG. The power failure detection signal D of the AC voltage monitoring circuit 62 of the power supply board 50 changes from high level to low level. When the NMI control signal is reset by the power-down reset circuit 65 and DC32V falls to the backup start voltage level V (point P6), the NMI control signal is reset and DC32V becomes the gaming machine component guaranteed voltage level V.₁To drop. The reset control signal and each substrate CPU reset signal are reset after a predetermined time T5 (after about 100 ms) from the reset of the NMI control signal (point P7). This is because the forced reset signal is output after a certain period of time has elapsed since the detection of the power failure detection signal in consideration of the time for software processing. Thereby, the CPU 66 of the main control board 30, the CPU 67 of the payout control board 31, the CPU 70 of the symbol control board 32 b, and other sub-control boards are stopped simultaneously. After that, DC32V is the switching power supply IC minimum drive voltage level V₂DC5V is the CPU operation guaranteed minimum voltage level V_ThreeAnd attenuates to zero level. Accordingly, the forced interrupt terminals NMI of the CPU 66 of the main control board 30 and the CPU 67 of the payout control board 31 are set to the low level, and the non-maskable interrupt is applied to the CPUs 66 and 67, and the NMI states of the main control board 30 and the payout control board 31 are changed. Then, after a predetermined time elapses, the CPU operating state of each control board is stopped. As a result, the CPU 66 of the main control board 30 can save data indicating the current game state, and thereafter prohibit access to the RAM. Further, the CPU 67 of the payout control board 31 can save data indicating the current prize ball payout state and the ball lending payout state, and thereafter prohibit access to the RAM.
[0042]
The CPU reset signal output about 100 ms after the fall of the signal at which the power failure detection signal D output from the AC voltage monitoring circuit 62 changes from high level to low level is changed from high level to low level (point P7).
Here, as described above, the RAMs of the main control board 30 and the payout control board 31 are backed up by the battery, and the data stored in the RAM is stored for a predetermined time (about 3 days in this specific example) even when the power is turned off. Retained.
[0043]
As described above, when the power is turned off, the control boards are reset all at once. Moreover, the power failure detection signal D output from the AC voltage monitoring circuit 62 is always reset about 100 ms after the high level changes to the low level. Thereby, it is possible to unify the control, and it is possible to prevent the adverse effect that the firing motor 33a is driven even though the operation of the main control board 30 is stopped.
[0044]
Next, the operation of this specific example having the above-described configuration will be described when the power is turned on and when the power is turned off. Since the processing from the time when the power is turned on until the power is turned off is the same as the conventional one, the detailed description is omitted. Here, for the sake of convenience, first, the process at the time of power-off will be described according to the flowchart shown in FIG.
The flowchart shown in FIG. 12 is a process executed by the CPU 66 of the main control board 30 and the CPU 67 of the payout control board 31 and executed when the signal at which the forced interrupt terminal NMI of each CPU changes from the high level to the low level falls. Process.
When the processing executed by the CPU 66 and the CPU 67 shifts to this routine, first, processing for writing the predetermined value 55H in a plurality of predetermined areas of the RAM is performed (step S100). The predetermined value to be written may be any value, but 55H or AAH in which each bit in one byte is alternately “1” and “0” is preferable.
[0045]
After a predetermined value is written in a predetermined area of the RAM, data saving is executed (step S110). In the data saving process, the current progress of the game on the main control board 30, for example, whether or not the probability is high, whether or not it is a big hit, and whether or not the big winning opening 40 is open. In the special symbol display device 32, whether or not the symbol is changing, whether or not it is being stored, whether or not there is any storage, whether or not random numbers are being extracted, the number of unpaid winning balls, and unpaid lending This is a process of writing each data indicating the progress of the game, such as the number of balls, in a predetermined area of the RAM. On the other hand, the payout control board 31 is a process of writing each data indicating the payout state of the current number of prize balls and the payout state of the lending balls into a predetermined area of the RAM. This save process need not be configured to execute this process as long as it is an algorithm that always writes the current state to a predetermined area of the RAM. When data saving is executed, access to the RAM is then prohibited (step S120).
[0046]
This RAM access prohibition process is to improve the accuracy and certainty of data to be saved by prohibiting writing to the RAM when the power supply voltage is unstable.
When access to the RAM is prohibited, a process of waiting for the reset terminal RES to fall to the low level is executed (step S130). When the reset terminal RES falls to the low level (step S130: Yes), the process returns.
In this specific example, when a forced interrupt is executed, a reset process is always executed after a predetermined time by the power-down reset circuit 65 even if the power is restored thereafter. As a result, it is possible to prevent the adverse effect that the execution of the forced interrupt and the recovery process are alternately repeated when the power source is unstable.
[0047]
Here, in this specific example, the CPU reset signal is output about 100 ms after the power failure detection signal D output from the AC voltage monitoring circuit 62 changes from the high level to the low level. It is calculated as follows.
The CPU 67 of the payout control board 31 executes the power failure processing routine described above when the forced interrupt terminal NMI becomes low level. At this time, the driving of the ball cutting motor 31c and the ball lending motor 31d is also stopped. When there is a game ball that is paid out immediately before the driving of these motors stops, it is necessary to detect the falling game ball by the prize ball payout switch 31a or the ball rental payout switch 31b. Therefore, it is necessary to ensure a time during which the detecting game balls can be detected by the respective detection switches when the driving of the motor is stopped. On the other hand, if this time is ensured too long, the voltage of the 5V power source for driving the IC may be lowered and may not be detected by each detection switch. Therefore, in this specific example, about 100 ms is set due to the balance between the two. Therefore, the distance from each motor to the detection switch and the voltage drop state may be changed as appropriate. In short, it may be configured to secure a time for detecting a falling game ball within a time during which driving of the IC is guaranteed after the forced interrupt terminal NMI becomes low level.
[0048]
Next, processing when power is turned on will be described.
When the power is turned on and the security check is completed, the CPU 66 of the main control board 30 executes a “power-on routine” shown in FIG. This routine is executed only once when the signal at which the reset terminal RES changes from low level to high level.
When the process moves to this routine, it is determined whether or not it is normal (step S150). In this specific example, as described above, the DC5V backup power supply is configured to store and hold the data stored in the RAMs of the CPU 66 and the CPU 67 for about three days by the capacitor. For this reason, when the power is restored from a power failure or when the power is turned on in the morning in a normal business state, the value written in the predetermined area of the RAM is stored and held. Thereby, when it is determined that the normal time is reached, the recovery process (step S160) is executed, and the process returns to the return. The main control board 30 and the payout control board 31 execute processing from the stored data at the time of power failure, and the other boards execute from the initial state. The data before the power failure is transmitted from the main control board 30 to various boards.
[0049]
In the restoration process, the CPU 66 of the main control board 30 performs preparations for executing the normal process from the data indicating the progress of the saved game, and sends a command code notifying each sub-control board that the power supply has been restored from the power failure. To do. The symbol control board 32b that has received this command code performs a process of displaying messages such as “execution of power failure recovery processing” and “continuing from the game content before the power failure” on the screen of the LCD 32a. Or the sound control board | substrate 35 alert | reports that there was a power failure by an audio | voice.
Thereafter, the CPU 66 periodically executes a well-known “main routine” shown in FIG. 14 by a hardware interrupt every 2 ms. This main routine consists of this process and the rest process, but details are omitted, but normal interruptOrJudgment (NoStepS200),initialSetting(StepS210), random number update processing (StepS220), each input process (StepS230), the success / failure determination process (StepS240), image output processing (StepS250), each output process (StepS260), out symbol random number update processing (StepEach process of S270) is executed.
Thereby, when the power failure occurs, the CPU 66 of the main control board 30 can continue to control the game from the progress state of the game before the power failure and does not give the player an unexpected disadvantage or discomfort.
On the other hand, if a negative determination is made in step S150 that it is not normal, an initial setting process (step S170) is executed, and the process returns to the return. As a case where it is not normal time, it is conceivable that the power is cut off for three days or more, or the data written in the RAM is changed due to a computer runaway or the like. In these cases, the predetermined value written in the predetermined area of the RAM is different from the predetermined value without being stored and held.
In the initial setting process, processes such as clearing the RAM value and transmitting initial data to each sub-control board are executed.
[0050]
On the other hand, when the power supply is turned on and the security check is completed, the CPU 67 of the payout control board 31 executes a “main routine” shown in FIG.
In this routine, it is determined whether or not it is normal time by the same process as the process of step S150 described above (step S300). If an affirmative determination is made with the normal time, the ball cutting motor is based on the stored data. 31c is driven to execute payout of the winning ball (step S310), and the ball lending motor 31d is driven to execute lending of the lending ball (step S320). Thus, if there is unpaid prize ball data at the time of the power failure, the prize balls are paid out based on the data stored and retained after the restoration of the power failure. Similarly, if there is unpaid ball lending data when a power failure occurs, the ball lending is paid out based on the data stored and retained after the power failure is restored. Thereby, even if a power failure occurs, there is no disadvantage to the player.
If a negative determination is made that it is not normal time by the determination processing in step S300, normal processing is executed after initial setting (step S330) is executed.
[0051]
The startup memory recovery subroutine shown in FIG. 16 is a recovery processing subroutine of S160 shown in FIG. 13. First, when the process is started, the main control board 30 determines whether or not a power failure occurs during startup (step S400). If YES (starting), the process proceeds to step S410. If NO (not starting), the process returns. Next, the main control board 30 displays on the LCD 32a the final display symbol immediately before the power failure stored in the memory in step S410, and displays the start memory number on the special symbol start memory display device 32c as shown in FIG. Further, a soundless signal is transmitted from the sound control board 35 to the speaker 49, and the speaker 49 is set not to sound. Subsequently, the main control board 30 starts to start a special symbol on the LCD 32a as shown in FIG. 18B (step S420), and the process returns to the return. As a result, the player can visually recognize whether the confirmed symbol immediately before the power failure was a win, a failure, or a high-probability symbol.
[0052]
The jackpot mid-processing data recovery subroutine shown in FIG. 17 is a restoration processing subroutine of S160 shown in FIG. 13. First, when processing is started, the main control board 30 determines whether or not a power failure occurs during jackpot (step S500). ). If YES (during a big hit), the process proceeds to step S510. If NO (not a big hit), the process returns.
Next, the main control board 30 determines whether or not a power failure occurs while the special winning opening 40 is open (step S510). If YES (opening), the process proceeds to step S520. If NO (not opening), the process proceeds to step S530. In step S520, the remaining number of rounds immediately before the power failure, the remaining round time, and the remaining number of winnings that are stored in the memory are displayed on the LCD 32a and are also output from the sound control board 35 to the speaker 49, and the process proceeds to step S530. For example, if there is a power outage when 20 seconds have passed from the start of opening in the middle of 5 rounds and 7 wins are won, as shown in Fig. 19 (a), "there are 5 remaining rounds", "10 seconds remaining", "remaining The number of winnings is 3 balls ”is displayed. When returning, the special winning opening 40 is closed when 30 seconds have elapsed or when 10 balls have been won. Instead of the above message, a message that produces a similar effect such as “The round has been digested 11 times”, “20 seconds have passed since the opening”, or “7 balls have already been won” may be used.
Subsequently, the main control board 30 determines whether or not a game ball is being fired (step S530). For example, whether or not the game ball is in a firing state is determined by appropriate means such as whether or not the touch switch 24a is turned on and whether or not the game ball has passed through the out port 41. If YES (fired state), the process proceeds to step S540. If NO (not fired), the process proceeds to step S550. This confirms whether or not the player has an intention to play.
Subsequently, in step S540, the main control board 30 determines that the player is touching the launch handle 24, executes control from the middle of the big winning opening during the big hit, and applies to the symbol control board 32b. A signal for executing control from the middle is output.
On the other hand, in step S550, it is determined that the player has not touched the launch handle 24, and as shown in FIG. 19B, a message “Please touch the launch handle quickly” is displayed on the LCD 32a, and the sound control board is displayed. 35 to the speaker 49.
Subsequently, in step S560, it is determined whether or not a predetermined time (for example, a few hours) has elapsed since the start of the recovery process. If YES (elapse of a predetermined time), the process proceeds to step S570, and if NO (before the predetermined time elapses), the process returns. In S570, it is determined that the customer has returned, and the data is unnecessary, so the data is cleared and the process returns.
[0053]
Here, in this specific example, the AC voltage monitoring circuit 62 is configured to monitor the voltage of the DC12V power supply, but may be configured to monitor the voltage of the DC32V power supply. In such a configuration, the backup signal, which is a forced interrupt signal, can be quickly lowered, and time can be given to control. On the other hand, the same operation timing is obtained when the power is turned on.
In such a configuration of the power supply board 50, a backup signal is output to the NMI terminal of each CPU of the main control board 30 and the payout control board 31 by the DC32V monitoring circuit, and after the backup signal output from the DC32V monitoring circuit falls. A reset signal for stopping the control after a lapse of a predetermined time is transmitted from the reset signal generation circuit to each control board all at once. On the other hand, a power-on reset generation circuit that monitors the voltage of DC5V outputs reset signals for starting control operations to each control board all at once, and a sub-control board including a symbol control board 32b provided with a delay circuit on each control board The control operation is started up in the order of the payout control board 31 and the main control board 30. That is, the operation is started by providing a time difference in the operation of each control board based on one reset signal output from the power supply board 50.
In addition, the 24V AC voltage may be full-wave rectified here, and a configuration in which a power failure occurs when the predetermined reference voltage is not output for a predetermined time or more may be employed.
[0054]
(Effect of embodiment)
As described above, according to the specific example described in detail, since the power failure detection signal D is detected based on the AC waveform of the 24V AC power source 51, the adverse effect due to noise on the AC voltage can be eliminated, and the power control during power failure can be accurately controlled. You can expect sex. Further, the sub control board and the main control board 30 including the payout control board 31 and the symbol control board 32b save the data according to the power failure detection signal D output from the AC voltage monitoring circuit 62 before stopping the control operation. Therefore, the accuracy and certainty of the data stored and held can be ensured.
Thus, when power is supplied to the main control board 30 and the sub control board by the power supply board 50, the sub control board is started earlier than the main control board 30 by the reset circuit of the power supply board 50, and when the power is shut off, The main control board 30 and the sub control board are simultaneously stopped by the reset circuit of the power supply board 50, so that the control becomes more accurate.
That is, when the main control board 30 starts operating, the sub control board has already started operating, and when the main control board 30 stops operating, the sub control board also stops operating at the same time. As a result, it is possible to prevent the sub control board from receiving data unilaterally transmitted by the main control board 30. For example, even if a power failure occurs during data transmission and the transmission process is terminated, the main control board 30 knows that the data has not been completely received. can do.
In addition, since the control boards stop operating at the same time when the power is cut off, when the main control board 30 stops operating, the other control boards do not continue to operate and the control is unified. It also has an excellent effect that it can be achieved.
Furthermore, when each control board is provided with a reset circuit, even if it is configured to start up or end the operation at the same timing, the timing may not always be the same due to component value errors, etc. Although it is difficult, in the present invention, the operation is started or stopped by the reset circuit of the power supply board 50 or based on the signal output from the reset circuit of the power supply board 50. It has an excellent effect that can be unified. If only the power supply board 50 is checked for the reset timing and the like, the timing of each control board can be determined, the inspection efficiency can be improved, and the number of parts can be reduced.
Since the main control board 30 and the payout control board 31 are configured to include a backup RAM for storing and holding data in the event of a power failure, the main control board 30 can play the game before the power failure based on the stored data after the power failure is restored. The contents can be continued, and the payout control board 31 can continue from the payout state before the power failure to continue the payout process of the prize.
When the storage holding operation is started by the backup RAM, the main control board 30 and the payout control board 31 start the operation all at once, so that the control can be unified. As a result, for example, accurate prize payout can be performed without causing a problem of whether or not winning data transmitted from the main control board 30 to the payout control board 31 is stored and held immediately before the power is shut off. It has an excellent effect of being able to.
If the memory retention is executed by the backup RAM, the operation of the main control board 30 and the sub control board is always stopped by the reset circuit. As a result, after the voltage drops due to an instantaneous power failure and the storage is executed by the backup RAM, the main control board 30 and the sub control board do not immediately resume operation when the power supply is restored. After stopping, it has an excellent effect that the processing after power-on can be executed according to the procedure. As a result, control can be further unified.
[0055]
【The invention's effect】
  Claim 12According to the described invention,In addition, the sub-control board and the main control board, including the prize payout control board, output the power failure detection signal all at once before stopping the control operation. And certainty can be ensured. Since each control board stops operating at the same time when the power is cut off, when the main control board stops operating, the other control boards do not continue to operate and the control can be unified. It also has an excellent effect of being able to. After the power failure recovery, the main control board can continue the game contents before the power failure based on the stored data, and the payout control board continues the payout process by continuing from the payout state before the power failure. be able to.
[Brief description of the drawings]
FIG. 1 is an external perspective view showing a gaming machine 10 employing the present invention.
FIG. 2 is a back view of the gaming machine 10 as seen from the back side.
3 is a front view showing a configuration of a game board 22 of the gaming machine 10. FIG.
4 is a block diagram showing an electrical configuration of the gaming machine 10. FIG.
FIG. 5 is a block diagram showing a configuration for supplying power from a power supply board 50;
FIG. 6 is a block diagram showing the relationship between the power supply board 50, the main control board 30, and each sub-control board.
7 is a circuit diagram showing a configuration of a power-on reset circuit 61. FIG.
8 is a circuit diagram showing a configuration of an AC voltage monitoring circuit 62. FIG.
9 is a timing chart showing the operation of the AC voltage monitoring circuit 62. FIG.
FIG. 10 is a timing chart showing a state when power is turned on.
FIG. 11 is a timing chart showing a state when power is shut off.
FIG. 12 is a flowchart showing processing in a “power failure processing routine”;
FIG. 13 is a flowchart showing processing in a “power-on routine”;
14 is a flowchart showing processing performed in a “main routine” of the main control board 30. FIG.
FIG. 15 is a flowchart showing processing performed in a “main routine” of the payout control board 31;
FIG. 16 is a flowchart showing a “starting memory restoration subroutine” in the restoration process of the power-on routine.
FIG. 17 is a flowchart showing a “big hit processing data recovery subroutine” in the recovery process of the power-on routine.
18A is an explanatory diagram showing an initial display mode on the LCD panel unit 32a in the startup memory recovery subroutine, and FIG. 18B is an explanatory diagram showing a display mode during change.
19A is an explanatory diagram showing an initial display mode in the LCD panel unit 32a in the big hit middle processing data recovery subroutine, and FIG. 19B is an explanatory diagram showing a display mode when it is determined that the game state is not in effect. It is.
[Explanation of symbols]
10 ... Pachinko machine 13 ... Card reader (prepaid card unit)
22 ... Game board 24 ... Launch handle
24a ... touch switch 24b ... firing stop switch
30 ... Main control board 31 ... Dispensing control board
31a ... Prize ball payout switch 31b ... Ball rental payout switch
31c ... Ball cutting motor 31d ... Ball lending motor
32 ... Special symbol display device 32a ... LCD panel unit (LCD)
32b ... design display control board (design control board)
33 ... Launch control board 33a ... Launch motor 34 ... Lamp control board
35 ... Sound control board 36 ... Ordinary electric accessory (starting port)
36a ... First type start switch 37 ... Normal symbol display device
40 ... Large winning opening 40a ... Continuous action switch (VSW)
40b ... count switch (count SW)
45 ... Other prize opening switches 46 ... Tamaguchi switch
47 ... CR settlement display board 48 ... Touch lamp
49 ... Speaker 50 ... Power supply board
61 ... Power-on reset circuit 62 ... AC voltage monitoring circuit
63 ... Timer 1 circuit 64 ... Timer 2 circuit
65. Power-down reset circuit
66, 67, 70, 72, 74, 76 ... CPU (one-chip microcomputer)
68, 69, 71, 73, 75, 77 ... OR circuit

Claims (2)

A main control board that controls the progress of the game,
A sub control board including at least a prize payout control board for paying out a prize to a player;
In a gaming machine including an AC power supply, converting the AC power source into a DC power source, and supplying the converted DC power source to the main control board and the sub control board,
A power failure monitoring circuit that generates a power failure detection signal based on the waveform of the AC voltage of the AC power source supplied to the power supply board,
A power failure signal output means for simultaneously outputting power failure detection signals generated by the power failure monitoring circuit to the main control board and the sub control board;
The main control board stores and holds data indicating the progress of the game when the power failure detection signal output by the power failure signal output means is input, and stops the operation.
The premium payout control board stores and holds unpaid premium payout data when the blackout detection signal output by the blackout signal output means is input, and executes the operation stop,
At the time of power failure recovery, the main control board determines whether or not a power outage has been made while the prize winning opening is open based on the stored game progress data, and at the time of power failure recovery, the player launches a game ball. A game machine characterized by determining whether or not the game ball is open, and informing that the player is urged to launch when it is determined that a power failure has occurred during opening and the game ball has not been fired upon recovery from the power failure. In the gaming machine according to claim 1,
If the game ball is not fired even after a predetermined time has passed after the notification for prompting the launch, the stored data at the time of the power failure is cleared.

Images