JP5212196B2 - Data transmission apparatus, information processing apparatus, and operating frequency control method - Google Patents

Description

  The present invention relates to the fields of a data transmission device, an information processing device, and an operating frequency control method.

PCI Express (registered trademark) is known as a serial transfer interface that replaces the PCI bus. PCI Express is standardized as a standard expansion bus that can be used for all computers as a successor to PCI. Low-voltage differential signal transmission, point-to-point independent communication channels, packetized split transactions, It has features such as high scalability due to differences in link configuration.

  The lane, which is the minimum configuration transmission line used in PCI Express, is capable of full duplex communication of 2.5 Gbps in one direction and 5.0 Gbps in both directions. Since 10 bits including 2 bits such as a clock signal are consumed to send 8 bits of data, the effective data transfer rate is 2.0 Gbps (250 MB / s) in one direction and 4.0 Gbps (500 MB / s) in both directions. However, as for the actual PCI Express port, products with multiple lanes, such as x2, x4, x8, x12, x16, x32, etc. have appeared, and this high speed makes it an interface for video cards that replaces AGP. It is getting used.

  The data transfer method in PCI Express is more similar to packet transmission / reception on the network than the PCI bus. Similarly, the internal configuration is similar to a network, and has a three-layer structure including a transaction layer, a data link layer, and a physical layer. For example, when data is transmitted, the issued transmission request is packetized in the transaction layer and passed to the data link layer. The data link layer is responsible for transmission / reception control with the connected counterpart device, and adds a sequence number and CRC to the packet and passes them to the physical layer. The physical layer is the part responsible for serial transfer, and packets are sent as serial data by SERDES that performs 8b / 10b conversion.

  In general, in an information processing apparatus such as a PC (Personal Computer), a parallel bus represented by a PCI bus or the like is used as an interface between devices. However, the parallel bus has a low latency, and a mechanism for dynamically optimizing the packet size and buffer size cannot be constructed. Therefore, as a means for realizing higher speed and higher efficiency of the internal bus, an information processing apparatus and a data communication apparatus adopting PCI Express are proposed instead of a parallel interface such as a PCI bus. (For example, see Patent Document 1).

  Incidentally, it is known that PCI Express flow control is performed on a credit basis. This is a mechanism that does not cause an overflow or underflow by checking the buffer availability on the receiving side before starting data transfer.

  Specifically, the receiving side (for example, the receiving end point) notifies the transmitting side of the buffer capacity (credit value) that it can receive at the time of link initialization. The transmission side (for example, the transmission side endpoint) compares the buffer capacity on the reception side with the length of the packet to be transmitted, and transmits a packet if there is a certain remaining in the buffer capacity on the reception side. Then, the transmission side subtracts the size of the packet transmitted by itself from the notified buffer capacity of the reception side. Further, when empty information on the buffer capacity is transmitted from the receiving side, the corresponding amount is added. By such credit-based flow control, the transmission side can transfer packets without exceeding the buffer capacity of the reception side.

  According to such flow control, when the buffer capacity on the receiving side is sufficiently large with respect to the data transmission rate on the transmitting side, the transmitting side notifies the buffer capacity (credit free capacity information register value) on the receiving side notified to 0. Before receiving, it is possible to receive free space capacity information (Update FC) from the receiving side. Therefore, in this case, the transmission side can continuously transmit data to the reception side.

  On the other hand, if the buffer capacity on the receiving side is not sufficient (small) with respect to the data transmission rate on the transmitting side, increasing the data transmission rate by increasing the circuit operation (clock frequency) on the transmitting side will eventually Before receiving the buffer capacity empty information (Update FC) from the receiving side, the notified buffer capacity (credit free capacity information register value) of the receiving side becomes 0 on the transmitting side. In this case, the transmitting side cannot transmit data to the receiving side. Since the receiving side receives the buffer capacity availability information (Update FC) and receives a notification from the receiving side that the buffer capacity has been secured, the transmitting side can send data to the receiving side. is there. In such a situation, the credit-based flow control causes a waiting time and a corresponding decrease in the data transfer rate.

  Therefore, in credit-based flow control such as PCI Express, since the buffer capacity on the receiving side is 0, data transmission to the receiving side is not permitted no matter how fast the circuit operation on the transmitting side is. The power consumption was wasted.

  Accordingly, in the present invention, in view of the above problems, a data transmission apparatus, an information processing apparatus, and an operation frequency control method that save power consumption by optimizing the data transfer speed and circuit operation in the flow control based on the credit base design. The purpose is to provide.

  Therefore, in order to solve the above problems, a data transmission device according to the present invention includes transmission means for transmitting data to a data reception device, and information related to the amount of data transmitted from the data reception device and receivable by the data reception device. Receiving means, and frequency control means for controlling an operating frequency corresponding to a transfer rate of data transmission by the transmitting means, wherein the frequency control means determines the amount of data that can be received by the data receiving device. When the transmission time required for the transmission means to transmit the data having is smaller than the reception time from the start of data transmission until the reception means receives the information, the transmission time and the reception time The frequency control means reduces the operating frequency value until the values are equal.

  In order to solve the above problems, an information processing apparatus according to the present invention includes a data receiving apparatus and a data transmitting apparatus that transmits data to the data receiving apparatus, wherein the data transmitting apparatus includes the data receiving apparatus. Transmitting means for transmitting data to, receiving means for receiving information related to the amount of data that can be received by the data receiving apparatus transmitted from the data receiving apparatus, and an operation corresponding to a transfer rate of data transmission by the transmitting means Frequency control means for controlling the frequency, and the frequency control means starts data transmission when a transmission time required for the transmission means to transmit data having a data amount that can be received by the data receiving device. If the reception means is smaller than the reception time until the information is received, the transmission time and the reception time Characterized in that it is a frequency control means for reducing the operating frequency value to be equal.

  In order to solve the above problem, an operating frequency control method according to the present invention transmits data to a data receiving device, receives information related to the amount of data that can be received by the data receiving device, transmitted from the data receiving device. And controlling the operating frequency corresponding to the transfer rate of the data transmission to the data receiving device, and the transmission time required to transmit the data having a data amount that can be received by the data receiving device starts the data transmission. If the reception time is shorter than the reception time until the information is received, the operating frequency value is lowered until the values of the transmission time and the reception time become equal.

  In addition, what applied the arbitrary combination of the component of this invention, expression, or a component to a method, an apparatus, a system, a computer program, a recording medium, etc. is also effective as an aspect of this invention.

  According to the present invention, it is possible to provide a data transmission device, an information processing device, and an operating frequency control method that save power consumption by optimizing the data transfer rate and circuit operation in the flow control based on the credit base design. .

1 is an example of a diagram illustrating a configuration of a PCI Express system. It is an example of the figure which shows the structure of the information processing apparatus 1 which has a PCI Express platform. It is a sequence diagram explaining the flow control prescribed | regulated by PCI Express. 1 is an example of a diagram showing a configuration between PCI Express data communication devices according to the present invention. It is a sequence diagram explaining the flow control by an Example. FIG. 3 is an example of a diagram illustrating a relationship between an operating frequency f of a circuit on a transmission side and a data transfer rate R. It is a figure which shows typically the state of transmission data and Update FC. It is a figure which shows typically the state of transmission data and Update FC. It is a figure which shows typically the state of transmission data and Update FC.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings in each embodiment.

<Configuration>
(System configuration)
FIG. 1 is an example of a diagram illustrating a configuration of a PCI Express system. The PCI Express graphics 113 is connected to the root complex 112 to which the CPU 110 and the memory 111 are connected by the PCI Express 114a, and the switch 117a in which the endpoint 115a and the legacy endpoint 116a are connected by the PCI Express 114b is connected by the PCI Express 114c. Further, the switch 117b in which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d, and the switch 117c in which the PCI bridge 119 to which the PCI bus slot 118 is connected are connected by the PCI Express 114e are connected by the PCI Express 114f. Tree structure (tree structure).

  FIG. 2 is an example of a diagram illustrating a configuration of the information processing apparatus 1 having a PCI Express platform. That is, an example of the PCI Express platform actually mounted on the information processing apparatus 1 is shown. In the illustrated example, for example, graphics 125 is connected by a x16 PCI Express 126a to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. A functioning I / O hub 127 is connected by a PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, the Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  By the way, PCI Express flow control is performed point-to-point between links, not end-to-end. Accordingly, in FIG. 1, all data communication devices such as the route complex 112, the switch 117, the end point 115a, the legacy end point 116a, and the PCI bridge 119 connected by PCI Express are data “transmitting” devices according to the present invention. obtain. Similarly in FIG. 2, all data communication devices such as the memory hub 124, the I / O hub 127, the graphics 125, the mobile dock 135, the Gigabit Ethernet 136, and the add-in card 137 are included in the data “sending” device according to the present invention. Can be.

  For example, in the memory hub 124 and the graphics 125 connected by the PCI Express 126a, it is often assumed that the memory hub 124 is mainly a data “sending” device and the graphics 125 is a data “receiving” device. . However, as long as any data communication is performed from the graphics 125 to the memory hub 124, the memory hub 124 becomes a data “reception” device and the graphics 125 becomes a data “transmission” device. That is, the data communication device connected to PCI Express has a function that can be either a data transmission side or a data reception side.

(Flow control)
Next, flow control (flow control) defined by PCI Express will be described. As a general flow control, there is a method in which the transmitting side first transmits data and transmits again when a problem occurs on the receiving side. On the other hand, in PCI Express, the transmission side confirms the free capacity of the reception side buffer in advance, and transmits a packet when sufficient free capacity is secured.

  PCI Express flow control is realized by DLLP (Data Link Layer Packet) generated by the data link layer. The DLLP type can be broadly divided into “Init FC” and “Update FC”. These flow control DLLPs have formats for storing “Hdr FC” and “Data FC” values. From these values, for example, the sending side knows how much the buffer on the receiving side is left. Be able to.

  FIG. 3 is a sequence diagram illustrating flow control defined by PCI Express. PCI Express flow control is performed on a credit basis. First, the receiving side notifies the transmitting side of the buffer capacity (credit value) that it can receive at the time of link initialization. The transmission side compares the buffer capacity on the reception side with the length of the packet to be transmitted, and if there is a certain remaining in the buffer capacity on the reception side, transmits the packet. Then, the transmission side subtracts the size of the packet transmitted by itself from the notified buffer capacity of the reception side. In addition, the transmission side adds the corresponding amount when empty information of the buffer capacity is transmitted from the reception side. In the following, description will be made with the transmission side (data transmission device) and the reception side (data reception device) appearing in the figure.

  First, the receiving side issues an Init FC and notifies the transmitting side of a credit value (a value indicating a buffer capacity that can be received by the receiving side) (S301). Note that the credit value information (internal credit counter) on the receiving side has been initialized. When receiving the Init FC, the transmission side sets the initial value of the internal credit counter (credit free capacity information register) to the credit value specified by the Init FC (S302). This is the initialization procedure.

  Then, the transmission side transmits data (S303). At this time, the transmission side decreases the value of the credit counter by the amount of transmitted data for every data transmission (S304).

  Every time data is received, the receiving side issues an Update FC and notifies the transmitting side of a predetermined credit value (for example, a buffer capacity value corresponding to the received data) (S305). Each time the transmission side receives the Update FC, the transmission side increases the credit counter value by the value set in the Update FC (S306). This is to recover the value of the credit counter.

  In this way, the transmission side can perform data transmission corresponding to the receivable buffer capacity notified from the reception side. Transmission data and Update FC are basically handled as one set, and one Update FC is issued for one Init FC. This is because when one Update FC is issued for a plurality of transmission data, recovery of the value of the credit counter is delayed, and in order to perform data transmission at a high speed, it is desirable to immediately issue the Update FC.

  The flow control defined by PCI Express has been described above. Of course, the data transmission apparatus according to the present invention also performs the flow control operation in accordance with the above-mentioned rules.

<Example>
FIG. 4 is an example of a diagram showing a configuration between PCI Express data communication apparatuses according to the present invention. As shown in the figure, two data communication devices are connected by PCI Express, and one data communication device continuously transmits data to the other data communication device. In this case, the data transmitting side can be regarded as a data transmitting device (hereinafter simply referred to as a transmitting side) and the receiving side can be regarded as a data receiving device (hereinafter simply referred to as a receiving side).

Here, the preconditions for setting the embodiment are set as follows.
-The payload of data to be transmitted on the transmission side is 128 bytes.
-Set the credit value in Init FC on the receiving side to 512 bytes.
The time required for the transmission side to transmit data corresponding to the credit value capacity of the reception side (transmission time) is t1.
-Let t2 be the time (reception time) from when the transmission side starts transmitting a data packet until it receives the corresponding Update FC.
The PCI Express physical layer is sufficiently fast for the circuit of the data communication apparatus, and the data transfer time t1 corresponding to the credit value capacity is determined by the operation speed of the circuit on the transmission side.

  The above-described flow control will be described again under such conditions. FIG. 5 is a sequence diagram illustrating flow control according to the embodiment.

  First, the receiving side issues an Init FC and notifies the transmitting side of a credit value (512 bytes) (S501). When receiving the Init FC, the transmission side sets the initial value of the internal credit counter to the credit value (512 bytes) specified by the Init FC (S502). This is the initialization procedure.

  Then, the transmission side transmits data 1 (128 bytes) (S503). At this time, the transmission side decreases the value of the credit counter by the transmitted data amount (128 bytes) every time data is transmitted (S504). When the sending side starts sending data, the credit counter still has room, so it sends up to a total of four 128-byte packets without waiting for Update FC, and the credit counter value is reduced by the amount of data sent (128 bytes). (S505-S510). When the fourth 128-byte packet is transmitted (S509), the value of the credit counter becomes 0 (S510), so the transmission side waits for the next data transmission (waiting time T) until it receives Update FC.

  Here, in order to eliminate the waiting time T (to avoid a decrease in the data transfer rate), it is only necessary to increase the buffer capacity (credit value) on the receiving side. However, since the circuit scale and cost increase, the buffer capacity on the receiving side also has a certain limit. Even if the buffer capacity on the receiving side can be increased to some extent, if the data transmission speed is increased by increasing the circuit operation on the transmitting side, it will eventually be possible to receive free buffer capacity information (Update FC) from the receiving side. In addition, on the transmitting side, the notified credit counter on the receiving side becomes zero.

  Therefore, even if you try to increase the data transmission speed by increasing the circuit frequency with the credit counter on the receiving side set to 0, the flow control works and the buffer capacity availability information (Update FC) is received from the receiving side. Until the receiving side receives a notification (Update FC) that the buffer capacity has been secured, the transmitting side cannot perform data transmission. In other words, during this time, the transmitting side is forced to “wait”.

  On the other hand, every time data is received, the receiving side issues an Update FC and notifies the transmitting side of a predetermined credit value (128 bytes) (S511). Each time the transmission side receives the Update FC, the transmission side increments the credit counter value by the value set in the Update FC (S512), and starts the next data transmission again.

  FIG. 6 is an example of a diagram showing the relationship between the operating frequency f of the circuit on the transmission side and the data transfer rate R. When the operating frequency f increases, the data transfer time t1 decreases, but the time t2 until the Update FC is received is constant. Therefore, the magnitude relationship between t1 and t2 varies depending on the operating frequency f. Depending on the magnitude relationship between t1 and t2, cases are classified as follows.

(1) t1> t2
In this case, the transmitting side can transmit data continuously in proportion to the operating frequency f without waiting for an Update FC from the receiving side. The transmission data and Update FC state at this time are schematically shown in FIG. When t1> t2, the data transfer rate R is determined by t1. Therefore, when the operating frequency f of the circuit on the transmission side is increased and t1 is shortened, the data transfer rate R increases. Further, when the operating frequency f of the circuit is lowered and t1 is lengthened, the data transfer rate R is lowered. Therefore, when t1> t2, the data transmitting apparatus according to the present invention increases the operating frequency of the circuit until t1 = t2 or until the operating frequency reaches the upper limit of the designed circuit.

(2) t1 = t2
In this case, the transmission side can continuously transfer data without waiting for the update FC on the reception side.
FIG. 8 schematically shows the transmission data and Update FC state at this time. When t1 = t2, the data transfer rate R is determined by t1 and t2. Even if the operating frequency f of the circuit on the transmission side is increased and t1 is shortened, the data transfer rate R is not improved because t2 is constant. Further, when the operating frequency f of the circuit is lowered and t1 is lengthened, the data transfer rate R is lowered. Therefore, when t1 = t2, the data transmitting apparatus according to the present invention maintains the operating frequency of this circuit.

(3) t1 <t2
In this case, the transmission side is waiting for an Update FC from the reception side. The transmission data and Update FC state at this time are schematically shown in FIG. When t1 <t2, the data transfer rate R is determined by t2. However, even if the operating frequency f of the circuit on the transmission side is increased to shorten t1, the data transfer rate R does not increase because t2 is constant. Even if the operation clock f of the circuit is lowered to increase t1, the data transfer rate R does not decrease because t2 is constant. Therefore, when t1 <t2, the data transmitting apparatus according to the present invention lowers the operating frequency of the circuit until t1 = t2 or until the operating frequency reaches the lower limit of the designed circuit.

  That is, the data transmission apparatus according to the present invention has a time (transmission time) required for the transmission side to transmit data corresponding to the credit value capacity of the reception side and the corresponding Update FC after the transmission side starts transmission of the data packet. The operating frequency of the circuit is adjusted (circuit frequency control means) so that the time until receiving the signal (reception time) becomes equal.

  Actually, the transmission side starts communication at the highest operating frequency in the initial state, and collects sample information. The sample information is credit value information by Init FC, actual measurement time of reception time until the transmission side starts data transmission and receives corresponding Update FC, and the like. When the actual measurement time is longer than the transmission time required to transmit data corresponding to the credit value capacity on the receiving side (t1 <t2), control is performed to lower the operating frequency until the actual measurement time and the transmission time are equal. . When the operating frequency is lowered, the power consumption is reduced. At this time, the data transmission rate does not change before and after the operating frequency is lowered (t1 = t2), and the fastest data rate is realized.

  If the actual measurement time is shorter than the transmission time required to transmit data corresponding to the credit value capacity on the receiving side (t1> t2), data transmission is continued at the highest operating frequency.

  Acquisition of sample information is performed continuously, and the operating frequency is controlled according to the reception time until the update FC is received.

  After the control to lower the operating frequency, when the actual reception time until Update FC is received is shorter than the transmission time required to transmit the data for the credit value capacity on the receiving side (t1> t2 ), Control to increase the operating frequency until the actual measurement time and the transmission time become equal.

  As described above, according to the data transmission device of the present invention, it is possible to realize data transmission with the minimum power consumption while maintaining the data transmission speed. That is, it is possible to provide a data transmission apparatus, an information processing apparatus, and a method that save power consumption by optimizing the data transfer speed and circuit operation in the flow control based on the credit base design.

  As mentioned above, this invention is not limited to the specific embodiment which concerns, A various deformation | transformation and change are possible within the range of the summary of this invention described in the claim. In other words, the present invention can also be applied to a data transmission apparatus that performs flow control based on information on the amount of data that can be received by the data reception apparatus, which corresponds to a credit value, without using flow control by PCI Express. it can.

  1 Information processing equipment

JP 2008-21024

Claims (5)

Transmitting means for transmitting data to the data receiving device;
Receiving means for receiving information related to the amount of data that can be received by the data receiving device, transmitted from the data receiving device;
Frequency control means for controlling an operating frequency corresponding to a transfer rate of data transmission by the transmission means,
The frequency control means is configured such that a transmission time required for the transmission means to transmit data having a data amount that can be received by the data reception apparatus is from the start of data transmission until the reception means receives the information. A data transmission device comprising frequency control means for lowering the operating frequency value until the transmission time and the reception time are equal to each other when the transmission time is smaller than the reception time.   The frequency control means is frequency control means for increasing the operating frequency until the value of the transmission time and the reception time are equal when the value of the transmission time is greater than the value of the reception time. The data transmission device according to claim 1. In an information processing apparatus having a data receiving apparatus and a data transmitting apparatus that transmits data to the data receiving apparatus,
The data transmission device includes:
Transmitting means for transmitting data to the data receiving device;
Receiving means for receiving information related to the amount of data that can be received by the data receiving device, transmitted from the data receiving device;
Frequency control means for controlling an operating frequency corresponding to a transfer rate of data transmission by the transmission means,
The frequency control means is configured such that a transmission time required for the transmission means to transmit data having a data amount that can be received by the data reception apparatus is from the start of data transmission until the reception means receives the information. An information processing apparatus, comprising: frequency control means for reducing an operating frequency value until the transmission time and the reception time are equal to each other when the transmission time and the reception time are equal to each other.   The frequency control means is frequency control means for increasing the operating frequency until the value of the transmission time and the reception time are equal when the value of the transmission time is greater than the value of the reception time. The information processing apparatus according to claim 3. Send data to the data receiver,
Transmitted from the data receiving device, receiving information related to the amount of data that can be received by the data receiving device;
Controlling the operating frequency corresponding to the transfer rate of data transmission to the data receiving device;
When the transmission time required for transmitting data having a receivable data amount of the data reception device is smaller than the reception time from the start of data transmission to the reception of the information, the transmission time and the reception An operating frequency control method, wherein the operating frequency value is lowered until the time value becomes equal.

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