JP2011176760A - Bias circuit, lna, lnb, receiver for communication, transmitter for communication, and sensor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias circuit capable of achieving reduction of temperature dependence, reduction of power voltage dependency, sufficient attenuation of noise superposed on a power voltage and a negative voltage and improvement of the degree of freedom in selection of a manufacturing process; and to provide an LNA, an LNB, a receiver for communication, a transmitter for communication, and a sensor system. <P>SOLUTION: The HEMT bias circuit 11 for an HEMT 1 having a source terminal 4 grounded includes: a double-power type operational amplifier AMP1; a resistive element RI; a first reference voltage source VX; and a second reference voltage source VY, wherein a positive input terminal, a negative input terminal and an output terminal of the operational amplifier AMP1 are connected to a drain terminal 3 of the HEMT 1, the second reference voltage source VY and a gate terminal of the HEMT 1, respectively. One-side terminal and the other-side terminal of the resistive element RI are connected to the drain terminal 3 of the HEMT 1 and the first reference voltage source VX, respectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a bias circuit for supplying a bias voltage to an FET, an LNA, an LNB, a communication receiver, a communication transmitter, and a sensor system. In particular, the present invention relates to a satellite broadcast reception LNB (Low Noise Block converter). The present invention relates to a bias circuit for HEMT (High Electron Mobility Transistor) used for LNA (Low Noise Amplifier).

  Conventionally, in satellite broadcasting, a minute signal of Ku band (12 GHz to 18 GHz) is transmitted from a communication satellite to a receiving side such as an individual home. On the receiving side, a signal from a communication satellite is received by an antenna, amplified and down-converted by an LNB, and transmitted to a tuner.

  Here, in order to satisfactorily receive a minute signal, a low NF (Noise Figure) is required for the LNA that amplifies the signal received by the antenna in the LNB. For this reason, HEMT is generally used for LNA. The HEMT is characterized by being able to support Ku-band reception and having a low NF. In order to design the gain and NF of the LNA using the HEMT to desired values, it is necessary to optimally design the drain voltage and drain current of the HEMT.

  The drain current characteristics of the HEMT will be described. FIG. 19 is a circuit diagram for explaining the bias of the HEMT. FIG. 20 is a graph showing the relationship between the gate voltage and drain current of the HEMT.

  The HEMT has a characteristic that the current value of the drain current ID is determined with respect to the voltage value of the gate voltage VG. Therefore, for example, when the optimum drain voltage VD is designed to be 2 V and the optimum drain current ID is 8 mA, the necessary gate voltage VG is about −0.4 V as shown in FIG. Therefore, it is necessary to apply a predetermined bias to the HEMT (FET) used for the LNA so that a desired drain voltage VD and a desired drain current ID can be obtained simultaneously. Therefore, the HEMT is driven at an appropriate operating point by supplying the gate voltage VG of about −0.4 V with a bias circuit. The bias circuit automatically searches and determines a gate voltage VG that simultaneously satisfies VD = 2V and ID = 8 mA.

  A plurality of bias circuits as described above have been proposed in the past for automatically controlling and supplying a gate voltage so as to simultaneously determine a desired drain voltage and a desired drain current. Among them, there is a bias circuit disclosed in Patent Document 1 as a basic circuit.

  FIG. 21 is a circuit diagram showing a configuration of a conventional HEMT bias circuit 500 disclosed in Patent Document 1. In FIG.

  The HEMT 501 bias circuit 500 is a bias circuit for the HEMT 501 whose source terminal is grounded. As shown in FIG. 21, the HEMT 501 bias circuit 500 includes a bipolar transistor BIP501, an emitter-side resistance element RE, a collector-side resistance element RC, a resistance element R501, and a resistance element R502.

  The emitter terminal of the bipolar transistor BIP501 is connected to the drain terminal of the HEMT 501 and is connected to the power supply voltage VDD via the emitter-side resistance element RE. The collector terminal of the bipolar transistor BIP501 is connected to the gate terminal of the HEMT 501 and to the negative power supply voltage VNEG via the collector-side resistance element RC. The base terminal of the bipolar transistor BIP501 is grounded via a resistance element R501 and is connected to the power supply voltage VDD via a resistance element R502.

  In the HEMT bias circuit 500, the HEMT 501 is incorporated in a negative feedback loop. Thereby, the drain voltage VD and the drain current ID of the HEMT 501 are automatically determined so as to be approximate expressions represented by the following expressions (1) and (2).

  The values in the above formulas are as follows.

V _D: voltage value of the drain voltage VD I _D: the current value V _B of the drain current ID: voltage V _BE of the base voltage VB: base-emitter voltage the voltage value of the VBE VDD: the voltage value of the power supply voltage VDD R _E: Resistance value of emitter-side resistance element RE R ₁ : Resistance value of resistance element R 501 R ₂ : Resistance value of resistance element R 502.

JP 59-194522 A (published November 5, 1984)

  However, the conventional HEMT bias circuit 500 has four problems: (1) temperature dependency, (2) power supply voltage dependency, (3) noise from power supply voltage and negative power supply voltage, and (4) limitation of the manufacturing process. Has a point. In the HEMT bias circuit 500, it is necessary to maintain a desired drain voltage and a desired drain current even when the ambient temperature or the power supply voltage varies. Further, it is necessary to prevent noise superimposed on the power source from being transmitted to the drain terminal and the gate terminal of the HEMT 501.

(1) Temperature Dependence In the HEMT bias circuit 500 shown in FIG. 21, the drain voltage VD and the drain current ID of the HEMT 501 are determined using the potential difference due to the base-emitter voltage VBE of the bipolar transistor BIP501. Yes. Therefore, there is a problem that the drain voltage VD and the drain current ID change depending on the ambient temperature.

  The base-emitter voltage VBE is expressed by the following equations (3) and (4).

  The values in the above formulas are as follows.

V _BE : Voltage value of base-emitter voltage VBE k: Boltzmann constant T: Absolute temperature q: Elementary charge I _C : Collector current b: Proportional constant m: Constant Eg: Band gap energy of silicon.

  The temperature dependence of the drain voltage VD and the drain current ID is obtained by differentiating the equations (1) and (2) with respect to the temperature T, and is represented by the following equations (5) and (6).

  Here, for example, it is assumed that ID = 8 mA, VD = 2V, and VDD = 3.3V are set. At this time, the parameters of the HEMT bias circuit 500 of FIG. 21 are selected such that R501 = 1 kΩ, R502 = 1.75 kΩ, and RE = 50Ω, and VBE = 0.8 V, Eg = 1.12 eV, m = −3. When / 2 is calculated as Expression (5) and Expression (6), the following Expression (7) and Expression (8) are obtained.

  That is, with a temperature change of 100 ° C., the drain voltage VD decreases by about 0.1 V, and the drain current ID increases by about 2 mA. In particular, the temperature dependence of the drain current ID is a problem. When the drain current ID increases as the ambient temperature rises, the temperature further rises due to heat generation of the HEMT 501. In response to this, the drain current ID further increases. Thereafter, thermal positive feedback occurs until the thermal equilibrium between heat dissipation and heat generation is reached. For this reason, there is a restriction that the ambient temperature of the HEMT bias circuit 500 must be kept low.

(2) Power supply voltage dependency The output signal of the LNA is determined by the drain voltage VD and the gate voltage VG of the HEMT 501. As shown in the above equations (1) and (2), the drain voltage VD in the HEMT bias circuit 500 of FIG. 21 is a linear function of the power supply voltage VDD. It can be seen that there is a strong correlation with fluctuations in noise.

(3) Noise from power supply voltage and negative power supply voltage When power supply voltage VDD and negative power supply voltage VNEG contain noise, PSRR (Power Supply Rejection Ratio) becomes important. PSRR is an index indicating how much noise from a certain power supply voltage (here, power supply voltage VDD and negative power supply voltage VNEG) attenuates at a terminal of interest.

(3-1) PSRR for power supply voltage VDD
In order to know in detail the dependency of the drain voltage VD and the gate voltage VG on the power supply voltage VDD, it is necessary to solve a small signal equivalent circuit. Thus, PSRR with respect to the power supply voltage VDD in the HEMT bias circuit 500 of FIG. 21 is shown using FIG. FIG. 22 is a small signal equivalent circuit 510 for the power supply voltage VDD of the HEMT bias circuit 500. The following equations (9) and (10) are obtained according to Kirchhoff's current law.

  The values in the above formulas are as follows.

gm: transconductance of the bipolar transistor BIP501 ge: collector-emitter conductance Gm of the bipolar transistor BIP501: HEMT501 of mutual conductance gds: between HEMT501 the drain and the source of the conductance VDD: voltage value V _D of the power supply voltage VDD: the voltage of the drain voltage VD Value V _G : Voltage value of the gate voltage VG V _B : Voltage value of the base voltage VB R _E : Resistance value of the emitter-side resistance element RE R _C : Resistance value of the collector-side resistance element RC

  Then, when the simultaneous linear equations of the equations (9) and (10) are solved with respect to the drain voltage VD and the gate voltage VG, the result is differentiated by the power supply voltage VDD, and expressed in decibels, the following equations (11) and (11) As shown in (12), the PSRR of the power supply voltage VDD with respect to the drain voltage VD and the gate voltage VG is known. Note that terms that are sufficiently small in the calculation process are approximated to simplify the equation.

  It can be seen from the equations (11) and (12) that the noise of the power supply voltage VDD is transmitted to the drain voltage VD and the gate voltage VG without being attenuated.

  Next, it is confirmed whether this attenuation is sufficient when viewed as an LNA. For example, suppose that it is actually desired to design ID = 8 mA, VD = 2V, and VDD = 3.3V. At this time, when Gm = 50 mS, R501 = 1 kΩ, R502 = 1.75 kΩ, and RE = 50Ω, the PSRR of the drain voltage VD and the gate voltage VG with respect to the power supply voltage VDD is expressed by the following equations (13) and ( 14).

  This value is bad for LNA applications and causes a problem when the power supply voltage VDD has noise. In the case of this example, if the signal power is -90 dBm, the noise power superimposed on the negative power supply voltage VNEG must be suppressed to an extremely minute level of at least about -90 dBm.

(3-2) PSRR for negative power supply voltage VNEG
As shown in FIG. 20, the gate voltage of the HEMT needs to be a negative voltage. That is, the HEMT used for the LNA requires two power supply voltages, a positive power supply voltage and a negative power supply voltage.

  Usually, the LNB installed in the parabolic antenna is connected to a television or a video set by a coaxial cable, and is supplied with power from the television or video set side via the coaxial cable. At this time, only the positive voltage power source is supplied. Therefore, a negative power supply voltage is often generated from a positive power supply voltage using a charge pump.

  FIG. 23 is a circuit diagram showing a configuration of negative voltage generation circuit 520. FIG. 24 is a waveform diagram showing a voltage waveform of the negative voltage VNEG.

  As shown in FIG. 23, the negative voltage generation circuit 520 is realized by a charge pump circuit. In the charge pump circuit, a pulsed voltage is applied to the capacitors 521 and 522, and electric charges are charged and discharged between the two capacitors 521 and 522, whereby the output terminal is gradually set to the negative voltage VNEG. The voltage waveform of the negative voltage VNEG is obtained by superimposing pulsed noise on a negative DC voltage as shown in FIG.

  In order to supply a negative voltage to the gate terminal of the HEMT 501 in the HEMT bias circuit 500 of FIG. 21, the output terminal of the negative voltage generation circuit 520 of FIG. 23 is connected to the VNEG terminal. At this time, if pulse-like noise superimposed on a negative DC voltage as shown in FIG. 24 leaks to the gate terminal and drain terminal of the HEMT 501, the output signal quality of the LNA deteriorates.

  FIG. 25 shows PSRR with respect to the negative power supply voltage VNEG in the HEMT bias circuit 500 of FIG. FIG. 25 is a small signal equivalent circuit 530 for the negative power supply voltage VNEG of the HEMT bias circuit 500. The following equations (15) and (16) are obtained according to Kirchhoff's current law.

  Each value in the above equations is the same as the above equations (9) and (10) except that VNEG is the voltage value of the negative power supply voltage VNEG.

  When the simultaneous linear equations of the equations (15) and (16) are solved with respect to the drain voltage VD and the gate voltage VG, the negative power supply voltage VNEG is differentiated and expressed in decibels, the following equation (17) and As shown in Expression (18), the PSRR of the negative power supply voltage VNEG with respect to the drain voltage VD and the gate voltage VG is known. Note that terms that are sufficiently small in the calculation process are approximated to simplify the equation.

  From Expression (17) and Expression (18), it can be seen that the noise of the negative power supply voltage VNEG is transmitted to the drain voltage VD and the gate voltage VG after being attenuated.

  Next, it is confirmed whether this attenuation is sufficient when viewed as an LNA. For example, suppose that it is actually desired to design ID = 8 mA, VD = 2V, and VDD = 3.3V. At this time, when Gm = 50 mS, R501 = 1 kΩ, R502 = 1.75 kΩ, RE = 50Ω, RC = 40 kΩ, and gm = 1 mS, the PSRR of the drain voltage VD and the gate voltage VG with respect to the negative power supply voltage VNEG is The following equations (19) and (20) are obtained.

  This value is not a sufficient amount of attenuation for LNA applications. In the case of this example, if the signal power is -90 dBm, the noise power to be superimposed on the negative power supply voltage VNEG must be suppressed to an extremely minute level of at least about -70 dBm.

(4) Limitation of Manufacturing Process Although there is no particular problem when the HEMT bias circuit 500 of FIG. 21 is realized with individual components, the manufacturing process is limited when it is intended to be realized with an integrated circuit (IC). There is a problem.

  As shown in FIG. 21, in order to control the drain voltage VD and drain current ID of the HEMT 501 using the VBE potential difference of the bipolar transistor BIP501, a PNP type bipolar transistor is essential. In this case, however, the conventional HEMT bias circuit 500 cannot be integrated by an inexpensive CMOS process, for example.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is as follows.
-Reduction of temperature dependence-Reduction of power supply voltage dependence-Sufficient attenuation of noise superimposed on power supply voltage and negative voltage (ie, improvement of PSRR with respect to power supply voltage and negative voltage)
The object is to provide a bias circuit, an LNA, an LNB, a communication receiver, a communication transmitter, and a sensor system that can realize an improvement in the degree of freedom in selecting a manufacturing process.

  In order to solve the above-described problem, the bias circuit of the present invention is a bias circuit for an amplifying FET whose source terminal is grounded, and includes a dual power supply type differential amplifier, a first resistance element, and a first resistance element. The differential amplifier includes a reference voltage source and a second reference voltage source. The differential amplifier has a positive input terminal connected to the drain terminal of the amplification FET, a negative input terminal connected to the second reference voltage source, and an output. The terminal is connected to the gate terminal of the amplification FET, and the first resistance element has one terminal connected to the drain terminal of the amplification FET and the other terminal connected to the first reference voltage source. It is characterized by that.

  According to the above configuration, the drain current and drain voltage of the amplifying FET can be simultaneously set to desired values, temperature dependence and power supply voltage dependence can be eliminated, and a very high noise removal rate can be obtained. It becomes. Furthermore, since the differential amplifier can be configured without requiring a special manufacturing process, the degree of freedom in selecting the manufacturing process can be improved.

  In the bias circuit of the present invention, the amplification FET is preferably a HEMT.

  The bias circuit of the present invention is a bias circuit for an amplifying FET whose source terminal is grounded, and includes a single power source type differential amplifier, a first reference voltage source, a second reference voltage source, 1 transistor, a 1st resistance element, a 2nd resistance element, and a negative power supply voltage source, The said 1st transistor has a 1st conduction | electrical_connection terminal, a 2nd conduction | electrical_connection terminal, and a control terminal, The said differential The amplifier has a first input terminal connected to the second reference voltage source, a second input terminal connected to the drain terminal of the amplification FET, an output terminal connected to the control terminal of the first transistor, One transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET, and the first resistance element has one terminal connected to the drain terminal of the amplification FET. Connected, the other terminal is The second resistance element is connected to the first reference voltage source, and has one terminal connected to the gate terminal of the amplification FET and the other terminal connected to the negative power supply voltage source. Yes.

  According to the above configuration, the drain current and drain voltage of the amplifying FET can be simultaneously set to desired values, temperature dependence and power supply voltage dependence can be eliminated, and a very high noise removal rate can be obtained. It becomes. Furthermore, since the differential amplifier can be configured without requiring a special manufacturing process, the degree of freedom in selecting the manufacturing process can be improved.

  In the bias circuit of the present invention, the amplification FET is preferably a HEMT.

  In the bias circuit of the present invention, the first transistor is a P-channel MOSFET, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are each a source of the P-channel MOSFET. It is preferable that the first input terminal and the second input terminal of the differential amplifier are a positive input terminal and a negative input terminal, respectively.

  In the bias circuit of the present invention, the first transistor is a PNP bipolar transistor, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are emitters of the PNP bipolar transistor, respectively. A terminal, a collector terminal, and a base terminal, and the first input terminal and the second input terminal of the differential amplifier are preferably a positive input terminal and a negative input terminal, respectively.

  In the bias circuit of the present invention, the first transistor is an N-channel MOSFET, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are each a drain of the N-channel MOSFET. A terminal, a source terminal, and a gate terminal, and the first input terminal and the second input terminal of the differential amplifier are preferably a negative input terminal and a positive input terminal, respectively.

  In the bias circuit of the present invention, the first transistor is an NPN bipolar transistor, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are each a collector of the NPN bipolar transistor. A terminal, an emitter terminal, and a base terminal, and the first input terminal and the second input terminal of the differential amplifier are preferably a negative input terminal and a positive input terminal, respectively.

  The bias circuit of the present invention is a bias circuit for an amplifying FET whose source terminal is grounded, and includes a single power supply type first differential amplifier, a single power supply type second differential amplifier, 1 transistor, 2nd transistor, 1st resistance element, 2nd resistance element, 3rd resistance element, 4th resistance element, 5th resistance element, reference voltage source, and negative power supply voltage source The first transistor has a first conduction terminal, a second conduction terminal, and a control terminal; the second transistor has a first conduction terminal, a second conduction terminal, and a control terminal; The first differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fifth resistance element, a second input terminal connected to the drain terminal of the amplification FET, and an output terminal. Is connected to the control terminal of the first transistor, The second differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fourth resistance element and the fifth resistance element, and the second input terminal connected to the reference voltage source. Connected, the output terminal is connected to the control terminal of the second transistor, the first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET, The second transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal grounded through the fifth resistance element, the fourth resistance element, and the third resistance element in this order, and the second transistor One resistance element has one terminal connected to the drain terminal of the amplification FET, the other terminal connected to the second conduction terminal of the second transistor, and the second resistance element has one terminal connected to the amplification terminal. FE It is connected to the gate terminal and the other terminal is characterized in that it is connected to the negative supply voltage source.

  According to the above configuration, the drain current and drain voltage of the amplifying FET can be simultaneously set to desired values, temperature dependence and power supply voltage dependence can be eliminated, and a very high noise removal rate can be obtained. It becomes. Furthermore, since the differential amplifier can be configured without requiring a special manufacturing process, the degree of freedom in selecting the manufacturing process can be improved.

  In the bias circuit of the present invention, the amplification FET is preferably a HEMT.

  In the bias circuit of the present invention, the first transistor and the second transistor are P-channel MOSFETs, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor. Are respectively a source terminal, a drain terminal, and a gate terminal of the P-channel MOSFET, and a first input terminal and a second input terminal of the first differential amplifier are a positive input terminal and a negative input terminal, respectively. The first input terminal and the second input terminal of the second differential amplifier are preferably a positive input terminal and a negative input terminal, respectively.

  In the bias circuit of the present invention, the first transistor and the second transistor are PNP-type bipolar transistors, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor. Are respectively an emitter terminal, a collector terminal, and a base terminal of the PNP-type bipolar transistor, and a first input terminal and a second input terminal of the first differential amplifier are a positive input terminal and a negative input terminal, respectively. The first input terminal and the second input terminal of the second differential amplifier are preferably a positive input terminal and a negative input terminal, respectively.

  In the bias circuit according to the present invention, the first transistor and the second transistor are N-channel MOSFETs, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor. Are respectively a drain terminal, a source terminal, and a gate terminal of the N-channel MOSFET, and a first input terminal and a second input terminal of the first differential amplifier are a negative input terminal and a positive input terminal, respectively. The first input terminal and the second input terminal of the second differential amplifier are preferably a negative input terminal and a positive input terminal, respectively.

  In the bias circuit of the present invention, the first transistor and the second transistor are NPN bipolar transistors, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor. Are respectively a collector terminal, an emitter terminal, and a base terminal of the NPN bipolar transistor, and a first input terminal and a second input terminal of the first differential amplifier are a negative input terminal and a positive input terminal, respectively. The first input terminal and the second input terminal of the second differential amplifier are preferably a negative input terminal and a positive input terminal, respectively.

  In the bias circuit of the present invention, a constant current source is preferably used instead of the third resistance element.

  In the bias circuit of the present invention, it is preferable that the fourth resistance element is removed.

  In the bias circuit of the present invention, it is preferable that a constant current source is used instead of the third resistance element, and the fourth resistance element is removed.

  The bias circuit of the present invention further includes a voltage withstand voltage protection element, and the protection element is inserted between the second conduction terminal of the first transistor and the gate terminal of the amplification FET. preferable.

  In the bias circuit of the present invention, it is preferable that the reference voltage source is composed of a band gap reference circuit that outputs a band gap voltage.

  The bias circuit of the present invention includes the first differential amplifier, the second differential amplifier, the first transistor, the second transistor, the first resistance element, the second resistance element, and the third resistance element. The fourth resistance element and the fifth resistance element are preferably formed of an integrated circuit.

  In the bias circuit of the present invention, the reference voltage source, the negative power supply voltage source, or both are preferably integrated with the integrated circuit.

  In order to solve the above problems, the LNA of the present invention includes an amplification FET whose source terminal is grounded, and the bias circuit, and uses the gate terminal of the amplification FET as an input terminal, and the drain of the amplification FET. The terminal is an output terminal.

  In order to solve the above problems, the LNB of the present invention is an LNB that amplifies and downconverts a signal received by an antenna and transmits it to the subsequent stage, and includes at least one LNA as an LNA that amplifies the signal. It is characterized by being.

  In order to solve the above problems, a communication receiver according to the present invention is a communication receiver, and includes a receiving device that receives a signal from a communication path, and an LNA that amplifies a signal output from the receiving device. The above-mentioned LNA is provided.

  In order to solve the above problems, the communication transmitter of the present invention is a communication transmitter, and transmits the LNA as an LNA for amplifying a signal to be transmitted and a signal amplified by the LNA to a communication path. And a transmission device.

  In order to solve the above problems, a sensor system according to the present invention is a sensor system that detects a change in an object and generates a signal corresponding to the detected change, and is output from the sensing device. The above-mentioned LNA is provided as an LNA for amplifying a signal to be amplified.

  As described above, the bias circuit of the present invention is a bias circuit for an amplifying FET whose source terminal is grounded, and is a dual power supply type differential amplifier, a first resistance element, and a first reference voltage source. And a second reference voltage source, wherein the differential amplifier has a positive input terminal connected to the drain terminal of the amplification FET, a negative input terminal connected to the second reference voltage source, and an output terminal The first resistance element is connected to the gate terminal of the amplification FET, and one terminal is connected to the drain terminal of the amplification FET, and the other terminal is connected to the first reference voltage source. .

  The bias circuit of the present invention is a bias circuit for an amplifying FET whose source terminal is grounded, and includes a single power source type differential amplifier, a first reference voltage source, a second reference voltage source, A first transistor, a first resistance element, a second resistance element, and a negative power supply voltage source, wherein the first transistor has a first conduction terminal, a second conduction terminal, and a control terminal, The differential amplifier has a first input terminal connected to the second reference voltage source, a second input terminal connected to the drain terminal of the amplification FET, an output terminal connected to the control terminal of the first transistor, The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET, and the first resistance element has one terminal connected to the drain of the amplification FET. Connected to the other terminal A child is connected to the first reference voltage source, and the second resistance element has one terminal connected to the gate terminal of the amplification FET and the other terminal connected to the negative power supply voltage source. is there.

  The bias circuit of the present invention is a bias circuit for an amplifying FET whose source terminal is grounded, and includes a single power supply type first differential amplifier, a single power supply type second differential amplifier, The first transistor, the second transistor, the first resistance element, the second resistance element, the third resistance element, the fourth resistance element, the fifth resistance element, the reference voltage source, and the negative power source voltage source The first transistor has a first conduction terminal, a second conduction terminal, and a control terminal, and the second transistor has a first conduction terminal, a second conduction terminal, and a control terminal, The first differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fifth resistance element, a second input terminal connected to the drain terminal of the amplification FET, Output terminal connected to the control terminal of the first transistor The second differential amplifier has a first input terminal connected to the second transistor second conduction terminal via the fourth resistance element and the fifth resistance element, and a second input terminal connected to the reference voltage source. The output terminal is connected to the control terminal of the second transistor, the first transistor has a first conduction terminal connected to the power supply voltage, and a second conduction terminal connected to the gate terminal of the amplification FET. The second transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal grounded through the fifth resistance element, the fourth resistance element, and the third resistance element in this order, The first resistance element has one terminal connected to the drain terminal of the amplification FET, the other terminal connected to the second conduction terminal of the second transistor, and the second resistance element has one terminal connected to the terminal. For amplification Is connected to the gate terminal of the ET, the other terminal is configured to be connected to the negative supply voltage source.

  According to each of the above configurations, the drain current and drain voltage of the amplifying FET can be simultaneously set to desired values, temperature dependence and power supply voltage dependence can be eliminated, and a very high noise removal rate can be obtained. There is an effect that can be done. Furthermore, since the differential amplifier can be configured without requiring a special manufacturing process, there is also an effect that the degree of freedom in selecting the manufacturing process can be improved.

1 is a circuit diagram showing a first embodiment of a bias circuit in the present invention. It is a circuit diagram which shows 2nd Embodiment of the bias circuit in this invention. 3 is a small signal equivalent circuit for the power supply voltage VDD of the bias circuit of FIG. 2. 3 is a small signal equivalent circuit for the negative power supply voltage source VNEG of the bias circuit of FIG. 2. It is a circuit diagram which shows 3rd Embodiment of the bias circuit in this invention. It is a circuit diagram which shows 6th Embodiment of the bias circuit in this invention. 7 is a small signal equivalent circuit for a power supply voltage VDD of a first negative feedback loop including an operational amplifier AMP3 in the bias circuit of FIG. It is a circuit diagram which shows 7th Embodiment of the bias circuit in this invention. It is a circuit diagram which shows 8th Embodiment of the bias circuit in this invention. It is a circuit diagram which shows 9th Embodiment of the bias circuit in this invention. It is a circuit diagram which shows one Embodiment of LNA in this invention. It is a circuit diagram which shows other embodiment of LNA in this invention. It is a figure which shows the example of 1 structure of a protection element. It is a circuit diagram which shows one structural example of a band gap reference circuit. It is a circuit block diagram which shows other embodiment of LNA in this invention. It is a circuit block diagram which shows one Embodiment of LNB in this invention. It is a block diagram which shows one Embodiment of the receiver for communication in this invention, and the transmitter for communication. It is a block diagram which shows one Embodiment of the sensor system in this invention. It is a circuit diagram for demonstrating the bias of HEMT. It is a graph which shows the relationship between the gate voltage and drain current of HEMT. It is a circuit diagram which shows the structure of the conventional HEMT bias circuit. 22 is a small-signal equivalent circuit for the power supply voltage VDD of the conventional HEMT bias circuit of FIG. It is a circuit diagram which shows the structure of a negative voltage generation circuit. It is a wave form diagram which shows the voltage waveform of the negative voltage VNEG. FIG. 22 is a small signal equivalent circuit for the negative power supply voltage VNEG of the conventional HEMT bias circuit of FIG. 21. 22 is a graph showing characteristics of (a) HEMT drain voltage and (b) HEMT drain current with respect to temperature change in the bias circuit of FIG. 6 and the conventional HEMT bias circuit of FIG. 21. It is a table | surface which shows the formula of the drain voltage and drain current of HEMT when showing the value of FIG. 22 is a graph showing characteristics of (a) HEMT drain voltage and (b) HEMT drain current with respect to power supply voltage change in the bias circuit of FIG. 6 and the conventional HEMT bias circuit of FIG. 21. 22 is a graph showing PSRR characteristics of (a) the HEMT drain terminal and (b) the HEMT gate terminal with respect to the power supply voltage VDD in the bias circuit of FIG. 6 and the conventional HEMT bias circuit of FIG. It is a table | surface which shows the formula of PSRR of the drain terminal and gate terminal of HEMT when showing the value of FIG. FIG. 22 is a graph showing PSRR characteristics of (a) the HEMT drain terminal and (b) the HEMT gate terminal with respect to the negative power supply voltage VNEG in the bias circuit of FIG. 6 and the conventional HEMT bias circuit of FIG. 21. FIG. 32 is a table showing PSRR equations for the drain terminal and the gate terminal of the HEMT when the values of FIG. 31 are shown.

  Each embodiment of the present invention will be described below with reference to the drawings. The configuration other than that described in each embodiment is the same as that of the above-described embodiment. Further, for convenience of explanation, in each embodiment, members having the same functions as those shown in the drawings of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted.

[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration example of the HEMT bias circuit 11 according to the present embodiment.

  The HEMT bias circuit 11 (bias circuit) of the present embodiment is a bias circuit for HEMT 1 (amplifying FET) whose source terminal 4 is grounded. As shown in FIG. 1, the HEMT bias circuit 11 includes an operational amplifier AMP1 (dual power supply type differential amplifier), a resistor element RI (first resistor element), a first reference voltage source VX, a second reference voltage source VY, and A negative power supply voltage source VNEG is provided.

  The operational amplifier AMP1 is a dual power supply type operational amplifier, and is configured as a differential amplifier. The positive power supply terminal and the negative power supply terminal of the operational amplifier AMP1 are connected to the power supply voltage VDD and the negative power supply voltage source VNEG, respectively. The positive input terminal (non-inverting input terminal) of the operational amplifier AMP1 is connected to the drain terminal 3 of the HEMT1. The negative input terminal (inverting input terminal) of the operational amplifier AMP1 is connected to the second reference voltage source VY. The output terminal of the operational amplifier AMP1 is connected to the gate terminal 2 of the HEMT1.

  The resistance element RI has two terminals, one terminal is connected to the drain terminal 3 of the HEMT 1 and the other terminal is connected to the first reference voltage source VX.

  The first reference voltage source VX and the second reference voltage source VY are voltage sources that generate a positive voltage. The first reference voltage source VX and the second reference voltage source VY are not affected at all by fluctuations in the temperature T and the power supply voltage VDD. The negative power supply voltage source VNEG is a voltage source that generates a negative power supply voltage (also referred to as a negative power supply voltage VNEG). The power supply voltage VDD is a positive power supply voltage and can be shared with other external members.

  In the HEMT bias circuit 11, HEMT1 is incorporated in the negative feedback loop of the operational amplifier AMP1. As a result, the drain voltage VD and the drain current ID of the HEMT 1 are automatically determined so as to be approximate expressions represented by the following expressions (21) and (22).

  The values in the above formulas are as follows.

V _D: voltage value of the drain voltage VD I _D: the current value of the drain current ID V _X: the voltage value of the first reference voltage source VX V _Y: the voltage value of the second reference voltage source VY R _I: the resistance of the resistance element RI value.

  That is, a predetermined voltage VY is obtained at the drain terminal 3 of the HEMT 1 by applying the reference voltage VY of the second reference voltage source VY to the input of the operational amplifier AMP1. Further, by inserting the resistor element RI between the first reference voltage source VX and the drain terminal 3 of the HEMT 1, a potential difference between the reference voltage VX and the reference voltage VY is generated at both ends of the resistor element RI. Obtain the current ID.

  Since Expression (21) and Expression (22) are not a function of the temperature T or the power supply voltage VDD, the drain voltage VD and the drain current ID of the HEMT 1 are not affected by these fluctuations. Therefore, the HEMT bias circuit 11 can eliminate temperature dependency and power supply voltage dependency.

  Further, since PSRR from the power supply voltage VDD and the negative power supply voltage VNEG to the gate terminal 2 of the HEMT 1 is equal to the PSRR of the operational amplifier AMP1, it is possible to obtain a very high noise removal rate.

  Furthermore, the operational amplifier AMP1 can be configured without requiring a special manufacturing process. Therefore, in the conventional HEMT bias circuit 500 shown in FIG. 21, a PNP type bipolar transistor is essential, but in the HEMT bias circuit 11, the type of transistor is not limited. Therefore, the HEMT bias circuit 11 has a high degree of freedom in selecting a manufacturing process, and an integrated circuit can be manufactured in various processes such as a CMOS process, a MOS process, a bipolar process, and a BiCMOS process.

  However, a single power supply is the mainstream in recent operational amplifiers (differential amplifiers). Further, the operational amplifier AMP1 shown in FIG. 1 has a demerit that it requires both positive and negative power supplies across the GND level.

[Embodiment 2]
FIG. 2 is a circuit diagram showing a configuration example of the HEMT bias circuit 12 of the present embodiment.

  The HEMT bias circuit 12 (bias circuit) of the present embodiment is a bias circuit for the HEMT 1 whose source terminal is grounded. As shown in FIG. 2, the HEMT bias circuit 12 includes an operational amplifier AMP2 (single power supply type differential amplifier, first differential amplifier), a resistor element RI, a first reference voltage source VX, a second reference voltage source VY, A negative power supply voltage source VNEG, a P-channel MOSFET (hereinafter referred to as PMOS transistor) PMOS1 (first transistor), and a resistance element RG (second resistance element) are provided.

  The operational amplifier AMP2 is a single power supply type operational amplifier, and is configured as a differential amplifier. The positive power supply terminal of the operational amplifier AMP2 is connected to the power supply voltage VDD. The positive input terminal (non-inverting input terminal, first input terminal) of the operational amplifier AMP2 is connected to the second reference voltage source VY. The negative input terminal (inverted input terminal, second input terminal) of the operational amplifier AMP2 is connected to the drain terminal of the HEMT1. The output terminal of the operational amplifier AMP2 is connected to the gate terminal (control terminal) of the PMOS transistor PMOS1.

  The source terminal (first conduction terminal) of the PMOS transistor PMOS1 is connected to the power supply voltage VDD. The drain terminal (second conduction terminal) of the PMOS transistor PMOS1 is connected to the gate terminal of HEMT1.

  The resistance element RG has two terminals, one terminal is connected to the gate terminal of the HEMT 1 and the other terminal is connected to the negative power supply voltage source VNEG.

  In the HEMT bias circuit 12, HEMT1 is incorporated in the negative feedback loop of the operational amplifier AMP2. Thereby, the drain voltage VD and the drain current ID of the HEMT 1 are automatically determined so as to be approximate expressions represented by the above formulas (21) and (22). According to the equations (21) and (22), the drain voltage VD and the drain current ID of the HEMT 1 are not affected by the temperature T and the power supply voltage VDD. It becomes possible to exclude sex.

<PSRR for power supply voltage VDD>
Next, PSRR of the drain voltage VD and the gate voltage VG of the HEMT 1 that is biased by the HEMT bias circuit 12 with respect to the power supply voltage VDD will be described with reference to FIG. FIG. 3 is a small signal equivalent circuit 13 for the power supply voltage VDD of the HEMT bias circuit 12 of FIG. The following equations (23) and (24) are obtained according to Kirchhoff's current law.

  The values in the above formulas are as follows.

gm: mutual conductance of PMOS transistor PMOS1 gp: conductance between drain and source of PMOS transistor PMOS1 Gm: mutual conductance of HEMT1 gds: conductance between drain and source of HEMT1 VDD: voltage value of power supply voltage VDD A2: DC gain of operational amplifier AMP2 V _D : Voltage value of the drain voltage VD V _G : Voltage value of the gate voltage VG R _I : Resistance value of the resistance element RI R _G : Resistance value of the resistance element RG

  Then, when the simultaneous linear equations of the equations (23) and (24) are solved with respect to the drain voltage VD and the gate voltage VG, the result is differentiated by the power supply voltage VDD, and expressed in decibels, the following equations (25) and As shown in (26), the PSRR of the power supply voltage VDD with respect to the drain voltage VD and the gate voltage VG is known. In the calculation process, terms that are sufficiently small are approximated to simplify the equation.

  It can be seen from the equations (25) and (26) that the noise of the power supply voltage VDD is attenuated and transmitted to the drain voltage VD and the gate voltage VG.

  Next, it is confirmed whether this attenuation is sufficient when viewed as an LNA. For example, suppose that it is actually desired to design ID = 8 mA, VD = 2 V, VDD = 3.3 V, and A2 = 10000. At this time, when Gm = 40 mS and RI = 62.5Ω are set, the PSRR of the drain voltage VD and the gate voltage VG with respect to the power supply voltage VDD is expressed by the following equations (27) and (28).

  This value is a sufficient amount of attenuation when viewed as an LNA. For example, when the signal power input to the LNA is −90 dBm, it can be seen that the LNA can obtain good signal amplification even if the noise power of −20 dBm is superimposed on the power supply voltage VDD.

<PSRR for negative power supply voltage VNEG>
Next, PSRR of the drain voltage VD and the gate voltage VG of the HEMT 1 that is biased by the HEMT bias circuit 12 with respect to the negative power supply voltage source VNEG is shown with reference to FIG.

  As the negative power supply voltage source VNEG of the HEMT bias circuit 12, the negative voltage generation circuit 520 shown in FIG. 23 can be used. In this case, the output terminal of the negative voltage generation circuit 520 in FIG. 23 is connected to one terminal of the resistance element RG. However, if pulse-like noise superimposed on the negative DC voltage of the negative power supply voltage source VNEG leaks out to the gate terminal and drain terminal of the HEMT 1, the output signal quality of the LNA deteriorates.

  FIG. 4 is a small signal equivalent circuit 14 for the negative power supply voltage source VNEG of the HEMT bias circuit 12 of FIG. The following equations (29) and (30) are obtained by Kirchhoff's current law.

  The values in the above equations are the same as the above equations (23) and (24) except that VNEG is the voltage value of the negative power supply voltage VNEG.

  Then, when the simultaneous linear equations of the equations (29) and (30) are solved with respect to the drain voltage VD and the gate voltage VG, the negative power supply voltage VNEG is differentiated and expressed in decibels, the following equation (31) and As shown in Expression (32), the PSRR of the negative power supply voltage VNEG with respect to the drain voltage VD and the gate voltage VG is known. In the calculation process, terms that are sufficiently small are approximated to simplify the equation.

  From Expression (31) and Expression (32), it can be seen that the noise of the negative power supply voltage VNEG is attenuated and transmitted to the drain voltage VD and the gate voltage VG.

  Next, it is confirmed whether this attenuation is sufficient when viewed as an LNA. For example, assume that it is actually desired to design ID = 8 mA, VD = 2V, VDD = 3.3V, and A2 = 10000. At this time, when Gm = 40 mS, gm = 1 mS, RI = 62.5Ω, and RG = 40 kΩ, the PSRR of the drain voltage VD and the gate voltage VG with respect to the negative power supply voltage VNEG is expressed by the following formula (33) and formula (34)

  This value is a sufficient amount of attenuation when viewed as an LNA. In the case of this example, if the signal power is −90 dBm, the noise power superimposed on the negative power supply voltage VNEG can be allowed even if the noise power is as large as +10 dBm.

  As described above, in the HEMT bias circuit 12, the PSRR of the drain voltage VD and the gate voltage VG with respect to the power supply voltage VDD and the negative power supply voltage VNEG becomes sufficiently small. Therefore, a very high noise removal rate can be obtained.

[Embodiment 3]
FIG. 5 is a circuit diagram showing a configuration example of the HEMT bias circuit 15 according to the present embodiment.

  In the HEMT bias circuit 15 (bias circuit) of the present embodiment, the PMOS transistor PMOS1 in the configuration of the HEMT bias circuit 12 of the second embodiment is an N-channel MOSFET (hereinafter referred to as an NMOS transistor) NMOS1 (first Transistor) and the connection destination of the positive input terminal and the negative input terminal of the operational amplifier AMP2 is replaced.

  That is, the positive input terminal (second input terminal) of the operational amplifier AMP2 is connected to the drain terminal of the HEMT1. The negative input terminal (first input terminal) of the operational amplifier AMP2 is connected to the second reference voltage source VY. The output terminal of the operational amplifier AMP2 is connected to the gate terminal (control terminal) of the NMOS transistor NMOS1. The drain terminal (first conduction terminal) of the NMOS transistor NMOS1 is connected to the power supply voltage VDD. The source terminal (second conduction terminal) of the NMOS transistor NMOS1 is connected to the gate terminal of HEMT1.

  As shown in FIG. 5, the HEMT bias circuit 15 has substantially the same structure as the HEMT bias circuit 12 of the second embodiment shown in FIG. Therefore, the HEMT bias circuit 15 can obtain substantially the same effect as the HEMT bias circuit 12 with respect to temperature dependency, power supply voltage dependency, and each PSRR.

[Embodiment 4]
The HEMT bias circuit of the present embodiment has a configuration in which the PMOS transistor PMOS1 is replaced with a PNP bipolar transistor (not shown) in the configuration of the HEMT bias circuit 12 of the second embodiment. The source terminal, drain terminal, and gate terminal of the PMOS transistor PMOS1 correspond to the emitter terminal, collector terminal, and base terminal of the PNP bipolar transistor, respectively. The HEMT bias circuit according to the present embodiment has substantially the same structure as the HEMT bias circuit 12 according to the second embodiment, and has substantially the same effect.

[Embodiment 5]
The HEMT bias circuit of the present embodiment has a configuration in which the NMOS transistor NMOS1 is replaced with an NPN bipolar transistor in the configuration of the HEMT bias circuit 15 of the third embodiment (not shown). The drain terminal, source terminal, and gate terminal of the NMOS transistor NMOS1 correspond to the collector terminal, emitter terminal, and base terminal of the NPN bipolar transistor, respectively. The HEMT bias circuit according to the present embodiment has substantially the same structure as the HEMT bias circuit 15 according to the third embodiment, and has substantially the same effect.

[Embodiment 6]
FIG. 6 is a circuit diagram illustrating a configuration example of the HEMT bias circuit 16 according to the present embodiment.

  The HEMT bias circuit 16 (bias circuit) of the present embodiment is a bias circuit for the HEMT 1 whose source terminal is grounded. As shown in FIG. 6, the HEMT bias circuit 16 includes an operational amplifier AMP2, an operational amplifier AMP3 (second differential amplifier), a resistor element RI, a resistor element RG, a resistor element R1 (fourth resistor element), and a resistor element R2 (fifth element). A resistance element), a resistance element RR (third resistance element), a PMOS transistor PMOS1, a PMOS transistor PMOS2 (second transistor), a reference voltage source VREF, and a negative power supply voltage source VNEG.

  In the HEMT bias circuit 16, the voltages from the first reference voltage source VX and the second reference voltage source VY used in the first to fifth embodiments are used as the operational amplifier AMP3, the PMOS transistor PMOS2, the resistance element R2, and the resistance element R1. , And a resistor element RR.

  The positive input terminal (first input terminal) of the operational amplifier AMP3 is connected to the drain terminal of the PMOS transistor PMOS2 via the resistance element R1 and the resistance element R2. The negative input terminal (second input terminal) of the operational amplifier AMP3 is connected to the reference voltage source VREF. The output terminal of the operational amplifier AMP3 is connected to the gate terminal (control terminal) of the PMOS transistor PMOS2.

  The source terminal (first conduction terminal) of the PMOS transistor PMOS2 is connected to the power supply voltage VDD. The drain terminal (second conduction terminal) of the PMOS transistor PMOS2 is grounded through the resistance element R2, the resistance element R1, and the resistance element RR in this order.

  As described above, the PMOS transistor PMOS2, the resistor element R2, and the resistor element R1 are incorporated in the negative feedback loop of the operational amplifier AMP3. Here, the potential between the drain terminal of the PMOS transistor PMOS2 and the resistance element R2 is VX. The potential between the resistance element R2 and the resistance element R1 is VY. A potential between the resistance element R1 and the resistance element RR is VZ. The potential VX corresponds to the voltage from the first reference voltage source VX. The potential VY corresponds to the voltage from the second reference voltage source VY.

  The positive input terminal of the operational amplifier AMP2 is connected to the potential VY, that is, the path between the resistance element R2 and the resistance element R1. The other terminal of the resistor element RI is connected to the potential VX, that is, a path between the drain terminal of the PMOS transistor PMOS2 and the resistor element R2.

  The reference voltage source VREF is a voltage source that generates a positive voltage. The reference voltage source VREF is not affected at all by changes in the temperature T and the power supply voltage VDD.

  In the HEMT bias circuit 16, a first negative feedback loop including the operational amplifier AMP3 and a second negative feedback loop including the operational amplifier AMP2 are formed. In the HEMT bias circuit 16, the gate voltage VG to the HEMT 1 is automatically controlled using these two negative feedback loops so that the drain voltage VD and the drain current ID of the HEMT 1 have desired values. .

<Drain voltage VD and drain current ID>
In the HEMT bias circuit 16, HEMT1 is incorporated in the negative feedback loop of the operational amplifier AMP2. Thereby, the drain voltage VD and the drain current ID of the HEMT 1 are automatically determined so as to be approximate expressions represented by the following expressions (35) and (36).

  The values in the above formulas are as follows.

V _D : voltage value of drain voltage VD I _D : current value of drain current ID VREF: voltage value of reference voltage source VREF R _I : resistance value of resistance element RI R _R : resistance value of resistance element RR R ₁ : resistance element the resistance value of R1 R _2: the resistance value of the resistance element R2.

<Temperature dependence of drain voltage VD and drain current ID>
The temperature coefficients of the drain voltage VD and the drain current ID are obtained by differentiating the equations (35) and (36) with the temperature T as shown in the following equations (37) and (38).

  As shown in the equations (37) and (38), the temperature coefficients of the drain voltage VD and the drain current ID are zero. Therefore, the HEMT bias circuit 16 can completely eliminate the temperature dependence.

<Dependence of drain voltage VD and drain current ID on power supply voltage>
The coefficient of variation of the drain voltage VD and the drain current ID with respect to the power supply voltage VDD is expressed by the following expressions (39) and (40) by differentiating the expressions (35) and (36) with the power supply voltage VDD. Asking.

  As shown in the equations (39) and (40), the coefficient of variation of the drain voltage VD and the drain current ID with respect to the power supply voltage VDD is zero. Therefore, the HEMT bias circuit 16 can completely eliminate the power supply voltage dependency.

<PSRR for power supply voltage VDD>
Next, PSRR of the drain voltage VD and the gate voltage VG of the HEMT 1 that is biased by the HEMT bias circuit 16 with respect to the power supply voltage VDD will be described.

  Since the above-described expressions (39) and (40) indicating the dependence on the fluctuation of the power supply voltage VDD are obtained by differentiating the approximate expressions (35) and (36) with respect to the power supply voltage VDD, they are strictly is not. In order to obtain PSRR indicating how much noise is attenuated at the VD terminal and the VG terminal when noise is superimposed on the power supply voltage VDD, it is usually obtained using a small signal equivalent circuit.

  However, in the HEMT bias circuit 16 shown in FIG. 6, the two negative feedback loops of the first negative feedback loop including the operational amplifier AMP3 and the second negative feedback loop including the operational amplifier AMP2 interact with each other. Analysis of a small signal equivalent circuit becomes extremely complicated. Therefore, in order to simplify the analysis, the two negative feedback loops are individually verified.

(First negative feedback loop)
First, it is verified how much the output potentials VX, VY, VZ of the first negative feedback loop including the operational amplifier AMP3 are affected by the power supply voltage VDD.

  FIG. 7 is a small signal equivalent circuit 17 for the power supply voltage VDD in the first negative feedback loop including the operational amplifier AMP3. The following equations (41), (42), and (43) are obtained by Kirchhoff's current law.

  The values in the above formulas are as follows.

gm: mutual conductance of PMOS transistor PMOS2 gds: conductance between drain and source of PMOS transistor PMOS2
A1: DC operational amplifier AMP3 gain VDD: the voltage value of the power supply voltage VDD VREF: reference voltage source VREF voltage value V _X: voltage V _Y of the potential VX: Voltage value V _Z potential VY: voltage value of the potential VZ R _R : Resistance value of resistance element RR R ₁ : Resistance value of resistance element R ₁ R ₂ : Resistance value of resistance element R ₂ .

  When the simultaneous linear equations of the equations (41), (42), and (43) are solved with respect to the potentials VX, VY, and VZ, the result is differentiated by the power supply voltage VDD, and expressed in decibels, the following equation is obtained: As shown in Equation (44), Equation (45), and Equation (46), PSRR of power supply voltage VDD with respect to potentials VX, VY, and VZ is known. In the calculation process, terms that are sufficiently small are approximated to simplify the equation.

  It can be seen from the equations (44), (45), and (46) that the noise of the power supply voltage VDD is transmitted to the potentials VX, VY, and VZ after being attenuated.

  Next, it is confirmed whether or not this attenuation is sufficient when viewed as a voltage source. For example, suppose that it is actually desired to design ID = 8 mA, VD = 2 V, VDD = 3.3 V, and A1 = 10000. At this time, when RR = 12 kΩ, R1 = 8 kΩ, and R2 = 5 kΩ are set, PSRR with respect to the power supply voltage VDD of the potentials VX, VY, and VZ is expressed by the following equations (47), (48), and (49) )become that way.

  This value is a sufficient amount of attenuation when viewed as a voltage source.

(Second negative feedback loop)
Next, the second negative feedback loop including the operational amplifier AMP2 will be described.

  The values shown in Expression (47), Expression (48), and Expression (49) can be approximated to the ground level in terms of small signals. That is, in the small signal analysis of the second negative feedback loop including the operational amplifier AMP2, the potentials VX, VY, and VZ can be terminated at the GND level.

  Therefore, an equivalent circuit for obtaining PSRR of the drain voltage VD and the gate voltage VG of the HEMT 1 in the second negative feedback loop with respect to the power supply voltage VDD is the small signal equivalent circuit 13 shown in FIG. Therefore, the small signal equivalent circuit 13 of FIG. 3 is an equivalent circuit of the HEMT bias circuit 12 of the second embodiment. Therefore, the PSRR for the drain voltage VD of the HEMT 1 and the gate voltage VG with respect to the power supply voltage VDD is the same as that of the embodiment. The effect equivalent to that of the second HEMT bias circuit 12 can be obtained.

<PSRR for negative power supply voltage VNEG>
As described above, in the small signal analysis of the second negative feedback loop including the operational amplifier AMP2, the potentials VX, VY, and VZ can be terminated at the GND level.

  Therefore, the equivalent circuit expected from the negative power supply voltage source VNEG is the small signal equivalent circuit 14 shown in FIG. Therefore, the small signal equivalent circuit 14 of FIG. 4 is an equivalent circuit of the HEMT bias circuit 12 of the second embodiment. Therefore, the PSRR for the drain voltage VD of the HEMT 1 and the negative power supply voltage VNEG of the gate voltage VG It is possible to obtain the same effect as that of the HEMT bias circuit 12 of the form 2.

  As described above, in the HEMT bias circuit 16, the PSRR of the drain voltage VD and the gate voltage VG with respect to the power supply voltage VDD and the negative power supply voltage VNEG becomes sufficiently small. Therefore, a very high noise removal rate can be obtained.

[Embodiment 7]
FIG. 8 is a circuit diagram showing a configuration example of the HEMT bias circuit 18 according to the present embodiment.

  The HEMT bias circuit 18 (bias circuit) of the present embodiment has a configuration in which the resistance element RR is replaced with a constant current source IB in the configuration of the HEMT bias circuit 16 of the sixth embodiment. With this configuration, the drain voltage VD and the drain current ID of the HEMT 1 are expressed by the following equations (50) and (51).

  The values in the above equations are the same as the above equations (35) and (36) except that IB is the current value of the constant current source IB.

  In the integrated circuit, the relative value of the resistance values of the two resistance elements can be reduced. That is, the merit of the HEMT bias circuit 18 having the above configuration is that the current variation can be reduced because the expression of the drain current ID is the ratio of the resistance values. However, in Formula (50), since the term R1 exists in the drain voltage VD, the variation in the drain voltage VD remains large.

  According to the equations (50) and (51), it is understood that the temperature coefficient of the drain voltage VD and the drain current ID becomes zero by differentiating with the temperature T. Therefore, the HEMT bias circuit 18 can completely eliminate the temperature dependence.

  Further, by differentiating the expressions (50) and (51) with the power supply voltage VDD, it can be seen that the coefficient of variation of the drain voltage VD and the drain current ID with respect to the power supply voltage VDD becomes zero. Therefore, the HEMT bias circuit 18 can completely eliminate the power supply voltage dependency.

  Further, in the HEMT bias circuit 18, the PSRR of the drain voltage VD and the gate voltage VG with respect to the power supply voltage VDD and the negative power supply voltage VNEG becomes sufficiently small, so that a very high noise removal rate can be obtained.

  Therefore, the HEMT bias circuit 18 can obtain the same effects as the HEMT bias circuit 16 of the sixth embodiment shown in FIG. 6 with respect to temperature dependency, power supply voltage dependency, and each PSRR.

[Embodiment 8]
FIG. 9 is a circuit diagram showing a configuration example of the HEMT bias circuit 19 according to the present embodiment.

  The HEMT bias circuit 19 (bias circuit) of the present embodiment has a configuration in which the resistance element R1 is removed from the configuration of the HEMT bias circuit 18 of the seventh embodiment. With this configuration, the drain voltage VD and the drain current ID of the HEMT 1 are expressed by the following equations (52) and (53).

  The advantage of the HEMT bias circuit 19 having the above configuration is that if the reference voltage source VREF having a small variation in the drain voltage VD is applied and a current source having a small variation is applied to the constant current source IB, the drain voltage VD and the drain voltage VD The current ID is hardly affected by variations in the manufacturing process.

  The HEMT bias circuit 19 can obtain the same effects as the HEMT bias circuit 16 of the sixth embodiment shown in FIG. 6 with respect to temperature dependency, power supply voltage dependency, and each PSRR.

[Embodiment 9]
FIG. 10 is a circuit diagram showing a configuration example of the HEMT bias circuit 20 according to the present embodiment.

  The HEMT bias circuit 20 (bias circuit) of the present embodiment is different from the configuration of the HEMT bias circuit 16 of the sixth embodiment in that the PMOS transistors PMOS1 and PMOS2 are replaced by NMOS transistors NMOS1 and NMOS2 (first transistor and second transistor). And the connection destinations of the positive input terminal and the negative input terminal of the operational amplifiers AMP2 and OPAMP3 are replaced.

  That is, the positive input terminal (second input terminal) of the operational amplifier AMP2 is connected to the drain terminal of the HEMT1. The negative input terminal (first input terminal) of the operational amplifier AMP2 is connected to the potential VY. The output terminal of the operational amplifier AMP2 is connected to the gate terminal of the NMOS transistor NMOS1. The positive input terminal (second input terminal) of the operational amplifier AMP3 is connected to the reference voltage source VREF. The negative input terminal (first input terminal) of the operational amplifier AMP3 is connected to the source terminal of the NMOS transistor NMOS2 via the resistance element R1 and the resistance element R2. The output terminal of the operational amplifier AMP3 is connected to the gate terminal (control terminal) of the NMOS transistor NMOS2. The drain terminal (first conduction terminal) of the NMOS transistor NMOS1 is connected to the power supply voltage VDD. The source terminal (second conduction terminal) of the NMOS transistor NMOS1 is connected to the gate terminal of HEMT1. The drain terminal of the NMOS transistor NMOS2 is connected to the power supply voltage VDD. The source terminal of the NMOS transistor NMOS2 is grounded through the resistor element R2, the resistor element R1, and the resistor element RR in this order.

  As shown in FIG. 10, the HEMT bias circuit 20 has substantially the same structure as the HEMT bias circuit 16 of the sixth embodiment shown in FIG. Therefore, the HEMT bias circuit 20 can obtain substantially the same effect as the HEMT bias circuit 16 with respect to temperature dependency, power supply voltage dependency, and each PSRR.

[Embodiment 10]
The HEMT bias circuit of the present embodiment has a configuration (not shown) in which the PMOS transistors PMOS1 and PMOS2 are replaced with PNP-type bipolar transistors in the configuration of the HEMT bias circuit 16 of the sixth embodiment. The HEMT bias circuit according to the present embodiment has substantially the same structure as the HEMT bias circuit 16 according to the sixth embodiment, and has substantially the same effect.

[Embodiment 11]
The HEMT bias circuit of the present embodiment has a configuration (not shown) in which the NMOS transistors NMOS1 and NMOS2 are replaced with NPN bipolar transistors in the configuration of the HEMT bias circuit 20 of the ninth embodiment. The HEMT bias circuit according to the present embodiment has substantially the same structure as the HEMT bias circuit 20 according to the ninth embodiment, and has substantially the same effect.

[Embodiment 12]
FIG. 11 is a circuit diagram showing a configuration example of the LNA 50 of the present embodiment. As shown in FIG. 11, the LNA 50 includes a HEMT 1 and a HEMT bias circuit 51 (bias circuit). In the LNA 50, the input portion of the LNA 50 is provided at the gate terminal of the HEMT 1, and the output portion of the LNA 50 is provided at the drain terminal of the HEMT 1.

  The HEMT bias circuit 51 has a configuration in which the PMOS transistors PMOS 1 and PMOS 2 in the configuration of the HEMT bias circuit 16 of the sixth embodiment are replaced with active elements 52 and 53 (first transistor and second transistor). The active elements 52 and 53 have two conduction terminals (indicated by “1” and “3” in the figure) and one control terminal (indicated by “2” in the figure). In the active elements 52 and 53, a predetermined voltage is applied to the control terminal, whereby the two pain lead terminals are brought into conduction. By simply providing them as the active elements 52 and 53, the positive and negative polarities (signs) of the input terminals of the operational amplifiers AMP2 and AMP3 do not matter.

  The HEMT bias circuit 51 is integrated (integrated circuit) (integrated circuit 54). The integrated circuit 54 includes a VREF terminal for connection to the reference voltage source VREF, a VNEG terminal for connection to the negative power supply voltage source VNEG, a VD terminal for connection to the drain terminal of HEMT1, and a gate terminal of HEMT1. A VG terminal for connection is provided.

  The LNA 50 including the HEMT 1 to which the HEMT bias circuit 51 is connected has a structure similar to that of the HEMT bias circuit 16 of the sixth embodiment, and the above HEMT is related to temperature dependency, power supply voltage dependency, and each PSRR. An effect similar to that of the bias circuit 16 can be obtained.

  The transistors applicable as the active elements 52 and 53 may be PMOS transistors, NMOS transistors, NPN bipolar transistors, PNP bipolar transistors, and the like, and these may be combined. That is, it can be said that the HEMT bias circuit 51 is one of the HEMT bias circuits of the sixth and ninth to eleventh embodiments, or a combination of these HEMT bias circuits.

  In FIG. 11, the positive and negative polarities of the input terminals of the operational amplifiers AMP2 and AMP3 are uncertain because the positive and negative polarities of the operational amplifier AMP2 depend on the polarity of the transistor used for the active element 52. This is because the positive and negative polarities of the operational amplifier AMP3 depend on the polarity of the transistor used for 53, so that a plurality of combinations are expressed collectively. The sign of each input terminal (indicated by “1” and “2” in the figure) of the operational amplifiers AMP2 and AMP3 is determined according to the active elements 52 and 53.

  As described above, the HEMT bias circuit 51 has as many variations as the number of combinations of transistors applied to the active elements 52 and 53. Further, the HEMT bias circuit 51 can be modified as shown in the seventh and eighth embodiments. Furthermore, as the HEMT bias circuit 51, the HEMT bias circuit of the first to fifth embodiments may be applied.

[Embodiment 13]
In the twelfth embodiment, when the HEMT bias circuit 51 is integrated, the breakdown voltage of the active element 52 often becomes a problem. This is because a voltage between VDD and VG is always applied to the active element 52. Since the gate voltage VG is a negative voltage, the potential difference between VDD and VG is higher than the potential difference between VDD and GND. Therefore, if integration is performed by a manufacturing process in which the potential difference between VDD and GND is not guaranteed, there is a problem in terms of reliability.

  In addition, assuming that the circuit is initially started up or the circuit operation is switched, it is assumed that a voltage between VDD and VNEG is transiently applied to the active element 52. Also in this case, since the negative power supply voltage VNEG is a negative voltage, there may be a problem in terms of device reliability. Therefore, it is desirable for the HEMT bias circuit to solve these problems.

  FIG. 12 is a circuit diagram illustrating a configuration example of the LNA 60 according to the present embodiment. As shown in FIG. 12, the LNA 60 has a configuration in which a voltage breakdown voltage protection element 61 is provided in the HEMT bias circuit 51 in addition to the configuration of the LNA 50 of the twelfth embodiment.

  The protection element 61 is inserted between the active element 52 and the VG terminal (that is, the gate terminal of the HEMT 1). As the protection element 61, for example, as shown in FIG. 13, (a) a resistance element, (b) a PMOS transistor, (c) a PNP-type bipolar transistor, or the like can be used.

  By providing the protection element 61, the active element 52 can be driven within the allowable withstand voltage of the active element 52. Therefore, the LNA 60 can provide excellent reliability in addition to obtaining the same effect as the HEMT bias circuit 16 of the sixth embodiment with respect to temperature dependency, power supply voltage dependency, and each PSRR. It becomes.

[Embodiment 14]
The voltage source for applying a potential to the VREF terminal of the HEMT bias circuits of the sixth to thirteenth embodiments needs to be a voltage source having no temperature dependency and no power supply voltage dependency. Therefore, a voltage source including a band gap reference circuit is shown as an example of such a voltage source.

  FIG. 14 is a circuit diagram showing a configuration example of the band gap reference circuit 70. The band gap reference circuit 70 has a conventional general configuration. A general bandgap reference circuit is known as a circuit configuration as shown in FIG. 14, and is known as a voltage source from which a voltage (BGR voltage) having no temperature dependence and no power supply voltage dependence is obtained.

  By applying the band gap voltage (BGR voltage) generated by the band gap reference circuit 70 to the VREF terminal of the HEMT bias circuit 71 (bias circuit), when the HEMT bias circuit 71 is applied to the LNA, the temperature dependence In addition, the power supply voltage dependency can be further reduced.

[Embodiment 15]
Any of the HEMT bias circuits of the first to fourteenth embodiments is a circuit suitable for integration. As an example, the integrated circuit 54 is shown in the twelfth embodiment. In the twelfth embodiment, the reference voltage source VREF and the negative power supply voltage source VNEG are excluded from the integrated circuit 54. However, the reference voltage source VREF and the negative power supply voltage source VNEG also correspond to the circuits constituting the voltage source. Similarly, it can be easily integrated.

  FIG. 15 is a circuit block diagram showing a configuration example of the LNA 80 according to the present embodiment. As shown in FIG. 15, in the LNA 80, the HEMT 1 receives a bias from the integrated circuit 81. The integrated circuit 81 is a circuit in which a HEMT bias circuit 82 (bias circuit), a reference voltage generation circuit 83, and a negative voltage generation circuit 84 are integrated. As the HEMT bias circuit 82, any of the HEMT bias circuits described above can be applied.

  As the reference voltage generation circuit 83, the bandgap reference circuit 70 shown in the fourteenth embodiment can be applied. Thereby, it is possible to integrate by a standard CMOS process or bipolar process.

  As the negative voltage generation circuit 84, a negative voltage generation circuit 520 as shown in FIG. 23 can be applied. According to this, since the negative voltage generation circuit 84 can be configured only by the pulse generation source, the capacitor, and the diode, it is possible to integrate by a CMOS process or a bipolar process without requiring a special manufacturing process. It is.

  As described above, the LNA 80 includes the HEMT bias circuit 82, the reference voltage generation circuit 83, and the negative voltage generation circuit 84 as the integrated circuit 81. Thereby, it is possible to reduce the mounting area and the mounting cost.

[Embodiment 16]
FIG. 16 is a block diagram illustrating a configuration example of the LNB 100 according to the present embodiment.

  As shown in FIG. 16, the LNB 100 includes a feed horn 101 (antenna), a horizontally polarized LNA 104 (LNA), a vertically polarized LNA 105 (LNA), a 2nd LNA 106 (LNA), an image removal BPF 107, and a Ku band amplifier 108. , Mixer 109, local oscillator 110, low band amplifier 111, local frequency selector 112, horizontal / vertical selector 113, LNA-H HEMT bias circuit 114 (bias circuit), LNA-V HEMT bias circuit 115 (bias circuit), A 2nd LNA HEMT bias circuit 116 (bias circuit), a negative voltage generation circuit 117, a band gap reference circuit 118, a power supply regulator 119, and a connector 120 are provided. The LNB 100 amplifies and down-converts the signal received by the feed horn 101 and transmits it to the TV set 122 and the video set 123 in the subsequent stage.

  What should be noted in the present embodiment is that, in the LNB 100, the HEMT bias circuit of the above-described embodiment is used as a bias circuit for the LNA using the HEMT. That is, as the LNA-H HEMT bias circuit 114, the LNA-V HEMT bias circuit 115, and the 2nd LNA HEMT bias circuit 116, any one of the HEMT bias circuits of the above-described embodiments is used. Thereby, in LNB100, it becomes possible to improve the temperature dependence in a LNA part, power supply voltage dependence, and each PSRR from the past.

  Hereinafter, the configuration and operation of the LNB 100 will be briefly described.

  A radio signal transmitted from a communication satellite using a Ku-band carrier is fed by a horizontally polarized antenna 102 (a left-handed circularly polarized antenna) or a vertically polarized antenna 103 (a right-handed circularly polarized antenna) inside the feed horn 101. , Converted into current. The current converted by the horizontally polarized antenna 102 is output to the horizontally polarized LNA 104. The current converted by the vertically polarized antenna 103 is output to the vertically polarized LNA 105.

  In the horizontal polarization LNA 104 and the vertical polarization LNA 105, the current signal is converted into a voltage signal and then amplified. These amplified signals are further amplified by the 2nd LNA 106 and then output to the image removal BPF 107. Since a very low NF is required for the horizontal polarization LNA 104, the vertical polarization LNA 105, and the 2nd LNA 106, HEMT is used.

  The image removal BPF 107 removes unnecessary signals such as signals in the image band. Then, it is further amplified by the Ku band amplifier 108 and then output to the mixer 109. Since the Ku-band amplifier 108 does not require low NF, HEMT is rarely used.

  In the mixer 109, the signal from the Ku-band amplifier 108 is multiplied by the local signal output from the local oscillator 110 to be converted into an L-BAND (1 to 2 GHz band) signal. Then, amplification is performed by the L-BAND amplifier 111 and matching is performed at 75Ω in order to drive the coaxial cable 121.

  The LNB 100 includes a connector 120 to which a coaxial cable 121 is connected. The LNB 100 is connected to the TV set 122 and the video set 123 via the coaxial cable 121. The coaxial cable 121 has the following four roles.

  (1) A role of transmitting a signal received by the LNB 100 to the TV set 122 or the video set 123. That is, it is a role to transmit the output signal of the L-BAND amplifier 111 to the TV set 122 or the video set 123.

  (2) The role of transmitting power for driving the LNB 100 to the LNB 100 from the TV set 122 or the video set 123 side. The transmitted power is supplied to the power regulator 119. Power transmission for driving the LNB 100 is usually as high as about 18V. For this reason, after being stepped down by the power supply regulator 119, the stabilized power supply voltage is supplied to each block in the LNB 100.

  (3) A switching signal for switching whether to receive a horizontally polarized wave (left-handed circularly polarized wave) signal or a vertically polarized wave (right-handed circularly polarized wave) signal from the TV set 122 or the video set 123 side, The role of transmitting to the LNB 100. The transmitted switching signal is supplied to the horizontal / vertical selector 113. The horizontal / vertical selector 113 drives the LNA-H HEMT bias circuit 114 or the LNA-V HEMT bias circuit 115 based on the switching signal. As a result, the bias power source of the horizontal polarization LNA 104 and the vertical polarization LNA 105 is switched.

  (4) A role of transmitting a switching signal for switching the frequency of the local oscillator 110 from the TV set 122 or the video set 123 side to the LNB 100 in order to switch the band of the received signal. The transmitted switching signal is supplied to the local frequency selector 112. The local frequency selector 112 switches the oscillation frequency of the local oscillator 110 so that the selected local frequency is obtained by discriminating the switching signal.

  Note that the LNB 100 includes a negative voltage generation circuit 117 and a band gap reference circuit 118, which may be appropriately provided as necessary.

  The LNB 100 has a plurality of functional blocks. Therefore, the LNA-H HEMT bias circuit 114, the LNA-V HEMT bias circuit 115, and the 2nd LNA HEMT bias circuit 116 may be integrated with some or all of the functional blocks. Good. By integrating, the mounting area and the mounting cost of the components can be reduced, and the LNB 100 can be reduced in size and cost.

  In FIG. 16, Ku-band amplifier 108, mixer 109, local oscillator 110, low-band amplifier 111, local frequency selector 112, horizontal / vertical selector 113, LNA-H HEMT bias circuit 114, and LNA-V HEMT bias. An example in which the circuit 115, the 2nd LNA HEMT bias circuit 116, the negative voltage generation circuit 117, and the band gap reference circuit 118 are integrated (integrated circuit 124) is shown.

[Embodiment 17]
FIG. 17 is a block diagram illustrating a configuration example of the communication system 150 according to the present embodiment.

  As illustrated in FIG. 17, the communication system 150 is a system configured such that a transmitter 151 (a communication transmitter) and a receiver 152 (a communication receiver) communicate with each other via a communication path 153. . The communication path 153 may be of any type, such as when wireless, wired, electromagnetic coupling, or light is used.

  The transmitter 151 includes a transmission device 154, an LNA 155, a HEMT bias circuit 156 (bias circuit), and a signal processing circuit 157. In the transmitter 151, the LNA 155 amplifies the signal processed by the signal processing circuit 157 and outputs the amplified signal to the transmission device 154. The transmission device 154 is driven by receiving a signal from the LNA 155 and transmits the signal to the receiver 152 via the communication path 153. A gate voltage as a bias voltage is applied to the LNA 155 from the HEMT bias circuit 156.

  The receiver 152 includes a receiving device 158, an LNA 159, a HEMT bias circuit 160 (bias circuit), and a signal processing circuit 161. In the receiver 152, the signal transmitted via the communication path 153 is received by the receiving device 158 and output to the LNA 159. The LNA 159 amplifies the input signal and outputs it to the signal processing circuit 161. A gate voltage as a bias voltage is applied to the LNA 159 from the HEMT bias circuit 160.

  As the HEMT bias circuit 156 of the transmitter 151 and the HEMT bias circuit 160 of the receiver 152, the HEMT bias circuit of the above-described embodiment is used. As a result, it is possible to configure the communication system 150 that is more stable with respect to temperature fluctuations and power supply voltage fluctuations than before and that has high power supply noise removal performance due to high PSRR.

[Embodiment 18]
FIG. 18 is a block diagram illustrating a configuration example of the sensor system 170 according to the present embodiment.

  As shown in FIG. 18, the sensor system 170 includes a sensing device 171, an LNA 172, a HEMT bias circuit 173 (bias circuit), and a signal processing circuit 174. The sensing device 171 detects a change in an object and generates a signal corresponding to the detected change, but the type of physical quantity to be detected is not limited. In the sensor system 170, the signal detected and generated by the sensing device 171 is amplified by the LNA 172 and output to the signal processing circuit 174. A gate voltage as a bias voltage is applied to the LNA 172 from the HEMT bias circuit 173.

  As the HEMT bias circuit 173, the HEMT bias circuit of the above-described embodiment is used. As a result, it is possible to configure the sensor system 170 that is more stable with respect to temperature fluctuations and power supply voltage fluctuations than before and that has high power supply noise removal performance due to high PSRR.

  Finally, in Embodiments 1 to 18 described above, the HEMT bias circuit for HEMT has been described. However, the HEMT bias circuit is not necessarily limited to the HEMT, and can be applied to transistors other than the HEMT. For example, a general transistor such as a JFET, MOSFET, or bipolar transistor can be used, and can be used as a bias circuit for this. Needless to say, the HEMT is particularly effective, but the same effect can be obtained with other transistors.

  The effect of the bias circuit according to the present invention is shown quantitatively and visually. Here, as an example, a result of comparison between the HEMT bias circuit 16 of FIG. 6 described in the sixth embodiment and the conventional HEMT bias circuit 500 shown in FIG. 21 is shown.

  In addition, the specification with respect to HEMT1 * 501 was defined as follows.

  (1) VDD = 3.3V.

  (2) The drain voltage to the HEMT is VD = 2V.

  (3) The drain current to the HEMT is ID = 8 mA.

  In the following, the HEMT bias circuit 16 of FIG. 6 is described as the present embodiment, and the conventional HEMT bias circuit 500 of FIG. 21 is described as a conventional example.

  FIG. 26 shows the characteristics of (a) HEMT drain voltage and (b) HEMT drain current with respect to temperature changes. FIG. 27 shows HEMT drain voltage and drain current equations for the values shown in FIG.

  In the conventional example, as described above, both the drain voltage and the drain current are highly temperature dependent. On the other hand, according to the present embodiment, both the drain voltage and the drain current have very little temperature dependency.

  Therefore, in this embodiment, the dependency of the drain voltage VD and the drain current ID supplied to the HEMT on the ambient temperature is smaller than that of the conventional example. Therefore, when the LNB is used, the NF and gain of the LNA can be stably maintained even under different temperature conditions.

  FIG. 28 shows the characteristics of (a) the HEMT drain voltage and (b) the HEMT drain current with respect to the power supply voltage change.

  In the conventional example, as described above, both the drain voltage and the drain current are highly dependent on the power supply voltage. On the other hand, according to the present embodiment, both the drain voltage and the drain current have extremely small power supply voltage dependency.

  Therefore, in this embodiment, the dependency of the drain voltage VD and the drain current ID supplied to the HEMT on the power supply voltage is smaller than that of the conventional example. Therefore, when the LNB is used, the NF and gain of the LNA can be stably maintained even under different power supply voltage conditions.

  FIG. 29 shows PSRR characteristics of (a) the HEMT drain terminal and (b) the HEMT gate terminal with respect to the power supply voltage VDD. FIG. 30 shows the PSRR equation of the drain terminal and the gate terminal of the HEMT when the values of FIG. 29 are shown.

  In the conventional example, as described above, both the drain terminal and the gate terminal have high PSRR, and the noise suppression ratio from the power supply voltage VDD is poor. On the other hand, according to the present embodiment, the PSRR of the drain terminal and the gate terminal with respect to the power supply voltage VDD is extremely small.

  Therefore, in this embodiment, noise from the power supply voltage VDD to the drain terminal and gate terminal of the HEMT is strongly suppressed as compared with the conventional example. That is, PSRR from the power supply voltage VDD is sufficiently small. Therefore, even in a situation where noise is superimposed on the power supply voltage VDD, signal amplification with the LNA can be performed satisfactorily.

  FIG. 31 shows the PSRR characteristics of (a) the HEMT drain terminal and (b) the HEMT gate terminal with respect to the negative power supply voltage VNEG. FIG. 32 shows PSRR equations for the drain terminal and the gate terminal of the HEMT when the values of FIG. 31 are shown.

  In the conventional example, as described above, both the drain terminal and the gate terminal have high PSRR, and the noise suppression ratio from the negative power supply voltage VNEG is poor. On the other hand, according to this embodiment, the PSRR of the drain terminal and the gate terminal with respect to the negative power supply voltage VNEG is extremely small.

  Therefore, in this embodiment, noise from the negative power supply voltage VNEG to the drain terminal and gate terminal of the HEMT is strongly suppressed as compared with the conventional example. That is, PSRR from the negative power supply voltage VNEG becomes sufficiently small. Therefore, even in a situation where noise is superimposed on the negative power supply voltage VNEG, signal amplification with the LNA can be performed satisfactorily.

  As described above, according to the configuration of the present embodiment, the HEMT drain current ID and the drain voltage VD are simultaneously set to desired values, and the HEMT bias circuit with low temperature dependency and power supply voltage dependency and good PSRR is provided. It can be seen that it can be configured.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be suitably used for bias circuits, LNAs, LNBs, communication receivers, communication transmitters, and sensor systems.

1 HEMT (Amplification FET)
11, 12, 15, 16, 18-20 HEMT bias circuit (bias circuit)
50, 60, 80 LNA
51, 71, 82 HEMT bias circuit (bias circuit)
52 Active element (first transistor)
53 Active element (second transistor)
54, 81 Integrated circuit 61 Protection element 70, 118 Band gap reference circuit 83 Reference voltage generation circuit 84, 117 Negative voltage generation circuit 100 LNB
101 Feed horn (antenna)
104 Horizontally polarized LNA (LNA)
105 LNA for vertical polarization (LNA)
106 2nd LNA (LNA)
114 HEMT bias circuit (bias circuit) for LNA-H
115 HEMT bias circuit (bias circuit) for LNA-V
116 HEMT bias circuit (bias circuit) for 2nd LNA
121 Coaxial cable 122 TV set 123 Video set 150 Communication system 151 Transmitter (transmitter for communication)
152 receiver (communication receiver)
153 Communication path 154 Transmission device 155,159 LNA
156, 160 HEMT bias circuit (bias circuit)
157, 161 Signal processing circuit 158 Receiving device 170 Sensor system 171 Sensing device 172 LNA
173 HEMT bias circuit (bias circuit)
174 Signal processing circuit 500 HEMT bias circuit 520 Negative voltage generation circuit VD Drain voltage ID Drain current AMP1 Operational amplifier (dual power supply type differential amplifier)
AMP2 operational amplifier (single power supply type differential amplifier, first differential amplifier)
AMP3 operational amplifier (second differential amplifier)
PMOS1 P-channel MOSFET (first transistor)
PMOS2 P-channel MOSFET (second transistor)
NMOS1 N-channel MOSFET (first transistor)
NMOS2 N-channel MOSFET (second transistor)
RI resistance element (first resistance element)
RG resistance element (second resistance element)
RR resistance element (third resistance element)
R1 resistance element (fourth resistance element)
R2 resistance element (5th resistance element)
IB constant current source VDD power source voltage VX first reference voltage source VY second reference voltage source VREF reference voltage source VNEG negative power source voltage source

Claims (26)

A bias circuit for an amplifying FET whose source terminal is grounded,
A dual power supply type differential amplifier, a first resistance element, a first reference voltage source, and a second reference voltage source;
The differential amplifier has a positive input terminal connected to the drain terminal of the amplification FET, a negative input terminal connected to the second reference voltage source, an output terminal connected to the gate terminal of the amplification FET,
The bias circuit, wherein the first resistance element has one terminal connected to the drain terminal of the amplifying FET and the other terminal connected to the first reference voltage source.   The bias circuit according to claim 1, wherein the amplification FET is a HEMT. A bias circuit for an amplifying FET whose source terminal is grounded,
A single power supply type differential amplifier, a first reference voltage source, a second reference voltage source, a first transistor, a first resistance element, a second resistance element, and a negative power supply voltage source;
The first transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The differential amplifier has a first input terminal connected to the second reference voltage source, a second input terminal connected to the drain terminal of the amplification FET, and an output terminal connected to the control terminal of the first transistor. ,
The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET,
The first resistance element has one terminal connected to the drain terminal of the amplification FET, the other terminal connected to the first reference voltage source,
The bias circuit, wherein the second resistance element has one terminal connected to the gate terminal of the amplification FET and the other terminal connected to the negative power supply voltage source.   4. The bias circuit according to claim 3, wherein the amplifying FET is a HEMT. The first transistor is a P-channel MOSFET,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are a source terminal, a drain terminal, and a gate terminal of the P-channel MOSFET, respectively.
The bias circuit according to claim 3 or 4, wherein the first input terminal and the second input terminal of the differential amplifier are a positive input terminal and a negative input terminal, respectively. The first transistor is a PNP bipolar transistor,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are an emitter terminal, a collector terminal, and a base terminal of the PNP bipolar transistor, respectively.
The bias circuit according to claim 3 or 4, wherein the first input terminal and the second input terminal of the differential amplifier are a positive input terminal and a negative input terminal, respectively. The first transistor is an N-channel MOSFET,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are a drain terminal, a source terminal, and a gate terminal of the N-channel MOSFET, respectively.
The bias circuit according to claim 3 or 4, wherein the first input terminal and the second input terminal of the differential amplifier are a negative input terminal and a positive input terminal, respectively. The first transistor is an NPN bipolar transistor,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are a collector terminal, an emitter terminal, and a base terminal of the NPN bipolar transistor, respectively.
The bias circuit according to claim 3 or 4, wherein the first input terminal and the second input terminal of the differential amplifier are a negative input terminal and a positive input terminal, respectively. A bias circuit for an amplifying FET whose source terminal is grounded,
A single power supply type first differential amplifier, a single power supply type second differential amplifier, a first transistor, a second transistor, a first resistance element, a second resistance element, and a third resistance element A fourth resistance element, a fifth resistance element, a reference voltage source, and a negative power supply voltage source,
The first transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The second transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The first differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fifth resistance element, a second input terminal connected to the drain terminal of the amplification FET, An output terminal connected to the control terminal of the first transistor;
The second differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fourth resistance element and the fifth resistance element, and the second input terminal connected to the reference voltage source. Connected, the output terminal is connected to the control terminal of the second transistor,
The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET,
The second transistor has a first conduction terminal connected to a power supply voltage, a second conduction terminal grounded through the fifth resistance element, the fourth resistance element, and the third resistance element in this order,
The first resistance element has one terminal connected to the drain terminal of the amplification FET, the other terminal connected to the second conduction terminal of the second transistor,
The bias circuit, wherein the second resistance element has one terminal connected to the gate terminal of the amplification FET and the other terminal connected to the negative power supply voltage source.   The bias circuit according to claim 9, wherein the amplification FET is a HEMT. The first transistor and the second transistor are P-channel MOSFETs,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor are a source terminal, a drain terminal, and a gate terminal of the P-channel MOSFET, respectively.
The first input terminal and the second input terminal of the first differential amplifier are a positive input terminal and a negative input terminal, respectively.
The bias circuit according to claim 9 or 10, wherein the first input terminal and the second input terminal of the second differential amplifier are a positive input terminal and a negative input terminal, respectively. The first transistor and the second transistor are PNP-type bipolar transistors,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor are an emitter terminal, a collector terminal, and a base terminal of the PNP bipolar transistor, respectively.
The first input terminal and the second input terminal of the first differential amplifier are a positive input terminal and a negative input terminal, respectively.
The bias circuit according to claim 9 or 10, wherein the first input terminal and the second input terminal of the second differential amplifier are a positive input terminal and a negative input terminal, respectively. The first transistor and the second transistor are N-channel MOSFETs,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor are a drain terminal, a source terminal, and a gate terminal of the N-channel MOSFET, respectively.
The first input terminal and the second input terminal of the first differential amplifier are a negative input terminal and a positive input terminal, respectively.
11. The bias circuit according to claim 9, wherein the first input terminal and the second input terminal of the second differential amplifier are a negative input terminal and a positive input terminal, respectively. The first transistor and the second transistor are NPN bipolar transistors,
The first conduction terminal, the second conduction terminal, and the control terminal of the first transistor and the second transistor are a collector terminal, an emitter terminal, and a base terminal of the NPN bipolar transistor, respectively.
The first input terminal and the second input terminal of the first differential amplifier are a negative input terminal and a positive input terminal, respectively.
11. The bias circuit according to claim 9, wherein the first input terminal and the second input terminal of the second differential amplifier are a negative input terminal and a positive input terminal, respectively.   The bias circuit according to claim 9, wherein a constant current source is used instead of the third resistance element.   The bias circuit according to claim 9, wherein the fourth resistance element is removed. Instead of the third resistance element, a constant current source is used,
The bias circuit according to claim 9, wherein the fourth resistance element is removed. Further equipped with a voltage withstand voltage protection element,
18. The bias circuit according to claim 9, wherein the protection element is inserted between a second conduction terminal of the first transistor and a gate terminal of the amplification FET. .   The bias circuit according to any one of claims 9 to 18, wherein the reference voltage source includes a band gap reference circuit that outputs a band gap voltage.   The first differential amplifier, the second differential amplifier, the first transistor, the second transistor, the first resistance element, the second resistance element, the third resistance element, the fourth resistance element, and the above The bias circuit according to claim 9, wherein the fifth resistance element is configured by an integrated circuit.   21. The bias circuit according to claim 20, wherein the reference voltage source, the negative power source voltage source, or both are integrated with the integrated circuit. An amplifying FET whose source terminal is grounded;
The bias circuit according to any one of claims 1 to 21,
An LNA characterized in that the gate terminal of the amplification FET is an input terminal and the drain terminal of the amplification FET is an output terminal. An LNB that amplifies and down-converts a signal received by an antenna and transmits it to the subsequent stage,
Comprising at least one LNA for amplifying the signal,
The LNB according to claim 22, wherein the LNA is the LNA according to claim 22. A communication receiver,
A receiving device for receiving a signal from the communication path;
An LNA for amplifying a signal output from the receiving device,
The communication receiver according to claim 22, wherein the LNA is the LNA according to claim 22. A transmitter for communication,
An LNA that amplifies the signal to be transmitted;
A transmission device for transmitting the signal amplified by the LNA to a communication path,
The communication transmitter according to claim 22, wherein the LNA is the LNA according to claim 22. A sensor system,
A sensing device that detects a change in an object and generates a signal corresponding to the detected change;
An LNA for amplifying a signal output from the sensing device,
The sensor system according to claim 22, wherein the LNA is the LNA according to claim 22.

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