JP4800433B1 - Bias circuit, LNA, and LNB - Google Patents

Abstract

An object of the present invention is to prevent the occurrence of excessive through current when switching on / off of bias supply.
A HEMT bias circuit 10 supplies a bias to a HEMT 1 whose source terminal is grounded, and includes an operational amplifier AMP1, a resistor element RI, a switch SWg, a switch SWd, a reference voltage source VREF, and a reference voltage source. The operational amplifier AMP1 includes a VDRAIN and a negative power supply voltage source VNEG. The operational amplifier AMP1 has a positive input terminal connected to the drain terminal of the HEMT1, a negative input terminal connected to the reference voltage source VDRAIN, and an output terminal connected to the gate terminal of the HEMT1. The negative power supply terminal can be connected to the negative power supply voltage source VNEG or the ground by switching the switch SWg, and the resistance element RI has a first terminal and a second terminal, and the first terminal is connected to the drain terminal of the HEMT1. The second terminal is connected to the reference voltage source VREF or the group by switching the switch SWd. There is a possible connection to the command.
[Selection] Figure 1

Description

  The present invention relates to a bias circuit capable of switching on and off a bias supplied to a field effect transistor (FET), an LNA (low noise amplifier), and an LNB (low noise block converter). The present invention relates to a technique for protecting a HEMT (High Electron Mobility Transistor) used in a broadcast receiving LNB LNA when a bias is switched on and off.

  Conventionally, in satellite broadcasting, a minute signal of Ku band (12 GHz to 18 GHz) is transmitted from a communication satellite to a receiving side such as an individual home. On the receiving side, a signal from a communication satellite is received by an antenna, amplified and down-converted by an LNB, and transmitted to a tuner.

  Here, in order to satisfactorily receive a minute signal, a low NF (Noise Figure) is required for the LNA that amplifies the signal received by the antenna in the LNB. For this reason, HEMT is generally used for LNA. The HEMT is characterized by being able to support Ku-band reception and having a low NF. In order to design the gain and NF of the LNA using the HEMT to desired values, it is necessary to optimally design the drain voltage and drain current of the HEMT.

  The drain current characteristics of the HEMT will be described. FIG. 9 is a circuit diagram for explaining the bias of the HEMT. FIG. 10 is a graph showing the relationship between the gate voltage and the drain current of the HEMT.

  The HEMT has a characteristic that the current value of the drain current ID is determined with respect to the voltage value of the gate voltage VG. Therefore, for example, when the optimum drain voltage VD is designed to be 2V and the optimum drain current ID is 8 mA, the gate voltage VG must be about -0.4V as shown in FIG. As described above, the HEMT used for the LNA is supplied using a bias circuit because it is necessary to apply a predetermined bias so that a desired drain voltage VD and a desired drain current ID can be simultaneously obtained. The bias circuit automatically searches for and determines a gate voltage VG of about −0.4 V that simultaneously satisfies VD = 2 V and ID = 8 mA.

  A plurality of bias circuits as described above have been proposed in the past for automatically controlling and supplying a gate voltage so as to simultaneously determine a desired drain voltage and a desired drain current. Among them, there is a bias circuit disclosed in Patent Document 1 as a basic circuit.

  FIG. 11 is a circuit diagram showing a configuration of a conventional HEMT bias circuit 500 disclosed in Patent Document 1. In FIG. The HEMT bias circuit 500 is a bias circuit for the HEMT 501 whose source terminal is grounded. As shown in FIG. 11, the HEMT bias circuit 500 includes a bipolar transistor BIP501, an emitter-side resistance element RE, a collector-side resistance element RC, a resistance element R501, and a resistance element R502.

  The emitter terminal of the bipolar transistor BIP501 is connected to the drain terminal of the HEMT 501 and is connected to the power supply voltage VDD via the emitter-side resistance element RE. The collector terminal of the bipolar transistor BIP501 is connected to the gate terminal of the HEMT 501 and to the negative power supply voltage VNEG via the collector-side resistance element RC. The base terminal of the bipolar transistor BIP501 is connected to the source terminal of the HEMT 501 via the resistance element R501 and to the power supply voltage VDD via the resistance element R502.

  In the HEMT bias circuit 500, the HEMT 501 is incorporated in a negative feedback loop. Thereby, the drain voltage VD and the drain current ID of the HEMT 501 are automatically determined so as to be approximate expressions represented by the following expressions (1) and (2).

The values in the above formulas are as follows.
V _D : voltage value of the drain voltage VD I _D : current value of the drain current ID V _B : voltage value of the base voltage VB V _BE : voltage value of the base-emitter voltage VBE VDD: voltage value of the power supply voltage VDD R _E : Resistance value R ₁ of emitter-side resistance element RE: Resistance value R _{2 of} resistance element R 501: Resistance value of resistance element R 502.

  However, the above-described conventional HEMT bias circuit 500 has four problems: temperature dependency, power supply voltage dependency, noise from power supply voltage and negative power supply voltage, and manufacturing process limitation. In the HEMT bias circuit 500, it is necessary to maintain a desired drain voltage and a desired drain current even when the ambient temperature or the power supply voltage varies. Further, it is necessary to prevent noise superimposed on the power source from being transmitted to the drain terminal and the gate terminal of the HEMT 501.

  Here, the above four problems have already been solved by the technique described in Japanese Patent Application No. 2010-040887. In the HEMT bias circuit provided by the above technique, the HEMT drain current and drain voltage are simultaneously set to desired values, temperature dependence and power supply voltage dependence are eliminated, and a very high noise removal rate is obtained. Is possible. In addition, since a special manufacturing process is not required, it is possible to improve the degree of freedom in selecting a manufacturing process.

  The technology described in Japanese Patent Application No. 2010-040887 is a prior art related to the invention of this application.

  By the way, signal radio waves from satellite broadcasting use horizontally polarized waves and vertically polarized waves, or left-handed circularly polarized waves and right-handed circularly polarized waves in order to effectively use frequency resources. The LNB that receives these polarized waves includes a horizontally polarized wave (left-handed circularly polarized wave) antenna, a horizontally polarized wave (left-handed circularly polarized wave) LNA connected to the antenna, and a vertically polarized wave (right-handedly polarized wave). A circularly polarized wave) antenna and a vertically polarized wave (right circularly polarized wave) LNA connected to the antenna.

  FIG. 12 is a block diagram showing a configuration of a general LNB 100. As shown in FIG. 12, the LNB 100 includes a feed horn 101 having a horizontal polarization antenna 102 (first polarization antenna) and a vertical polarization antenna 103 (second polarization antenna), and a horizontal polarization LNA 104 (first polarization antenna). Wave amplifier), vertical polarization LNA 105 (second polarization amplifier), LNA 106, image removal filter 107, Ku-band amplifier 108, mixer 109, local oscillator 110, IF amplifier 111, frequency selector 112, polarization A wave selector 113, a power supply regulator 114, and a connector 115 are provided.

  The LNB 100 amplifies and down-converts the signal received by the feed horn 101 and transmits it to the TV set 117 and the video set 118 in the subsequent stage connected by the coaxial cable 116. The LNB 100 has a configuration for receiving horizontal polarization and vertical polarization, but of course may have a configuration for receiving left-handed circular polarization and right-handed circular polarization. That is, the horizontal polarization antenna 102 and the horizontal polarization LNA 104 may be configured for left-handed circular polarization, and the vertical polarization antenna 103 and the vertical polarization LNA 105 may be configured for right-handed circular polarization.

  Radio waves (horizontal polarization (first polarization) and vertical polarization (second polarization)) transmitted from a communication satellite using a Ku-band carrier are either a horizontal polarization antenna 102 or a vertical polarization antenna inside the feed horn 101. Each is received by 103 and converted into a current signal. The current signal (first polarization signal) converted by the horizontally polarized antenna 102 is output to the horizontally polarized LNA 104. The current signal (second polarization signal) converted by the vertical polarization antenna 103 is output to the vertical polarization LNA 105.

  The current signals from the antennas are converted into voltage signals by the horizontal polarization LNA 104 and the vertical polarization LNA 105 and then amplified. The amplified signal is further amplified by the LNA 106 and then output to the image removal filter 107. The image removal filter 107 removes unnecessary signals such as signals in the image band. The signal from the image removal filter 107 is further amplified by the Ku band amplifier 108 and then output to the mixer 109.

  In the mixer 109, the signal from the Ku-band amplifier 108 is multiplied by the local signal output from the local oscillator 110 to be converted into an IF (1 to 2 GHz band) signal. The converted signal is amplified and output by the IF amplifier 111. The IF amplifier 111 is connected to the connector 115 through a coupling capacitor, and performs matching at 75Ω in order to drive the coaxial cable 116.

  The LNB 100 is connected to the TV set 117 and the video set 118 via the coaxial cable 116 connected to the connector 115. Thereby, the signal received by the LNB 100 is transmitted to the TV set 117 and the video set 118.

  Also, the TV set 117 and the video set 118 transmit power and signals to the LNB 100 via the coaxial cable 116. In LNB 100, connector 115 is connected to frequency selector 112, polarization selector 113, and power supply regulator 114 via an inductor.

  For example, power for driving the LNB 100 is transmitted to the LNB 100 from the TV set 117 or the video set 118 side via the coaxial cable 116. The transmitted power is supplied to the power regulator 114. Since power transmission for driving the LNB 100 is usually as high as about 18 V, the power supply regulator 114 steps down the voltage and then the stabilized power supply voltage is supplied to each block in the LNB 100.

  In addition, a switching signal for switching the frequency of the local oscillator 110 is transmitted to the LNB 100 from the TV set 117 and the video set 118 via the coaxial cable 116 in order to switch the band of the received signal. The transmitted switching signal is supplied to the frequency selector 112. The frequency selector 112 switches the oscillation frequency of the local oscillator 110 so that the local frequency selected by determining the switching signal becomes the local frequency.

  Furthermore, in order to select whether to receive horizontal polarization or vertical polarization, polarization selection for selecting the polarization to be received from the TV set 117 or video set 118 side via the coaxial cable 116. A signal is transmitted to the LNB 100. The transmitted polarization selection signal is supplied to the polarization selector 113.

  Here, in a general LNB system, power is supplied to the LNB 100 by applying a voltage to the coaxial cable 116 from the TV set 117 or the video set 118 side. The polarization selection signal is realized by using the level of this voltage, and an instruction is given as to which polarization is received based on the level of the voltage. The polarization selector 113 determines whether the voltage is high or low and selects a polarization to be received. As a method of selecting the polarization to be received, the method of turning on the power of the LNA receiving one of the LNA 104 for horizontal polarization and the LNA 105 for vertical polarization and turning off the power of the LNA not receiving is simple. is there.

  FIG. 13 shows a schematic configuration of an LNA 200 that is an example of the LNA 104 for horizontal polarization and the LNA 105 for vertical polarization. The LNA 200 includes a HEMT 201, a HEMT bias circuit 202, and switches 203 and 204. Since very low NF is required for the horizontally polarized LNA 104 and the vertically polarized LNA 105, the HEMT 201 is used. As the HEMT bias circuit 202 for the HEMT 201, for example, a HEMT bias circuit based on the technique described in Japanese Patent Application No. 2010-040887 is used.

  The gate terminal of the HEMT 201 is connected to the HEMT bias circuit 202 via the switch 203 when the switch 203 is on, and is connected to the ground when the switch 203 is off. The switch 203 is turned on or off according to the polarization selection signal output from the polarization selector 113, and conducts or cuts off between the gate terminal of the HEMT 201 and the HEMT bias circuit 202. The drain terminal of the HEMT 201 is connected to the HEMT bias circuit 202 via the switch 204 when the switch 204 is on, and is connected to the ground when the switch 204 is off. The switch 204 is turned on or off according to the polarization selection signal, and conducts or cuts off between the drain terminal of the HEMT 201 and the HEMT bias circuit 202. Accordingly, the LNA 200 can be turned on (operated) or turned off (stopped) by turning on or off the bias to the HEMT 201.

JP 59-194522 A (published November 5, 1984)

  However, the LNA 200 has a problem in that when the bias is switched from on to off or from off to on, the operation of the drain voltage VD and the operation of the gate voltage VG overlap each other, so that a large through current flows to the HEMT 201.

  FIG. 14 shows a timing chart when switching the bias of the HEMT 201 on and off. As shown in FIG. 14, in order to switch the bias of the HEMT 201 on and off, the polarization selection signal changes from low level (OFF) to high level (ON), and from high level (ON) to low level (OFF). At the same time, the drain voltage VD and the gate voltage VG start to change. A large through current (drain current ID) flows through the HEMT 201 from when the drain voltage VD and the gate voltage VG are changed to when they are stabilized, that is, while both are operating. Excessive through current causes physical damage to the HEMT 201 and impairs long-term reliability.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a bias circuit, an LNA, which can prevent the occurrence of excessive through current when switching on / off of bias supply. , And providing an LNB.

In order to solve the above-described problem, the bias switching circuit of the present invention is a bias circuit that supplies a bias to an amplifying FET whose source terminal that amplifies an input signal is grounded. , A first resistance element, a first switch, a second switch, a first reference voltage source, a second reference voltage source, and a negative power supply voltage source, and the differential amplifier has a positive input terminal as described above The drain terminal of the amplifying FET is connected, the negative input terminal is connected to the second reference voltage source, the output terminal is connected to the gate terminal of the amplifying FET, and the negative power supply terminal is switched by switching the first switch. The first resistance element has a first terminal and a second terminal, and the first terminal is connected to the drain terminal of the amplification FET, and the second terminal is connectable to a negative power supply voltage source or ground. Is the second switch It is connectable to the first reference voltage source or the ground by switching, when switching on the supply of the bias from the off, ground connection of the negative power supply terminal of the differential amplifier by switching the first switch After switching from the negative power supply voltage source to the first switch, the second switch is switched to switch the connection destination of the second terminal of the first resistance element from the ground to the first reference voltage source, and the bias supply is switched from on to off. When switching to the second switch, the second switch of the first resistance element is switched from the first reference voltage source to the ground by switching the second switch, and then the first switch is switched to switch the differential. The connection destination of the negative power supply terminal of the amplifier is switched from the negative power supply voltage source to the ground .

  According to the above configuration, the timing for applying and erasing the voltage to the gate terminal and the timing for applying and erasing the voltage to the drain terminal with respect to the amplification FET according to the switching timing of the first switch and the second switch. It is possible to control so that a large through current does not flow.

  For example, when switching the bias supply from OFF to ON, the first switch is switched to switch the connection destination of the negative power supply terminal of the differential amplifier from the ground to the negative power supply voltage source, and then the second switch is switched. The connection destination of the second terminal of the first resistance element is switched from the ground to the first reference voltage source. According to this, after applying a voltage to the gate terminal of the amplifying FET, the voltage is applied to the drain terminal of the amplifying FET. Therefore, since the carrier existing in the channel of the amplifying FET decreases during the period from when the voltage is applied to the gate terminal of the amplifying FET until the voltage is applied to the drain terminal of the amplifying FET, it is difficult for the through electrode to flow. It becomes possible to do.

  When switching the bias supply from on to off, the second switch is switched to switch the connection destination of the second terminal of the first resistance element from the first reference voltage source to the ground, and then the first switch is switched. As a result, the connection destination of the negative power supply terminal of the differential amplifier is switched from the negative power supply voltage source to the ground. According to this, after the voltage at the drain terminal of the amplifying FET is erased, the voltage at the gate terminal of the amplifying FET is erased. Therefore, since the gate terminal of the amplifying FET remains at a negative voltage during the period from erasing the voltage at the drain terminal of the amplifying FET until erasing the voltage at the gate terminal of the amplifying FET, excessive drain It is possible to prevent a current from flowing.

  Therefore, it is possible to prevent an excessive through current from being generated when the bias supply is switched from OFF to ON and when the bias supply is switched from ON to OFF.

In the bias circuit of the present invention, as described above, when the bias supply is switched from OFF to ON, the connection destination of the negative power supply terminal of the differential amplifier is switched from the ground to the negative by switching the first switch. After switching to the power supply voltage source, by switching the second switch, the connection destination of the second terminal of the first resistance element is switched from the ground to the first reference voltage source, and the bias supply is switched from on to off. Switching the second switch to switch the connection destination of the second terminal of the first resistance element from the first reference voltage source to the ground, and then switching the first switch to switch the negative switch of the differential amplifier. It is desirable to switch the connection destination of the power supply terminal from the negative power supply voltage source to the ground.

  In the bias circuit of the present invention, the amplification FET is preferably a HEMT.

In order to solve the above-described problem, the bias switching circuit of the present invention is a bias circuit that supplies a bias to an amplifying FET whose source terminal for amplifying an input signal is grounded. A dynamic amplifier, a single power source type second differential amplifier, a first transistor, a second transistor, a first resistance element, a second resistance element, a third resistance element, and a fourth resistance element, A fifth resistance element; a first switch; a second switch; a reference voltage source; and a negative power supply voltage source. The first transistor includes a first conduction terminal, a second conduction terminal, and a control terminal. The second transistor has a first conduction terminal, a second conduction terminal, and a control terminal. The first differential amplifier has a first input terminal via the fifth resistance element. Is connected to the second conduction terminal, and the second input terminal is The amplifying FET is connected to the drain terminal, the output terminal is connected to the control terminal of the first transistor, and the second differential amplifier has the first input terminal connected to the fourth resistance element and the fifth resistance element. Through this order, the second transistor is connected to the second conduction terminal, the second input terminal is connected to the reference voltage source, the output terminal is connected to the control terminal of the second transistor, and the first transistor is The first conduction terminal is connected to the power supply voltage, the second conduction terminal is connected to the gate terminal of the amplification FET, the second transistor has the first conduction terminal connected to the power supply voltage, and the second conduction terminal The fifth resistance element, the fourth resistance element, and the third resistance element are connected to the ground through the order, and the first resistance element has a first terminal and a second terminal, and the first terminal Is on Connected to the drain terminal of the amplifying FET, the second terminal is connected to the second conduction terminal of the second transistor, the second resistance element has a third terminal and a fourth terminal, the third terminal Is connected to the gate terminal of the amplifying FET, the fourth terminal is connected to the negative power supply voltage source, and the first switch is connected to the gate terminal of the amplifying FET. The gate terminal of the amplifying FET is connectable to the ground, the second switch is connected to the control terminal of the second transistor, and the control terminal of the second transistor is switched to the second transistor by switching the second switch. When the bias supply is switched from OFF to ON, the amplification FET is switched by switching the first switch. After the connection between the gate terminal of the first transistor and the ground is cut off, the second switch is switched to cut off the connection between the control terminal of the second transistor and the first conduction terminal of the second transistor, and the bias supply is turned on. When switching from OFF to OFF, the control terminal of the second transistor is connected to the first conduction terminal of the second transistor by switching the second switch, and then the first switch is switched to switch the amplification FET. The gate terminal is connected to the ground .
The bias switching circuit according to the present invention is a bias circuit for supplying a bias to an amplifying FET whose source terminal for amplifying an input signal is grounded. A power source type second differential amplifier, a first transistor, a second transistor, a first resistance element, a second resistance element, a third resistance element, a fourth resistance element, and a fifth resistance element; A first switch; a second switch; a reference voltage source; a negative power supply voltage source; a first capacitor; and a second capacitor. The first transistor includes a first conduction terminal, a second conduction terminal, and The second transistor has a first conduction terminal, a second conduction terminal, and a control terminal. The first differential amplifier has a first input terminal via the fifth resistance element. Connected to the second conduction terminal of the second transistor. The second input terminal is connected to the drain terminal of the amplifying FET, the output terminal is connected to the control terminal of the first transistor, and the second differential amplifier has a first input terminal connected to the fourth resistance element and the A fifth resistance element is connected in this order to the second conduction terminal of the second transistor, a second input terminal is connected to the reference voltage source, an output terminal is connected to the control terminal of the second transistor, The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET, and the second transistor has a first conduction terminal connected to the power supply voltage, A second conduction terminal is connected to the ground through the fifth resistance element, the fourth resistance element, and the third resistance element in this order, and the first resistance element has a first terminal and a second terminal. The first terminal is connected to the drain terminal of the amplifying FET, the second terminal is connected to the second conduction terminal of the second transistor, and the second resistance element has a third terminal and a fourth terminal. And the third terminal is connected to the gate terminal of the amplification FET, the fourth terminal is connected to the negative power supply voltage source, the first switch is connected to the gate terminal of the amplification FET, The gate terminal of the amplification FET can be connected to the ground by switching the first switch, the second switch is connected to the control terminal of the second transistor, and the second switch is switched to switch the second switch. The control terminal of the transistor can be connected to the first conduction terminal of the second transistor, the first capacitor has a fifth terminal and a sixth terminal, and the fifth terminal is the drain of the amplification FET. The second capacitor has a seventh terminal and an eighth terminal, the seventh terminal is connected to the gate terminal of the amplifying FET, and the sixth terminal is connected to the ground terminal. When the eighth terminal is connected to the source terminal of the amplification FET and the bias supply is switched from OFF to ON, the connection between the gate terminal of the amplification FET and the ground is cut off by switching the first switch. Later, when switching the second switch, the connection between the control terminal of the second transistor and the first conduction terminal of the second transistor is cut off, and when the bias supply is switched from on to off, the second switch After connecting the control terminal of the second transistor to the first conduction terminal of the second transistor, or simultaneously, It is characterized by connecting to ground the gate terminal of the amplifier FET by switching the switch.

  According to the above configuration, the timing for applying and erasing the voltage to the gate terminal and the timing for applying and erasing the voltage to the drain terminal with respect to the amplification FET according to the switching timing of the first switch and the second switch. It is possible to control so that a large through current does not flow.

  For example, when switching the bias supply from off to on, the first switch is switched to cut off the connection between the gate terminal of the amplifying FET and the ground, and then the second switch is switched to control the second transistor. And the first conduction terminal of the second transistor are disconnected. According to this, after applying a voltage to the gate terminal of the amplifying FET, the voltage is applied to the drain terminal of the amplifying FET. Therefore, since the carrier existing in the channel of the amplifying FET decreases during the period from when the voltage is applied to the gate terminal of the amplifying FET until the voltage is applied to the drain terminal of the amplifying FET, it is difficult for the through electrode to flow. It becomes possible to do.

  When the bias supply is switched from on to off, the second switch is switched to connect the control terminal of the second transistor to the first conduction terminal of the second transistor, and then the first switch is switched for amplification. Connect the gate terminal of the FET to ground. According to this, after the voltage at the drain terminal of the amplifying FET is erased, the voltage at the gate terminal of the amplifying FET is erased. Therefore, since the gate terminal of the amplifying FET remains at a negative voltage during the period from erasing the voltage at the drain terminal of the amplifying FET until erasing the voltage at the gate terminal of the amplifying FET, excessive drain It is possible to prevent a current from flowing.

  Therefore, it is possible to prevent an excessive through current from being generated when the bias supply is switched from OFF to ON and when the bias supply is switched from ON to OFF.

As described above, when the bias supply is switched from OFF to ON as described above, the bias circuit of the present invention cuts off the connection between the gate terminal of the amplification FET and the ground by switching the first switch. By switching the second switch, the connection between the control terminal of the second transistor and the first conduction terminal of the second transistor is cut off, and when the bias supply is switched from on to off, the second switch is turned on. It is desirable to connect the gate terminal of the amplifying FET to the ground by switching the first switch after the control terminal of the second transistor is connected to the first conduction terminal of the second transistor by switching.

In addition, as described above, the bias circuit of the present invention further includes a first capacitor and a second capacitor, and the first capacitor has a fifth terminal and a sixth terminal, and the fifth terminal is used for the amplification. Connected to the drain terminal of the FET, the sixth terminal is connected to the ground, the second capacitor has a seventh terminal and an eighth terminal, and the seventh terminal is connected to the gate terminal of the amplification FET. The eighth terminal is preferably connected to the source terminal of the amplification FET.

  According to the above configuration, since the first capacitor and the second capacitor are provided, the time required for discharging the drain voltage of the amplifying FET when the bias supply is switched from on to off, It is possible to control the time required for charging the gate voltage.

  Therefore, when the bias voltage is switched from on to off by setting the charging time of the gate voltage longer than the discharging time of the drain voltage, the amplification FET can be switched even if the first switch and the second switch are switched simultaneously. It is possible to make a sequence in which the voltage at the gate terminal of the amplification FET is erased after the voltage at the drain terminal is erased.

As described above, when the bias supply is switched from OFF to ON as described above, the bias circuit of the present invention cuts off the connection between the gate terminal of the amplification FET and the ground by switching the first switch. By switching the second switch, the connection between the control terminal of the second transistor and the first conduction terminal of the second transistor is cut off, and when the bias supply is switched from on to off, the second switch is turned on. After the switching, the control terminal of the second transistor is connected to the first conduction terminal of the second transistor, or at the same time, the gate terminal of the amplification FET can be connected to the ground by switching the first switch. desirable.

  In the bias circuit of the present invention, the amplification FET is preferably a HEMT.

  Further, in the bias circuit of the present invention, the first transistor is an N-channel MOSFET, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are each a drain of the N-channel MOSFET. A terminal, a source terminal, and a gate terminal, the second transistor is a P-channel MOSFET, and the first conduction terminal, the second conduction terminal, and the control terminal of the second transistor are the P-channel MOSFET, respectively. Source terminal, drain terminal, and gate terminal of the first differential amplifier. The first input terminal and the second input terminal of the first differential amplifier are a negative input terminal and a positive input terminal, respectively. The first input terminal and the second input terminal are preferably a positive input terminal and a negative input terminal, respectively.

  The bias circuit of the present invention further includes a sixth resistance element, and the sixth resistance element is provided on a path that electrically connects the second conduction terminal of the first transistor and the gate terminal of the amplification FET. It is preferable to be provided.

  According to the above configuration, the first transistor can be driven within the allowable breakdown voltage of the first transistor. Therefore, it is possible to have excellent reliability.

  In order to solve the above problems, the LNA of the present invention includes an amplification FET having a source terminal for amplifying an input signal grounded, and the bias circuit, and the input terminal is provided at the gate terminal of the amplification FET. An output terminal is provided at the drain terminal of the amplifying FET.

  According to the above configuration, by providing the bias circuit, it is possible to drive the amplification FET at an appropriate operating point and to obtain the effect exhibited by the bias circuit.

  In order to solve the above-described problem, the LNB of the present invention is an LNB that amplifies and down-converts a signal received by an antenna and transmits the signal to a subsequent stage, receives the first polarization, and converts the first polarization to the first polarization. A first polarization antenna that converts the first polarization signal; a second polarization antenna that receives the second polarization and converts the second polarization signal to a second polarization signal; and A first polarization amplifier to amplify, a second polarization amplifier to amplify the second polarization signal, and a polarization selection to select which of the first polarization and the second polarization is received And the first polarization and the second polarization are respectively a horizontal polarization and a vertical polarization, or a left-handed circular polarization and a right-handed circular polarization, and the first polarization amplifier and The second polarization amplifier is the LNA, and the first polarization amplifier and the second polarization amplifier. The width device switches the first switch and the second switch according to a polarization selection signal indicating which of the first polarization and the second polarization output from the polarization selector is received. It is characterized by switching each.

  According to the above configuration, since the gain and NF of the first polarization amplifier and the second polarization amplifier can be optimized by providing the LNA, the first polarization antenna and the second polarization antenna It is possible to satisfactorily receive a minute signal received by the polarization antenna.

  Further, the LNB of the present invention is preferably partially integrated.

  According to said structure, the mounting area and mounting cost of components are reduced, and it becomes possible to achieve size reduction and cost reduction in LNB.

As described above, the bias circuit according to the present invention includes the dual power supply type differential amplifier, the first resistance element, the first switch, the second switch, the first reference voltage source, and the second reference voltage source. A negative power supply voltage source, wherein the differential amplifier has a positive input terminal connected to the drain terminal of the amplification FET, a negative input terminal connected to the second reference voltage source, and an output terminal for the amplification The negative power supply terminal is connected to the negative power supply voltage source or the ground by switching the first switch, the first resistance element has a first terminal and a second terminal. The first terminal is connected to the drain terminal of the amplifying FET, the second terminal can be connected to the first reference voltage source or the ground by switching the second switch, and the bias supply is switched from OFF to ON. When switching The second switch of the first resistance element is switched by switching the second switch after the connection destination of the negative power supply terminal of the differential amplifier is switched from the ground to the negative power supply voltage source by switching the first switch. Is switched from ground to the first reference voltage source, and when the bias supply is switched from on to off, the second switch is switched to change the connection destination of the second terminal of the first resistance element to the first reference voltage source. After switching from one reference voltage source to the ground, the connection destination of the negative power supply terminal of the differential amplifier is switched from the negative power supply voltage source to the ground by switching the first switch .

The bias circuit of the present invention includes a single power supply type first differential amplifier, a single power supply type second differential amplifier, a first transistor, a second transistor, a first resistance element, The first transistor includes a two-resistance element, a third resistance element, a fourth resistance element, a fifth resistance element, a first switch, a second switch, a reference voltage source, and a negative power supply voltage source. Has a first conduction terminal, a second conduction terminal, and a control terminal, the second transistor has a first conduction terminal, a second conduction terminal, and a control terminal, and the first differential amplifier is: The first input terminal is connected to the second conduction terminal of the second transistor via the fifth resistance element, the second input terminal is connected to the drain terminal of the amplification FET, and the output terminal is connected to the first transistor. The second differential amplifier is connected to the control terminal and the first differential amplifier The power terminal is connected to the second conduction terminal of the second transistor through the fourth resistance element and the fifth resistance element in this order, the second input terminal is connected to the reference voltage source, and the output terminal is The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET, and the second transistor has a first conduction terminal connected to the control terminal of the second transistor. One conduction terminal is connected to the power supply voltage, the second conduction terminal is connected to the ground through the fifth resistance element, the fourth resistance element, and the third resistance element in this order, and the first resistance element is A first terminal connected to a drain terminal of the amplifying FET; a second terminal connected to a second conduction terminal of the second transistor; and the second resistance element. The second And a fourth terminal, the third terminal is connected to the gate terminal of the amplification FET, the fourth terminal is connected to the negative power supply voltage source, and the first switch is connected to the amplification FET. The gate terminal of the amplification FET is connectable to the ground by switching the first switch, the second switch is connected to the control terminal of the second transistor, and the second switch is connected to the gate terminal. By switching the switch, the control terminal of the second transistor can be connected to the first conduction terminal of the second transistor. When the bias supply is switched from OFF to ON, the amplification switch is switched by switching the first switch. After disconnecting the connection between the gate terminal of the FET and the ground, the control terminal of the second transistor and the above-mentioned are switched by switching the second switch. When the connection with the first conduction terminal of the second transistor is cut off and the supply of bias is switched from on to off, the control terminal of the second transistor is switched to the first transistor of the second transistor by switching the second switch. After connecting to the conduction terminal, the gate terminal of the amplification FET is connected to the ground by switching the first switch .
Furthermore, the bias circuit of the present invention is a bias circuit for supplying a bias to an amplifying FET whose source terminal for amplifying an input signal is grounded. The bias circuit includes a single power source type first differential amplifier and a single power source. Type second differential amplifier, first transistor, second transistor, first resistor element, second resistor element, third resistor element, fourth resistor element, fifth resistor element, A first switch, a second switch, a reference voltage source, a negative power supply voltage source, a first capacitor, and a second capacitor, wherein the first transistor has a first conduction terminal, a second conduction terminal, and a control; The second transistor has a first conduction terminal, a second conduction terminal, and a control terminal, and the first differential amplifier has a first input terminal through the fifth resistance element. Connected to the second conduction terminal of the second transistor; Two input terminals are connected to the drain terminal of the amplifying FET, an output terminal is connected to the control terminal of the first transistor, and the second differential amplifier has a first input terminal connected to the fourth resistor element and the first resistor. 5 resistor elements are connected in this order to the second conduction terminal of the second transistor, the second input terminal is connected to the reference voltage source, the output terminal is connected to the control terminal of the second transistor, The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET, the second transistor has a first conduction terminal connected to the power supply voltage, Two conduction terminals are connected to the ground through the fifth resistance element, the fourth resistance element, and the third resistance element in this order, and the first resistance element has a first terminal and a second terminal, The first terminal is connected to the drain terminal of the amplification FET, the second terminal is connected to the second conduction terminal of the second transistor, and the second resistance element has a third terminal and a fourth terminal. The third terminal is connected to the gate terminal of the amplification FET, the fourth terminal is connected to the negative power supply voltage source, the first switch is connected to the gate terminal of the amplification FET, The gate terminal of the amplification FET can be connected to the ground by switching one switch, the second switch is connected to the control terminal of the second transistor, and the second transistor is switched by switching the second switch. The control terminal of the second transistor can be connected to the first conduction terminal of the second transistor. The first capacitor has a fifth terminal and a sixth terminal. The fifth terminal is a drain of the amplification FET. The sixth capacitor is connected to the ground, the second capacitor has a seventh terminal and an eighth terminal, the seventh terminal is connected to the gate terminal of the amplification FET, When the eighth terminal is connected to the source terminal of the amplification FET and the bias supply is switched from OFF to ON, the connection between the gate terminal of the amplification FET and the ground is cut off by switching the first switch. Later, when switching the second switch, the connection between the control terminal of the second transistor and the first conduction terminal of the second transistor is cut off, and when the bias supply is switched from on to off, the second switch After switching the control terminal of the second transistor to the first conduction terminal of the second transistor or simultaneously with the first transistor. It is configured to connect to ground the gate terminal of the amplifier FET by switching the switch.

  Therefore, depending on the switching timing of the first switch and the second switch, the timing for applying and erasing the voltage to the gate terminal and the timing for applying and erasing the voltage to the drain terminal with respect to the amplifying FET Can be controlled not to flow. Therefore, there is an effect that it is possible to prevent an excessive through current from being generated when the bias supply is switched from OFF to ON and when the bias supply is switched from ON to OFF.

  The LNA of the present invention includes an amplifying FET whose source terminal for amplifying an input signal is grounded, and the bias circuit, the input terminal being provided at the gate terminal of the amplifying FET, and the drain terminal of the amplifying FET. Is provided with an output terminal.

  Therefore, by providing the bias circuit, it is possible to drive the amplifying FET at an appropriate operating point and to obtain the effect of the bias circuit.

  The LNB of the present invention receives a first polarization, converts the first polarization into a first polarization signal, receives the second polarization, and converts the second polarization to the first polarization. A second polarization antenna for converting to a two-polarization signal; a first polarization amplifier for amplifying the first polarization signal; a second polarization amplifier for amplifying the second polarization signal; A polarization selector that selects whether to receive one polarization or the second polarization, wherein the first polarization and the second polarization are respectively a horizontal polarization and a vertical polarization, or Left-hand circular polarization and right-hand circular polarization, the first polarization amplifier and the second polarization amplifier are the LNA, and the first polarization amplifier and the second polarization amplifier. Is a polarization selection signal indicating which of the first polarization and the second polarization output from the polarization selector is received, Serial first switch and the second switch is configured to switch, respectively.

  Therefore, by providing the LNA, it is possible to optimize the gain and NF of the first polarization amplifier and the second polarization amplifier. Therefore, the first polarization antenna and the second polarization antenna There is an effect that the received minute signal can be satisfactorily received.

1 is a circuit diagram showing a first embodiment of a bias circuit in the present invention. FIG. 2 is a circuit diagram illustrating a configuration example of a control signal generation circuit that supplies a control signal to the bias circuit of FIG. 1. 2 is a timing chart showing signal waveforms when switching bias on and off in an LNA including the bias circuit of FIG. 1. It is a circuit diagram which shows 2nd Embodiment of the bias circuit in this invention. FIG. 3 is a circuit diagram illustrating a configuration example of a control signal generation circuit that supplies a control signal to the bias circuit of FIG. 2. FIG. 3 is a timing chart showing signal waveforms when switching bias on / off in an LNA including the bias circuit of FIG. 2. It is a circuit diagram which shows 3rd Embodiment of the bias circuit in this invention. It is a circuit block diagram which shows one Embodiment of LNA in this invention. It is a circuit diagram for demonstrating the bias of HEMT. It is a graph which shows the relationship between the gate voltage and drain current of HEMT. It is a circuit diagram which shows the structure of the conventional HEMT bias circuit. It is a circuit block diagram which shows the structure of the conventional LNB. It is a circuit block diagram which shows schematic structure of LNA used in the said conventional LNB. It is a timing chart which shows each signal waveform when switching ON / OFF of a bias in LNA of FIG.

  Each embodiment of the present invention will be described below with reference to the drawings. The configuration other than that described in each embodiment is the same as that of the above-described embodiment. Further, for convenience of explanation, in each embodiment, members having the same functions as those shown in the drawings of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted.

[Embodiment 1]
(Configuration of HEMT bias circuit)
FIG. 1 is a circuit diagram showing a configuration example of the HEMT bias circuit 10 of the present embodiment.

  The HEMT bias circuit 10 (bias circuit) of the present embodiment is a bias circuit for HEMT 1 (amplifying FET) whose source terminal is grounded. The HEMT 1 amplifies the input signal. As shown in FIG. 1, the HEMT bias circuit 10 includes an operational amplifier AMP1 (dual power supply type differential amplifier), a resistance element RI (first resistance element), a switch SWg (first switch), and a switch SWd (second switch). , A negative power supply voltage source VNEG, a reference voltage source VDRAIN (second reference voltage source), and a reference voltage source VREF (first reference voltage source).

  The operational amplifier AMP1 is a dual power supply type operational amplifier, and is configured as a differential amplifier. The positive power supply terminal of the operational amplifier AMP1 is connected to the power supply voltage VDD. The negative power supply terminal of the operational amplifier AMP1 is connected to the switch SWg. By switching the switch SWg, the negative power supply terminal of the operational amplifier AMP1 is connected to the negative power supply voltage source VNEG or grounded. The positive input terminal (non-inverting input terminal) of the operational amplifier AMP1 is connected to the drain terminal of the HEMT1. The negative input terminal (inverting input terminal) of the operational amplifier AMP1 is connected to the reference voltage source VDRAIN. The output terminal of the operational amplifier AMP1 is connected to the gate terminal of the HEMT1.

  The resistance element RI has two terminals, one terminal (first terminal) is connected to the drain terminal of the HEMT 1 and the other terminal (second terminal) is connected to the switch SWd. By switching the switch SWd, the other terminal of the resistance element RI is connected to the reference voltage source VREF or grounded.

  The switch SWg connects the negative power supply terminal of the operational amplifier AMP1 between the negative power supply voltage source VNEG and the ground according to the control signal SG and the inverted control signal / SG (SG bar) obtained by inverting the control signal SG. It is to switch with. The switch SWg connects the negative power supply terminal of the operational amplifier AMP1 to the negative power supply voltage source VNEG when the control signal SG is at a high level and the inverted control signal / SG is at a low level. The switch SWg grounds the negative power supply terminal of the operational amplifier AMP1 when the control signal SG is at a low level and the inverted control signal / SG is at a high level.

  In accordance with the control signal SD and the inverted control signal / SD (SD bar) obtained by inverting the control signal SD, the switch SWd connects the connection terminal of the drain terminal of the resistance element RI, that is, the HEMT1, between the reference voltage source VREF and the ground. Switch between them. The switch SWd connects the drain terminal of the HEMT 1 to the reference voltage source VREF when the control signal SD is at a high level and the inverted control signal / SD is at a low level. The switch SWd grounds the drain terminal of the HEMT 1 when the control signal SD is at a low level and the inverted control signal / SD is at a high level.

  The control signal SG, the inversion control signal / SG, the control signal SD, and the inversion control signal / SD are generated by the control signal generation circuit and supplied from the control signal generation circuit to the switch SWg and the switch SWd, respectively. The control signal generation circuit will be described later.

  The negative power supply voltage source VNEG generates a negative power supply voltage (also referred to as a negative power supply voltage VNEG) to the negative power supply terminal of the operational amplifier AMP1. The reference voltage source VDRAIN generates a positive voltage (also referred to as a reference voltage VDRAIN) with respect to the negative input terminal of the operational amplifier AMP1. The reference voltage source VREF generates a positive voltage (also referred to as a reference voltage VREF) with respect to the drain terminal of the HEMT 1. The reference voltage source VDRAIN and the reference voltage source VREF are not affected at all by changes in the temperature T and the power supply voltage VDD. The power supply voltage VDD is a positive power supply voltage and can be shared with other external members.

(Drain voltage VD and drain current ID)
In the HEMT bias circuit 10, HEMT1 is incorporated in the negative feedback loop of the operational amplifier AMP1. Thus, while the negative power supply terminal of the operational amplifier AMP1 is connected to the negative power supply voltage source VNEG and the drain terminal of HEMT1 is connected to the reference voltage source VREF, the drain voltage VD and the drain current ID of the HEMT1 are as follows: This is a mechanism that is automatically determined so as to be approximate expressions represented by Equations (3) and (4).

The values in the above formulas are as follows.
V _D : voltage value of drain voltage VD I _D : current value of drain current ID V _DRAIN : voltage value of reference voltage source VDRAIN V _REF : voltage value of reference voltage source VREF RI: resistance value of resistance element RI

  That is, by applying the reference voltage VDRAIN of the reference voltage source VDRAIN to the input of the operational amplifier AMP1, a predetermined voltage (= reference voltage VDRAIN) is obtained at the drain terminal of the HEMT1. Further, by inserting the resistor element RI between the reference voltage source VREF and the drain terminal of the HEMT 1, a potential difference between the reference voltage VREF and the reference voltage VDRAIN is generated at both ends of the resistor element RI. obtain.

  Since Expressions (3) and (4) are not a function of the temperature T or the power supply voltage VDD, the drain voltage VD and the drain current ID of the HEMT 1 are not affected by these fluctuations. Therefore, the HEMT bias circuit 10 can eliminate temperature dependency and power supply voltage dependency.

  Further, since PSRR (Power Supply Rejection Ratio) from the power supply voltage VDD and the negative power supply voltage VNEG to the gate terminal of the HEMT 1 is equal to the PSRR of the operational amplifier AMP1, it is possible to obtain a very high noise removal rate. PSRR is an index indicating how much noise from a certain power supply voltage (here, power supply voltage VDD and negative power supply voltage VNEG) attenuates at a terminal of interest.

  Furthermore, the operational amplifier AMP1 can be configured without requiring a special manufacturing process. Therefore, in the conventional HEMT bias circuit 500 shown in FIG. 11, a PNP type bipolar transistor is essential, but in the HEMT bias circuit 10, the type of transistor is not limited. Therefore, the HEMT bias circuit 10 has a high degree of freedom in selecting a manufacturing process, and an integrated circuit can be manufactured in various processes such as a CMOS process, a MOS process, a bipolar process, and a BiCMOS process.

  However, a single power supply is the mainstream in recent operational amplifiers (differential amplifiers). Further, the operational amplifier AMP1 shown in FIG. 1 has a demerit that it requires both positive and negative power supplies across the GND level.

(LNA and LNB)
The HEMT bias circuit 10 described above can be applied to an LNA (Low Noise Amplifier) in which a HEMT is used. Therefore, the LNA can be realized as an LNA including at least the HEMT 1 and the HEMT bias circuit 10.

  FIG. 8 is a circuit block diagram illustrating a configuration example of the LNA 70. The LNA 70 includes a HEMT 1 and a HEMT bias circuit 10. In the LNA 70, an input unit 71 is provided at the gate terminal of the HEMT 1, and an output unit 72 is provided at the drain terminal of the HEMT 1.

  In the LNA 70 including such a HEMT bias circuit 10, it is possible to drive the HEMT 1 at an appropriate operating point and to obtain the effects exhibited by the above-described HEMT bias circuit 10.

  The LNA 70 can be applied to an LNB (Low Noise Block converter) for receiving satellite broadcasts. As the LNB, for example, there is the LNB 100 of FIG. 12 described above. When applied to the LNB 100, the LNA 70 is used as the horizontally polarized LNA 104 and the vertically polarized LNA 105. Since the LNB 100 includes the LNA 70, the gain and NF of the horizontally polarized LNA 104 and the vertically polarized LNA 105 can be optimized. Therefore, the feed horn 101 (the horizontally polarized antenna 102 and the vertically polarized antenna 103) can be optimized. ) Can be received satisfactorily.

  The LNB 100 has a plurality of functional blocks. Therefore, any of the functional blocks may be combined and integrated, or all the functional blocks may be integrated. By partially integrating or entirely integrating the LNB 100, the component mounting area and the mounting cost are reduced, and the LNB 100 can be reduced in size and cost.

  Here, the HEMT bias circuit 10 can switch on / off of the bias supplied to the HEMT 1 by switching the switch SWg and the switch SWd. That is, the LNA 70 can be switched on / off.

  The LNB 100 shown in FIG. 12 has a specification for selecting and receiving horizontal polarization (left-hand circular polarization) and vertical polarization (right-hand circular polarization) as signal radio waves from satellite broadcasting. In accordance with the polarization selection signal output from the polarization selector 113, the receiving LNA of the horizontal polarization LNA 104 and the vertical polarization LNA 105 is turned on, and the LNA not receiving is turned off. Then, select the polarization to be received.

  Therefore, by selecting the LNA 70 including the HEMT 1 and the HEMT bias circuit 10 so as to switch the switch SWg and the switch SWd according to the polarization selection signal, the selection of the received polarization can be easily performed. It becomes possible.

  However, since the polarization selection signal is a binary (high level and low level) signal, a control signal SG, an inversion control signal / SG, a control signal SD, and an inversion control signal / SD are obtained from the polarization selection signal. A control signal generation circuit to be generated is required. Therefore, in the LNB 100, for example, as shown in FIG. 8, a control signal generation circuit 50 connected to the HEMT bias circuit 10 is provided. The control signal generation circuit 50 is provided for each LNA (horizontal polarization LNA 104 and vertical polarization LNA 105).

(Control signal generation circuit)
Next, the control signal generation circuit 50 will be described.

  FIG. 2 is a circuit diagram illustrating a configuration example of the control signal generation circuit 50. As shown in FIG. 2, the control signal generation circuit 50 includes NOT gates 51, 52, 55, and 57, a capacitor 53, a NOR gate 54, and a NAND gate 56.

  The control signal generation circuit 50 also includes an input unit 58 to which a polarization selection signal is input, an output unit 59 to which a control signal SG is output, an output unit 60 to which an inverted control signal / SG is output, and a control signal SD. And an output unit 62 from which an inversion control signal / SD is output. The input unit 58 is connected to the polarization selector 113. The output unit 59 and the output unit 60 are connected to the switch SWg of the HEMT bias circuit 10. The output unit 61 and the output unit 62 are connected to the switch SWd of the HEMT bias circuit 10.

  The NOT gates 51, 52, 55, and 57 are 1-input 1-output logic circuits that perform NOT operations, and are also called inverters. The NOR gate 54 is a 2-input 1-output logic circuit that performs a NOR operation. The NAND gate 56 is a 2-input 1-output logic circuit that performs a NAND operation. The input part of the NOT gate 51 is connected to the input part 58, and the output part of the NOT gate 51 is connected to the input part of the NOT gate 52. The output part of the NOT gate 52 is connected to the first input part of the NOR gate 54 and the first input part of the NAND gate 56. The capacitor 53 has two terminals, one terminal is connected to the output part of the NOT gate 52, and the other terminal is grounded. The second input part of the NOR gate 54 and the second input part of the NAND gate 56 are connected to the input part 58. The output part of the NOR gate 54 is connected to the input part of the NOT gate 55 and to the output part 60. The output part of the NOT gate 55 is connected to the output part 59. The output part of the NAND gate 56 is connected to the input part of the NOT gate 57 and to the output part 62. The output part of the NOT gate 57 is connected to the output part 61.

  In the control signal generation circuit 50, when the polarization selection signal is at a high level, the control signal SG and the control signal SD are at a high level, and the inverted control signal / SG and the inverted control signal / SD are at a low level. On the other hand, when the polarization selection signal is at a low level, the control signal SG and the control signal SD are at a low level, and the inversion control signal / SG and the inversion control signal / SD are at a high level. Therefore, the LNA 70 can be turned on or off according to the high level and low level of the polarization selection signal.

  However, in the control signal generation circuit 50, a delay element 63 is configured by the NOT gates 51 and 52 and the capacitor 53. Thereby, the level change of the control signal SD and the inverted control signal / SD and the level change of the control signal SG and the inverted control signal / SG are shifted (delayed) by a predetermined time.

(ON / OFF switching timing)
Next, the bias ON / OFF switching timing in the LNA 70 including the HEMT 1 and the HEMT bias circuit 10 will be described.

  FIG. 3 is a timing chart showing signal waveforms when the bias is switched on and off in the LNA 70.

<Time t1>
When the polarization selection signal changes from low level to high level, the second input part of the NOR gate 54 and the second input part of the NAND gate 56 change to high level, while the delay element 63 causes the first input of the NOR gate 54 to change. And the first input part of the NAND gate 56 remain at the low level, the output part of the NOR gate 54 changes to the low level, and the output part of the NAND gate 56 maintains the high level. As a result, the control signal SG becomes high level and the control signal SD becomes low level.

<Time t2>
When a predetermined time (period A) elapses after the polarization selection signal changes from the low level to the high level, the first input portion of the NOR gate 54 and the first input portion of the NAND gate 56 change to the high level. The output part of the NOR gate 54 maintains the low level, and the output part of the NAND gate 56 changes to the low level. As a result, both the control signal SG and the control signal SD become high level.

<Time t3>
When the polarization selection signal changes from the high level to the low level, the second input part of the NOR gate 54 and the second input part of the NAND gate 56 change to the low level, while the delay element causes the first input part of the NOR gate 54 to change. Since the first input portion of the NAND gate 56 remains at the high level, the output portion of the NOR gate 54 maintains the low level, and the output portion of the NAND gate 56 changes to the high level. As a result, the control signal SG becomes high level and the control signal SD becomes low level.

<Time t4>
When a predetermined time (period B) elapses after the polarization selection signal changes from the high level to the low level, the first input portion of the NOR gate 54 and the first input portion of the NAND gate 56 change to the low level. The output part of the NOR gate 54 changes to high level, and the output part of the NAND gate 56 maintains high level. As a result, both the control signal SG and the control signal SD are at a low level.

  As described above, when the polarization selection signal is changed from the low level to the high level in order to switch the LNA 70 from the off state to the on state, the control signal SG becomes the high level and the inversion control signal / SD becomes the high level, and the drain voltage VD. The period A during which the gate voltage VG is applied to the HEMT 1 is provided first. During this period A, carriers present in the channel of the HEMT 1 are reduced, and the through electrode is less likely to flow.

  Therefore, by setting the period A to a sufficient time or a time until the HEMT 1 reaches pinch-off, the control signal SD becomes a high level after the period A has elapsed, and the drain voltage VD is applied to the HEMT 1. It is possible to prevent an excessive drain current ID from flowing.

  On the other hand, when the polarization selection signal is changed from the high level to the low level in order to switch the LNA 70 from on to off, the control signal SG becomes high level and the inversion control signal / SD becomes high level, and the gate voltage VG is applied to HEMT1. The period B in which the drain voltage VD becomes zero is provided first while the voltage is applied. In the period B, the gate voltage VG remains in the negative power supply voltage, so that an excessive drain current ID does not flow. Therefore, it is possible to prevent an excessive drain current ID from flowing.

  Note that the period A and the period B can be set depending on the configuration of the delay element 63.

  As described above, the HEMT bias circuit 10 switches the connection of the negative power supply terminal of the operational amplifier AMP1 from the ground to the negative power supply voltage source VNEG by switching the switch SWg when switching the supply of bias to the HEMT1 from OFF to ON. After switching, the connection destination of the second terminal of the resistor element RI is switched from the ground to the reference voltage source VREF by switching the switch SWd, and when the bias supply to the HEMT 1 is switched from on to off, the switch SWd is changed. After switching the connection destination of the second terminal of the resistance element RI from the reference voltage source VREF to the ground, the connection destination of the negative power supply terminal of the operational amplifier AMP1 is switched from the negative power supply voltage source VNEG to the ground by switching the switch SWg. It has a configuration.

  Thus, when the supply of bias to the HEMT 1 is switched from OFF to ON, a sequence in which the drain voltage is applied to the drain terminal of the HEMT 1 after the gate terminal of the HEMT 1 is first biased to a negative voltage state. That is, the sequence is such that a voltage is applied to the drain terminal of HEMT 1 after a voltage is applied to the gate terminal of HEMT 1. Therefore, since the carrier existing in the channel of the HEMT 1 is reduced during the period from when the voltage is applied to the gate terminal of the HEMT 1 to when the voltage is applied to the drain terminal of the HEMT 1, it is possible to make it difficult for the through electrode to flow. .

  On the other hand, when the bias supply to the HEMT 1 is switched from on to off, the drain voltage of the HEMT 1 is set to zero and then the gate voltage of the HEMT 1 is set to zero. That is, the sequence is such that the voltage at the drain terminal of HEMT1 is erased and then the voltage at the gate terminal of HEMT1 is erased. Therefore, since the gate terminal of HEMT1 remains at a negative voltage during the period from erasing the voltage at the drain terminal of HEMT1 to erasing the voltage at the gate terminal of HEMT1, it is possible to prevent excessive drain current from flowing. It becomes possible to do.

  That is, in the HEMT bias circuit 10, the timing for applying and erasing the voltage to the gate terminal and the timing for applying and erasing the voltage to the drain terminal are largely set for the HEMT 1 according to the switching timing of the switch SWg and the switch SWd. It is possible to control so that no through current flows.

  Therefore, it is possible to prevent excessive through current from being generated when the bias supply to the HEMT 1 is switched from OFF to ON and when the bias supply to the HEMT 1 is switched from ON to OFF.

[Embodiment 2]
(Configuration of HEMT bias circuit)
FIG. 4 is a circuit diagram showing a configuration example of the HEMT bias circuit 20 of the present embodiment.

  The HEMT bias circuit 20 according to the present embodiment is a bias circuit for the HEMT 1 whose source terminal is grounded. As shown in FIG. 4, the HEMT bias circuit 20 includes an operational amplifier AMP2 (first differential amplifier), an operational amplifier AMP3 (second differential amplifier), a resistance element RI, a resistance element RG (second resistance element), and a resistance element RGG. (Sixth resistance element), resistance element RR (third resistance element), resistance element R1 (fourth resistance element), resistance element R2 (fifth resistance element), capacitor CD (first capacitor), capacitor CG (second Capacitor), N-channel MOSFET (hereinafter referred to as NMOS transistor) 21 (first transistor), P-channel MOSFET (hereinafter referred to as PMOS transistor) 22 (second transistor), switch SWg, switch SWd, negative power supply voltage A source VNEG and a reference voltage source VREF are provided.

  In the HEMT bias circuit 20, the voltages from the reference voltage source VDRAIN and the reference voltage source VREF used in the first embodiment are the operational amplifier AMP3, the PMOS transistor 22, the resistor element R2, the resistor element R1, the resistor element RR, and It is generated by a circuit comprising a reference voltage source VREF.

  The operational amplifier AMP2 is a single power supply type operational amplifier, and is configured as a differential amplifier. The positive input terminal (second input terminal) of the operational amplifier AMP2 is connected to the drain terminal of the HEMT1. The negative input terminal (first input terminal) of the operational amplifier AMP2 is connected to the drain terminal of the PMOS transistor 22 via the resistance element R2. The negative input terminal of the operational amplifier AMP2 is connected to the positive input terminal of the operational amplifier AMP3 via the resistance element R1. The output terminal of the operational amplifier AMP2 is connected to the gate terminal (control terminal) of the NMOS transistor 21.

  The operational amplifier AMP3 is a single power supply type operational amplifier, and is configured as a differential amplifier. The positive input terminal (first input terminal) of the operational amplifier AMP3 is connected to the drain terminal of the PMOS transistor 22 via the resistance element R1 and the resistance element R2. Further, the positive input terminal of the operational amplifier AMP3 is grounded via the resistance element RR. The negative input terminal (second input terminal) of the operational amplifier AMP3 is connected to the reference voltage source VREF. The output terminal of the operational amplifier AMP3 is connected to the gate terminal (control terminal) of the PMOS transistor 22. The PMOS transistor 22, the resistor element R2, and the resistor element R1 are incorporated in the negative feedback loop of the operational amplifier AMP3.

  The drain terminal (first conduction terminal) of the NMOS transistor 21 is connected to the power supply voltage VDD. The source terminal (second conduction terminal) of the NMOS transistor 21 is connected to the gate terminal of the HEMT 1 via the resistance element RGG. The source terminal of the NMOS transistor 21 is connected to the negative power supply voltage source VNEG via the resistance element RG. That is, one terminal (third terminal) of the resistance element RG is connected to the gate terminal of the HEMT 1 and the other terminal (fourth terminal) is connected to the negative power supply voltage source VNEG.

  The source terminal (first conduction terminal) of the PMOS transistor 22 is connected to the power supply voltage VDD. The drain terminal (second conduction terminal) of the PMOS transistor 22 is grounded through the resistance element R2, the resistance element R1, and the resistance element RR in this order. Further, the drain terminal of the PMOS transistor 22 is connected to the drain terminal of the HEMT 1 through the resistance element RI.

  The capacitor CD has two terminals, one terminal (fifth terminal) is connected to the drain terminal of the HEMT 1, and the other terminal (sixth terminal) is grounded. The capacitor CG has two terminals, one terminal (seventh terminal) is connected to the gate terminal of HEMT1, and the other terminal (eighth terminal) is connected to the source terminal of HEMT1.

  The switch SWg has two terminals in this embodiment, and one terminal is connected to one point on the path where the resistance element RGG and the resistance element RG are electrically connected, and the other terminal is grounded. Has been. The switch SWg is turned on / off according to the inversion control signal / SG. The switch SWg is turned on when the inversion control signal / SG is at a high level, and turned off when the inversion control signal / SG is at a low level. By switching the switch SWg, the gate terminal of the HEMT 1 is connected to the negative power supply voltage source VNEG or grounded.

  The switch SWd has two terminals in this embodiment, one terminal is connected to the output terminal of the operational amplifier AMP3, and the other terminal is connected to the power supply voltage VDD. The switch SWd is turned on / off according to the inversion control signal / SD. The switch SWd is turned on when the inversion control signal / SD is at a high level, and turned off when the inversion control signal / SD is at a low level. By switching the switch SWd, the gate terminal of the PMOS transistor 22 is connected to the output terminal of the operational amplifier AMP3 or to the power supply voltage VDD.

  In this embodiment, the negative power supply voltage source VNEG generates a negative power supply voltage (negative power supply voltage VNEG) with respect to the gate terminal of the HEMT 1. In this embodiment, the reference voltage source VREF generates a positive voltage (reference voltage VREF) with respect to the negative input terminal of the operational amplifier AMP3.

(Drain voltage VD and drain current ID)
In the HEMT bias circuit 20, a first negative feedback loop including the operational amplifier AMP3 and a second negative feedback loop including the operational amplifier AMP2 are formed. Then, HEMT1 is incorporated in the second negative feedback loop. As a result, while the switch SWg and the switch SWd are on, the drain voltage VD and the drain current ID of the HEMT 1 are automatically determined so as to be approximated by the following equations (5) and (6). It is a mechanism to be done.

The values in the above formulas are as follows.
V _D : voltage value of drain voltage VD I _D : current value of drain current ID V _REF : voltage value of reference voltage source VREF R _I : resistance value R _R of resistance element RI _R : resistance value R ₁ of resistance element RR resistance value of the element R1 _{R 2:} the resistance value of the resistance element R2.

  The temperature coefficients of the drain voltage VD and the drain current ID are obtained by differentiating the equations (5) and (6) with the temperature T and become zero. Therefore, the HEMT bias circuit 20 can completely eliminate the temperature dependence.

  Further, the coefficient of variation of the drain voltage VD and the drain current ID with respect to the power supply voltage VDD is obtained by differentiating the equations (5) and (6) with the power supply voltage VDD and becomes zero. Therefore, the HEMT bias circuit 20 can completely eliminate power supply voltage dependency.

(LNA and LNB)
The HEMT bias circuit 20 described above can be applied to LNAs and LNBs similarly to the HEMT bias circuit 10 of the above-described embodiment. Then, by configuring the LNA including the HEMT 1 and the HEMT bias circuit 20 so as to switch the switch SWg and the switch SWd according to the polarization selection signal, it is possible to easily select the received polarization. It becomes. Generation of the inversion control signal / SG and the inversion control signal / SD from the polarization selection signal is performed by a control signal generation circuit.

(Control signal generation circuit)
Next, an example of the control signal generation circuit will be described.

  FIG. 5 is a circuit diagram showing a configuration example of the control signal generation circuit 50a. As shown in FIG. 5, the control signal generation circuit 50 a includes NOT gates 51, 52, and 57, a capacitor 53, and a NAND gate 56. That is, the control signal generation circuit 50a has a configuration in which the NOR gate 54 and the NOT gate 55 are excluded from the configuration of the control signal generation circuit 50 shown in FIG.

  The input part of the NOT gate 51 is connected to the input part 58. The output part of the NOT gate 51 is connected to the input part of the NOT gate 52 and to the output part 60. The output part of the NOT gate 52 is connected to the first input part of the NAND gate 56. A second input portion of the NAND gate 56 is connected to the input portion 58. The output part of the NAND gate 56 is connected to the input part of the NOT gate 57 and to the output part 62. The output part of the NOT gate 57 is connected to the output part 61. The output unit 59 is connected to the input unit 58.

  The output unit 60 from which the inversion control signal / SG is output is connected to the switch SWg of the HEMT bias circuit 20. The output unit 62 that outputs the inversion control signal / SD is connected to the switch SWd of the HEMT bias circuit 20. The output unit 59 from which the control signal SG is output and the output unit 61 from which the control signal SD is output are not connected to the HEMT bias circuit 20.

  In the control signal generation circuit 50a, when the polarization selection signal is at a high level, the control signal SG and the control signal SD are at a high level, and the inversion control signal / SG and the inversion control signal / SD are at a low level. On the other hand, when the polarization selection signal is at a low level, the control signal SG and the control signal SD are at a low level, and the inversion control signal / SG and the inversion control signal / SD are at a high level. Therefore, the LNA can be turned on or off according to the high level and low level of the polarization selection signal.

  However, in the control signal generation circuit 50 a, the delay element 63 is configured by the NOT gates 51 and 52 and the capacitor 53. Thereby, the level change of the control signal SD and the inverted control signal / SD and the level change of the control signal SG and the inverted control signal / SG are shifted (delayed) by a predetermined time.

  In HEMT bias circuit 20, inversion control signal / SG and inversion control signal / SD are required, and control signal SG and control signal SD are not required. Therefore, in the control signal generation circuit 50a, the output unit 59 and the output unit 61 are not necessarily provided. However, since the control signal generation circuit 50 a can be used for the HEMT bias circuit 10, the output unit 59 and the output unit 61 are necessary when used for the HEMT bias circuit 10.

(ON / OFF switching timing)
Next, bias on / off switching timing in an LNA including the HEMT 1 and the HEMT bias circuit 20 will be described.

  FIG. 6 is a timing chart showing signal waveforms when the bias is switched on and off in the LNA.

<Time t1>
When the polarization selection signal changes from low level to high level, the control signal SG changes to high level. Further, while the second input portion of the NAND gate 56 changes to high level, the first input portion of the NAND gate 56 remains low level by the delay element 63, so that the output portion of the NAND gate 56 is high level. To maintain. As a result, the control signal SG becomes high level and the control signal SD becomes low level.

<Time t2>
When a predetermined time (period A) elapses after the polarization selection signal changes from the low level to the high level, the first input portion of the NAND gate 56 changes to the high level. Change to level. As a result, both the control signal SG and the control signal SD become high level.

<Time t3>
When the polarization selection signal changes from high level to low level, the control signal SG changes to low level. The delay element 63 keeps the first input portion of the NAND gate 56 at the high level, while the second input portion of the NAND gate 56 changes to the low level, so that the output portion of the NAND gate 56 has the high level. To change. As a result, both the control signal SG and the control signal SD are at a low level.

<Time t4>
When a predetermined time (period B) elapses after the polarization selection signal changes from the high level to the low level, the first input portion of the NAND gate 56 changes to the low level. Maintain level. As a result, both the control signal SG and the control signal SD maintain a low level.

  As described above, when the polarization selection signal is changed from the low level to the high level in order to switch the LNA from the off state to the on state, the inversion control signal / SG becomes the low level and the inversion control signal / SD becomes the high level. The period A during which the gate voltage VG is applied to the HEMT 1 is provided while the voltage VD remains zero. During this period A, carriers present in the channel of the HEMT 1 are reduced, and the through electrode is less likely to flow.

  Therefore, by setting the period A to a sufficient time or a time until the HEMT 1 reaches pinch-off, the inversion control signal / SD becomes a low level after the period A elapses, and the drain voltage VD is applied to the HEMT 1. However, it is possible to prevent an excessive drain current ID from flowing.

  On the other hand, in order to switch the LNA from on to off, the polarization selection signal is changed from the high level to the low level, the inversion control signal / SG is at the high level, and the inversion control signal / SD is at the high level. At this time, the drain voltage VD of the HEMT 1 is accumulated as a charge in the capacitor CD. Therefore, from the moment when the LNA is turned off, the charge of the capacitor CD passes through the resistance element RI, the resistance element R2, the resistance element R1, and the resistance element RR in this order, and is discharged to the GND level.

  In addition, the gate voltage of HEMT 1 is accumulated as a charge in the capacitor CG. Therefore, from the moment when the LNA is turned off, the negative voltage of the capacitor CG is charged from GND via the switch SWg and the resistance element RGG and reaches the GND level.

  The time tD required for discharging the drain voltage and the time tG required for charging the gate voltage are expressed by the following equations (7) and (8).

The values in the above formulas are as follows.
R _ON : ON resistance of switch SWg R _GG : Resistance value R _D of resistance element RGG C Capacitance value of capacitor CD C _G : Capacitance value of capacitor CG

  In the LNA including the HEMT 1 and the HEMT bias circuit 20, each value is set so that “tD <tG”. As a result, it is possible to generate the period B in which the drain voltage VD first becomes the GND level and the gate voltage VG is applied. In the period B, since the gate voltage VG remains in the negative power supply voltage, it is possible to prevent an excessive drain current ID from flowing.

  In this embodiment, the period A can be set by the configuration of the delay element 63, and the period B is determined by the set time tG.

  As described above, when switching the bias supply to the HEMT 1 from OFF to ON, the HEMT bias circuit 20 switches the switch SWd after cutting off the connection between the gate terminal of the HEMT 1 and the ground by switching the switch SWg. Thus, the connection between the gate terminal and the source terminal of the PMOS transistor 22 is cut off. When the bias supply to the HEMT 1 is switched from on to off, the gate terminal of the PMOS transistor 22 is switched to the source terminal by switching the switch SWd. The gate terminal of HEMT 1 is connected to the ground by switching the switch SWg at the same time as the connection to.

  Thus, when the supply of bias to the HEMT 1 is switched from OFF to ON, a sequence in which the drain voltage is applied to the drain terminal of the HEMT 1 after the gate terminal of the HEMT 1 is first biased to a negative voltage state. That is, the sequence is such that a voltage is applied to the drain terminal of HEMT 1 after a voltage is applied to the gate terminal of HEMT 1. Therefore, since the carrier existing in the channel of the HEMT 1 is reduced during the period from when the voltage is applied to the gate terminal of the HEMT 1 to when the voltage is applied to the drain terminal of the HEMT 1, it is possible to make it difficult for the through electrode to flow. .

  On the other hand, since the HEMT bias circuit 20 includes the capacitor CD and the capacitor CG, the time required to discharge the drain voltage of the HEMT 1 and the gate voltage of the HEMT 1 when the bias supply to the HEMT 1 is switched from on to off. It is possible to control the time required for charging.

  Therefore, when switching the bias supply to the HEMT 1 from on to off by setting the charging time of the gate voltage longer than the discharging time of the drain voltage, even if the switch SWg and the switch SWd are simultaneously switched, A sequence in which the gate voltage of the HEMT 1 is made zero after making the drain voltage zero can be prevented, and an excessive drain current can be prevented from flowing.

  Therefore, in the HEMT bias circuit 20, as in the HEMT bias circuit 10 described above, excessive switching is performed when the bias supply to the HEMT 1 is switched from OFF to ON and when the bias supply to the HEMT 1 is switched from ON to OFF. It is possible to prevent the occurrence of a through current.

  The control signal generation circuit used for the HEMT bias circuit 20 is not limited to the control signal generation circuit 50a, and the control signal generation circuit 50 may be used. When the control signal generation circuit 50 is used, the HEMT bias circuit 20 switches the supply of the bias to the HEMT 1 from on to off after connecting the gate terminal of the PMOS transistor 22 to the source terminal by switching the switch SWd. By switching the switch SWg, the gate terminal of the HEMT 1 can be connected to the ground.

  When the control signal generation circuit 50 is used, the HEMT bias circuit 20 does not necessarily include the capacitor CD and the capacitor CG.

  In any configuration, it is possible to prevent excessive through current from being generated when the bias supply to the HEMT 1 is switched from OFF to ON and when the bias supply to the HEMT 1 is switched from ON to OFF. Become.

  As described above, in the HEMT bias circuit 20, when the bias supply to the HEMT 1 is switched from on to off, it is possible to perform switching of the switch SWg and switching of the switch SWd at the same time, or a sequence of shifting the switching. It is possible to expand the range of control.

  The control signal generation circuits 50 and 50a described above are merely examples, and the present invention is not limited to this. The control signal generation circuit may be any circuit capable of generating the control signal SD, the inversion control signal / SD, the control signal SG, and the inversion control signal / SG that performs the level change shown in FIGS. 3 and 6.

  By the way, when integrating the HEMT bias circuit 20, the breakdown voltage of the NMOS transistor 21 may be a problem. This is because the voltage between VDD and VG is applied to the NMOS transistor 21 when the switch SWg is off. Since the gate voltage VG is a negative voltage, the potential difference between VDD and VG is higher than the potential difference between VDD and GND. Therefore, if integration is performed by a manufacturing process in which the potential difference between VDD and GND is not guaranteed, there is a problem in terms of reliability.

  Assuming the initial start-up of the circuit or the switching of the circuit operation, it is assumed that a voltage between VDD and VNEG is transiently applied to the NMOS transistor 21. Also in this case, since the negative power supply voltage VNEG is a negative voltage, there may be a problem in terms of device reliability. Therefore, it is desired to solve these problems in the HEMT bias circuit.

  On the other hand, the HEMT bias circuit 20 includes a resistance element RGG inserted between the source terminal of the NMOS transistor 21 and the gate terminal of the HEMT 1. As a result, the NMOS transistor 21 can be driven within the allowable breakdown voltage of the NMOS transistor 21. Therefore, the HEMT bias circuit 20 can have excellent reliability.

[Embodiment 3]
FIG. 7 is a circuit diagram showing a configuration example of the HEMT bias circuit 30 according to the present embodiment. As shown in FIG. 7, the HEMT bias circuit 30 of the present embodiment has a configuration excluding the resistance element RGG from the configuration of the HEMT bias circuit 20 of the second embodiment.

  The HEMT bias circuit 30 can be applied to the LNA and the LNB in the same manner as the HEMT bias circuit 20 of the above embodiment. Then, by configuring the LNA including the HEMT 1 and the HEMT bias circuit 30 so as to switch the switch SWg and the switch SWd according to the polarization selection signal, it is possible to easily select the polarization to be received. Become. Generation of the inversion control signal / SG and the inversion control signal / SD from the polarization selection signal is performed by a control signal generation circuit.

  As the control signal generation circuit, for example, the control signal generation circuit 50 shown in FIG. 2 or the control signal generation circuit 50a shown in FIG. 5 can be used. In any case, the inversion control signal / SG output from the output unit 60 may be supplied to the switch SWg, and the inversion control signal / SD output from the output unit 62 may be supplied to the switch SWd. Changes in the drain voltage and gate voltage of the HEMT 1 at the time of on / off switching are as described above.

  The HEMT bias circuit 30 can achieve the same effects as the HEMT bias circuits 10 and 20 described above. Further, when the problem of the breakdown voltage of the NMOS transistor 21 is not particularly concerned, the HEMT bias circuit 30 can operate without any problem. According to the configuration of the HEMT bias circuit 30, the circuit area can be reduced. It becomes possible to plan.

  Finally, in the first to third embodiments, the HEMT bias circuit for HEMT has been described. However, the HEMT bias circuit is not necessarily limited to the HEMT, and can be applied to transistors other than the HEMT. For example, a general transistor such as a JFET, MOSFET, or bipolar transistor can be used, and can be used as a bias circuit for this. Needless to say, the HEMT is particularly effective, but the same effect can be obtained with other transistors.

  In the HEMT bias circuit of each embodiment, positive logic is used. However, even if negative logic is used, the HEMT bias circuit can be realized from the same viewpoint. Further, it can be modified as follows.

  The HEMT bias circuits 20 and 30 include the NMOS transistor 21 and the PMOS transistor 22, but are not limited thereto. For example, a PMOS transistor may be provided instead of the NMOS transistor 21, or an NMOS transistor may be provided instead of the PMOS transistor 22. Furthermore, a PNP bipolar transistor, an NPN bipolar transistor, or the like can be used.

  When a PMOS transistor or a PNP bipolar transistor is provided in place of the NMOS transistor 21, the positive input terminal and the negative input terminal of the operational amplifier AMP2 may be switched (the positive input terminal of the operational amplifier AMP2 is connected to the resistor element R1 and is negative). The input terminal is connected to the drain terminal of HEMT1). When an NMOS transistor or an NPN bipolar transistor is provided instead of the PMOS transistor 22, the positive input terminal and the negative input terminal of the operational amplifier AMP3 may be switched (the positive input terminal of the operational amplifier AMP3 is connected to the reference voltage source VREF and is negative). The input terminal is connected to the resistor element R1).

In the HEMT bias circuits 20 and 30, a constant current source may be used instead of the resistance element RR. In this case, the drain current ID becomes “I _D = (R ₂ / R ₁ ) × IB”, which is a ratio of resistance values, so that current variation can be reduced.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be suitably used for bias circuits, LNAs, LNBs, communication receivers, communication transmitters, and sensor systems.

1 HEMT (Amplification FET)
10, 20, 30 HEMT bias circuit (bias circuit)
21 NMOS transistor (first transistor)
22 PMOS transistor (second transistor)
50, 50a Control signal generation circuit 100 LNB
102 Horizontal polarization antenna (first polarization antenna)
103 Vertical polarization antenna (second polarization antenna)
104 LNA for horizontal polarization (first polarization amplifier)
105 Vertically polarized LNA (second polarization amplifier)
113 Polarization selector 116 Coaxial cable 117 TV set 118 Video set VD Drain voltage ID Drain current AMP1 Operational amplifier (dual power supply type differential amplifier)
AMP2 operational amplifier (first differential amplifier)
AMP3 operational amplifier (second differential amplifier)
RI resistance element (first resistance element)
RG resistance element (second resistance element)
RR resistance element (third resistance element)
R1 resistance element (fourth resistance element)
R2 resistance element (5th resistance element)
RGG resistance element (sixth resistance element)
SWg switch (first switch)
SWd switch (second switch)
CD capacitor (first capacitor)
CG capacitor (second capacitor)
VDD power supply voltage VNEG negative power supply voltage source VREF reference voltage source (first reference voltage source)
VDRAIN reference voltage source (second reference voltage source)

Claims (10)

A bias circuit for supplying a bias to an amplifying FET whose source terminal for amplifying an input signal is grounded;
A dual power supply type differential amplifier, a first resistance element, a first switch, a second switch, a first reference voltage source, a second reference voltage source, and a negative power supply voltage source;
The differential amplifier has a positive input terminal connected to the drain terminal of the amplification FET, a negative input terminal connected to the second reference voltage source, an output terminal connected to the gate terminal of the amplification FET, A power supply terminal can be connected to the negative power supply voltage source or the ground by switching the first switch,
The first resistance element has a first terminal and a second terminal, the first terminal is connected to the drain terminal of the amplification FET, and the second terminal is switched to the first reference by switching the second switch. Can be connected to a voltage source or ground,
When switching the supply of bias from OFF to ON, the second switch is switched after the connection destination of the negative power supply terminal of the differential amplifier is switched from ground to the negative power supply voltage source by switching the first switch. Thus, the connection destination of the second terminal of the first resistance element is switched from the ground to the first reference voltage source,
When switching the bias supply from on to off, the second switch is switched to switch the connection destination of the second terminal of the first resistance element from the first reference voltage source to the ground, and then the first switch. the differential negative power supply characteristics and to Luba bias circuit to a connection destination to switch to ground from the negative power supply voltage source terminal of the amplifier by switching. The bias circuit according to claim 1 , wherein the amplification FET is a HEMT. A bias circuit for supplying a bias to an amplifying FET whose source terminal for amplifying an input signal is grounded;
A single power supply type first differential amplifier, a single power supply type second differential amplifier, a first transistor, a second transistor, a first resistance element, a second resistance element, and a third resistance element A fourth resistance element, a fifth resistance element, a first switch, a second switch, a reference voltage source, and a negative power supply voltage source,
The first transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The second transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The first differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fifth resistance element, a second input terminal connected to the drain terminal of the amplification FET, An output terminal connected to the control terminal of the first transistor;
The second differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor through the fourth resistance element and the fifth resistance element in this order, and a second input terminal connected to the reference Connected to the voltage source, the output terminal is connected to the control terminal of the second transistor,
The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET,
The second transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the ground through the fifth resistance element, the fourth resistance element, and the third resistance element in this order,
The first resistance element has a first terminal and a second terminal, the first terminal is connected to the drain terminal of the amplification FET, and the second terminal is connected to the second conduction terminal of the second transistor. And
The second resistance element has a third terminal and a fourth terminal, the third terminal is connected to the gate terminal of the amplification FET, the fourth terminal is connected to the negative power supply voltage source,
The first switch is connected to the gate terminal of the amplification FET, and the gate terminal of the amplification FET can be connected to the ground by switching the first switch.
The second switch is connected to the control terminal of the second transistor, and the control terminal of the second transistor can be connected to the first conduction terminal of the second transistor by switching the second switch.
When switching the bias supply from OFF to ON, the first switch is switched to cut off the connection between the gate terminal of the amplification FET and the ground, and then the second switch is switched to switch the second transistor. Cutting off the connection between the control terminal and the first conduction terminal of the second transistor;
When switching the bias supply from on to off, the second switch is switched to connect the control terminal of the second transistor to the first conduction terminal of the second transistor, and then the first switch is switched. features and to Luba bias circuit to connect the gate terminal of the amplifier FET to ground. A bias circuit for supplying a bias to an amplifying FET whose source terminal for amplifying an input signal is grounded;
A single power supply type first differential amplifier, a single power supply type second differential amplifier, a first transistor, a second transistor, a first resistance element, a second resistance element, and a third resistance element A fourth resistance element, a fifth resistance element, a first switch, a second switch, a reference voltage source, a negative power supply voltage source, a first capacitor, and a second capacitor,
The first transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The second transistor has a first conduction terminal, a second conduction terminal, and a control terminal,
The first differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor via the fifth resistance element, a second input terminal connected to the drain terminal of the amplification FET, An output terminal connected to the control terminal of the first transistor;
The second differential amplifier has a first input terminal connected to the second conduction terminal of the second transistor through the fourth resistance element and the fifth resistance element in this order, and a second input terminal connected to the reference Connected to the voltage source, the output terminal is connected to the control terminal of the second transistor,
The first transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the gate terminal of the amplification FET,
The second transistor has a first conduction terminal connected to the power supply voltage, a second conduction terminal connected to the ground through the fifth resistance element, the fourth resistance element, and the third resistance element in this order,
The first resistance element has a first terminal and a second terminal, the first terminal is connected to the drain terminal of the amplification FET, and the second terminal is connected to the second conduction terminal of the second transistor. And
The second resistance element has a third terminal and a fourth terminal, the third terminal is connected to the gate terminal of the amplification FET, the fourth terminal is connected to the negative power supply voltage source,
The first switch is connected to the gate terminal of the amplification FET, and the gate terminal of the amplification FET can be connected to the ground by switching the first switch.
The second switch is connected to the control terminal of the second transistor, and the control terminal of the second transistor can be connected to the first conduction terminal of the second transistor by switching the second switch.
The first capacitor has a fifth terminal and a sixth terminal, the fifth terminal is connected to the drain terminal of the amplification FET, the sixth terminal is connected to the ground,
The second capacitor has a seventh terminal and an eighth terminal, the seventh terminal is connected to the gate terminal of the amplification FET, the eighth terminal is connected to the source terminal of the amplification FET,
When switching the bias supply from OFF to ON, the first switch is switched to cut off the connection between the gate terminal of the amplification FET and the ground, and then the second switch is switched to switch the second transistor. Cutting off the connection between the control terminal and the first conduction terminal of the second transistor;
When switching the bias supply from on to off, the first switch is switched after or simultaneously with connecting the control terminal of the second transistor to the first conduction terminal of the second transistor by switching the second switch. features and to Luba bias circuitry to connect to ground the gate terminal of the amplifier FET by switching. 5. The bias circuit according to claim 3 , wherein the amplifying FET is a HEMT. The first transistor is an N-channel MOSFET, and the first conduction terminal, the second conduction terminal, and the control terminal of the first transistor are a drain terminal, a source terminal, and a gate terminal of the N-channel MOSFET, respectively. Yes,
The second transistor is a P-channel MOSFET, and the first conduction terminal, the second conduction terminal, and the control terminal of the second transistor are a source terminal, a drain terminal, and a gate terminal of the P-channel MOSFET, respectively. Yes,
The first input terminal and the second input terminal of the first differential amplifier are a negative input terminal and a positive input terminal, respectively.
6. The bias circuit according to claim 3 , wherein the first input terminal and the second input terminal of the second differential amplifier are a positive input terminal and a negative input terminal, respectively. A sixth resistance element;
The sixth resistive element, claim 3-6, characterized in that provided electrically connected to the path and a gate terminal of the second conduction terminal and the amplifier FET of the first transistor 2. The bias circuit according to item 1. An amplifying FET whose source terminal amplifies the input signal is grounded;
A bias circuit according to any one of claims 1 to 7 ,
An input terminal is provided at the gate terminal of the amplification FET,
An LNA, wherein an output terminal is provided at a drain terminal of the amplifying FET. An LNB that amplifies and down-converts a signal received by an antenna and transmits it to the subsequent stage,
A first polarization antenna that receives the first polarization and converts the first polarization into a first polarization signal;
A second polarization antenna that receives the second polarization and converts the second polarization into a second polarization signal;
A first polarization amplifier for amplifying the first polarization signal;
A second polarization amplifier for amplifying the second polarization signal;
A polarization selector that selects which of the first polarization and the second polarization is received;
The first polarization and the second polarization are respectively a horizontal polarization and a vertical polarization, or a left-handed circular polarization and a right-handed circular polarization,
The first polarization amplifier and the second polarization amplifier are LNAs according to claim 8 ,
The first polarization amplifier and the second polarization amplifier receive a polarization selection signal indicating which of the first polarization and the second polarization output from the polarization selector is received. In response, the LNB switches the first switch and the second switch, respectively. The LNB of claim 9 , wherein the LNB is partially integrated.

Images