JP2007006180A - Antenna switch circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an antenna switch circuit device the maximum permissible input power of which is improved. <P>SOLUTION: The antenna switch circuit device includes: a compound semiconductor integrated circuit including a first terminal connected to an antenna and a plurality of through FETs connected to the first terminal; and a CMOS integrated circuit including a decoder circuit, a booster circuit, and a plurality of CMOS inverters respectively receiving a signal from the decoder circuit and a signal from the booster circuit, and the antenna switch circuit device selectively executes a first mode wherein signals from the first through FETs are transmitted to the first terminal or a second mode wherein the signal from the first terminal is transmitted through the through FET that is turned on, and an output circuit of the booster circuit is clamped on the basis of a gate-channel reverse current of the turned-off through FET in at least either of the first and second modes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an antenna switch circuit device, and more particularly to an antenna switch circuit device using an FET.

  The market for wireless communication systems such as mobile phones and wireless LANs is expanding rapidly, and technological progress to achieve this is remarkable. The main components of the wireless communication device are an antenna switch circuit, a control circuit, a transceiver, and the like. Unlike the trunk line application, the communication device used for the above application needs to be small, easy to use, and rich in mass productivity. In particular, triple-band mobile phones that are compatible with GSM (Global System for Mobile communications), DCS (Digital Cellular System) / PCS (Personal Communications Service), etc., are small and mass-productive SPDT (Single-Pole Double- Throw) switch is required.

  A compound semiconductor element such as GaAs having a high electron mobility is used for an antenna switch circuit device that meets such requirements. That is, a GaAs FET or the like is placed in a through and shunt on a high-frequency transmission line, and the connection destination of the antenna terminal is connected to either the transmitter or the receiver terminal by complementarily turning on or off by a gate control signal. Can be switched.

A wireless device corresponding to the above application needs to be small, and there is a technical disclosure example of a compound semiconductor integrated circuit (Patent Document 1). However, the transmission output of a mobile phone required in a new system such as GSM is larger than that of a conventional mobile phone. The prior art is insufficient to achieve downsizing while providing means for realizing this.
JP 2002-368193 A

  The present invention provides an antenna switch circuit device with improved maximum allowable input power.

According to one aspect of the invention,
A first terminal connected to the antenna;
A compound semiconductor integrated circuit including a plurality of through FETs connected to the first terminal;
A CMOS integrated circuit including a decoder circuit, a booster circuit, and a plurality of CMOS inverters to which signals from the decoder circuit are input;
With
The booster circuit is connected to the power supply terminal of the first CMOS inverter of the plurality of CMOS inverters, and the first of the plurality of through FETs is controlled by a high level control signal from the first CMOS inverter. The first through FETs of the plurality of through FETs are turned on by a low level control signal output from a CMOS inverter different from the first CMOS inverter among the plurality of CMOS inverters. A first mode for transmitting a signal from the first through FET to the first terminal by turning off all but the FET; and
One of the plurality of through FETs is turned on by a high level control signal from a CMOS inverter other than the first CMOS inverter among the plurality of CMOS inverters, and a low level control is performed from another CMOS inverter. A second mode in which a signal from the first terminal is transmitted through the turned-on through FET by turning off all other through-FETs by a signal;
Selectively run,
In at least one of the first and second modes, the output circuit of the booster circuit is clamped based on the reverse current between the gate and the channel of the through FET that has been turned off. An apparatus is provided.

  According to the present invention, an antenna switch circuit device including a compound semiconductor integrated circuit and a CMOS integrated circuit and having an improved maximum allowable input power is provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is an equivalent circuit diagram of an antenna switch circuit device according to a first specific example of the present invention.
A first through FET 12 and a second through FET 22 are connected to a terminal A connected to the antenna. The other electrode of the first through FET 12 is connected to a terminal B connected to the transmitter. The other electrode of the second through FET 22 is connected to a terminal C connected to the receiver. These FETs constitute an SPDT switch.

  The gates of the first through FET 12 and the second through FET 22 are connected to the decoder circuit 34 through gate resistors 10 and 20, respectively. For example, when a high level signal such as 3.5 volts is applied to the gate of the FET, the FET is turned on, and when a low level signal such as 0 volt is applied, the FET is turned off. When the first through FET 12 is on and the second through FET 22 is off, the terminal A-B conducts and the transmission mode is set. In the reverse case, the terminals A-C are turned on to enter the reception mode.

  In this specific example, the booster circuit 30 is connected only to the power supply terminal of the CMOS inverter 32 connected to the gate of the first through FET 12 connected to the terminal B connected to the transmitter, and the output buffer Output from the CMOS inverter controls the first through FET 12 and the second through FET 22, respectively. An unboosted power supply voltage Vdd is applied to the power supply terminal of the CMOS inverter 36 connected to the second through FET 22. In the reception mode in which the terminal C and the receiver are connected, since the high frequency power from the antenna terminal is small, the necessity for further boosting the high level is relatively small. The reason why the maximum allowable input power can be improved by raising the gate control voltage of the first through FET by the booster circuit 30 will be described in detail later.

  The first through FET 12, the second through FET 22, the gate resistors 10 and 20, and the resistors 14 and 24, for example, are arranged on a semi-insulating GaAs substrate to constitute the compound semiconductor integrated circuit 16. The resistors 14 and 24 connected in parallel between the drain and the source of the FET are arranged to make the drain and the source have the same potential when the FET is turned off, and have sufficiently large impedance as compared with the capacitance when the FET is turned off. . This can be substituted if the drain-source parasitic resistance is a finite value.

  The booster circuit 30, the CMOS inverters 32 and 36, and the decoder circuit 34 are arranged on a silicon substrate to constitute a CMOS integrated circuit 38. The CMOS inverter output terminals F and G from the CMOS integrated circuit 38 are connected to terminals D and E connected to the gate resistance of the compound semiconductor integrated circuit 16 by, for example, conductive parts provided in the package. When the compound semiconductor integrated circuit 16 and the CMOS integrated circuit 38 are mounted in the same package, the antenna switch circuit device can be downsized.

FIG. 2 is a circuit diagram showing an example of the booster circuit 30 used in the antenna switch circuit device according to this example.
The booster circuit 30 includes an oscillation circuit unit 56 and a charge pump circuit unit 58 and is formed on the CMOS integrated circuit 38. The oscillation circuit unit 56 includes a loop circuit of the CMOS inverter 40 connected in series and CMOS inverters 42 and 44 connected thereto. A clock signal φ is generated from the CMOS inverter 42, and a clock signal φ ⁻ is generated from the CMOS inverter 44.

The clock signals φ and φ ⁻ are input to the gate of the NMOSFET 48 connected in series via the capacitor 46. In this case, φ and φ ⁻ are alternately input, and the voltage (Vpp) obtained by boosting is output from the terminal H. Note that each connection point of the NMOSFETs 48 connected in series is connected to the power supply terminal T via diode-connected NMOSFETs 52 and 54. In this way, the charge pump circuit unit 58 is configured. Since the booster circuit 30 in this specific example does not include the voltage control circuit unit, the CMOS integrated circuit 38 can be downsized.

Next, the operation of the booster circuit 30 will be described.
FIG. 3 is an equivalent circuit diagram showing a current path including a booster circuit 30, a CMOS inverter, a through FET, and the like.
The boosted High level signal is supplied to the terminal D on the compound semiconductor integrated circuit 16 through the PMOS on-resistance 60 of the CMOS inverter 32 by the output voltage (Vpp) of the booster circuit 30. This High level signal is supplied to the gate of the first through FET 12 via the gate resistor 10 and injects a gate forward current. At this time, the first through FET 12 is turned on. The input of the CMOS inverter 32 is at a low level.

  On the other hand, since a high level signal is input to the CMOS inverter 36 at this time, the output is a low level signal. Since this Low level signal is applied from the terminal E to the gate via the gate resistor 20, the second through FET 22 is turned off. As a result, a gate reverse current flows out from the terminal E from the gate of the second through FET 22.

  The reverse current is absorbed by the ground via the terminal G of the CMOS integrated circuit 38 and the NMOS on-resistance 66 of the CMOS inverter 36. The gate-n channel forward junction of the first through FET 12 is equivalently represented by a diode 62, and the gate-n channel reverse junction of the second through FET 22 is equivalently represented by a diode 64. This reverse bias current increases exponentially with respect to the absolute value of the reverse bias voltage. The value is orders of magnitude smaller than the forward bias current. Due to such characteristics, the output voltage (Vpp) of the booster circuit 30 is clamped by the diode 64. A desired boosted voltage (Vpp) can be obtained by setting the current supply capability of the booster circuit 30 corresponding to the reverse junction characteristics of the diode 64.

FIG. 4 is a circuit diagram illustrating a booster circuit of a comparative example.
The booster circuit of this comparative example includes an oscillation circuit unit 56, a charge pump circuit unit 58, and a voltage control circuit unit 70. Generally, the charge pump circuit requires a voltage control circuit because the output voltage varies depending on the load impedance. The voltage control circuit unit 70 includes a band gap reference circuit (BGR) 72, an operational amplifier (OP) 74, diode-connected NMOSFETs 78 and 79, and a current control NMOSFET 76. Components similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. Since the voltage control circuit unit 70 has a large area, the CMOS integrated circuit becomes large, and it is difficult to reduce the size of the antenna switch circuit device.

  On the other hand, according to this example, the boosted voltage (Vpp) can be clamped by the gate-n channel reverse junction 64. As a result, the voltage control circuit unit occupying a large area is not necessary, and the antenna switch circuit device can be miniaturized.

  Next, the reason why the maximum allowable voltage and the maximum allowable input power corresponding to the maximum allowable voltage can be improved according to this specific example will be described in detail. Here, HEMT (High Electron Mobility Transisitor) is used as an example of FET. Of course, a GaAs MESFET, a junction FET, or the like may be used, and the material may be InP, GaN, or the like.

In the case of HEMT, the threshold voltage (Vth) is about minus 1 volt, and the high level is about 3.5 volts and the low level is about 0 volt as the gate control potential. In the transmission mode in FIG. 1, the terminal D is 3.5 volts and the terminal E is 0 volts. The first through FET 12 is turned on, and a forward current flows between the gate and the source. The second through FET 22 is turned off, and the reverse gate current (that is, the leakage current) flows out from the gate with the same magnitude. DC potential of the terminal A and terminal B, the potential of the terminal D, a reduced value by the forward gate bias voltage V _F. V _F is because it is almost 0.5 volts, the potential of the terminal A and the terminal B is approximately 3 volts.

  Since the gate-source voltage (Vgs) of the first through FET 12 in the on state is approximately 0.5 volts, (Vgs−Vth) is approximately 1.5 volts. On the other hand, since the gate-source voltage (Vgs) of the second through FET 22 in the off state is approximately minus 3 volts, (Vgs−Vth) is approximately minus 2 volts. In addition, since the resistor 24 is connected between the drain and source of the second through FET 22 in the off state, the terminal C has the same potential as the terminal A and is approximately 3 volts.

  Here, it is assumed that the high-frequency signal is not distorted in the on-state FET. On the other hand, in the FET in the off state, there is a maximum voltage amplitude that can maintain the off state, and this will be referred to as a maximum allowable voltage.

FIG. 5 is a schematic cross-sectional view of a HEMT that is an example of a through FET.
The gate (G) -source (S) and the gate (G) -drain (D) have the same structure, the capacitance is the same, and the voltage between the drain (D) -source (S) in the off state is the same. Assume that one half is applied between the gate (G) and the source (S). A high-frequency signal is applied to the high-purity GaAs layer 208 and the n-type AlGaAs layer 210 of the FET in the off state. However, because of the high resistance, high frequency signals cannot pass.

  When the high frequency amplitude gradually increases and the peak voltage Vp exceeds 2 volts, which is the absolute value of the DC potential of (Vgs−Vth), the high frequency current starts to flow near the peak and cannot be said to be in the OFF state. Between the drain (D) and the source (S), the peak voltage Vp is 4 volts at this time (8 volts at the peak-peak). When the maximum permissible voltage is 4 volts, the maximum permissible input power, which is the power when supplied to a load impedance of 50Ω, can be considered to be about 22 dBm.

  With this maximum allowable input power of 22 dBm, it has become difficult to satisfy high system requirements. That is, in GSM800 or the like, the transmitter output is required to be about 35 dBm. This corresponds to Vp of approximately 18 volts in terms of voltage. In order to improve this, there are a first method using a multi-stage FET or a multi-gate FET, a second method in which the gate control voltage is made higher than the system power supply voltage, and a third method using both of them. is there. The first specific example mainly relates to the second method, and the maximum allowable input power can be improved by making the gate control voltage higher than 3.5 volts by the booster circuit. Further, a CMOS integrated circuit incorporating a booster circuit that does not include a voltage control circuit having a large area enables a small antenna switch circuit device with improved maximum allowable input power.

FIG. 6 is an equivalent circuit diagram showing an antenna switch circuit device according to a second specific example.
In this specific example, a series circuit of a first shunt FET 91 and a DC cut capacitor 84 is arranged in parallel between the terminal B and the ground. Similarly, a series circuit of the second shunt FET 90 and the DC cut capacitor 82 is arranged in parallel between the terminal C and the ground. The gate of the first shunt FET 91 is connected to the gate resistor 89 and further connected to the terminal E, and is controlled by the same gate signal as that of the second through FET 22. Similarly, the gate of the second shunt FET 90 is connected to the gate resistor 88 and further connected to the terminal D and controlled by the same gate signal as that of the first through FET 12.

  The FET and the resistor are all formed in the compound semiconductor integrated circuit 16. The merit of the second specific example is that, for example, leakage of a high-frequency signal that occurs when the second shunt FET 22 is off can be dropped to the ground via the second shunt FET 90 that is on. That is, the isolation between the terminal A and the terminal C can be improved, and the separation between the transmitter and the receiver becomes more complete. Further, the impedance when the switch circuit is viewed from the terminal C can be reduced. Components similar to those in FIG. 1 are denoted by the same reference numerals and detailed description thereof is omitted. By forming the shunt FET, the resistor, and the DC cut capacitor in the compound semiconductor integrated circuit 16, it is possible to reduce the size. Of course, the shunt FET may be arranged even when the shunt FET is not shown in the following specific examples.

FIG. 7 is an equivalent circuit diagram showing an antenna switch circuit device according to a third specific example.
In this specific example, the output voltage (Vpp) of the booster circuit 30 is connected to the power supply terminals of the CMOS inverters 32 and 36, and the output from the CMOS inverter as the output buffer is the first through FET 12 and the first through FET 12, respectively. The gate of the 2-through FET 22 is controlled. In this way, since the gate control voltage of any through FET can be boosted, the maximum allowable input power can be improved in any FET. Components similar to those in FIG. 1 are denoted by the same reference numerals and detailed description thereof is omitted.

FIG. 8 is an equivalent circuit diagram showing an antenna switch circuit device according to a fourth specific example.
In this specific example, a low-pass filter 31 for removing a ripple present in the booster circuit 30 is provided, and the gate voltage can be controlled with high accuracy. Components similar to those in FIG. 1 are denoted by the same reference numerals and detailed description thereof is omitted.

FIG. 9 is an equivalent circuit diagram showing an antenna switch circuit device according to a fifth specific example.
In this specific example, the through FET is a triple gate FET, and gate resistors 101, 102, 103 and 109, 110, 111 are connected to each of them. The number of gates is not limited to three, and may be appropriately selected according to demand. Further, a single gate FET may be connected in series. In any case, in terms of an equivalent circuit, a single gate FET can be connected in series, so that the maximum allowable input power can be improved. Therefore, in this specific example, the maximum allowable input power can be further improved by the third method in combination with the introduction of the booster circuit 30. By using a triple gate FET and raising the gate control voltage to about 6 volts, for example, a maximum allowable input power of about 35 dBm corresponding to GSM800 can be obtained. It should be noted that the same components as those in FIG.

FIG. 10 is a circuit diagram showing an antenna switch circuit device according to a sixth specific example.
In this specific example, a first shunt FET 122 having an NMOSFET structure, a second shunt FET 130 having an NMOSFET structure, and DC cut capacitors 120 and 128 are formed on a CMOS integrated circuit 38. The first shunt FET 122 is connected to the terminal L, and the second shunt FET 130 is connected to the terminal N on the CMOS integrated circuit 3. A terminal K connected to the terminal B and a terminal M connected to the terminal C are provided on the compound semiconductor integrated circuit 16. Terminals L, F, G, and H provided on the CMOS integrated circuit 38 are connected to terminals K, D, E, and M provided on the compound semiconductor integrated circuit 16 and a conductive portion provided on the package. It is connected.

  The second shunt FET 130 is turned on or off by the same gate control signal as the first through FET 12, and the first shunt FET 122 is turned off or turned on complementarily by the second through FET 22 by the same gate control signal. . As a result, terminal A is connected to either terminal B or terminal C.

  This specific example is different from the second specific example illustrated in FIG. 6 in that the shunt FET and the DC cut capacitors 120 and 128 are formed on the CMOS integrated circuit 38. In general, in compound semiconductor integrated circuits, it is difficult to increase the diameter of a wafer and the productivity of the manufacturing process is inferior. Therefore, the mass productivity of large area chips is insufficient. On the other hand, the manufacturing process of the CMOS integrated circuit is extremely productive. Therefore, mass production is easy even with a large-area chip. As a result, the entire antenna switch circuit device can be downsized, the mass productivity can be further improved, and the price can be reduced. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 11 is an equivalent circuit diagram of an SP4T switch circuit device according to a seventh specific example.
In the compound semiconductor integrated circuit 16, four through FETs 105, 113, 140, and 142 are formed. The four through FETs are all triple gates. The terminal A connected to the antenna is connected to any one of the transmitter and the receiver through any one of the four through FETs. The CMOS integrated circuit 38 includes a booster circuit 30, a second decoder circuit 144, and an output circuit unit 150.

  The second decoder circuit 144 generates four input signals from the signals from the terminals P and Q by an OR circuit and a CMOS inverter. The output circuit unit 150 includes a CMOS inverter 148, a booster circuit 30, and the like. Outputs from the CMOS inverter are connected to terminals R, F, G, and S, respectively. Further, the gates of the FETs are connected to terminals U, D, E, and W, respectively. Terminals R, F, G, and S provided in the CMOS integrated circuit 38 are respectively connected to terminals U, D, E, and W provided in the compound semiconductor integrated circuit 16 through a conductive portion of the package.

  Any one of the outputs (terminals R, F, G, S) from the CMOS inverter 148 is set to the high level, and any one of the four through FETs 105, 113, 140, 142 is turned on. Further, the remaining three of the CMOS inverters 148 are set to the Low level, and the remaining through FETs are turned off. As a result, the SP4T switch operates.

  Also in this specific example, by mounting the compound semiconductor integrated circuit 16 including the triple gate FET and the CMOS integrated circuit 38 including the second decoder circuit or the like in one package, the maximum allowable input power is improved and the size is reduced. An SPnT antenna switch circuit device can be realized.

  In the above, the form of this invention was demonstrated, referring a specific example. However, the present invention is not limited to these specific examples. For example, the compound semiconductor material is not limited to GaAs, and various III-V compound semiconductors such as InP-based and GaN-based semiconductors, II-VI group compound semiconductors, and the like may be used.

  In addition, even if those skilled in the art have made various design changes regarding the shape, size, material, arrangement relationship, etc. of each element such as FET, DC cut capacitor, resistor, decoder control circuit, booster circuit, CMOS inverter, As long as it has the gist of the present invention, it is included in the scope of the present invention.

It is an equivalent circuit diagram of the antenna switch circuit device concerning the 1st example of implementation of the present invention. It is an equivalent circuit diagram showing the booster circuit in the first specific example. It is an equivalent circuit diagram showing the current path from the booster circuit in the first specific example. It is an equivalent circuit diagram showing the booster circuit of the comparative example. It is a schematic cross section of FET which comprises the antenna switch circuit device concerning the example of this invention. It is an equivalent circuit schematic of the antenna switch circuit device concerning the 2nd example of the present invention. It is an equivalent path | route figure of the antenna switch circuit apparatus concerning the 3rd example of this invention. It is an equivalent circuit schematic of the antenna switch circuit device concerning the 4th example of the present invention. It is an equivalent circuit schematic of the antenna switch circuit device concerning the 5th example of the present invention. It is an equivalent circuit schematic of the antenna switch circuit device concerning the 6th example of the present invention. It is an equivalent circuit schematic of the antenna switch circuit device concerning the 7th example of the present invention.

Explanation of symbols

12 1st through FET
16 Compound Semiconductor Integrated Circuit 22 Second Through FET
30 Booster circuit 31 Low-pass filter 32, 36 CMOS inverter 34 Decoder circuit 38 CMOS integrated circuits 40, 42, 44 CMOS inverters 48, 50, 52, 54 NMOSFET
56 Oscillating circuit 58 Charge pump circuit 60 PMOS on-resistance 62 Gate-n-channel forward junction 64 Gate-n-channel reverse junction 66 NMOS on-resistance 70 Voltage control circuit 72 Band gap reference circuit 74 Operational amplifiers 78 and 79 NMOSFET
90 Second Shunt FET
91 1st shunt FET
140 3rd through FET
142 4th Through FET
144 Second decoder circuit 150 Output circuit 152, 154, 156 CMOS inverter 200 Source electrode 202 Gate electrode 204 Drain electrode 206 GaAs substrate 208 High-purity GaAs layer 210 n-type AlGaAs layer

Claims (5)

A first terminal connected to the antenna;
A compound semiconductor integrated circuit including a plurality of through FETs connected to the first terminal;
A CMOS integrated circuit including a decoder circuit, a booster circuit, and a plurality of CMOS inverters to which signals from the decoder circuit are input;
With
The booster circuit is connected to the power supply terminal of the first CMOS inverter of the plurality of CMOS inverters, and the first of the plurality of through FETs is controlled by a high level control signal from the first CMOS inverter. The first through FETs of the plurality of through FETs are turned on by a low level control signal output from a CMOS inverter different from the first CMOS inverter of the plurality of CMOS inverters. A first mode for transmitting a signal from the first through FET to the first terminal by turning off all but the FET; and
One of the plurality of through FETs is turned on by a high level control signal from a CMOS inverter other than the first CMOS inverter among the plurality of CMOS inverters, and a low level control is performed from another CMOS inverter. A second mode in which a signal from the first terminal is transmitted through the turned-on through FET by turning off all other through-FETs by a signal;
Selectively run,
In at least one of the first and second modes, the output circuit of the booster circuit is clamped based on the reverse current between the gate and the channel of the through FET that has been turned off. apparatus. Including the two through FETs and the two CMOS inverters;
2. The antenna switch circuit device according to claim 1, wherein the booster circuit is connected only to one of the power supply terminals of the two CMOS inverters. Including the two through FETs and the two CMOS inverters;
2. The antenna switch circuit device according to claim 1, wherein the booster circuit is connected to any power supply terminal of the two CMOS inverters.   The antenna switch according to any one of claims 1 to 3, wherein the through FET is configured by a plurality of single gate FETs having drains and sources connected in cascade or a multi-gate FET. Circuit device. The antenna switch circuit device according to claim 1, wherein the output voltage of the booster circuit is supplied via a low-pass filter.

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