JPS62248015A - Stabilizing constant-voltage circuit - Google Patents

Stabilizing constant-voltage circuit

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Publication number
JPS62248015A
JPS62248015A JP9118186A JP9118186A JPS62248015A JP S62248015 A JPS62248015 A JP S62248015A JP 9118186 A JP9118186 A JP 9118186A JP 9118186 A JP9118186 A JP 9118186A JP S62248015 A JPS62248015 A JP S62248015A
Authority
JP
Japan
Prior art keywords
current
circuit
comparator
current source
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9118186A
Other languages
Japanese (ja)
Inventor
Yoichiro Minami
南 洋一郎
Katsuharu Kimura
克治 木村
Susumu Uriya
瓜屋 晋
Shigeaki Ashida
芦田 茂昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9118186A priority Critical patent/JPS62248015A/en
Publication of JPS62248015A publication Critical patent/JPS62248015A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To reduce the current consumption by connecting a current limiting circuit in parallel to a comparator current source, releasing the battery saving, and thereafter, increasing a current only for a prescribed time and shortening the rise time. CONSTITUTION:A comparator circuit consists of transistors Q1-Q4 and a resistance R1 being a comparator current source, and a stabilizing constant-voltage circuit is constituted of a two-stage constitution with an emitter ground amplifier consisting of a transistor Q5 and a resistance R2. Also, to the resistance R1 of the output source of the comparator circuit, a current control circuit consisting of an npn transistor Q6 to whose base a control signal CONT is inputted is connected in parallel. In this state, by varying a current IEE by the signal CONT, a current is increased only for a prescribed time after the battery saving has been released, a capacitive load is charged quickly and an output voltage is raised in a short time, and thereafter, the current is decreased. In this way, the power consumption can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は安定化定電圧回路に関し、特に容量性負荷を有
し、出力トランジスタにPNP )ランノスタを有し、
低電圧動作の選択呼出受信機に搭載される半導体集積回
路に適する安定化定電圧回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a stabilized constant voltage circuit, and in particular has a capacitive load, a PNP (PNP) runnostar as an output transistor,
The present invention relates to a stabilizing constant voltage circuit suitable for a semiconductor integrated circuit installed in a selective call receiver operating at a low voltage.

〔従来の技術〕[Conventional technology]

近年この種の安定化定電圧回路の搭載される半導体集積
回路が実装される選択呼出受信機は、受信機の小型化、
低価格化、低消費電流化が極めて重要な課題である。特
に電池1本で長期間にわたって動作させることが必要で
あシ、消費電流を減小上ぜふ六−めに1源を周期的に接
断させることによシ、受信動作を間けつに行っている。
In recent years, selective call receivers equipped with semiconductor integrated circuits equipped with this type of stabilizing voltage regulator have become smaller and smaller.
Lower prices and lower current consumption are extremely important issues. In particular, it is necessary to operate for a long period of time with a single battery, and in order to reduce the current consumption, it is possible to perform reception operations intermittently by periodically disconnecting and disconnecting one power source. ing.

(このことを以降パンテリーセービングと称する)。(This is hereinafter referred to as pantry saving).

このバッテリーセービングを行なうことによシ消費電流
の低減になるが、そのために安定化定電圧回路の出力電
圧を短時間で安定に立ち上げ供給する必要がある。また
安定化定電圧回路の出力には大きな容量性負荷がつく場
合が多いために、出力電圧を短時間で立ち上げることの
大きな妨げとなる。
By performing this battery saving, the current consumption is reduced, but for this purpose, it is necessary to stably raise and supply the output voltage of the stabilizing voltage regulator circuit in a short time. Furthermore, since a large capacitive load is often attached to the output of the stabilizing voltage regulator, it becomes a major hindrance to raising the output voltage in a short time.

従来のこの種の安定化定電圧回路は容量性負荷を短時間
で立ち上げるために、出力段PNPトランジスタを。
Conventional stabilizing voltage regulator circuits of this type use a PNP transistor in the output stage in order to start up the capacitive load in a short time.

1、 半導体集積回路(IC)に搭載せずに高い電流増
幅率(hFE)を得られる個別トランジスタにしていた
1. Individual transistors were used to obtain a high current amplification factor (hFE) without being mounted on a semiconductor integrated circuit (IC).

1)、  バー モイカルPNP (V−PNP ) 
)ランノスタにしてICに搭載していた。
1), Ver Moical PNP (V-PNP)
) It was installed in the IC as a runnostar.

3、 ラテラルPNP (L−PNP) トランジスタ
にしていた。ただし安定化定電圧回路に含まれるコンパ
レータの差動対電流源に大きな電流を流せるようにして
、 L −PNP トランジスタの低いhFEのために
起る。出力L −PNP l−ランジスタのベース電流
増加に対応していた。
3. It was a lateral PNP (L-PNP) transistor. However, this occurs due to the low hFE of the L-PNP transistor, which allows a large current to flow through the differential pair current source of the comparator included in the stabilizing constant voltage circuit. The output L-PNP corresponds to an increase in the base current of the transistor.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の安定化定電圧回路は 前記1の場合2選択呼出受は機において小型化は重要な
問題であシ、外付はトランジスタを用いることは小型化
に大きな障害である。
In the above-mentioned conventional stabilizing constant voltage circuit, miniaturization is an important problem in the case of 2-select call receiving machine, and the use of external transistors is a major obstacle to miniaturization.

前記第2の場合、 V −PNP トランジスタを用い
ることによシ集積回路化における製造プロセスの工程数
増加更に歩留まシ低下が起こp、ICがコスト高となり
低価格化を阻むものとなシ問題である。
In the second case, the use of V-PNP transistors increases the number of steps in the manufacturing process for integrated circuits, lowers the yield, and increases the cost of ICs, which hinders price reductions. That's a problem.

前記3の場合、小型化、低価格化に関しては問題となら
ない。
In the case of 3 above, there is no problem regarding miniaturization and cost reduction.

しかし、 L −PNPは1,2の場合と比較して。However, L-PNP compared to the case of 1 and 2.

hFEが低いために、容量性負荷を短時間で立ち上げる
ためには、安定化定電圧回路のコンパレータ差動対に流
す電流を前述のように考えられるベース電流増加分だけ
増加する必要があり、消費電流が増加するという欠点が
ある。上記欠点を第2図を用いて説明する。
Because hFE is low, in order to start up the capacitive load in a short time, it is necessary to increase the current flowing through the comparator differential pair of the stabilizing voltage regulator circuit by the amount of the increase in base current considered as described above. This has the disadvantage that current consumption increases. The above drawbacks will be explained using FIG. 2.

第2図に示すように従来回路は+Q1〜Q4及びR,か
らなるコンパレータ回路と+ Qs s R2から成る
エミッタ接地増幅器の2段構成になっていた。ここで1
.は定電流源である。
As shown in FIG. 2, the conventional circuit has a two-stage configuration including a comparator circuit consisting of +Q1 to Q4 and R, and a common emitter amplifier consisting of +QssR2. Here 1
.. is a constant current source.

基準電圧回路1によシ作られた基準電圧Viにより■2
はvz=v1となり、出力電圧■oはVo = R2I
f +V2    −−(1)と表わされる。R2をI
C内部でトリミングすることにより出力電圧を任意に設
定している。
■2 due to the reference voltage Vi created by the reference voltage circuit 1
becomes vz=v1, and the output voltage ■o is Vo = R2I
It is expressed as f +V2 --(1). R2 to I
The output voltage is arbitrarily set by trimming inside the C.

この回路において電源が投入された場合、出力電圧V。When the power is turned on in this circuit, the output voltage V.

の立ち上がり時間はコンデンサCIの充電特性で決定さ
れる。充電時間は次式になる。
The rise time of is determined by the charging characteristics of capacitor CI. The charging time is given by the following formula.

ここでvl=0.85■、vBF、□=0.65v、R
1=500Ω。
Here, vl=0.85■, vBF, □=0.65v, R
1=500Ω.

CI=47μF r Vo=1−05 V r %Bp
Np) ” 25とするとt=5ms、■EE=400
μAとなる。
CI=47μF r Vo=1-05 V r %Bp
Np) ” 25, t=5ms, ■EE=400
It becomes μA.

負荷によるコンパレータ差動対のバイアスオフセットに
ついて考える。ここで起るバイアスオフセットはそのま
ま出力電圧V、に表われるために。
Let us consider the bias offset of the comparator differential pair due to the load. This is because the bias offset that occurs here appears directly in the output voltage V.

出力電圧変動を±10 rnVに押えるためには、負荷
電流IL=1mAで 無負荷で■。=Icl=工。2とするとトナシエ。。=
 2I、=100μ八へ度でよい。従来回路では立ち上
がシの充電特性を改善するためにバッテリーセービング
解除後常時300μAも多く電流を流している必要があ
った。
In order to suppress the output voltage fluctuation to ±10 rnV, load current IL = 1 mA and no load. =Icl=engineering. If it's 2, it's Tonashie. . =
2I, = 100μ8 degrees. In the conventional circuit, in order to improve the charging characteristics at startup, it was necessary to constantly flow as much as 300 μA of current after canceling battery saving.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によると、差動対とコンパレータ差動対から成る
コンパレータ回路と、該コンパレータ回路の出力端子に
接続される増巾器とを含み、前記コン7ぐレータ雷賠涯
に梼捗されふ1疏制御回路を有することを特徴とする安
定化定電圧回路が得られる。
According to the present invention, the present invention includes a comparator circuit consisting of a differential pair and a comparator differential pair, and an amplifier connected to the output terminal of the comparator circuit. A stabilized constant voltage circuit characterized by having a channel control circuit is obtained.

〔実施例〕〔Example〕

次に本発明の1実施例を第1図を用いて詳細に説明する
Next, one embodiment of the present invention will be described in detail with reference to FIG.

第1図は本発明の一実施例の回路図を示し。FIG. 1 shows a circuit diagram of an embodiment of the present invention.

Ql−Q4及びR1から成るコンパレータ回路とQ51
R2からなるエミッタ接地増幅器の2段構成で安定化定
電圧回路は成り、コンパレータ回路のQl  、Q2の
エミッタに接続された抵抗R3とその他端にコレクタで
接続し、ベースに制御信号C0NTが入力するようにし
たNPN トランジスタQ6から成る電流制御回路を有
している。ここで制御信号C0NTはバッテリーセービ
ングが解除されてから30 mSの間高電位である信号
であるとする。
Comparator circuit consisting of Ql-Q4 and R1 and Q51
A stabilizing constant voltage circuit consists of a two-stage configuration of a common emitter amplifier consisting of R2, and the collector is connected to Ql of the comparator circuit, the resistor R3 connected to the emitter of Q2, and the other end, and the control signal C0NT is input to the base. It has a current control circuit consisting of an NPN transistor Q6. Here, it is assumed that the control signal C0NT is a signal that remains at a high potential for 30 mS after battery saving is canceled.

まず、バッテリーセービングが解除され基準電圧が立ち
上がり同時に制御信号が高電位になシQ6がオン状態と
なる。
First, battery saving is canceled and the reference voltage rises. At the same time, the control signal becomes high potential and Q6 is turned on.

この状態で流れる電流工EF、は 以下余白 ここでV。E(SAT)はトランジスタQ6の飽和電圧
である。
The electric current EF flowing in this state is V here in the margin below. E(SAT) is the saturation voltage of transistor Q6.

R3に適当な値を選ぶことによ5 C0NT信号が高電
位の間だけ■。正を大きく立ち上が逆時間全従来回路と
同等とし、消費電流を低減できる。
By choosing an appropriate value for R3, 5 ■ only while the C0NT signal is at high potential. The positive and negative rise times are all equal to those of conventional circuits, and current consumption can be reduced.

次に具体的な数値を示す。Specific figures are shown below.

(2) 、 (5)式より CI ”=47 AF + vo=1.05 V t 
hpE(pNp) ”” 25 +VCE(SAT)=
50 mV I VBg t =o、65 V r R
3=500Ω。
From formulas (2) and (5), CI''=47 AF + vo=1.05 V t
hpE(pNp) ”” 25 +VCE(SAT)=
50 mV I VBg t = o, 65 V r R
3=500Ω.

V1= 0.85 V 、 Rt = 2 kΩとする
とI g E =400 μA + t =5 rnS
となシ、消費電流を立ち上げ時のみ400μAに増加し
て通常は100μAで動作させることによシ消費電流を
300μA減少できる。
When V1 = 0.85 V and Rt = 2 kΩ, I g E = 400 μA + t = 5 rnS
Furthermore, by increasing the current consumption to 400 μA only at startup and normally operating at 100 μA, the current consumption can be reduced by 300 μA.

次に他の実施例を第3図、第4図を用いて説明する。Next, another embodiment will be explained using FIG. 3 and FIG. 4.

第3図は第1図における。差動対電流源抵抗R1をトラ
ンジスタQ6に代えたもので前記トランジスタQ6と並
列に立ち上げ時の電流制御用のトランジスタQ7を有し
ている。トランジスタQ7はトランジスタQa  、Q
s抵抗R4よシ成る定電流源により制御信号C0NTが
低レベルの時に動作状態になシI。を増加させる。
FIG. 3 is similar to FIG. 1. The differential pair current source resistor R1 is replaced with a transistor Q6, and a transistor Q7 for current control during startup is provided in parallel with the transistor Q6. Transistor Q7 is transistor Qa, Q
A constant current source consisting of a resistor R4 causes the device to enter the operating state when the control signal C0NT is at a low level. increase.

制御信号C0NTが高レベルの時はQ7は動作したラン
ジスタQ6の電流のみで決まる。
When the control signal C0NT is at a high level, Q7 is determined only by the current of the activated transistor Q6.

以上のように、制御信号により 工1.Eを変化させる
ことによシアパンテリーセービング解除時のみ電流を増
加させ立ち上げ時間の短縮をはかる。このことにより常
時”EEに大きな電流を流す必要がなく消費電流を低減
できる。
As mentioned above, the control signal causes the operation 1. By changing E, the current is increased only when the shield pantries saving is canceled, thereby shortening the start-up time. This eliminates the need for a large current to flow through EE all the time, reducing current consumption.

第4図は第1図の差動対電流源抵抗R1をR1とR5の
直列接続に代えて、R1の両端に電流制御用のスイクチ
ングトランノスタQllのコレクタ・エミッタを接続し
たものである。制御信号が高レベルの時Qllはオンす
るために、R1は無視することができIEEEはR5で
決まること′になる。
In Figure 4, the differential pair current source resistor R1 in Figure 1 is replaced with a series connection of R1 and R5, and the collector-emitter of a switching trannoctor Qll for current control is connected to both ends of R1. . Since Qll is turned on when the control signal is at a high level, R1 can be ignored and IEEE is determined by R5.

制御信号C0NTが低レベルの場合tQstのエミッタ
・コレクメ間は高インピーダンスになるために工EEは
R1+R5で決定されることになる。
When the control signal C0NT is at a low level, the impedance between the emitter and collector of tQst becomes high, so that the current EE is determined by R1+R5.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、コンパレータの電流源に
並列に電流制御回路を入れることによりパンテリーセー
ビング解除後一定時間のみ電流を増加させて容量性負荷
を急速充電し出力電圧を短時間で立ち上げ、その後は電
流を減らすことによシ、消費電流を減らすことができる
効果がある。
As explained above, the present invention increases the current only for a certain period of time after pantry saving is canceled by inserting a current control circuit in parallel with the current source of the comparator, rapidly charging the capacitive load, and increasing the output voltage in a short time. By increasing the current and then decreasing the current, it is effective to reduce the current consumption.

特に選択呼出受信機のように小型化、低価格化。In particular, selective calling receivers are becoming smaller and cheaper.

低消費電流化が必要である装置に実装されるICにおい
ては出力トランジスタがICに内蔵されL −PNPを
用いて立ち上げ時間゛を短縮するための消費電流の増加
を大幅に押えることが可能であり。
In ICs that are mounted in devices that require low current consumption, the output transistor is built into the IC and the increase in current consumption can be significantly suppressed by using L-PNP to shorten startup time. can be.

効果が犬である。The effect is a dog.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の安定化定電圧回路の一実施例の回路図
、第2図は従来回路の一例の回路図、第3図、第4図は
本発明の他の実施例の回路図である。 Ql”Qtt・・・トランジスタr R1”” R5・
・・抵抗。 C,・・・コンデンサ、1・・・基準電圧回路。 第1図 第2図
FIG. 1 is a circuit diagram of one embodiment of the stabilizing voltage regulator circuit of the present invention, FIG. 2 is a circuit diagram of an example of a conventional circuit, and FIGS. 3 and 4 are circuit diagrams of other embodiments of the present invention. It is. Ql"Qtt...transistor r R1"" R5.
··resistance. C,... Capacitor, 1... Reference voltage circuit. Figure 1 Figure 2

Claims (4)

【特許請求の範囲】[Claims] (1)差動対とコンパレータ電流源から成るコンパレー
タ回路と、該コンパレータ回路の出力端子に接続される
増巾器とを含み、前記コンパレータ電流源に接続される
電流制御回路を有することを特徴とする安定化定電圧回
路。
(1) A comparator circuit comprising a differential pair and a comparator current source, an amplifier connected to an output terminal of the comparator circuit, and a current control circuit connected to the comparator current source. Stabilized constant voltage circuit.
(2)コンパレータ電流源としての電流源用抵抗と並列
に接続される抵抗とトランジスタの直列回路および前記
トランジスタのベースに接続された電流制御回路を有す
る特許請求の範囲第(1)項記載の安定化定電圧回路。
(2) The stability according to claim (1), comprising a series circuit of a resistor and a transistor connected in parallel with a current source resistor serving as a comparator current source, and a current control circuit connected to the base of the transistor. Constant voltage circuit.
(3)コンパレータ電流源としての電流源用抵抗と直列
に接続された電流制御用抵抗と、該電流制御用抵抗の両
端にコレクタ・エミッタを接続しベースを電流制御用端
子としたトランジスタを有する特許請求の範囲第(1)
項記載の安定化定電圧回路。
(3) A patent that includes a current control resistor connected in series with a current source resistor serving as a comparator current source, and a transistor whose collector and emitter are connected to both ends of the current control resistor and whose base is the current control terminal. Claim No. (1)
Stabilizing constant voltage circuit as described in section.
(4)第1の電流源を有し前記電流源と並列に第2の電
流源と、前記第2の電流源を断続する制御回路を有する
特許請求の範囲第(1)項記載の安定化定電圧回路。
(4) Stabilization according to claim (1), which has a first current source, a second current source in parallel with the current source, and a control circuit that connects and connects the second current source. Constant voltage circuit.
JP9118186A 1986-04-22 1986-04-22 Stabilizing constant-voltage circuit Pending JPS62248015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9118186A JPS62248015A (en) 1986-04-22 1986-04-22 Stabilizing constant-voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9118186A JPS62248015A (en) 1986-04-22 1986-04-22 Stabilizing constant-voltage circuit

Publications (1)

Publication Number Publication Date
JPS62248015A true JPS62248015A (en) 1987-10-29

Family

ID=14019282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9118186A Pending JPS62248015A (en) 1986-04-22 1986-04-22 Stabilizing constant-voltage circuit

Country Status (1)

Country Link
JP (1) JPS62248015A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029914U (en) * 1988-06-30 1990-01-23
EP0433724A2 (en) * 1989-12-20 1991-06-26 International Business Machines Corporation Voltage regulator with power boost system
JP2002026260A (en) * 2000-07-04 2002-01-25 Mitsubishi Electric Corp Semiconductor device
JP2008287307A (en) * 2007-05-15 2008-11-27 Ricoh Co Ltd Overcurrent protection circuit and electronic equipment comprising the overcurrent protection circuit
JP2010252441A (en) * 2009-04-13 2010-11-04 Powerchip Technology Corp Control circuit for boosting circuits
WO2011104933A1 (en) * 2010-02-25 2011-09-01 シャープ株式会社 Bias circuit, lna, lnb, receiver for communication, transmitter for communication, and sensor system
JP2011176760A (en) * 2010-02-25 2011-09-08 Sharp Corp Bias circuit, lna, lnb, receiver for communication, transmitter for communication, and sensor system
JP4800433B1 (en) * 2010-08-27 2011-10-26 シャープ株式会社 Bias circuit, LNA, and LNB

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029914U (en) * 1988-06-30 1990-01-23
EP0433724A2 (en) * 1989-12-20 1991-06-26 International Business Machines Corporation Voltage regulator with power boost system
JP2002026260A (en) * 2000-07-04 2002-01-25 Mitsubishi Electric Corp Semiconductor device
JP2008287307A (en) * 2007-05-15 2008-11-27 Ricoh Co Ltd Overcurrent protection circuit and electronic equipment comprising the overcurrent protection circuit
JP2010252441A (en) * 2009-04-13 2010-11-04 Powerchip Technology Corp Control circuit for boosting circuits
WO2011104933A1 (en) * 2010-02-25 2011-09-01 シャープ株式会社 Bias circuit, lna, lnb, receiver for communication, transmitter for communication, and sensor system
JP2011176760A (en) * 2010-02-25 2011-09-08 Sharp Corp Bias circuit, lna, lnb, receiver for communication, transmitter for communication, and sensor system
CN102771047A (en) * 2010-02-25 2012-11-07 夏普株式会社 Bias circuit, LNA, LNB, receiver for communication, transmitter for communication, and sensor system
TWI449326B (en) * 2010-02-25 2014-08-11 Sharp Kk Bias circuit, LNA, LNB, communication receiver, communication transmitter and sensing system
CN102771047B (en) * 2010-02-25 2014-12-03 夏普株式会社 Bias circuit, LNA, LNB, receiver for communication, transmitter for communication, and sensor system
JP4800433B1 (en) * 2010-08-27 2011-10-26 シャープ株式会社 Bias circuit, LNA, and LNB

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