JP2007266143A - 不揮発性半導体記憶装置及びその製造方法 - Google Patents
不揮発性半導体記憶装置及びその製造方法 Download PDFInfo
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Abstract
【解決手段】本発明の不揮発性半導体記憶装置は、電気的に書き換え可能な複数のメモリセルが直列に接続された複数のメモリストリングスを有する不揮発性半導体記憶装置であって、前記メモリストリングスは、柱状半導体と、前記柱状半導体の周りに形成された第1の絶縁膜と、前記第1の絶縁膜の周りに形成された電荷蓄積層と、前記電荷蓄積層の周りに形成された第2の絶縁膜と、前記第2の絶縁膜の周りに形成された第1乃至第nの電極(nは2以上の自然数)とを有しており、前記メモリストリングスの前記第1乃至第nの電極と、別の前記メモリストリングスの前記第1乃至第nの電極とは、それぞれ、2次元的に広がる第1乃至第nの導電体層であることを特徴している。
【選択図】図1
Description
まず、本実施形態に係る一つのメモリストリングス10のメモリトランジスタMTr1mn〜MTr4mnにおける「読み出し動作」、「書き込み動作」及び「消去動作」について図3を参照しながら説明する。なお、「読み出し動作」及び「書き込み動作」については、メモリトランジスタMTr3mnを例にとって説明している。
メモリトランジスタMTr3mnからのデータの読み出し時には、ビット線BLmにVbl(例えば0.7V)、ソース線SLに0V、選択ゲート線SGD及びSGSにVdd(例えば3.0V)、P−Well領域にVPW(例えば0V)を印加する。そして、読み出したいビット(MTr3mn)が接続されているワード線WL3を0Vとし、それ以外のワード線WLをVread(例えば、4.5V)に設定する。これにより、読み出したいビット(MTr3mn)のしきい値Vthが0Vより大きいか小さいかで、ビット線BLmに電流が流れるかどうかが決まるため、ビット線BLmの電流をセンスすることによってビット(MTr3mn)のデータ情報を読み出すことが可能となる。なお、同様の動作によって他のビット(メモリトランジスタMTr1mn、MTr2mn、MTr4mn)のデータを読み出すことができる。
メモリトランジスタMTr3mnにデータ“0”を書き込む場合、即ち、メモリトランジスタMTr3mnの電荷蓄積層に電子を注入してメモリトランジスタのしきい値を上げる(しきい値を正の方向にシフトさせる)場合は、BLmに0V、ソース線SLにVdd、選択ゲート線SGDnにVdd(例えば3.0V)、選択ゲート線SGSにVoff(例えば0V)、P−Well領域にVPW(例えば0V)を印加し、書き込みたいビット(MTr3)のワード線WL3をVprog(例えば18V)、それ以外のワード線WLをVpass(例えば10V)とすることで、所望ビット(MTr3mn)のみ電荷蓄積層に印加される電界強度が強くなり電荷蓄積層に電子が注入され、メモリトランジスタMTr3mnのしきい値が正の方向にシフトする。
データの消去時には、複数のメモリストリングス10からなるブロック単位でメモリトランジスタMTr1mn〜MTr4mnのデータの消去を行う。
図6は、本実施形態に係る本発明の不揮発性半導体記憶装置1において、点線で示したメモリトランジスタMTr321のデータの読み出し動作を行う場合のバイアス状態を示した図である。ここでも、本実施形態におけるメモリトランジスタMTrは、半導体11と電荷蓄積層として機能する絶縁膜(酸化珪素膜、窒化珪素膜、酸化珪素膜の積層膜)と導電体層(本実施形態においてはポリシリコン層)とからなる所謂MONOS型縦型トランジスタであり、電荷蓄積層に電子が蓄積されていない状態のメモリトランジスタMTrのしきい値Vth(中性しきい値)が0V付近にあるとして説明する。
図7は、本実施形態に係る本発明の不揮発性半導体記憶装置1において、点線で示したメモリトランジスタMTr321のデータの書き込み動作を行う場合のバイアス状態を示した図である。
データの消去時には、複数のメモリストリングスからなるブロック単位でメモリトランジスタMTrのデータの消去を行う。図8は、本実施形態に係る本発明の不揮発性半導体記憶装置1において、選択したブロックのメモリトランジスタMTrのデータの消去動作を行う場合のバイアス状態を示した図である。
本実施形態に係る本発明の不揮発性半導体記憶装置1の消去動作シミュレーションの設定条件及び結果を図10〜図13に示す。
本実施形態に係る本発明の不揮発性半導体記憶装置1の鳥瞰図を図17に示す。本実施形態に係る本発明の不揮発性半導体記憶装置1は、半導体基板上にメモリトランジスタが積層された構造を有している。メモリトランジスタが積層されている領域(メモリトランジスタ領域)においては、メモリトランジスタの積層数に関係なく、5回のフォトエッチングプロセス(3回のクリティカルPEP、及び2回のラフPEP)によって製造することが可能である。
本実施形態においては、図45〜図77を用いて本発明の不揮発性半導体記憶装置の別の例について、その製造プロセスを説明する。なお、図45〜図77においては、実施形態1と同様、左側にワード線ドライバ回路やセンスアンプ回路等の周辺回路が形成される周辺回路領域を示し、右側にメモリトランジスタ領域を示し、メモリトランジスタ領域においては、領域Aの部分、領域Bの部分、X−X’及びY−Y’の断面に相当する部分を図示している。
本実施形態においては、本発明の不揮発性半導体記憶装置の電荷蓄積層にナノ結晶膜を含む膜を用いる。例えば、電荷蓄積層を、酸化珪素膜、ナノ結晶膜、酸化珪素膜の積層構造とする。ナノ結晶膜としては、シリコンのナノ結晶を含む酸化珪素膜を用いることができる。本実施形態に係る不揮発性半導体記憶装置においては、このナノ結晶膜中に離散分布したシリコンのナノ結晶に電荷が保持される。
本実施形態においては、本発明の不揮発性半導体記憶装置のメモリトランジスタ領域の構成の別の例について説明する。なお、その他の構成については、上述の実施形態1、2及び3と同様であるので、ここでは、改めて説明しない。
2 メモリトランジスタ領域
3 ワード線駆動回路
4 ソース側選択ゲート線(SGS)駆動回路
5 ドレイン側選択ゲート線(SGD)駆動回路
6 センスアンプ
10 メモリストリングス
11 柱状の半導体層
12 絶縁膜
13a〜13f 電極
14 P=型領域(P−Well領域)
15 N+領域15
100 半導体基板
102a、102b、102c、102d、102e104 STI
104 P−well領域
106a、106b チャネルインプラ領域
106c n+拡散領域
108a及び108b フォトレジストマスク
110a、110b ゲート電極
112a、112b、112c及び112d 浅いN型領域
114a、114b、114c、114d サイドウォール
116a、116b、116c、116d ソース/ドレイン領域
118 窒化珪素膜
120 BPSG膜
122a及び122b コバルトシリサイド
124 BPSG膜
126 ポリシリコン膜
132a、132b、132c 熱酸化膜
134 窒化珪素膜
136a、136b シリコン膜
138 フォトレジスト
140a、140b チタンシリサイド
142 酸化珪素膜
144a、144b、144c タングステンプラグ
146a及び146b 配線
148 酸化珪素膜
150、154、158、162、166 ポリシリコン膜
152、156、160、164 酸化珪素膜
168 窒化珪素膜
170 メモリプラグホール
172 ONO膜
174 フォトレジスト
176 酸化珪素膜
178 窒化珪素膜
180 柱状のアモルファスシリコン層
182 層間絶縁膜(BPSG)
187 酸化珪素膜
188a、188b、188c188d、188e タングステンプラグ
196a、196b タングステンプラグ
200 半導体基板
202a、202b、202c、202d、202e STI
204 P−well領域
206a、206b チャネルインプラ領域
208 濃いn+領域
210 BPSG膜
210 酸化珪素膜
212 ポリシリコン膜
214 窒化珪素膜
216、216b フォトレジストマスク
218 ポリシリコン膜
218a、218b ゲート電極
220a、220b、220c、220d 浅いN型領域
222a、222b、222c、222d サイドウォール
224a、224b、224c、224d サイドウォール
226 窒化珪素膜
228 BPSG膜
230 酸化珪素膜
232a、232b、232c コンタクトホール
234a、234b、234c タングステン(W)プラグ
238、242、246、250 ポリシリコン膜
238、242、246、250 ポリシリコン膜
240、244、248、252 酸化珪素膜
246a、246b、 ポリシリコン膜
248 酸化珪素膜
250a、250c、242a ポリシリコン膜
250c、246b、242a、238 ポリシリコン膜
252 酸化珪素膜
254、254a、254b フォトレジストマスク
256 BPSG膜
262 メモリプラグホール
264 TEOS膜
266 アモルファスシリコン膜
270 ONO膜
277,272a アモルファスシリコン膜
274、274a TEOS膜
282a、282b、282c、282d、282e、282f、282g コンタクトホール
284a、284b、284c、284d、284e、284f、284g タングステンプラグ
320a、322a、324a、326 導電体層
330a、332a、334a、336a 導電体層
330a〜330j、 導電体層
330c、332c、334c、336c 導電体層
330e、332e、334e、336e 導電体層
330g、332g、334g、336g 導電体層
330i、332i、334i、336i 導電体層
336a〜336j 導電体層
340a、340b、340c、340d 窒化珪素膜
BLm ビット線
SL ソース線
MTr1mn〜MTr4mn メモリトランジスタ
SSTrmn、SDTrmn 選択トランジスタ
Claims (50)
- 電気的に書き換え可能な複数のメモリセルが直列に接続された複数のメモリストリングスを有する不揮発性半導体記憶装置であって、
前記メモリストリングスは、柱状半導体と、前記柱状半導体の周りに形成された第1の絶縁膜と、前記第1の絶縁膜の周りに形成された電荷蓄積層と、前記電荷蓄積層の周りに形成された第2の絶縁膜と、前記第2の絶縁膜の周りに形成された第1乃至第nの電極(nは2以上の自然数)とを有しており、
前記メモリストリングスの前記第1乃至第nの電極と、別の前記メモリストリングスの前記第1乃至第nの電極とは、それぞれ、2次元的に広がる第1乃至第nの導電体層であることを特徴とする不揮発性半導体記憶装置。 - 前記2次元的に広がる第1乃至第nの導電体層は、それぞれ、板状の導電体層であることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記複数のメモリストリングスは、前記柱状半導体に垂直な面内にマトリクス状に配置されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記2次元的に広がる第1乃至第nの導電体層は、それぞれ、絶縁体を介して積層されており、前記前記2次元的に広がる第1乃至第nの導電体層内に前記複数のメモリストリングスがアレイ状に配置されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記電荷蓄積層は、絶縁膜であることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記第1の絶縁膜は、酸化珪素膜であり、前記電荷蓄積層は、窒化珪素膜であり、且つ前記第2の絶縁膜は、酸化珪素膜であることを特徴とする請求項5に記載の不揮発性半導体記憶装置。
- 前記柱状半導体は、円柱又は角柱であることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記柱状の半導体は、半導体基板に垂直に形成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスの前記第1乃至第nの電極を形成する導電体層は、端部において階段状に形成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記電荷蓄積層は、前記柱状半導体と前記メモリストリングスの前記第1乃至第nの電極との間に局在することを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記電荷蓄積層は、導電体であることを特徴とする請求項10に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスは、前記メモリストリングスの一端に接続された第1のトランジスタと、前記メモリストリングスの他端に接続された第2のトランジスタとを含むことを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記第1のトランジスタのゲート電極同士は、同一導電層によって形成されていることを特徴とする請求項12に記載の不揮発性半導体記憶装置。
- 前記第1のトランジスタのソースが接続されている前記半導体基板の拡散層の部分は、n−型であり、且つn+拡散層に直接接続されていることを特徴とする請求項12に記載の不揮発性半導体記憶装置。
- 前記第1のトランジスタのソースが接続されている前記半導体基板の拡散層の部分は、p−型であり、且つp+拡散層に直接接続されていることを特徴とする請求項12に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスのソースは、素子分離層が形成されていないことを特徴とする請求項4に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスのソースは、別の前記メモリストリングスのソースと素子分離層により電気的に絶縁されていることを特徴とする請求項16に記載の不揮発性半導体記憶装置。
- 前記柱状半導体は、n−型半導体であることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記複数のメモリセルは、ディプレション型のトランジスタであることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 更に、前記半導体基板の前記拡散層の上に絶縁膜を介してポリシリコンを備え、前記柱状半導体は、前記ポリシリコンと前記半導体基板上の前記n+拡散層の両方と接続していることを特徴とする請求項14に記載の不揮発性半導体記憶装置。
- 前記電荷蓄積層は、ナノ結晶を含む膜を有することを特徴とする請求項1に記載の不揮発性半導体記憶装置
- 前記メモリストリングスは、前記柱状半導体の中心軸に対して概略対称形状を有することを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスの前記第1乃至第nの電極は、それぞれ、ワード線であり、前記メモリストリングスの前記第1乃至第nの電極は、それぞれ、同一のワード線駆動回路によって駆動されることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記複数のメモリストリングスのドレインに接続されたビット線は、それぞれ、同一のセンスアンプに接続されていることを特徴とする請求項23に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスの前記第1乃至第nの電極のそれぞれの間には、第4の絶縁膜が形成されており、
前記メモリストリングスの前記第1乃至第nの電極及び前記第4の絶縁膜の端部は、階段状に形成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 前記メモリストリングスの前記第1乃至第nの電極のそれぞれの間には、第4の絶縁膜が形成されており、
前記メモリストリングスの前記第1乃至第nの電極及び前記第4の絶縁膜の端部は、階段状に形成されている端部と階段状に形成されていない端部とを含むことを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 半導体基板上に導電性不純物の拡散領域を形成し、
前記半導体基板上に第1の絶縁膜と導電体とを交互に複数形成し、
前記複数の第1の絶縁膜と前記導電体とに複数のホールを形成し、
前記ホールの表面に第2の絶縁膜を形成し、
前記ホールの底部にある前記第2の絶縁膜をエッチングし、
前記ホールに柱状半導体を形成することを特徴とする不揮発性半導体記憶装置の製造方法。 - 前記複数の導電体によって第1乃至第nの電極が形成され、
前記柱状半導体、並びに交互に形成された複数の前記第2の絶縁膜及び前記第1乃至第nの電極によって、電気的に書き換え可能な複数のメモリセルが直列に接続されたメモリストリングスを形成することを特徴とする請求項27に記載の不揮発性半導体記憶装置の製造方法。 - 前記複数のメモリストリングスは、前記柱状半導体に垂直な面内にマトリクス状に配置されていることを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記複数の導電体は、それぞれ、2次元的に広がっており、前記複数の導電体層に前記複数のメモリストリングスがアレイ状に配置されていることを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記第2の絶縁膜は、電荷蓄積層を含むことを特徴とする請求項27に記載の不揮発性半導体記憶装置の製造方法。
- 前記第2の絶縁膜は、酸化珪素膜、窒化珪素膜及び酸化珪素膜が順に積層されてなることを特徴とする請求項27に記載の不揮発性半導体記憶装置の製造方法。
- 前記柱状半導体は、円柱又は角柱であることを特徴とする請求項27に記載の不揮発性半導体記憶装置の製造方法。
- 前記柱状の半導体は、前記半導体基板に垂直に形成されていることを特徴とする請求項27に記載の不揮発性半導体記憶装置の製造方法。
- 前記メモリストリングスの前記第1乃至第nの電極を形成する導電体層は、端部において階段状に形成されていることを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記メモリストリングスは、前記メモリストリングスの一端に接続された第1のトランジスタと、前記メモリストリングスの他端に接続された第2のトランジスタとを含むことを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記第1のトランジスタのゲート電極同士は、同一導電層によって形成されていることを特徴とする請求項36に記載の不揮発性半導体記憶装置の製造方法。
- 前記第1のトランジスタのソースが接続されている前記半導体基板の拡散層の部分は、n−型であり、且つ前記半導体基板のn+型の拡散層に直接に接続されていることを特徴とする請求項36に記載の不揮発性半導体記憶装置の製造方法。
- 前記第1のトランジスタのソースが接続されている前記半導体基板の拡散層の部分は、n−型であり、且つ前記半導体基板のn+型の拡散層に直接に接続されていることを特徴とする請求項36に記載の不揮発性半導体記憶装置の製造方法。
- 前記複数のメモリストリングスのソース間は、素子分離層が形成されていないことを特徴とする請求項30に記載の不揮発性半導体記憶装置の製造方法。
- 前記メモリストリングスのソースは、別の前記メモリストリングスのソースと素子分離層により電気的に絶縁されていることを特徴とする請求項40に記載の不揮発性半導体記憶装置の製造方法。
- 前記柱状半導体は、n−型半導体であることを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記複数のメモリセルは、ディプレション型のトランジスタであることを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 更に、前記半導体基板の前記拡散層の上に絶縁膜を介してポリシリコンを備え、前記柱状半導体は、前記ポリシリコンと前記半導体基板上の前記n+拡散層の両方と接続していることを特徴とする請求項39に記載の不揮発性半導体記憶装置の製造方法。
- 前記電荷蓄積層は、ナノ結晶を含む膜を有することを特徴とする請求項31に記載の不揮発性半導体記憶装置の製造方法。
- 前記メモリストリングスは、前記柱状半導体の中心軸に対して概略対称形状を有することを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記メモリストリングスの前記第1乃至第nの電極は、それぞれ、ワード線であり、前記メモリストリングスの前記第1乃至第nの電極は、それぞれ、同一のワード線駆動回路によって駆動され、且つ、前記メモリストリングスの前記第1乃至第nの電極は、同一のセンスアンプに接続されていることを特徴とする請求項28に記載の不揮発性半導体記憶装置の製造方法。
- 前記複数のメモリストリングスのドレインに接続されたビット線は、それぞれ、同一のセンスアンプに接続されていることを特徴とする請求項47に記載の不揮発性半導体記憶装置の製造方法。
- 前記メモリストリングスの前記第1乃至第nの電極及び前記第1の絶縁膜の端部を階段状に加工する工程を含むことを特徴とする請求項28に記載の不揮発性半導体記憶装置。
- 前記メモリストリングスの前記第1乃至第nの電極及び第1の絶縁膜を前記半導体基板に対して水平方向に分離する工程を含むことを特徴とする請求項49に記載の不揮発性半導体記憶装置の製造方法。
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JP2006086674A JP5016832B2 (ja) | 2006-03-27 | 2006-03-27 | 不揮発性半導体記憶装置及びその製造方法 |
US11/654,551 US7936004B2 (en) | 2006-03-27 | 2007-01-18 | Nonvolatile semiconductor memory device and manufacturing method thereof |
CNB2007100884708A CN100550392C (zh) | 2006-03-27 | 2007-03-27 | 非易失性半导体存储器件及其制造方法 |
KR1020070029906A KR100884861B1 (ko) | 2006-03-27 | 2007-03-27 | 비휘발성 반도체 메모리 장치 및 그의 제조 방법 |
US13/064,559 US8551838B2 (en) | 2006-03-27 | 2011-03-31 | Nonvolatile semicondutor memory device and manufacturing method thereof |
US13/198,359 US9064735B2 (en) | 2006-03-27 | 2011-08-04 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US14/724,853 US9748260B2 (en) | 2006-03-27 | 2015-05-29 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US15/666,653 US10211219B2 (en) | 2006-03-27 | 2017-08-02 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US16/245,271 US10916559B2 (en) | 2006-03-27 | 2019-01-11 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US17/141,534 US11374021B2 (en) | 2006-03-27 | 2021-01-05 | Manufacturing method of a nonvolatile semiconductor memory device |
US17/141,504 US11362106B2 (en) | 2006-03-27 | 2021-01-05 | Manufacturing method of a nonvolatile semiconductor memory device |
US17/744,571 US11903205B2 (en) | 2006-03-27 | 2022-05-13 | Method for reading data of a first memory cell transistor of a nonvolatile semiconductor memory device |
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US20190148404A1 (en) | 2019-05-16 |
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JP5016832B2 (ja) | 2012-09-05 |
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US7936004B2 (en) | 2011-05-03 |
US9748260B2 (en) | 2017-08-29 |
US8551838B2 (en) | 2013-10-08 |
US20220328517A1 (en) | 2022-10-13 |
CN100550392C (zh) | 2009-10-14 |
US11362106B2 (en) | 2022-06-14 |
US20110284947A1 (en) | 2011-11-24 |
US11903205B2 (en) | 2024-02-13 |
CN101055875A (zh) | 2007-10-17 |
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