USRE46785E1 - Nonvolatile semiconductor memory device and method for driving same - Google Patents
Nonvolatile semiconductor memory device and method for driving same Download PDFInfo
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- USRE46785E1 USRE46785E1 US14/992,650 US201614992650A USRE46785E US RE46785 E1 USRE46785 E1 US RE46785E1 US 201614992650 A US201614992650 A US 201614992650A US RE46785 E USRE46785 E US RE46785E
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Definitions
- Embodiments described herein relate generally to a nonvolatile semiconductor memory device and method for driving the same.
- Semiconductor memory devices of flash memory and the like conventionally have been constructed by two-dimensionally integrating memory cells on the surface of a silicon substrate. In such a semiconductor memory device, it is necessary to increase the integration of the memory cells to reduce the cost per bit and increase the storage capacity. However, such increases of integration in recent years have become difficult in regard to both cost and technology.
- a collectively patterned three-dimensionally stacked memory for instance, refer to JP-A 2007-266143 (Kokai)
- a stacked body including electrode films alternately stacked with insulative films is formed on a silicon substrate; and subsequently, through-holes are made in the stacked body by collective patterning.
- a blocking film, a charge storage film, and a tunneling film are deposited in this order to form a memory film on the side face of the through-hole; and a silicon pillar is buried in the interior of the through-hole.
- a memory transistor is thereby formed at an intersection between each electrode film and the silicon pillar.
- a charge can be removed from and put into the charge storage layer from the silicon pillar to store information by controlling an electrical potential of each electrode film and each silicon pillar.
- the through-holes are made by collectively patterning the stacked body. Therefore, the number of lithography processes does not increase and cost increases can be suppressed even in the case where the number of stacks of the electrode films increases.
- FIG. 1 is a diagram of features of a nonvolatile semiconductor memory device according to a first embodiment
- FIG. 2 is a perspective view of the nonvolatile semiconductor memory device according to the first embodiment
- FIG. 3 is a cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment
- FIG. 4 is a circuit diagram of a memory string of the nonvolatile semiconductor memory device according to the first embodiment
- FIG. 5 is a plan view of electrode films of the nonvolatile semiconductor memory device according to the first embodiment
- FIG. 6 is a circuit diagram of a drive circuit of the nonvolatile semiconductor memory device according to the first embodiment
- FIG. 7 is a diagram of potentials applied to each electrode and interconnections during operations of the nonvolatile semiconductor memory device according to first embodiment
- FIG. 8 is a diagram of potentials applied to control gate electrodes of each level during operations of the nonvolatile semiconductor memory device according to the first embodiment
- FIG. 9 is a graph of a method for determining a potential to be applied, where the diameter of a through-hole is plotted on the horizontal axis and the potential difference between a control gate electrode and a silicon pillar is plotted on the vertical axis;
- FIG. 10 a diagram of features of a nonvolatile semiconductor memory device according to a second embodiment
- FIG. 11 is a cross-sectional view of processes of a method for manufacturing a nonvolatile semiconductor memory device according to a third embodiment
- FIG. 12 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment
- FIG. 13 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment
- FIG. 14 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment
- FIG. 15 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment
- FIG. 16 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment
- FIG. 17 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment.
- FIG. 18 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment.
- FIG. 19 is a cross-sectional view of processes of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment.
- a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit.
- the stacked body is provided on the substrate.
- the stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films.
- a through-hole is made in the stacked body to align in a stacking direction.
- the semiconductor pillar is buried in an interior of the through-hole.
- the charge storage film is provided between the electrode film and the semiconductor pillar.
- the drive circuit supplies a potential to the electrode film.
- the diameter of the through-hole differs by a position in the stacking direction.
- the drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
- FIG. 1 schematically illustrates features of a nonvolatile semiconductor memory device according to this embodiment.
- FIG. 2 is a perspective view illustrating the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 3 is a cross-sectional view illustrating the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 4 is a circuit diagram illustrating a memory string of the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 5 is a plan view illustrating electrode films of the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 6 is a circuit diagram illustrating a drive circuit of the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 1 and FIG. 2 For easier viewing of the drawings in FIG. 1 and FIG. 2 , only the conductive portions are illustrated, and the insulating portions are omitted. This is similar for FIG. 10 described below.
- the silicon pillars are illustrated with the same thickness regardless of the Z-direction position.
- a feature of a nonvolatile semiconductor memory device 1 is that a drive circuit 41 supplying a driving potential to a control gate electrode CG applies the driving potential to reduce the potential difference with a silicon pillar 31 as a diameter of a through-hole piercing the control gate electrode CG decreases in a collectively patterned three-dimensionally stacked memory device in which memory transistors are provided at intersections between the silicon pillar 31 and the control gate electrodes CG. More specifically, in the nonvolatile semiconductor memory device 1 , the diameter of the through-hole in which the silicon pillar 31 is buried decreases as the control gate electrode CG is disposed in a lower level. Therefore, the drive circuit 41 applies a lower driving potential to the control gate electrode CG disposed in a lower level.
- a silicon substrate 11 is provided in the nonvolatile semiconductor memory device 1 (hereinbelow, also referred to as “the device 1 ”) according to this embodiment.
- the peripheral circuit region is disposed around the memory cell region.
- a feature of the memory cell region is that a stacked body ML, in which memory cells are arranged three-dimensionally, is provided.
- the diameter of a through-hole 21 piercing the stacked body ML becomes finer downward.
- An insulating film 10 is provided on the silicon substrate 11 in the memory cell region. Thereupon, a conductive film, e.g., a polysilicon film 12 , is formed to form a back gate BG. Multiple electrode films 14 are alternately stacked with multiple insulating films 15 on the back gate BG; and the stacked body ML is formed.
- a conductive film e.g., a polysilicon film 12
- an XYZ orthogonal coordinate system In this coordinate system, two mutually orthogonal directions parallel to an upper face of the silicon substrate 11 are taken as an X direction and a Y direction. A direction orthogonal to both the X direction and the Y direction, that is, the stacking direction of each layer, is taken as a Z direction.
- the electrode film 14 is formed of, for example, polysilicon. In an X-direction central portion of the stacked body ML, the electrode film 14 is divided along the Y direction to form multiple control gate electrodes CG aligned in the X direction. Each layer of the electrode films 14 is patterned into the same pattern as viewed from above, i.e., the Z direction. As described below, at both X-direction end portions of the stacked body ML, the electrode film 14 is not divided along the Y direction to form one pair of comb-shaped configurations.
- the insulating films 15 are made of, for example, silicon oxide (SiO 2 ) and function as inter-layer insulating films to insulate the electrode films 14 from each other.
- the conductive film 17 is made of, for example, polysilicon, is divided along the Y direction, and forms multiple selection gate electrodes SG aligned in the X direction.
- Two selection gate electrodes SG are provided in the region directly above each of the control gate electrodes CG of the uppermost layer. That is, although the selection gate electrode SG is aligned in the same direction (the X direction) as the control gate electrode CG, the arrangement period is half.
- the selection gate electrodes SG include a selection gate electrode SGb on the bit line side and a selection gate electrode SGs on the source line side.
- An insulating film 19 is provided on the insulating film 18 .
- a source line SL is provided on the insulating film 19 to align in the X direction.
- the source line SL is disposed in a region directly above every other one of the control gate electrodes CG of the uppermost layer arranged along the Y direction.
- An insulating film 20 is provided on the insulating film 19 to cover the source line SL.
- Multiple bit lines BL are provided on the insulating film 20 to align in the Y direction.
- Each of the source lines SL and the bit lines BL are formed of a metal film.
- the configuration of the through-hole 21 is, for example, circular as viewed from the Z direction.
- the side face of the through-hole 21 inclines with respect to the perpendicular direction; and the through-hole 21 becomes finer downward.
- Each of the through-holes 21 pierces the control gate electrode CG of each of the levels; and the lower end reaches the back gate BG.
- the through-holes 21 are arranged in a matrix configuration along the X direction and the Y direction.
- control gate electrode CG is aligned in the X direction, multiple through-holes 21 arranged in the X direction pierce the same control gate electrode CG.
- the arrangement period of the through-holes 21 in the Y direction is half the arrangement period of the control gate electrodes CG. Thereby, two of the through-holes 21 arranged in the Y direction form one set; and the through-holes 21 belonging to the same set pierce the same control gate electrode CG.
- a communicating hole 22 is made in an upper layer portion of the back gate BG so that the lower end portion of one through-hole 21 communicates with the lower end portion of one other through-hole 21 distal one row in the Y direction as viewed from the one through-hole 21 .
- one continuous U-shaped hole 23 is made of one pair of the through-holes 21 adjacent to each other in the Y direction and the communicating hole 22 communicating between the pair.
- Multiple U-shaped holes 23 are made in the stacked body ML.
- An ONO (Oxide Nitride Oxide) film 24 is provided on an inner face of the U-shaped hole 23 via a barrier film (not illustrated) made of, for example, silicon nitride.
- a barrier film made of, for example, silicon nitride.
- an insulative blocking film 25 is stacked in order from the outside.
- the blocking film 25 is a film in which current substantially does not flow even when a voltage in the range of the drive voltage of the device 1 is applied and is formed of, for example, a high dielectric constant material having a dielectric constant higher than the dielectric constant of the material forming the charge storage film 26 , e.g., silicon oxide.
- the charge storage film 26 is a film capable of trapping charge and is formed of, for example, silicon nitride.
- the tunneling film 27 normally is insulative, the tunneling film 27 is a film in which a tunneling current flows when a prescribed voltage in the range of the drive voltage of the device 1 is applied and is formed of, for example, silicon oxide.
- the film thickness of the ONO film 24 is substantially uniform over the entire region on the inner face of the U-shaped hole 23 .
- a semiconductor material doped with an impurity e.g., polysilicon
- an impurity e.g., polysilicon
- a U-shaped silicon member 33 is provided in the interior of the U-shaped hole 23 .
- the portion of the U-shaped silicon member 33 positioned in the through-hole 21 forms the silicon pillar 31 ; and the portion positioned in the communicating hole 22 forms a connection member 32 .
- the silicon pillar 31 has a columnar configuration, e.g., a circular columnar configuration, aligned in the Z direction.
- the diameter of the through-hole 21 becomes finer downward. Therefore, the diameter of the silicon pillar 31 filled into the interior thereof also becomes finer downward.
- connection member 32 has a columnar configuration, e.g., a quadrilateral columnar configuration, aligned in the Y direction.
- Two of the silicon pillars 31 and one of the connection members 32 are formed integrally to form the U-shaped silicon member 33 . Accordingly, the U-shaped silicon member 33 is formed continuously without breaks along the longitudinal direction thereof.
- the U-shaped silicon member 33 is insulated from the back gate BG and the control gate electrode CG by the ONO film 24 .
- Multiple through-holes 51 are made in the insulating film 16 , the selection gate electrode SG, and the insulating film 18 .
- Each of the through-holes 51 is made in a region directly above each of the through-holes 21 to communicate with each of the through-holes 21 .
- the selection gate electrode SG is aligned in the X direction
- the through-holes 51 arranged in the X direction pierce the same selection gate electrode SG.
- the arrangement period of the through-hole 51 in the Y direction is the same as the arrangement period of the selection gate electrode SG with the same arrangement phase. Accordingly, one of the multiple through-holes 51 arranged in the Y direction corresponds to one of the selection gate electrodes SG; and the multiple through-holes 51 pierce mutually different selection gate electrodes SG.
- a gate insulating film 28 is formed on the inner face of the through-hole 51 .
- Polysilicon for example, is filled into the interior of the through-hole 51 to form a silicon pillar 34 .
- the silicon pillar 34 has a columnar configuration, e.g., a circular columnar configuration, aligned in the Z direction.
- the lower end portion of the silicon pillar 34 is connected to the upper end portion of the silicon pillar 31 formed in a region directly therebelow.
- the silicon pillar 34 is insulated from the selection gate electrode SG by the gate insulating film 28 .
- a U-shaped pillar 30 is formed of the U-shaped silicon member 33 and the pair of silicon pillars 34 connected to the upper end portions thereof.
- the positional relationship among the U-shaped pillar 30 , the control gate electrode CG, the selection gate electrode SG, the source line SL, and the bit line BL will now be described.
- One pair of the silicon pillars 34 and 31 adjacent in the Y direction is connected to each other by the connection member 32 to form the U-shaped pillar 30 .
- the control gate electrode CG, the selection gate electrode SG, and the source line SL are aligned in the X direction; and the bit line BL is aligned in the Y direction.
- the arrangement periods of the U-shaped pillar 30 and the control gate electrode CG in the Y direction are the same, the phases are shifted one half-period.
- one pair of the silicon pillars 31 belonging to each of the U-shaped pillars 30 i.e., the two silicon pillars 31 connected to each other by the connection member 32 , pierces mutually different control gate electrodes CG.
- two silicon pillars 31 mutually adjacent in the Y direction and belonging to two U-shaped pillars 30 mutually adjacent in the Y direction pierce a common control gate electrode CG.
- the multiple silicon pillars 34 arranged in the Y direction pierce mutually different selection gate electrodes SG. Accordingly, one pair of silicon pillars 34 belonging to each of the U-shaped pillars 30 pierces mutually different selection gate electrodes SG. On the other hand, the multiple U-shaped pillars 30 arranged in the X direction pierce a common pair of selection gate electrodes SG.
- One silicon pillar 34 of the pair of silicon pillars 34 belonging to each of the U-shaped pillars 30 is connected to the source line SL via a source plug SP buried in the insulating film 19 ; and one other silicon pillar 34 of the pair is connected to the bit line BL via a bit plug BP buried in the insulating films 19 and 20 . Accordingly, the U-shaped pillar 30 is connected between the bit line BL and the source line SL.
- the selection gate electrode SG pierced by the U-shaped pillar 30 and disposed on the bit line side is illustrated as the selection gate electrode SGb; and the selection gate electrode SG pierced by the U-shaped pillar 30 and disposed on the source line side is illustrated as the selection gate electrode SGs.
- the U-shaped pillars 30 arranged in the X direction are connected to a common source line SL and to mutually different bit lines BL.
- the arrangement period of the U-shaped pillar 30 in the X direction is the same as the arrangement period of the bit line BL. Therefore, in the X direction, the U-shaped pillar 30 and the bit line BL correspond one-to-one.
- two of the U-shaped pillars 30 arranged in the Y direction are connected to each of the source lines SL as one set and are connected to a common bit line BL.
- the silicon pillar 31 functions as a channel and the control gate electrode CG functions as a gate electrode.
- a vertical memory transistor 35 is formed at the intersection between the silicon pillar 31 and the control gate electrode CG.
- Each of the memory transistors 35 functions as a memory cell by the charge storage film 26 disposed between the silicon pillar 31 and the control gate electrode CG storing electrons.
- the multiple silicon pillars 31 are arranged in a matrix configuration along the X direction and the Y direction. Therefore, the multiple memory transistors 35 are arranged three-dimensionally along the X direction, the Y direction, and the Z direction.
- a selection transistor 36 is formed at the intersection between the silicon pillar 34 and the selection gate electrode SG with the silicon pillar 34 as the channel, the selection gate electrode SG as the gate electrode, and the gate insulating film 28 as the gate insulating film.
- the selection transistor 36 is a vertical transistor similar to the memory transistor 35 described above.
- connection member 32 is interposed between the connection member 32 and the back gate BG
- a back gate transistor 37 is formed with the connection member 32 as the channel, the back gate BG as the gate electrode, and the ONO film 24 as the gate insulating film.
- the back gate BG functions as an electrode to control the conducting state of the connection member 32 by an electric field.
- a memory string 38 connected between the bit line BL and the source line SL along each of the U-shaped pillars 30 is formed.
- the selection transistor 36 is provided at both end portions; the back gate transistor 37 is provided in the central portion; and the same number of memory transistors 35 as the number of stacks of the electrode films 14 is connected in series between the back gate transistor 37 and each of the selection transistors 36 .
- the multiple memory transistors 35 arranged three-dimensionally in the stacked body ML may be collected as the memory string 38 for each of the U-shaped silicon members 33 .
- the memory cell region of the device 1 is divided into multiple blocks 50 .
- the positional relationship between the block 50 and each of the conductive members will now be described.
- the multiple blocks 50 set in the memory cell region are arranged along the Y direction.
- the conductive members provided in the device 1 to align in the X direction i.e., the control gate electrode CG and the selection gate electrode SG, and the U-shaped pillar 30 aligned in the Z direction are organized into each of the blocks 50 .
- the back gate BG formed along the XY plane is subdivided and mutually separated electrically from each other for each of the blocks 50 .
- the bit line BL aligned in the Y direction extends to pass through all of the blocks 50 and is common to all of the blocks 50 .
- An element separation film (not illustrated) is formed in a region of the silicon substrate 11 between the blocks 50 .
- control gate electrodes CG belonging to each of the blocks 50 are organized further into two groups.
- the control gate electrodes CG are divided into the control gate electrode CG disposed in a region directly below the source line SL and pierced by the silicon pillar having an upper end portion connected to the source line SL (illustrated as a control gate electrode CGs in FIG. 5 ) and the control gate electrode CG disposed in a region outside of the region directly below the source line SL and pierced by a silicon pillar having an upper end portion connected to the bit line BL (illustrated as a control gate electrode CGb in FIG. 5 ).
- control gate electrodes CGs and the control gate electrodes CGb are alternately arranged along the Y direction; the control gate electrodes CGs are commonly connected to each other; and the control gate electrodes CGb are commonly connected to each other.
- the control gate electrodes CGs are electrically separated from the control gate electrodes CGb.
- the electrode films 14 (referring to FIG. 1 ) are not divided along the Y direction at both of the X-direction end portions of the stacked body ML; and incisions aligned in the X direction are made intermittently.
- the electrode films 14 are subdivided into a pair of mutually meshed comb-shaped patterns to form the control gate electrodes CGs and the control gate electrodes CGb, respectively.
- the control gate electrode CGs has three comb teeth and the control gate electrode CGb has two comb teeth in FIG. 5 to simplify the drawing, this embodiment is not limited thereto, and the number of comb teeth may be higher.
- the peripheral circuit region will now be described.
- the drive circuit 41 is provided in the peripheral circuit region to drive the memory string 38 .
- the drive circuit 41 includes a potential supply unit 42 b that applies a driving potential to the control gate electrode CGb of each of the levels formed in the stacked body ML and the selection gate electrode SGb, a potential supply unit 42 s that applies a driving potential to the control gate electrode CGs of each of the levels and the selection gate electrode SGs, and a decoder 43 that outputs a control signal.
- a pump circuit unit 44 is provided in the potential supply unit 42 b.
- the pump circuit unit 44 includes n pump circuits 45 ( 1 ) to 45 (n), where n is the number of levels of the electrode films 14 .
- Each of the pump circuits 45 is a circuit that increases the supplied voltage by a prescribed amount, where the voltage increase amount is different for each of the pump circuits.
- a switch circuit unit 46 is provided in the potential supply unit 42 b.
- the switch circuit unit 46 includes n switch elements 47 ( 1 ) to 47 (n). One end of a switch element 47 (k) is connected to a pump circuit 45 (k) and the other end is connected to the control gate electrode CGb of the kth level from the bottom of the stacked body ML, where k is an integer from 1 to n. Based on a control signal output by the decoder 43 , the switch element 47 (k) switches to connect or disconnect the pump circuit 45 (k) and the control gate electrode CGb of the kth level from the bottom.
- each of switch elements 47 is formed of a MOSFET; one of the source and drain is connected to the pump circuit 45 ; the other is connected to the control gate electrode CGb; and the gate is commonly connected to an output terminal of the decoder 43 .
- the pump circuit 45 is connected to the control gate electrode CGb only for the interval in which the decoder 43 outputs the prescribed control signal.
- the configuration of the potential supply unit 42 s also is similar to that of the potential supply unit 42 b.
- the potential supply unit 42 s also includes the pump circuit unit 44 and the switch circuit unit 46 ; and each of the switch elements 47 connect each of the pump circuits 45 to each of the control gate electrodes CGs based on a control signal output by the decoder 43 .
- FIG. 7 illustrates the potentials applied to the electrodes and the interconnections during operations of the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 8 illustrates the potentials applied to the control gate electrodes of each of the levels during operations of the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 9 is a graph illustrating a method for determining the potential to be applied, where the diameter of the through-hole is plotted on the horizontal axis and the potential difference between the control gate electrode and the silicon pillar is plotted on the vertical axis.
- the memory transistor 35 is taken to be an n-channel field effect transistor.
- the state in which electrons are stored in the charge storage film 26 and the threshold value is shifted to positive is taken to be the value “0;” and the state in which electrons are not stored in the charge storage film 26 and the threshold value is not shifted is taken to be the value “1.”
- the number of levels (n) of the control gate electrodes is taken to be 4.
- the memory transistor 35 (hereinbelow referred to as “selected cell”) to and from which data is to be written and read is taken to be the memory transistor of the third level from the bottom of the silicon pillar having an upper end portion connected to the bit line BL.
- control gate electrode CGb of the third level from the bottom is the gate electrode of the selected cell. Further, it is taken that in the initial state, electrons are not stored in any of the memory transistors 35 . Accordingly, the value “1” is written thereto.
- writing operations to write any data to each of the memory transistors 35 will be described.
- the writing of the date is performed for one block at a time in order and is performed simultaneously for multiple selected cells arranged in the X direction.
- these multiple selected cells belong to mutually different memory strings 38 , they share the same control gate electrode CG.
- the multiple memory strings 38 to which these selected cells belong are connected to mutually different bit lines BL, the multiple memory strings 38 pierce a common selection gate electrode SG and are connected to a common source line SL.
- the drive circuit 41 applies a selection gate potential V sg to the selection gate electrode SGb of the selected strings and applies an OFF potential V off to the selection gate electrode SGs.
- the drive circuit 41 applies the OFF potential V off to the selection gate electrodes SGb and SGs of the unselected memory strings 38 .
- the OFF potential V off is a potential of the gate electrode of the transistor such that the transistor is switched to the OFF state, e.g., a reference potential Vss.
- the reference potential Vss is, for example, a grounding potential (0 V).
- the selection gate potential V sg is a potential of the selection gate electrode SG of the selection transistor 36 such that the conducting state of the selection transistor 36 is determined by the potential of the silicon pillar (the body potential), e.g., a potential higher than the reference potential Vss.
- the potential of the back gate BG is taken as an ON potential V on .
- the ON potential V on is a potential of the gate electrode of the transistor such that the transistor is switched to the ON state, e.g., a power supply potential Vdd (e.g., 3.0 V).
- the selection transistors 36 on the bit line side of the selected strings are switched to the ON state and the OFF state by the potential of the bit lines BL; and the selection transistors 36 on the source line side are switched to the OFF state. All of the selection transistors 36 of the unselected memory strings 38 are switched to the OFF state. The back gate transistors 37 of all of the memory strings 38 are switched to the ON state.
- the reference potential Vss (e.g., 0 V) is applied to the bit lines BL connected to the selected cells to be written with the value “0;” and the power supply potential Vdd (e.g., 3.0 V) is applied to the bit lines BL connected to the selected cells to be written with the value “1.”
- the power supply potential Vdd is applied to all of the source lines SL.
- the drive circuit 41 increases the potential of the control gate electrode CG of the selected cells, e.g., the control gate electrodes CGb of the third layer from the bottom, to a writing potential V pgm (e.g., 18 V); and the potential of the other control gate electrodes CG, i.e., the control gate electrodes CGb of the layers other than the third layer from the bottom and all of the control gate electrodes CGs, are provided with an intermediate potential V pass (e.g., 10 V).
- V pgm e.g. 18 V
- the writing potential V pgm is applied to the control gate electrodes CGb of the third layer also for the unselected memory strings.
- the writing potential V pgm is a potential high enough to inject electrons from the silicon pillar 31 into the charge storage film 26 of the ONO film 24 , and is a potential higher than the reference potential Vss and the selection gate potential V sg . That is, Vss ⁇ V sg ⁇ V pgm .
- the intermediate potential V pass is a potential higher than the reference potential Vss
- the intermediate potential V pass is a potential lower than the writing potential V pgm . That is, Vss ⁇ V pass ⁇ V pgm .
- the value of the writing potential V pgm differs by the level where the control gate electrode CG to which the potential is to be applied is disposed.
- Vss the reference potential
- V sg a body potential V body of the selected cells approaches the reference potential Vss.
- the potential of the control gate electrodes CG of the selected cells is the writing potential V pgm (e.g., 18 V).
- the difference (V pgm ⁇ V body ) between the gate potential and the body potential of the selected cells is sufficiently large; high-temperature electrons are created by the potential difference; and the electrons are injected from the silicon pillar 31 into the charge storage film 26 via the tunneling layer 27 . Thereby, the value “0” is written into the selected cells.
- the potential of the bit lines BL is the positive potential Vdd (e.g., 3.0 V) and the potential of the selection gate electrode SGb on the bit line side is the selection gate potential V sg which is higher than the reference potential Vss. Therefore, the potential difference between the source potential and the gate potential of the selection transistors 36 on the bit line side is small, and the selection transistors 36 are switched to the OFF state by a back gate effect. Thereby, the silicon pillars 31 are in a floating state and the body potential V body of the selected cells is maintained at a high value by coupling with the control gate electrodes CG provided with the intermediate potential V pass (e.g., 10 V).
- V pgm ⁇ V body the difference between the writing potential V pgm (e.g., 18 V) of the control gate electrode CG of the selected cells and the body potential V body decreases, and electrons are not injected into the charge storage film 26 . As a result, the value “1” is written into the selected cells.
- the potential of the silicon pillars 31 is in the floating state because the selection transistors 36 at both of the end portions are switched to the OFF state.
- the body potential V body of the silicon pillars 31 can be controlled by the potential applied to the control gate electrodes CG, the voltage increase rate thereof, and the potential of the selection gate electrodes SG; and a high potential can be maintained.
- the difference (V pgm ⁇ V body ) between the gate potential and the body potential of the memory transistors 35 decreases, electrons are not injected into the charge storage film 26 , and the initial value is maintained.
- the writing row (the Y coordinate) is selected by controlling the conducting state of the selection transistors, and data is written to the memory strings 38 arranged in the X direction in order by row.
- the potential of the control gate electrodes is controlled by block. Therefore, for the writing disturbance, it is sufficient to consider the total time necessary for writing the data to the memory strings in the block. Thereby, the disturbance time can be controlled by adjusting the block size.
- V pgm potentials having multiple levels can be generated as the writing potential V pgm as illustrated in FIG. 8 .
- the writing potentials V pgm generated by each of the pump circuits 45 can be applied to the control gate electrodes CG of each of the levels by each of the switch elements 47 of the switch circuit unit 46 connecting each of the pump circuits 45 to the control gate electrodes CG of each of the levels based on the control signal output by the decoder 43 .
- the values of the writing potential V pgm can differ by the level where the control gate electrode CG to which the potential is to be applied is disposed.
- the value of the writing potential V pgm applied to a control gate electrode CG 4 of the uppermost level, that is, the 4th level from the bottom, is set to be (V pgm 0 );
- the value of the writing potential V pgm applied to a control gate electrode CG 3 of the third level from the bottom is set to be (V pgm 0 ⁇ V pgm 1 ) which is lower than (V pgm 0 );
- the value of the writing potential V pgm applied to a control gate electrode CG 2 of the 2nd level from the bottom is set to be (V pgm 0 ⁇ V pgm 2 ) which is lower than (V pgm 0 ⁇ V pgm 1 );
- the value of the writing potential V pgm applied to a control gate electrode CG 1 of the lowermost level is set to be (V pgm 0 ⁇ V pgm 3 ) which is lower than (
- the intensity of the electric field applied to the tunneling film 27 increases as the surface area ratio of the inner surface and the outer surface of the charge storage film 26 increases. Therefore, the intensity of the electric field applied to the tunneling film 27 increases as the diameter of the through-hole 21 decreases. Thereby, an electron current due to tunneling may undesirably flow into the tunneling film 27 of the memory transistor 35 to which the value of “0” is to be written; and a miswrite (a program disturbance) may occur in which the mistaken value of “1” is undesirably written.
- the amount of electrons injected from the silicon pillar 31 into the charge storage film 26 may increase for a memory transistor having a small through-hole 21 diameter; and the amount of charge injected into the charge storage film 26 undesirably becomes non-uniform.
- a writing potential V pgm having a lower potential is applied in memory transistors positioned lower and having smaller through-hole 21 diameters.
- the body potential V body of the silicon pillar 31 is a potential near the reference potential Vss. Therefore, the potential difference (V pgm ⁇ V body ) between the control gate electrode CG and the silicon pillar 31 decreases as the memory transistor is disposed lower. Also, the electric field applied to the tunneling film 27 decreases as the potential difference (V pgm ⁇ V body ) decreases.
- the drive circuit 41 applies the writing potential V pgm that is lower as the control gate electrode CG is disposed lower.
- the increase of the electric field intensity caused by smaller through-hole 21 diameters is canceled; and a more uniform electric field intensity can be applied to the tunneling film 27 .
- miswriting program disturbances
- the amount of electrons injected into the charge storage films 26 of the memory transistors 35 during one writing operation can be uniform; and the driving of the memory transistors can be stabilized. Because the amount of the injected electrons is made to be uniform, the writing operation duration of the memory transistors 35 also can be uniform. Thereby, the writing operation duration of the entire device 1 can be reduced; and the operation speed can be increased.
- the intensity of the electric field applied to the tunneling film 27 in one memory transistor can be uniform by determining the value of the writing potential V pgm such that a potential difference V follows Formula 1 recited below, where r ( ⁇ m) is the diameter of the through-hole 21 of the one memory transistor and V is the potential difference (V pgm ⁇ V body ) between the control gate electrode CG and the silicon pillar 31 .
- V is the potential difference (V pgm ⁇ V body ) between the control gate electrode CG and the silicon pillar 31 .
- V i.e., V pgm ⁇ V body
- V the value of the potential difference
- V the value of the potential difference
- V pgm ⁇ V body the value of the potential difference
- Formula 1 recited below provides an effective approximation at least for values of r in the range of 0.05 to 0.1 ⁇ m.
- V 6999.4 ⁇ r 3 ⁇ 1971.3 ⁇ r 2 +194.66 ⁇ r ⁇ 5.0952
- the drive circuit 41 applies the ON potential V on to the back gate BG, and the back gate transistors 37 are switched to the ON state.
- the drive circuit 41 applies the ON potential V on (e.g., 3.0 V) to the selection gate electrodes SGs and SGb of the selected strings, and the selection transistors 36 are switched to the ON state.
- the drive circuit 41 applies the OFF potential V off (e.g., 0 V) to the selection gate electrodes SGs and SGb of the unselected memory strings 38 , and the selection transistors 36 are switched to the OFF state.
- the drive circuit 41 applies a potential to the control gate electrode CG of the selected cells, i.e., the control gate electrode CGb of the third layer from the bottom, such that the conducting state differs due to the value of the selected cells.
- the potential is, for example, the reference potential Vss (e.g., 0 V) and is a potential such that a current does not flow in the body in the case where the value of the selected cell is “0,” i.e., when electrons are stored in the charge storage film 26 and the threshold is shifted to positive, and a current flows in the body in the case where the value of the selected cell is “1,” i.e., when electrons are not stored in the charge storage film 26 and the threshold is not shifted.
- a reading potential V read (e.g., 4.5 V) is applied to the control gate electrodes thereof such that the memory transistors 35 are switched to the ON state regardless of the values thereof.
- a potential Vb 1 (e.g., 0.7 V) is applied to each of the bit lines BL
- the reference potential Vss e.g., 0 V
- a current flows in the selected string if the value of the selected cell is “1” and a current does not flow in the selected string if the value of the selected cell is “0.”
- the value of the selected cell can be read by detecting the current flowing in the source line SL from the bit line BL via the selected string or by detecting the potential drop of the bit line BL.
- the change is amplified by a bit line amplifier circuit (not illustrated) and detected; and the detection result is stored as data in a data buffer (not illustrated).
- a current does not flow regardless of the values stored in the memory transistors 35 because the selection transistors 36 are in the OFF state.
- the drive circuit 41 varies the value of the reading potential V read by the level where the control gate electrode CG to which the potential is to be applied is disposed using the pump circuit 45 .
- the value of the reading potential V read applied to the control gate electrode CG 4 of the uppermost level, i.e., the 4th level from the bottom is set to be (V read 0 );
- the value of the reading potential V read applied to the control gate electrode CG 3 of the third level from the bottom is set to be (V read 0 ⁇ V read 1 ) which is lower than (V read 0 );
- the value of the reading potential V read applied to the control gate electrode CG 2 of the 2nd level from the bottom is set to be (V read 0 ⁇ V read 2 ) which is lower than (V read 0 ⁇ V read 1 );
- the value of the reading potential V read applied to the control gate electrode CG 1 of the lowermost level is set to be (V read 0 ⁇ V read 3 ) which is
- the intensity of the electric field applied to the tunneling film 27 of each of the memory transistors increases as the through-hole 21 diameter decreases.
- the electric field applied to the tunneling film 27 during the reading operation is too strong, electron current undesirably flows in the tunneling film 27 due to tunneling; and a phenomenon (read disturbance) occurs in which the value “0” written to the memory transistor undesirably changes to the value “1.”
- the reading potential V read has a lower potential as the control gate electrode CG is positioned lower with a smaller through-hole 21 diameter.
- the unit of erasing data is by block.
- the drive circuit 41 applies the ON potential V on to the back gate BG, and the back gate transistors 37 are switched to the ON state.
- the reference potential Vss (e.g., 0 V) is applied to all of the control gate electrodes CG of the block to be erased (hereinbelow referred to as “selected block”).
- the potentials of the bit lines BL and the source lines SL are increased to an erasing potential V erase (e.g., 15 V).
- the selection gate potential V sg which is lower than the erasing potential V erase is applied to the selection gate electrodes SGb and SGs. That is, V sg ⁇ V erase .
- the potential of the bit lines BL and the source lines SL is the erasing potential V erase (e.g., 15 V)
- the potential of the selection gate electrodes SGb and SGs is the selection gate potential V sg . Therefore, a hole current is produced by tunneling between bands due to the potential difference between the bit lines BL and the selection gate electrodes SGb and the potential difference between the source lines SL and the selection gate electrodes SGs; and the potential of the silicon pillars 31 , i.e., the body potential, increases.
- the reference potential Vss e.g., 0 V
- the potential of the selection gate electrodes SGb and SGs is increased to a potential approaching the potential of the bit lines BL and the source lines SL, and the electric field between a diffusion layer connected to the bit lines BL or the source lines SL and the selection gate electrodes SGb or SGs is reduced so that a hole current is not produced.
- the potential of the control gate electrodes CG is increased simultaneously with that of the silicon pillars 31 so that holes in the silicon pillars 31 are not injected into the charge storage films 26 . Thereby, the values already written to the memory transistors 35 of the unselected blocks are maintained as-is.
- the drive circuit 41 supplies a higher potential as the reference potential Vss as the control gate electrode CG is disposed lower, the potential difference between the silicon pillar 31 and the control gate electrode CG decreases as the memory transistor is disposed lower; and the electric field applied to the ONO film 24 can be uniform. Thereby, the application of an excessive electric field to the memory transistors having small through-hole diameters and the injection of electrons from the control gate electrode CG into the charge storage film 26 due to tunneling during the erasing operation can be prevented.
- the drive circuit 41 includes the multiple pump circuits 45 ; and each of the pump circuits 45 is connected to the control gate electrodes CG of each of the levels via each of the switch elements 47 .
- mutually different driving potentials can be applied to the control gate electrodes CG of each of the levels.
- the potential difference between the control gate electrode CG and the silicon pillar 31 can be reduced as the memory transistor is positioned lower and has a smaller through-hole 21 diameter; and the electric field intensity applied to the ONO films 24 of the memory transistors can be uniform.
- misoperation of the memory transistor can be prevented.
- Great effects can be obtained by applying such technology to at least one operation selected from the writing operation, the reading operation, and the erasing operation when supplying the potential to the control gate electrode to provide the greatest potential difference with the silicon pillar of the operation.
- FIG. 10 schematically illustrates features of a nonvolatile semiconductor memory device according to this embodiment.
- the through-hole has a two-level configuration. In each level, the through-hole becomes finer downward.
- the stacked body ML is made of two partial stacked bodies ML 1 and ML 2 arranged in the Z direction; and the partial stacked body ML 2 is stacked on the partial stacked body ML 1 .
- Multiple insulating films 15 and multiple electrode films 14 are stacked in each of the partial stacked bodies ML 1 and ML 2 .
- Each of a lower portion 21 a of the through-hole 21 made in the partial stacked body ML 1 and an upper portion 21 b made in the partial stacked body ML 2 have a tapered configuration that becomes finer downward. Therefore, the upper end portion of the lower portion 21 a is wider than the lower end portion of the upper portion 21 b; and a step is formed in the inner face of the through-hole 21 at the boundary portion between the lower portion 21 a and the upper portion 21 b.
- the drive circuit 41 applies potentials to the multiple electrode films 14 disposed in the partial stacked body ML 1 such that the potential difference with the silicon pillar 31 decreases as the electrode film 14 is disposed lower, that is, toward the silicon substrate 11 side. Similarly, the drive circuit 41 applies potentials to the multiple electrode films 14 disposed in the partial stacked body ML 2 such that the potential difference with the silicon pillar 31 decreases as the electrode film 14 is disposed lower.
- the fluctuation of the electric field intensity caused by the fluctuation of the through-hole 21 diameter can be compensated by varying the driving potential; and the electric field intensities applied to the ONO films 24 of the memory transistors 35 can be uniform. As a result, the misoperation of the memory transistor can be prevented. Otherwise, the configuration, operations, and effects of this embodiment are similar to those of the first embodiment described above.
- Three or more levels of partial stacked bodies may be stacked. In such a case, it is sufficient for the drive circuit 41 to apply the potential to the electrode film 14 (the control gate electrode CG) disposed in each of the partial stacked bodies such that the potential difference with the silicon pillar 31 decreases as the electrode film is disposed lower.
- This embodiment is an embodiment of a method for manufacturing the nonvolatile semiconductor memory device 1 according to the first embodiment described above.
- FIG. 11 to FIG. 19 are cross-sectional views of processes, illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment.
- FIG. 11 to FIG. 19 illustrate the same cross section as that of FIG. 3 .
- the silicon substrate 11 is prepared.
- a memory cell region is set in the silicon substrate 11 .
- a peripheral circuit region (not illustrated) is set around the memory cell region.
- An element separation film is formed in a prescribed region of the upper layer portion of the silicon substrate 11 .
- a thick film gate insulating film for high breakdown voltage transistors and a thin film gate insulating film for low breakdown voltage transistors are made separately in the peripheral circuit region.
- the insulating film 10 is formed on the silicon substrate 11 also in the memory cell region.
- the polysilicon film 12 is deposited on the insulating film 10 as a conductive film with a thickness of, for example, 200 nm.
- Photolithography and RIE Reactive Ion Etching
- RIE Reactive Ion Etching
- the trenches 52 are arranged in a matrix configuration along the X direction and the Y direction.
- the trenches 52 are recesses made in the upper face of the polysilicon film 12 .
- a silicon nitride film is deposited by, for example, CVD (Chemical Vapor Deposition) to form a sacrificial film 53 on the polysilicon film 12 .
- the sacrificial film 53 also is filled into the trenches 52 .
- the sacrificial film 53 and the polysilicon film 12 are patterned by, for example, photolithography and RIE.
- the polysilicon film 12 in the memory cell region is divided for every block 50 (referring to FIG. 5 ); the back gates BG made of the polysilicon film 12 are formed in flat-plate configurations in each of the blocks 50 ; and gate electrodes made of the polysilicon film 12 are formed in the peripheral circuit region.
- a spacer made of silicon oxide is formed and a diffusion layer is formed by ion implantation in the peripheral circuit region.
- an inter-layer insulating film is deposited in the peripheral circuit region, planarized, and recessed so that the upper face thereof is the same height as the upper face of the polysilicon film 12 .
- the sacrificial film 53 is recessed so that the sacrificial film 53 is removed from the polysilicon film 12 and left only in the interiors of the trenches 52 .
- the insulating films 15 made of, for example, silicon oxide are deposited alternately with the electrode films 14 made of, for example, polysilicon on the back gate BG (the polysilicon film 12 ) in the memory cell region to form the stacked body ML.
- the multiple through-holes 21 are collectively made in the stacked body ML by dry etching such as RIE to align in the Z direction.
- the through-holes 21 are arranged in a matrix configuration along the X direction and the Y direction. Also, the bottom portions of the through-holes 21 reach both end portions of the sacrificial films 53 filled into the trenches 52 . Thereby, two through-holes 21 adjacent to each other in the Y direction reach each of the sacrificial films 53 .
- the through-hole 21 has a circular configuration as viewed from the Z direction. At this time, the inner side face of the through-hole 21 unavoidably has a tapered configuration inclined with respect to the Z direction. As a result, the through-hole 21 is made in an inverted circular-conic trapezoidal configuration becoming finer downward such that the upper end portion is the widest.
- wet etching is performed via the through-holes 21 to remove the sacrificial film 53 (referring to FIG. 14 ) from the trenches 52 .
- the trench 52 becomes the communicating hole 22 ; and one continuous U-shaped hole 23 is formed of the communicating hole 22 and the two through-holes 21 communicating with both end portions thereof.
- a barrier film (not illustrated) made of, for example, silicon nitride is formed; and subsequently, a silicon oxide film, a silicon nitride film, and a silicon oxide film are continuously deposited.
- the blocking film 25 made of the silicon oxide film, the charge storage film 26 made of the silicon nitride film, and the tunneling film 27 made of the silicon oxide film are stacked in this order on the inner face of the U-shaped hole 23 via the barrier film to form the ONO film 24 .
- amorphous silicon is deposited on the entire surface. Thereby, amorphous silicon is filled into the U-shaped hole 23 to form the U-shaped silicon member 33 .
- the U-shaped silicon member 33 is formed from the pair of silicon pillars 31 filled into the through-holes 21 and the one connection member 32 filled into the communicating hole 22 . Subsequently, the amorphous silicon, the silicon oxide film, the silicon nitride film, and the silicon oxide film deposited on the stacked body ML are removed.
- the stacked body ML is patterned by, for example, RIE to make trenches 54 in the stacked body ML.
- the trench 54 is made to align in the X direction to link the regions between the two silicon pillars 31 connected to the connection member 32 and reach the insulating film 15 of the lowermost layer.
- the trenches 54 are made to divide the electrode films 14 into a pair of mutually meshed comb-shaped patterns.
- the trenches 54 are made in the X-direction central portion of the stacked body ML to align in the X direction.
- the electrode films 14 are divided into multiple control gate electrodes CG aligned in the X direction.
- the trenches 54 are not made in the regions directly above the regions between the connection members 32 in the Y direction.
- each of the control gate electrodes CG is pierced by two of the silicon pillars 31 arranged along the Y direction.
- the trenches 54 are not aligned in the X direction and are made to align intermittently in the Y direction.
- the control gate electrodes CGb and CGs alternately disposed along the Y direction at the X-direction central portion of the stacked body ML have common connections to each other at each of the X-direction end portions of the stacked body ML.
- an insulating film 16 is deposited on the stacked body ML and planarized.
- the insulating film 16 also is filled into the trenches 54 .
- the conductive film 17 made of, for example, amorphous silicon is deposited, etched, and left only in the memory cell region.
- a resist film (not illustrated) is formed, for example, on the conductive film 17 ; and the stacked body ML is patterned into a stairstep configuration by repeatedly performing etching using the resist film as a mask and performing slimming of the resist film.
- both X-direction end portions of the control gate electrodes CG for each level are not covered with the control gate electrodes CG of the level thereabove as viewed from above (the Z direction); and in subsequent processes, contacts can be formed from above to the control gate electrodes CG of each level.
- an etching stopper film made of, for example, silicon nitride is formed to cover the stacked body ML patterned into the stairstep configuration; an inter-layer insulating film (not illustrated) is formed thereupon; and the upper face is planarized. Thereby, the inter-layer insulating film is filled around the stacked body ML.
- the insulating film 18 is formed on the conductive film 17 .
- the through-holes 51 are made to pierce the insulating film 18 , the conductive film 17 , and the insulating film 16 to reach the upper ends of the through-holes 21 in the stacked body ML.
- an insulating film is deposited on the entire surface, and amorphous silicon is deposited. Etch-back is performed on the amorphous silicon and the insulating film to leave the amorphous silicon and the insulating film only in the through-holes 51 . Thereby, the gate insulating film 28 is formed on the inner face of the through-holes 51 and the amorphous silicon is filled. Then, heat treatment is performed at a temperature of, for example, 600° C. to crystallize the amorphous silicon in the through-holes 51 to form polysilicon.
- Ion implantation is performed on the polysilicon using arsenic (As) with, for example, an acceleration voltage of 40 keV and a dose of 3 ⁇ 10 15 cm ⁇ 2 to form a drain diffusion layer (not illustrated).
- As arsenic
- the silicon pillars 34 are formed in the through-holes 51 .
- the silicon pillars 34 connect to the silicon pillars 31 .
- patterning by RIE and the like is performed on the insulating film 18 and the conductive film 17 to make trenches 55 aligned in the X direction in the regions between the silicon pillars 34 adjacent to each other in the Y direction.
- the conductive film 17 is divided along the Y direction to form multiple selection gate electrodes SG aligned in the X direction.
- the insulating film 19 is formed on the insulating film 18 ; source plugs SP are buried in the insulating film 19 ; and the source lines SL are formed on the insulating film 19 to align in the X direction.
- the source lines SL are connected to the drain diffusion layers of some of the silicon pillars 34 via the source plugs SR Contacts (not illustrated) are formed in the inter-layer insulating film (not illustrated) provided around the stacked body ML to connect to each of the control gate electrodes CG and each of the selection gate electrodes SG from above.
- the insulating film 20 is formed on the insulating film 19 to cover the source lines SL.
- bit plugs BP are buried in the insulating films 20 and 19 and the bit lines BL are formed on the insulating film 20 to align in the Y direction.
- the bit lines BL are connected to the drain diffusion layers of the remaining silicon pillars 34 via the bit plugs BP.
- the drive circuit 41 (referring to FIG. 6 ) is formed in the peripheral circuit region by normal methods. Thereby, the nonvolatile semiconductor memory device 1 is manufactured.
- the nonvolatile semiconductor memory device 1 according to the first embodiment described above can be manufactured.
- the drive circuit 41 supplies mutually different potentials to the control gate electrode CG of each of the levels.
- the electric fields applied to the ONO films 24 of the memory transistors 35 are made to be uniform. Therefore, it is unnecessary to make the through-hole 21 diameters to be excessively uniform. Therefore, the aspect ratio of the through-hole 21 can be increased; the number of times that the through-holes 21 are made can be reduced when manufacturing the device 1 in which the prescribed number of levels of the electrode film 14 is stacked; and accordingly, the number of lithography processes can be reduced. As a result, the manufacturing cost of the nonvolatile semiconductor memory device 1 can be reduced.
- the series of processes described above forming the stacked body ML, making the through-hole 21 in the stacked body ML, and filling the silicon pillar 31 into the through-hole 21 may be performed twice to manufacture a nonvolatile semiconductor memory device 2 according to the second embodiment described above.
- a nonvolatile semiconductor memory device can be manufactured in which partial stacked bodies are stacked in three levels or more.
- portions of the through-holes 21 made in each of the partial stacked bodies are made collectively for the partial stacked body by dry etching.
- the invention is not limited thereto.
- mutually different potentials may be supplied to the control gate electrodes of each of the levels only for the writing operation and the reading operation.
- a common reference potential Vss may be used; and the drive circuit can be simplified.
- mutually different potentials may be supplied to the control gate electrodes of each of the levels only for one operation selected from the writing operation, the reading operation, and the erasing operation.
- the configurations of the control gate electrodes and the like are not limited to those of the exemplary embodiments described above.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Abstract
Description
V=6999.4×r3−1971.3×r2+194.66×r−5.0952
(Reading Operation)
Claims (21)
V=6999.4×r3−1971.3×r2+194.66×r−5.0952
V=6999.4×r3−1971.3×r2+194.66×r−5.0952
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US15/890,143 USRE48191E1 (en) | 2009-11-02 | 2018-02-06 | Nonvolatile semiconductor memory device and method for driving same |
US16/926,273 USRE49152E1 (en) | 2009-11-02 | 2020-07-10 | Nonvolatile semiconductor memory device and method for driving same |
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US14/992,650 USRE46785E1 (en) | 2009-11-02 | 2016-01-11 | Nonvolatile semiconductor memory device and method for driving same |
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Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5086959B2 (en) * | 2008-09-26 | 2012-11-28 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP5380190B2 (en) * | 2009-07-21 | 2014-01-08 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
JP5052575B2 (en) * | 2009-09-01 | 2012-10-17 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP4913188B2 (en) * | 2009-09-18 | 2012-04-11 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP2012059830A (en) * | 2010-09-07 | 2012-03-22 | Toshiba Corp | Semiconductor memory device |
KR101198253B1 (en) | 2010-12-30 | 2012-11-07 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and method for fabricating the same |
US8750040B2 (en) | 2011-01-21 | 2014-06-10 | Micron Technology, Inc. | Memory devices having source lines directly coupled to body regions and methods |
US8431961B2 (en) | 2011-02-03 | 2013-04-30 | Micron Technology, Inc. | Memory devices with a connecting region having a band gap lower than a band gap of a body region |
JP2012203969A (en) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | Nonvolatile semiconductor memory device |
KR101868799B1 (en) * | 2011-05-26 | 2018-06-21 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and method for fabricating the same |
JP2013065636A (en) * | 2011-09-15 | 2013-04-11 | Toshiba Corp | Nonvolatile semiconductor storage device and manufacturing method of the same |
US9171625B2 (en) | 2012-06-15 | 2015-10-27 | Micron Technology, Inc. | Apparatuses and methods to modify pillar potential |
JP2014013634A (en) * | 2012-07-03 | 2014-01-23 | Toshiba Corp | Nonvolatile semiconductor memory device and operation method thereof |
US8754459B2 (en) | 2012-08-31 | 2014-06-17 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US8780632B2 (en) | 2012-11-09 | 2014-07-15 | Sandisk Technologies Inc. | De-duplication techniques using NAND flash based content addressable memory |
US8634248B1 (en) | 2012-11-09 | 2014-01-21 | Sandisk Technologies Inc. | On-device data analytics using NAND flash based intelligent memory |
US8780635B2 (en) | 2012-11-09 | 2014-07-15 | Sandisk Technologies Inc. | Use of bloom filter and improved program algorithm for increased data protection in CAM NAND memory |
US8780634B2 (en) | 2012-11-09 | 2014-07-15 | Sandisk Technologies Inc. | CAM NAND with OR function and full chip search capability |
US8817541B2 (en) | 2012-11-09 | 2014-08-26 | Sandisk Technologies Inc. | Data search using bloom filters and NAND based content addressable memory |
US8773909B2 (en) | 2012-11-09 | 2014-07-08 | Sandisk Technologies Inc. | CAM NAND with or function and full chip search capability |
US8811085B2 (en) | 2012-11-09 | 2014-08-19 | Sandisk Technologies Inc. | On-device data analytics using NAND flash based intelligent memory |
US8792279B2 (en) | 2012-11-09 | 2014-07-29 | Sandisk Technologies Inc. | Architectures for data analytics using computational NAND memory |
US8780633B2 (en) | 2012-11-09 | 2014-07-15 | SanDisk Technologies, Inc. | De-duplication system using NAND flash based content addressable memory |
US10127150B2 (en) * | 2012-11-09 | 2018-11-13 | Sandisk Technologies Llc | Key value addressed storage drive using NAND flash based content addressable memory |
US9075424B2 (en) | 2013-03-06 | 2015-07-07 | Sandisk Technologies Inc. | Compensation scheme to improve the stability of the operational amplifiers |
JP2014183304A (en) | 2013-03-19 | 2014-09-29 | Toshiba Corp | Nonvolatile semiconductor storage device and method for manufacturing the same |
JP2015176620A (en) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | semiconductor memory device |
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JP5889486B1 (en) * | 2014-06-10 | 2016-03-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Columnar semiconductor memory device and manufacturing method thereof |
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JP6309909B2 (en) * | 2015-03-12 | 2018-04-11 | 東芝メモリ株式会社 | Nonvolatile semiconductor memory device |
JP6290124B2 (en) | 2015-03-12 | 2018-03-07 | 東芝メモリ株式会社 | Semiconductor memory device |
JP2016225614A (en) | 2015-05-26 | 2016-12-28 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP2017107626A (en) * | 2015-12-10 | 2017-06-15 | 株式会社東芝 | Semiconductor device |
JP6595357B2 (en) * | 2016-02-01 | 2019-10-23 | 東芝メモリ株式会社 | Memory device |
JP2018045752A (en) | 2016-09-16 | 2018-03-22 | 東芝メモリ株式会社 | Semiconductor device |
JP2018085160A (en) | 2016-11-25 | 2018-05-31 | 東芝メモリ株式会社 | Semiconductor device and operation method of semiconductor |
CN106847821B (en) | 2017-03-07 | 2018-09-14 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
US10593730B1 (en) | 2018-10-10 | 2020-03-17 | Micron Technology, Inc. | Three-dimensional memory array |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070097738A1 (en) * | 2005-11-03 | 2007-05-03 | Elpida Memory, Inc. | Electrically rewritable non-volatile memory element and method of manufacturing the same |
JP2007266143A (en) | 2006-03-27 | 2007-10-11 | Toshiba Corp | Non-volatile semiconductor memory device and manufacturing method therefor |
WO2009075370A1 (en) | 2007-12-11 | 2009-06-18 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
WO2010035609A1 (en) | 2008-09-26 | 2010-04-01 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
US20100096682A1 (en) | 2008-10-20 | 2010-04-22 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US20100109072A1 (en) | 2008-11-05 | 2010-05-06 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing same |
US20100117137A1 (en) | 2008-11-10 | 2010-05-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
US20110069552A1 (en) | 2009-09-18 | 2011-03-24 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of data read therein |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5798966A (en) * | 1997-03-31 | 1998-08-25 | Intel Corporation | Flash memory VDS compensation techiques to reduce programming variability |
US6631085B2 (en) * | 2000-04-28 | 2003-10-07 | Matrix Semiconductor, Inc. | Three-dimensional memory array incorporating serial chain diode stack |
US7218570B2 (en) * | 2004-12-17 | 2007-05-15 | Sandisk 3D Llc | Apparatus and method for memory operations using address-dependent conditions |
KR100673170B1 (en) * | 2005-03-10 | 2007-01-22 | 주식회사 하이닉스반도체 | Flash memory device with improved erase function and method for controlling erase operation of the same |
US7545675B2 (en) * | 2005-12-16 | 2009-06-09 | Sandisk Corporation | Reading non-volatile storage with efficient setup |
US7436703B2 (en) * | 2005-12-27 | 2008-10-14 | Sandisk Corporation | Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices |
JP4768557B2 (en) * | 2006-09-15 | 2011-09-07 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US7532518B2 (en) * | 2007-06-25 | 2009-05-12 | Spansion Llc | Compensation method to achieve uniform programming speed of flash memory devices |
JP2009087433A (en) * | 2007-09-28 | 2009-04-23 | Toshiba Corp | Nonvolatile semiconductor storage device |
US7961507B2 (en) * | 2008-03-11 | 2011-06-14 | Micron Technology, Inc. | Non-volatile memory with resistive access component |
KR100991220B1 (en) * | 2008-07-21 | 2010-11-04 | 삼성전자주식회사 | Contact structures in a substrate having a bonded interface, semiconductor devices including the same, and methods of fabricating the same |
US9153596B2 (en) * | 2009-02-23 | 2015-10-06 | Cypress Semiconductor Corporation | Adjacent wordline disturb reduction using boron/indium implant |
US11101266B2 (en) * | 2009-10-12 | 2021-08-24 | Monolithic 3D Inc. | 3D device and devices with bonding |
-
2009
- 2009-11-02 JP JP2009251891A patent/JP5259552B2/en active Active
-
2010
- 2010-08-05 US US12/851,054 patent/US8218358B2/en not_active Ceased
- 2010-08-31 KR KR1020100084677A patent/KR101082228B1/en not_active IP Right Cessation
-
2014
- 2014-07-09 US US14/327,359 patent/USRE45840E1/en active Active
-
2016
- 2016-01-11 US US14/992,650 patent/USRE46785E1/en active Active
-
2018
- 2018-02-06 US US15/890,143 patent/USRE48191E1/en active Active
-
2020
- 2020-07-10 US US16/926,273 patent/USRE49152E1/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070097738A1 (en) * | 2005-11-03 | 2007-05-03 | Elpida Memory, Inc. | Electrically rewritable non-volatile memory element and method of manufacturing the same |
JP2007266143A (en) | 2006-03-27 | 2007-10-11 | Toshiba Corp | Non-volatile semiconductor memory device and manufacturing method therefor |
US20070252201A1 (en) | 2006-03-27 | 2007-11-01 | Masaru Kito | Nonvolatile semiconductor memory device and manufacturing method thereof |
US20110287597A1 (en) | 2006-03-27 | 2011-11-24 | Kabushiki Kaisha Toshiba | Nonvolatile semicondutor memory device and manufacturing method thereof |
US20110284947A1 (en) | 2006-03-27 | 2011-11-24 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and manufacturing method thereof |
WO2009075370A1 (en) | 2007-12-11 | 2009-06-18 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US8372720B2 (en) | 2007-12-11 | 2013-02-12 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US20110175159A1 (en) | 2008-09-26 | 2011-07-21 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
WO2010035609A1 (en) | 2008-09-26 | 2010-04-01 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
US20100096682A1 (en) | 2008-10-20 | 2010-04-22 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US20100109072A1 (en) | 2008-11-05 | 2010-05-06 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing same |
US20100117137A1 (en) | 2008-11-10 | 2010-05-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
US20110069552A1 (en) | 2009-09-18 | 2011-03-24 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of data read therein |
Non-Patent Citations (1)
Title |
---|
U.S. Appl. No. 12/679,991, filed Mar. 25, 2010, Yoshiaki Fukuzumi, et al. |
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US8218358B2 (en) | 2012-07-10 |
JP5259552B2 (en) | 2013-08-07 |
USRE49152E1 (en) | 2022-07-26 |
USRE45840E1 (en) | 2016-01-12 |
US20110103153A1 (en) | 2011-05-05 |
JP2011096340A (en) | 2011-05-12 |
USRE48191E1 (en) | 2020-09-01 |
KR20110048452A (en) | 2011-05-11 |
KR101082228B1 (en) | 2011-11-09 |
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