JP2005339401A - Information processor and control method thereof, information processing controller, information processing unit and control method thereof, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing controller in a device capable of making another information processing unit within the same information processor unit use a part of sub-processors as an auxiliary processor. <P>SOLUTION: The information processing unit maps the local storage of the sub-processor in its own address space, and arranges a sub-processor program for requesting an execution to the sub-processor. A main processor performs starting, stopping and interruption of the sub-processor program execution by the sub-processor in response to a sub-processor program execution start request, an execution stop request, and an interruption request from the information processing unit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus that links operations between two or more connected devices, a control method thereof, an information processing controller, an information processing unit, a control method thereof, and a computer program, and in particular, two or more connected devices. The present invention relates to an information processing apparatus and a control method thereof, an information processing controller, an information processing unit and a control method thereof, and a computer program for coordinating operations between other devices.

  More specifically, the present invention relates to an information processing apparatus that virtually operates as a single device by a plurality of connected devices performing distributed processing by cooperative operation, a control method therefor, an information processing controller, and an information processing unit And a control method thereof, and a computer program, in particular, an information processing apparatus including an information processing controller having a multiprocessor configuration including one or more sub processors and a main processor that instructs each sub processor to execute the sub processor program. The present invention relates to an information processing apparatus that operates in cooperation with another unit in the same information processing apparatus or an external device, a control method thereof, an information processing controller, an information processing unit, a control method thereof, and a computer program.

  It is known that information resources can be shared, hardware resources can be shared, and collaboration among a plurality of users can be realized by interconnecting a plurality of computers via a network. As connection media between computers, there are various types such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet.

  Recently, in particular, technologies such as computers and networks have deeply penetrated into ordinary homes. Information devices such as personal computers and PDAs (Personal Digital Assistants) in the home, AV devices such as television receivers and video playback devices, various information appliances, and CE (Consumer Electronics) devices are mutually connected via the home network. It is connected. Such home networks are often interconnected to external wide area networks such as the Internet via routers.

  However, a usage form in which a plurality of AV devices are connected on the home network is assumed, but there has been a problem that until now, sufficient cooperation has not been established between the AV devices.

  Recently, research and development related to grid computing technology that realizes high computing performance by cooperative operation of devices in order to link devices on a network in order to cooperate with each other (for example, patent documents) 1-5).

  According to this grid computing technology, a plurality of information processing apparatuses on the network perform an emphasis operation to perform distributed processing, and can operate virtually as one information processing apparatus from the user.

  For example, when a plurality of information processing apparatuses having a recording reservation function are connected to a network, a recording reservation cooperation operation can be realized. In other words, when a plurality of information processing apparatuses link recording reservation operations via a home network, the information processing devices virtually operate as one recording device on the home network. Then, the user can make a recording reservation using any device connected to the home network using the user interface of any device.

  Furthermore, by cooperation of such a recording reservation function, it is possible to simultaneously record programs with overlapping reservation times (so-called back programs). Similarly, the playback operation of the recorded content can be linked between a plurality of devices, and simultaneous and synchronous content playback can be realized. By cooperating with the content reproduction function, the concept of channel switching can be introduced in content reproduction by simultaneously and synchronously reproducing the content recorded by different devices.

  According to such a single virtual device, even if the hardware resource and processing capability of the single device cannot meet the request from the user, they cooperate and operate on the network. By utilizing the surplus processing capacity of other devices, it is possible to meet the user's request and to realize a service that is not realistic with one normal device.

JP 2002-342165 A JP 2002-351850 A JP 2002-358289 A JP 2002-366533 A JP 2002-366534 A

  Each information processing apparatus that realizes grid computing includes an information processing controller. The information processing controller is equipped with one or more sub processors capable of executing a sub processor program developed on its own local memory, and a main processor that instructs the sub processor to execute the sub processor program.

  In such an information processing controller, the main processor performs resource management such as surplus processing capability of each sub-processor, and can execute a plurality of functions simultaneously in parallel. For example, additional processing related to recorded content such as recording reservation of a TV program, playback of recorded content, scene recognition, re-encoding / image quality improvement, and the like can be distributed using a sub processor.

  Here, when one or more processes are performed in the information processing controller, it is not always necessary to perform distributed processing using all the sub processors, and some of the sub processors can be used for other purposes.

  Each sub-processor has a local storage associated therewith and can execute a sub-processor program developed on the local storage. For example, in a grid computing system in which a plurality of devices as described above perform distributed processing through a cooperative operation to virtually operate as a single device, an information processing controller having a multiprocessor configuration includes a plurality of sub-processors. The above distributed processing technique is suitably realized by causing a part to be used as an auxiliary processor by an external information processing apparatus. In addition, the performance of the external information processing apparatus can be kept low, and high processing performance may be realized at low cost as the entire system.

  However, in the conventional method, it takes a complicated procedure and time from when the execution of the sub processor program is requested to when the sub processor program is started, and the external information processing apparatus can easily execute the sub processor program with low delay. It cannot be executed, and high processing performance cannot be realized.

  Conventionally, in order for an information processing controller in another information processing apparatus to execute a function program, a high processing capability and a communication device are required, and an information processing apparatus that does not have such a function has other information. The sub processor of the information processing controller in the processing device cannot be used. That is, an information processing apparatus that cannot use a sub processor of an information processing controller of another information processing apparatus needs to be equipped with a sub processor in its information processing controller, and cannot realize a low-cost device.

  The present invention has been made in view of the technical problems as described above, and the main purpose thereof is an excellent information processing apparatus capable of suitably linking operations between two or more connected devices, and the information processing apparatus. A control method, an information processing controller, an information processing unit, a control method thereof, and a computer program are provided.

  A further object of the present invention is to provide an excellent information processing apparatus and a control method therefor, which can suitably operate virtually as a single device by performing distributed processing by a plurality of connected devices by cooperative operation, An information processing controller, an information processing unit, a control method thereof, and a computer program are provided.

  A further object of the present invention is that an information processing apparatus including an information processing controller having a multiprocessor configuration including one or more sub-processors and a main processor that instructs each sub-processor to execute a program suitably operates in cooperation with an external device. It is to provide an excellent information processing apparatus and its control method, an information processing controller, an information processing unit and its control method, and a computer program.

  A further object of the present invention is to allow an information processing controller having a multiprocessor configuration to use some sub-processors in other units in the same information processing apparatus in a grid computing system that virtually operates as one device. An excellent information processing apparatus and its control method, an information processing controller, an information processing unit and its control method, and a computer program are provided.

The present invention has been made in consideration of the above problems, and a first aspect thereof is an information processing apparatus included in an information processing system in which a plurality of information processing apparatuses connected to a network perform distributed processing by cooperative operation. There,
An information processing controller comprising one or more sub-processors capable of executing a program expanded on its own local storage; and a main processor that instructs the sub-processor to execute the program;
An information processing unit in the information processing apparatus using a part of the sub processors in the information processing controller;
Address mapping means for mapping the local storage of the sub processor to be used to the address space of the information processing unit;
Sub processor program placement means for placing a sub processor program that the information processing unit requests the sub processor to execute on a local storage of the sub processor used by the information processing unit;
It is an information processing apparatus characterized by comprising.

  The present invention relates to an information processing system that realizes grid computing, in which a plurality of devices connected to a network perform distributed processing through cooperative operation, and thus preferably operate virtually as one device. At least some of the information processing devices constituting this type of system employ an information processing controller having a multiprocessor configuration, and the information processing controller can execute a sub processor program developed on its own local memory. The above-mentioned sub processor and a main processor that instructs the sub processor to execute the sub processor program are provided.

  In such an information processing controller, the main processor performs resource management such as surplus processing capability of each sub-processor, and can execute a plurality of functions simultaneously in parallel. Here, it is not always necessary to use all the sub-processors, and some of the sub-processors can be used for other purposes. For example, the use of the surplus sub-processors is permitted to other units in the same information processing apparatus. Can do.

  According to the present invention, the information processing controller can receive permission to use some of the sub processors in the information processing controller with a simple procedure and a short time.

  That is, other units in the same information processing apparatus map the local storage of the sub processor used in the information processing controller to its own address space, and arrange a sub processor program for requesting the sub processor to execute. Then, the main processor in the information processing controller may be requested to start, stop and interrupt the execution of the sub processor program. The main processor in the information processing controller starts, stops, or interrupts the sub processor program execution of the sub processor in response to the sub processor program execution start request, the execution stop request, and the interrupt request from the other unit. To. The main processor notifies the other unit of an interrupt from the sub processor.

  Therefore, according to the present invention, other units in the same information processing apparatus can cause the information processing apparatus controller to easily execute the sub-processor program with low delay, and can realize high processing performance. As a result, the other units can obtain the same performance without being equipped with a sub-processor, so that a low-cost device can be realized.

  Here, based on the surplus processing capability of each sub processor, the sub processor used by the other unit can be determined.

  In the other unit, when an access request to an address mapping the storage of the sub processor is made, the information processing controller converts the address to the address of the local storage of the sub processor, thereby realizing the access.

  Further, a protection means for prohibiting unauthorized access to the local storage of each sub processor of the information processing controller may be provided.

  This protection means prohibits an access request by the other unit to the local storage of a sub processor not used by the other unit as an unauthorized access.

  In addition, the protection means prohibits unauthorized access when there is a request for access to the local storage of the sub processor used by the other unit from the main processor or other sub processor of the information processing controller. To do.

According to a second aspect of the present invention, there is provided one or more sub-processors capable of executing a sub-processor program expanded on its own local storage, and a main processor that instructs the sub-processor to execute the sub-processor program. A computer program described in a computer-readable format so that a process for using an information processing unit by a sub-processor of a part of the information processing controller is executed on the information processing controller,
A resource management step for managing each sub-processor;
A sub-processor determining step for determining a sub-processor used by the information processing unit;
A sub processor program placement step of placing a processing sub processor program that the information processing unit requests the sub processor to execute on a local storage of the sub processor used by the information processing unit;
In response to the sub processor program execution start request, execution stop request, or interrupt request from the information processing unit, starting, stopping, or interrupting the sub processor program execution of the sub processor;
A computer program characterized by comprising:

According to a third aspect of the present invention, there is provided one or more sub-processors capable of executing a sub-processor program developed on its own local storage, and a main processor that instructs the sub-processor to execute the sub-processor program. A computer program written in a computer-readable format to execute processing for using resources of the information processing controller on the information processing unit,
An address mapping step for mapping the local storage of the sub processor to be used to its own address space;
A sub processor program placement step for placing a sub processor program for requesting execution of the sub processor on the local storage of the sub processor to be used;
A sub processor program execution requesting step for requesting the main processor to start, stop, or interrupt an execution of a sub processor program by a sub processor to be used;
A computer program characterized by comprising:

  The computer program according to each of the second and third aspects of the present invention defines a computer program described in a computer-readable format so as to realize predetermined processing on the information processing controller or another unit. In other words, by installing the computer program according to each of the second and third aspects of the present invention in the information processing controller or other unit, a cooperative action is exhibited and operates on the information processing controller and other unit. As a result, a cooperative operation in which another unit uses some of the sub-processors included in the information processing controller is realized, and it is possible to obtain the same operational effects as the information processing apparatus according to the first aspect of the present invention.

  According to the present invention, an excellent information processing apparatus and its control method, an information processing controller, an information processing unit and its control method, and a computer program capable of suitably linking operations between two or more connected devices Can be provided.

  In addition, according to the present invention, an excellent information processing apparatus and a control method therefor that can be suitably operated virtually as one apparatus by performing distributed processing by a plurality of connected apparatuses by cooperative operation. , An information processing controller, an information processing unit, a control method thereof, and a computer program can be provided.

  Further, according to the present invention, an information processing apparatus including an information processing controller having a multiprocessor configuration including one or more sub-processors and a main processor that instructs each sub-processor to execute a program suitably operates in cooperation with an external device. An excellent information processing apparatus and control method thereof, an information processing controller, an information processing unit and control method thereof, and a computer program can be provided.

  Further, according to the present invention, in a grid computing system that virtually operates as a single device, an information processing controller having a multiprocessor configuration causes some subprocessors to be used by other units in the same information processing apparatus. An excellent information processing apparatus and control method thereof, an information processing controller, an information processing unit and control method thereof, and a computer program can be provided.

  Other objects, features, and advantages of the present invention will become apparent from more detailed descriptions based on embodiments of the present invention described later and the accompanying drawings.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

A. System configuration The present invention makes it easy and efficient to perform a recording reservation operation in each device set in different places by suitably linking operations between two or more information processing apparatuses via a home network. is there. In order to link devices on the network, grid computing technology is used to achieve high computing performance through cooperative operation of devices.

  FIG. 1 schematically shows the configuration of a network system configured by applying grid computing.

  The network includes the Internet and other wide area networks, and private networks such as a LAN (Local Area Network) and a home network connected to the wide area network via a gateway or the like. The home network can be physically configured with a standard network interface such as 10BaseT, 100BaseTX, or Gigaether. Also, Upnp (Universal Plug and Play) can be used as a mechanism for finding other devices on the home network. According to Upnp, definition files described in XML (eXtended Markup Language) format are exchanged between devices connected to a network, and mutual authentication is performed through addressing processing, discovery processing, and service request processing. Alternatively, it can also be realized by broadcasting a packet describing prescribed device information in the same segment.

  A plurality of information processing apparatuses are connected on the network. Examples of information processing devices include AV devices equipped with recording media and having a recording reservation function, such as DVD recorders and HD recorders, or playback-only AV devices that do not have a recording function, such as compact discs, and other information A processing apparatus is mentioned. Another example of the information processing apparatus is a computer processing system such as a PDA or a personal computer. In the example illustrated in FIG. 1, a plurality of information processing apparatuses 1, 2, 3, and 4 are connected via a network 9.

A-1. Information processing apparatus and information processing controller Information processing apparatuses 1, 2, 3, and 4 are, for example, various AV (Audio and Visual) devices and portable devices (described later).

  As illustrated, the information processing apparatus 1 includes an information processing controller 11 as a computer function unit. The information processing controller 11 includes a main processor 21-1, sub processors 23-1, 23-2, and 23-3, a DMAC (direct memory access controller) 25-1, and a DC (disk controller) 27-1. . The information processing controller 11 is preferably configured as a one-chip IC (integrated circuit).

  The main processor 21-1 performs schedule management of program execution (data processing) by the sub processors 23-1, 23-2, and 23-3, and general management of the information processing controller 11 (information processing apparatus 1). . However, a program other than the program for performing management in the main processor 21-1 can be configured to operate. In this case, the main processor 21-1 also functions as a sub processor. The main processor 21-1 includes an LS (local storage) 22-1.

  One information processor may have one sub-processor, but preferably a plurality of sub-processors. In the illustrated example, there are a plurality of cases. Each sub-processor 23-1, 23-2, 23-3 executes a program in parallel and independently under the control of the main processor 21-1, and processes data. Further, in some cases, the program in the main processor 21-1 can operate in cooperation with the programs in the sub processors 23-1, 23-2, and 23-3. The sub-processors 23-1, 23-2, and 23-3 also include LS (local storage) 24-1, 24-2, and 24-3, respectively.

  The DMAC (direct memory access controller) 25-1 accesses a program and data stored in a main memory 26-1 including a DRAM (dynamic RAM) connected to the information processing controller 11 without the intervention of a processor. It is. The DC (disk controller) 27-1 controls access operations to the external recording units 28-1 and 28-2 connected to the information processing controller 11.

  The external recording units 28-1 and 28-2 may be either a fixed disk (hard disk) or a removable disk. As the removable disk, various recording media such as MO (magnetic disk), CD ± RW, DVD ± RW and other optical disks, memory disks, SRAM (static RAM), ROM and the like can be used. The DC 27-1 is called a disk controller, but in short, is an external recording unit controller. As shown in FIG. 1, the information processing controller 11 can be configured so that a plurality of external recording units 28 can be connected.

  The main processor 21-1, the sub processors 23-1, 23-2, 23-3, the DMAC 25-1, and the DC 27-1 are interconnected by a bus 29-1.

  An identifier capable of uniquely identifying the information processing apparatus 1 on which the information processing controller 11 is mounted is assigned as an information processing apparatus ID to the information processing controller 11. Similarly, identifiers that can specify the main processor 21-1 and the sub processors 23-1, 23-2, and 23-3 are assigned as the main processor ID and the sub processor ID.

  Since the other information processing apparatuses 2, 3, and 4 are configured in the same manner, description thereof is omitted here. Here, even if the unit having the same parent number has a different branch number, the same function is assumed unless otherwise noted. In the following description, when the branch number is omitted, it is assumed that no difference due to the difference in the branch number occurs.

A-2. Access to Main Memory from Each Sub-Processor As described above, each sub-processor 23 in one information processing controller independently executes a program and processes data, but different sub-processors are the same in main memory 26. If data is read from or written to the area at the same time, data mismatch may occur. Therefore, the access from the sub processor 23 to the main memory 26 is performed according to the following procedure.

  FIG. 2A shows a location in the main memory 26. As shown in the figure, the main memory 26 is composed of memory locations that can specify a plurality of addresses, and an additional segment for storing information indicating the state of data is allocated to each memory location. The additional segment includes an F / E bit, a sub processor ID, and an LS address (local storage address). Each memory location is also assigned an access key to be described later. The F / E bit is defined as follows.

  The F / E bit = 0 indicates that the data being processed being read by the sub-processor 23 or invalid data that is not the latest data because it is empty, and cannot be read. The F / E bit = 0 indicates that data can be written to the memory location, and is set to 1 after writing.

  The F / E bit = 1 indicates that the data at the memory location has not been read by the sub-processor 23 and is the latest unprocessed data. The data in the memory location can be read and set to 0 after being read by the sub-processor 23. Further, the F / E bit = 1 indicates that the memory location cannot write data.

  Furthermore, it is possible to set a read reservation for the memory location in the state where the F / E bit = 0 (reading impossible / writing possible). When a read reservation is made for a memory location with the F / E bit = 0, the sub-processor 23 adds the sub-processor ID and LS of the sub-processor 23 as read reservation information to an additional segment of the memory location where the read reservation is made. Write the address.

  Thereafter, when data is written to the memory location reserved for reading by the sub-processor 23 on the data writing side and the F / E bit is set to 1 (readable / not writable), an additional segment is set in advance as read reservation information. Is read into the sub processor ID and LS address written in.

  When it is necessary to process data in multiple stages by a plurality of sub-processors, the sub-processor 23 that performs the process in the previous stage controls the processed data by controlling the reading / writing of data in each memory location in this way. Immediately after writing to a predetermined address on the main memory 26, it becomes possible for another sub-processor 23, which performs the subsequent processing, to read the pre-processed data.

  FIG. 2B shows the memory location in the LS 24 in each sub processor 23. As shown in the figure, the LS 24 in each sub-processor 23 is also composed of memory locations that can specify a plurality of addresses. An additional segment is similarly allocated for each memory location. The additional segment includes a busy bit.

  When the sub-processor 23 reads the data in the main memory 26 to the memory location of its own LS 24, it reserves by setting the corresponding busy bit to 1. No other data can be stored in the memory location where the busy bit is 1. After reading to the memory location of the LS 24, the busy bit becomes 0 and can be used for any purpose.

  As shown in FIG. 2A, the main memory 26 connected to each information processing controller further includes a plurality of sandboxes that define areas in the main memory 26. The main memory 26 is composed of a plurality of memory locations, and the sandbox is a set of these memory locations. Each sandbox is assigned to each sub-processor 23 and can be used exclusively by the corresponding sub-processor. That is, each sub-processor 23 can use the sandbox assigned to itself, but cannot access data beyond this area.

  Further, in order to realize exclusive control of the main memory 26, a key management table as shown in FIG. The key management table is stored in a relatively high-speed memory such as SRAM in the information processing controller, and is associated with the DMAC 25. Each entry in the key management table includes a sub processor ID, a sub processor key, and a key mask.

  The process when the sub processor 23 uses the main memory 26 is as follows. First, the sub processor 23 outputs a read or write command to the DMAC 25. This command includes its own sub-processor ID and the address of the main memory 26 that is the use request destination.

  Before executing this command, the DMAC 25 refers to the key management table and checks the sub processor key of the sub processor of the use request source. Next, the DMAC 25 compares the checked sub-processor key of the use request source with the access key allocated to the memory location shown in FIG. Execute the above command only when two keys match.

  In the key mask on the key management table shown in FIG. 2C, when the arbitrary bit becomes 1, the corresponding bit of the sub-processor key associated with the key mask may become 0 or 1. it can.

  For example, assume that the sub-processor key is 1010. Normally, this sub-processor key only allows access to a sandbox with 1010 access keys. However, if the key mask associated with this sub-processor key is set to 0001, the match determination between the sub-processor key and the access key is masked only for the digit whose key mask bit is set to 1. The sub processor key 1010 enables access to a sandbox having an access key whose access key is either 1010 or 1011.

  As described above, the sandbox exclusivity of the main memory 26 is realized. That is, when it is necessary to process data in multiple stages by a plurality of sub-processors arranged in one information processing controller, only the sub-processor that performs the previous stage process and the sub-processor that performs the subsequent stage process, It becomes possible to access a predetermined address of the main memory 26, and data can be protected.

  Such exclusive memory control can be used as follows, for example. First, immediately after the information processing apparatus is activated, the key mask values are all zero. It is assumed that a program in the main processor is executed and operates in cooperation with a program in the sub processor. When the processing result data output by the first sub-processor is temporarily stored in the main memory and desired to be input to the second sub-processor, the corresponding main memory area must naturally be accessible from either sub-processor. is there. In such a case, the program in the main processor appropriately changes the value of the key mask and provides a main memory area that can be accessed from a plurality of sub processors, thereby enabling multi-stage processing by the sub processors. .

  More specifically, it is a multi-step process in the order of data from another information processing apparatus → processing by the first sub processor → first main memory area → processing by the second sub processor → second main memory area. When processing is performed, the second sub-processor cannot access the first main memory area with the following settings.

Sub-processor key of the first sub-processor: 0100
First main memory area access key: 0100,
Sub-processor key of the second sub-processor: 0101,
Second main memory area access key: 0101

  Therefore, by setting the key mask of the second sub processor to 0001, it is possible to allow the second sub processor to access the first main memory area.

A-3. 1. Generation and configuration of software cell In the network system of FIG. 1, a software cell is transmitted between information processing apparatuses 1, 2, 3, and 4 for distributed processing between information processing apparatuses 1, 2, 3, and 4. . That is, the main processor 21 included in the information processing controller in a certain information processing apparatus generates a software cell including a command, a program, and data, and transmits it to another information processing apparatus via the network 9 to perform processing. Can be dispersed.

  FIG. 3 shows an example of the configuration of the software cell. The illustrated software cell includes a transmission source ID, a transmission destination ID, a response destination ID, a cell interface, a DMA command, a program, and data.

  The transmission source ID includes the network address of the information processing apparatus that is the transmission source of the software cell, the information processing apparatus ID of the information processing controller in the information processing apparatus, and the main processor included in the information processing controller in the information processing apparatus 21 and the identifiers (main processor ID and sub processor ID) of each sub processor 23 are included.

  The transmission destination ID and the response destination ID respectively include the same information about the information processing apparatus that is the transmission destination of the software cell and the information processing apparatus that is the response destination of the execution result of the software cell.

  The cell interface is information necessary for using the software cell, and includes a global ID, necessary sub-processor information, a sandbox size, and a previous software cell ID.

  The global ID uniquely identifies the software cell throughout the network, and is created based on the transmission source ID and the date and time (date and time) of creation or transmission of the software cell.

  In the necessary sub-processor information, the number of sub-processors necessary for executing the software cell is set. As the sandbox size, the amount of memory in the main memory 26 and the LS 24 of the sub processor 23 necessary for executing the software cell is set.

  The previous software cell ID is an identifier of the previous software cell in a group of software cells that request sequential execution of streaming data or the like.

  The execution section of the software cell is composed of DMA commands, programs, and data. The DMA command includes a series of DMA commands necessary for starting the program, and the program includes a sub processor program executed by the sub processor 23. The data here is data processed by a program including the sub processor program.

  Further, the DMA command includes a load command, a kick command, a function program execution command, a status request command, and a status return command.

  The load command is a command for loading information in the main memory 26 into the LS 24 in the sub processor 23, and includes a main memory address, a sub processor ID, and an LS address in addition to the load command itself. The main memory address indicates an address of a predetermined area in the main memory 26 from which information is loaded. The sub processor ID and the LS address indicate the identifier of the sub processor 23 to which the information is loaded and the address of the LS 24.

  The kick command is a command for starting execution of the program, and includes a sub processor ID and a program counter in addition to the kick command itself. The sub processor ID identifies the sub processor 23 to be kicked, and the program counter gives an address for the program execution program counter.

  The function program execution command is a command for requesting execution of a function program from another information processing apparatus to another information processing apparatus (described later). The information processing controller in the information processing apparatus that has received the function program execution command identifies a function program to be activated by a function program ID (described later).

  The status request command is a command for requesting transmission of device information related to the current operation state (situation) of the information processing device indicated by the transmission destination ID to the information processing device indicated by the response destination ID. Although the function program will be described later, it is a program categorized into the function program in the software configuration diagram stored in the main memory 26 of the information processing controller shown in FIG. The function program is loaded into the main memory 26 and executed by the main processor 21.

  The status reply command is a command in which the information processing apparatus that has received the status request command responds to the information processing apparatus indicated by the response destination ID included in the status request command with its own apparatus information. The status reply command stores device information in the data area of the execution section.

  FIG. 4 shows the structure of the data area of the software cell when the DMA command is a status return command.

  The information processing device ID is an identifier for identifying the information processing device including the information processing controller, and indicates the ID of the information processing device that transmits the status reply command. The information processing apparatus ID is included in the information processing controller in the information processing apparatus by the main processor 21 included in the information processing controller in the information processing apparatus when the power is turned on. It is generated based on the number of sub processors 23 to be processed.

  The information processing device type ID includes a value representing the characteristics of the information processing device. The features of the information processing apparatus mentioned here include, for example, a hard disk recorder (described later), a PDA (Personal Digital Assistants), a portable CD (Compact Disc) player, and the like. The information processing device type ID may represent a function of the information processing device such as video / audio recording or video / audio reproduction. Values representing the characteristics and functions of the information processing device are predetermined. By calling the information processing device type ID, it is possible to grasp the characteristics and functions of the information processing device.

  The MS (master / slave) status indicates whether the information processing apparatus is operating as a master apparatus or a slave apparatus, as will be described later. When this is set to 0, it operates as a master apparatus. If it is set to 1, it indicates that it is operating as a slave device.

  The main processor operating frequency represents the operating frequency of the main processor 21 in the information processing controller. The main processor usage rate represents the usage rate in the main processor 21 for all programs currently running on the main processor 21. The main processor usage rate is a value representing the ratio of the processing capacity in use to the total processing capacity of the target main processor. For example, MIPS [Million Instructions Per Second], which is a unit for evaluating the processor processing capacity, is calculated as a unit. Or based on the processor usage time per unit time. The same applies to the sub-processor usage rate described later.

  The number of sub-processors represents the number of sub-processors 23 included in the information processing controller. The sub processor ID is an identifier for identifying each sub processor 23 in the information processing controller.

  The sub processor status represents the state of each sub processor 23, and there are states such as “unused”, “reserved”, and “busy”. “unused” indicates that the sub-processor is not currently used and is not reserved for use. “reserved” indicates a reserved state that is not currently used. Busy indicates that it is currently in use.

  The sub-processor usage rate represents the usage rate in the sub-processor for a program that is currently being executed in the sub-processor or that is reserved for execution in the sub-processor. That is, the sub processor usage rate indicates the current usage rate when the sub processor status is busy, and indicates the estimated usage rate that is to be used later when the sub processor status is reserved.

  One set of sub processor ID, sub processor status, and sub processor usage rate is set for one sub processor 23, and the number of sets corresponding to the sub processor 23 in one information processing controller is set.

  The total main memory capacity and the main memory usage represent the total capacity and the currently used capacity of the main memory 26 connected to the information processing controller, respectively.

  The number of external recording units represents the number of external recording units 28 connected to the information processing controller. The external recording unit ID is information that uniquely identifies the external recording unit 28 connected to the information processing controller. The external recording unit type ID represents the type of the external recording unit (for example, hard disk, CD ± RW, DVD ± RW, memory disk, SRAM, ROM, etc.).

  The external recording unit total capacity and the external recording unit usage amount represent the total capacity and the currently used capacity of the external recording unit 28 identified by the external recording unit ID, respectively.

  The external recording unit ID, the external recording unit type ID, the external recording unit total capacity, and the external recording unit usage amount are set for one external recording unit 28 and connected to the information processing controller. The number of sets is equal to the number of external recording units 28. That is, when a plurality of external recording units are connected to one information processing controller, different external recording unit IDs are assigned to the respective external recording units, the external recording unit type ID, the external recording unit total capacity, and the external recording unit. Department usage is also managed separately.

A-4 The main processor 21 included in the information processing controller in the information processing apparatus that executes the software cell generates the software cell having the above-described configuration, and the other information processing apparatus and the inside of the apparatus via the network 9 To the information processing controller. The transmission source information processing device, the transmission destination information processing device, the response destination information processing device, and the information processing controller in each device are identified by the transmission source ID, the transmission destination ID, and the response destination ID, respectively. .

  The main processor 21 included in the information processing controller in the information processing apparatus that has received the software cell stores the software cell in the main memory 26. Furthermore, the transmission destination main processor 21 reads the software cell and processes the DMA command included therein.

  Specifically, the transmission destination main processor 21 first executes a load command. As a result, information is loaded from the main memory address instructed by the load command into a predetermined area of the LS 24 in the sub processor identified by the sub processor ID and LS address included in the load command. The information loaded here is a sub-processor program or data included in the received software cell, or other designated data.

  Next, the main processor 21 outputs the kick command together with the program counter included in the kick command to the sub processor indicated by the sub processor ID included therein.

  The instructed sub processor executes the sub processor program according to the kick command and the program counter. After the execution result is stored in the main memory 26, the main processor 21 is notified that the execution has been completed.

  Note that the processor that executes the software cell in the information processing controller in the information processing apparatus of the transmission destination is not limited to the sub-processor 23, and the main processor 21 stores a program for main memory such as a function program included in the software cell. It can also be specified to execute.

  In this case, the transmission source information processing apparatus includes a main memory program and data processed by the main memory program instead of the sub processor program, and the DMA command is sent to the transmission destination information processing apparatus. A software cell as a load command is transmitted, and the main memory 26 stores the main memory program and data processed thereby.

  Next, the transmission source information processing apparatus identifies the main processor ID, the main memory address, and the main memory program for the information processing controller in the transmission destination information processing apparatus to the transmission destination information processing apparatus. And a software cell in which the DMA command is a kick command or a function program execution command, and causes the main processor 21 to execute the main memory program.

  As described above, in the network system according to the present embodiment, the transmission source information processing apparatus transmits the sub processor program or the main memory program to the transmission destination information processing apparatus using software cells, and the sub processor program is The sub processor 23 included in the information processing controller in the information processing apparatus of the transmission destination can be loaded, and the information processing apparatus of the transmission destination can execute the sub processor program or the main memory program.

  When the program included in the received software cell is a sub processor program, the information processing controller in the transmission destination information processing apparatus loads the sub processor program to the designated sub processor. Then, the sub processor program or the main memory program included in the software cell is executed.

  Therefore, even if the user does not operate the transmission destination information processing apparatus, the sub processor program or the main memory program can be automatically executed by the information processing controller in the transmission destination information processing apparatus.

  In this way, when the information processing controller in its own device does not have a main memory program such as a sub processor program or a function program, the information processing device receives them from another information processing device connected to the network. Can be acquired. Furthermore, data is transferred between each sub-processor by the DMA method, and the above-described sandbox is used, so that even if it is necessary to process data in multiple stages within one information processing controller, high speed and high security are achieved. The process can be executed.

A-5. Distributed Processing as Network System FIG. 5 shows a state in which a plurality of information processing apparatuses operate as one virtual information processing apparatus. As a result of distributed processing using software cells, as shown in the upper part of the figure, a plurality of information processing devices 1, 2, 3, and 4 connected to the network 9 It operates as one typical information processing apparatus 7. However, in order to realize such a virtual operation, the following processing needs to be executed with the following configuration.

A-6. System Software Configuration and Program Loading FIG. 6 shows the software configuration stored in the main memory 26 of each information processing controller. These software (programs) are recorded in the external recording unit 28 connected to the information processing controller before the information processing apparatus is turned on. Each program is classified into a control program, a function program, and a device driver according to functions or features.

  The control program is the same for each information processing controller, and is executed by the main processor 21 of each information processing controller, and includes an MS (master / slave) manager and a capacity exchange program described later.

  The function program is executed by the main processor 21, and a function program corresponding to the information processing apparatus is provided for each information processing controller such as recording, reproduction, and material search.

  A device driver is used for input / output (transmission / reception) of an information processing controller (information processing apparatus), such as broadcast reception, monitor output, bit stream input / output, network input / output, etc. Provided.

  When the information processing apparatus is physically connected to the network 9 by plugging in a cable or the like, the main power supply is turned on and the information processing apparatus is electrically and functionally connected to the network 9. The main processor 21 of the information processing controller of the information processing apparatus loads each program belonging to the control program and each program belonging to the device driver into the main memory 26.

  As a program loading procedure, the main processor 21 first reads the program from the external recording unit 28 by causing the DC 27 to execute a read command, and then causes the DMAC 25 to execute the write command to Write to memory 26.

  As for each program belonging to the function program, it may be configured to load only the necessary program into the memory when necessary, or, like programs belonging to other categories, each program is loaded immediately after the main power is turned on. You may comprise.

  Each program belonging to the function program does not need to be recorded in the external recording unit 28 of all information processing apparatuses connected to the network, but may be recorded in the external recording unit 28 of any one information processing apparatus. Since it can be loaded from another information processing apparatus by the above-described method, the function program can be executed as a single virtual information processing apparatus 7 as a result as shown in the lower part of FIG.

  Here, as described above, the function program processed by the main processor 21 may operate in cooperation with the sub processor program processed by the sub processor 23. Therefore, when there is a sub processor program that operates in cooperation with the target function program when the main processor 21 reads the function program from the external recording unit 28 and writes it to the main memory 26, the sub processor program also includes the same main program. It is assumed that data is written in the memory 26. In this case, there may be one or more sub-processor programs that operate in cooperation with each other. If there are a plurality of sub-processor programs, all sub-processor programs that operate in cooperation are written in the main memory 26. The sub processor program written in the main memory 26 is then written in the LS 24 in the sub processor 23 and operates in cooperation with the function program processed by the main processor 21.

  A sub processor program ID is also assigned to the sub processor program, whereby the sub processor program can be uniquely identified. The assigned sub-processor program ID is an identifier related to the function program ID of the function program that is the partner of the cooperative operation, for example, the function program ID as a parent number and a branch number added at the end. There may be an identifier that is not related to the function program ID of the function program that is the partner of the cooperative operation. In any case, when the function program and the sub processor program operate in cooperation, it is necessary to store the program ID which is the identifier of the other party in the own program. Even when the function program operates in cooperation with a plurality of sub processor programs, the function program stores the sub processor program IDs of all the sub processor programs.

  As shown in the software cell of FIG. 3, an identifier that can uniquely identify the program is assigned to the function program as the function program ID for each program. The function program ID is determined from the creation date and time, the information processing apparatus ID, and the like at the stage of creating the function program.

  The main processor 21 secures an area for storing device information (information regarding the operation state) of the information processing device on which the main processor 21 operates in the main memory 26, and records the information as a device information table of the own device. The device information referred to here is each information below the information processing device ID in the data area of the status reply command shown in FIG.

A-7. Determination of Master / Slave in the System In the above-described network system, when the main power supply to a certain information processing apparatus is turned on, the main processor 21 of the information processing controller of the information processing apparatus mains the master / slave manager (hereinafter referred to as MS manager). It is loaded into the memory 26 and executed.

  When the MS manager detects that the information processing apparatus on which it operates is connected to the network 9, it confirms the existence of another information processing apparatus connected to the same network 9. As used herein, “connection” or “presence” means that the information processing apparatus is not only physically connected to the network 9 but also electrically and functionally connected to the network 9. Indicates.

  In addition, an information processing apparatus in which the device operates is referred to as a self device, and another information processing device is referred to as another device. The apparatus also indicates the information processing apparatus.

  A method in which the MS manager confirms the presence of another information processing apparatus connected to the same network 9 will be described below.

  The MS manager generates a software cell in which the DMA command is a status request command, the transmission source ID and the response destination ID are the information processing apparatus, and the transmission destination ID is not specified, and the information processing apparatus is connected to the network. Send and set a timer for network connection confirmation. The timeout time of the timer is, for example, 10 minutes.

  When another information processing apparatus is connected to the network system, the other apparatus receives the software cell of the status request command, and sends it to the information processing apparatus that has issued the status request command specified by the response destination ID. On the other hand, the DMA command is a status return command, and a software cell including device information of itself (other device) is transmitted as data. The software cell of this status reply command includes at least information for identifying the other device (information processing device ID, information on the main processor, information on the sub processor, etc.) and the MS status of the other device.

  The MS manager of the information processing apparatus that has issued the status request command monitors the reception of the software cell of the status reply command transmitted from another apparatus on the network until the timer for network connection confirmation times out. As a result, when the status reply command indicating the MS status = 0 (master device) is received, the MS status in the device information table of the own device is set to 1. As a result, the device becomes a slave device.

  On the other hand, when no status reply command is received before the network connection confirmation timer times out, or when no status reply command indicating MS status = 0 (master device) is received, The MS status in the device information table of the own device is set to 0. This makes the device a master device.

  That is, if no information processing apparatus is connected to the network 9 in a state in which no apparatus is connected to the network 9 or a master apparatus does not exist on the network 9, the apparatus automatically becomes the master apparatus. Set as On the other hand, when a new information processing apparatus is connected to the network 9 in a state where a master apparatus already exists on the network 9, the apparatus is automatically set as a slave apparatus.

  For both the master device and the slave device, the MS manager periodically monitors the status of the other device by sending a status request command to the other device on the network 9 and inquiring status information. As a result, the main power source of the information processing apparatus connected to the network 9 is cut off or the information processing apparatus is disconnected from the network 9, so that the status from a specific other apparatus is determined within a predetermined period set in advance for determination. When there is a change in the connection state of the network 9, such as when a reply command is not returned or when a new information processing apparatus is connected to the network 9, the information is notified to the ability exchange program described later. .

A-8. Acquisition of device information in the master device and slave device When the main processor 21 receives an inquiry from another MS information processing device connected to the network 9 and a notification of completion of setting of the MS status of its own device, the capability exchange program Execute.

  When the own device is the master device, the capability exchange program acquires device information about all other information processing devices connected to the network 9, that is, device information of each slave device.

  As described above, the device information of the other device is obtained by generating a software cell in which the DMA command is a status request command and transmitting it to the other device, and then the DMA command is a status return command and as data. This is possible by receiving a software cell containing device information from another device.

  The capability exchange program sets an area for storing device information about all other devices (each slave device) connected to the network 9 in the same manner as the device information table of the device that is the master device. This information is secured in the main memory 26 and recorded as a device information table of another device (slave device). That is, the device information of all information processing devices connected to the network 9 including the device itself is recorded in the main memory 26 of the master device as a device information table.

  On the other hand, when the own device is a slave device, the capability exchange program obtains device information about all other devices connected to the network 9, that is, device information of each slave device other than the master device and the own device. The information processing apparatus ID and the MS status included in the apparatus information are acquired and recorded in the main memory 26 of the own apparatus. That is, the device information of the own device is recorded as a device information table in the main memory 26 of the slave device, and the master device connected to the network 9 other than the own device and the information processing device ID for each slave device. And the MS status are recorded as another device information table.

  Further, in both the master device and the slave device, when the capability exchange program is notified from the MS manager that the information processing device is newly connected to the network 9 as described above, the device of the information processing device Information is acquired and recorded in the main memory 26 as described above.

  Note that the MS manager and the capability exchange program are not limited to being executed by the main processor 21, but may be executed by any of the sub processors 23. The MS manager and the capability exchange program are preferably resident programs that always operate while the main power supply of the information processing apparatus is turned on.

A-9. When the information processing device is disconnected from the network , for both the master device and the slave device, the mains power of the information processing device connected to the network 9 is shut off from the MS manager as described above. Alternatively, when it is notified from the network 9 that the information processing apparatus has been disconnected, the apparatus information table of the information processing apparatus is deleted from the main memory 26 of the own apparatus.

  Further, when the information processing apparatus disconnected from the network 9 is a master apparatus, a new master apparatus is determined by the following method.

  For example, each of the information processing devices that are not disconnected from the network 9 replaces the information processing device ID of the own device and the other device with a numerical value, compares the information processing device ID of the own device with the information processing device ID of the other device, and When the information processing device ID of the own device is the smallest among the information processing devices that are not disconnected from the network 9, the slave device moves to the master device, sets the MS status to 0, and is described above as the master device. As described above, device information is acquired from all other information processing devices (each slave device) connected to the network 9 and recorded in the main memory 26.

A-10. Distributed processing based on device information To operate a plurality of information processing devices 1, 2, 3, 4 connected to the network 9 as a single virtual information processing device 7 as shown in the lower part of FIG. The master device needs to grasp the user operation and the operation state of the slave device.

  FIG. 7 shows a state in which four information processing apparatuses operate as one virtual information processing apparatus 7. In the illustrated example, it is assumed that the information processing apparatus 1 operates as a master apparatus, and the information processing apparatuses 2, 3, and 4 operate as slave apparatuses A, B, and C, respectively.

  When a user operates an information processing apparatus connected to the network 9, if the operation target is the master apparatus 1, the operation information is directly grasped by the master apparatus 1. If the operation target is a slave device, the operation information is transmitted from the operated slave device to the master device 1. That is, regardless of whether the user's operation target is the master device 1 or the slave device, the operation information is always grasped by the master device 1. The operation information is transmitted, for example, by a software cell whose DMA command is an operation information transmission command.

  Then, the main processor 21-1 included in the information processing controller 11 in the master device 1 selects a function program to be executed according to the operation information. At that time, if necessary, the main processor 21-1 included in the information processing controller 11 in the master device 1 may transfer the main memory 26-1 from the external recording units 28-1 and 28-2 of the own device by the above method. However, another information processing device (slave device) may transmit the function program to the master device 1.

  In the function program, required specifications related to the device such as information processing device type ID, main processor or sub-processor processing capacity, main memory usage, and conditions related to the external recording unit required for each execution unit (see FIG. 4) Is defined).

  The main processor 21-1 included in the information processing controller 11 in the master device 1 reads out the above required specifications necessary for each function program. Also, the device information table of each information processing device is read by referring to the device information table recorded in the main memory 26-1 by the capability exchange program in advance. The device information here is information related to the main processor, sub-processor, main memory, and external recording unit.

  The main processor 21-1 included in the information processing controller 11 in the master device 1 sequentially compares the device information of each information processing device connected on the network 9 with the required specifications necessary for executing the function program. To do.

  For example, when the function program requires a recording function, only the information processing apparatus having the recording function is specified and extracted based on the information processing apparatus type ID. Furthermore, a slave device that can ensure the conditions regarding the processing capability of the main processor or sub processor, the amount of main memory used, and the external recording unit necessary for executing the function program is specified as an execution request candidate device. Here, when a plurality of execution request candidate devices are specified, one execution request candidate device is specified and selected from the candidate devices.

  When the slave device to be executed is specified, the main processor 21-1 included in the information processing controller 11 in the master device 1 sets the main memory included in the information processing controller 11 in the own device for the specified slave device. The device information table of the slave device recorded in 26-1 is updated.

  Further, the main processor 21-1 included in the information processing controller 11 in the master device 1 generates a software cell whose DMA command is a function program execution command, and the cell interface of the software cell needs a function program related to the function program. Sub-processor information and sandbox size (see FIG. 3) are set and transmitted to the slave device requested to execute.

  The slave device requested to execute the function program executes the function program and updates the device information table of the own device. At that time, if necessary, the main processor 21 included in the information processing controller in the slave device, from the external recording unit 28 of the own device to the main memory 26 by the above method, the function program and the sub-operation that operates in cooperation with the function program Load the processor program.

  When the necessary function program or the sub processor program that operates in cooperation with the function program is not recorded in the external recording unit 28 of the slave device requested to execute the function program, the other information processing apparatus The system may be configured to transmit the sub-processor program to the functional program execution request destination slave device.

  The sub-processor program can be executed by another information processing apparatus using the aforementioned load command and kick command.

  After the execution of the function program, the main processor 21 included in the information processing controller in the slave device that has executed the function program transmits an end notification to the main processor 21-1 included in the information processing controller 11 in the master device 1. At the same time, the device information table of the own device is updated. The main processor 21-1 included in the information processing controller 11 in the master device 1 receives the end notification and updates the device information table of the slave device that has executed the function program.

  The main processor 21-1 included in the information processing controller 11 in the master device 1 identifies itself as an information processing device that can execute the function program from the reference result of the device information table of the own device and the other device. There is also a case of selecting. In that case, the master device 1 executes the function program.

  In the example illustrated in FIG. 7, distributed processing when the user operates slave device A (information processing device 2) and another slave device B (information processing device 3) executes a function program corresponding to the operation. This will be described with reference to FIG.

  In the example illustrated in FIG. 8, when the user operates the slave device A, distributed processing of the entire network system including the slave device A starts. First, the slave device A transmits the operation information to the master device 1. (Step 81).

  The master device 1 receives the operation information (step 72), and further checks the operation state of each information processing device from the device information table of the own device and other devices recorded in the main memory 26-1 of the own device. An information processing apparatus capable of executing a function program corresponding to the received operation information is selected (step 73). In the illustrated example, the case where the slave device B is selected is shown.

  Next, the master device 1 requests the selected slave device B to execute the function program (step 74).

  The slave device B receives the execution request (step 95), and further executes the function program requested to be executed (step 96).

  As described above, by operating only one information processing apparatus, the user operates a plurality of information processing apparatuses 1, 2, 3, and 4 without operating other information processing apparatuses. The information processing apparatus 7 can be operated.

A-11. Specific examples of information processing apparatuses and systems Information processing apparatuses 1, 2, 3, 4 connected to each other via a network 9 perform information processing by the information processing controllers 11, 12, 13, 14 as described above. So long as it is basically any configuration. FIG. 9 shows a configuration example of the information processing apparatus.

  An example of the information processing apparatus 1 including the information processing controller 11 is a hard disk recorder. 10 and 11 show the hardware configuration and software configuration of the hard disk recorder shown in FIG. As a hardware configuration of the hard disk recorder, a hard disk is built in as the external recording unit 28-1 shown in FIG. 1, and DVD ± R / RW, CD ± R / RW, and the external recording unit 28-2 shown in FIG. The optical disc such as Bluray-Disc (registered trademark) is configured to be mounted, and the broadcast receiving unit 32-1 and the video input unit 33 are connected to the bus 31-1 connected to the bus 29-1 of the information processing controller 11. -1, an audio input unit 34-1, a video output unit 35-1, an audio output unit 36-1, an operation panel unit 37-1, a remote control light receiving unit 38-1, and a network connection unit 39-1.

  The broadcast receiving unit 32-1, the video input unit 33-1 and the audio input unit 34-1 receive a broadcast signal or input a video signal and an audio signal from the outside of the information processing apparatus 1, and each has a digital format of a predetermined format. Data is converted and sent to the bus 31-1 for processing by the information processing controller 11. The video output unit 35-1 and the audio output unit 36-1 process the video data and audio data sent from the information processing controller 11 to the bus 31-1, and convert them into digital data or analog signals. The remote control light receiving unit 38-1 receives a remote control (remote operation) infrared signal from the remote control transmitter 43-1.

  As shown in FIGS. 9 and 10, a monitor display device 41 and a speaker device 42 are connected to the video output unit 35-1 and the audio output unit 36-1 of the information processing apparatus (hard disk recorder) 1.

  The information processing apparatus 2 including the information processing controller 12 illustrated in FIG. 9 is also a hard disk recorder, and is configured in the same manner as the information processing apparatus 1 as indicated by reference numerals in parentheses in FIG. However, as shown in FIG. 9, the monitor display device and the speaker device are not connected to the information processing device (hard disk recorder) 2.

  As shown in FIG. 11, the software configuration of the information processing apparatuses (hard disk recorders) 1 and 2, that is, the information processing controllers 11 and 12, includes an MS manager and a capability exchange program as control programs, and video and audio as function programs. A program for recording, video / audio reproduction, material search and program recording reservation is provided, and a program for broadcast reception, video output, audio output, external recording unit input / output and network input / output is provided as a device driver.

  Another example of the information processing apparatus 3 including the information processing controller 13 is a PDA (Personal Digital Assistant). FIG. 12 shows a hardware configuration of the information processing apparatus 3 configured as a PDA. In the example shown in the figure, the external recording unit 28-5 shown in FIG. 1 is configured so that a memory card disk can be mounted, and a liquid crystal display is provided on a bus 51 connected to the bus 29-3 of the information processing controller 13. The unit 52, the audio output unit 53, the camera unit 54, the audio input unit 55, the keyboard unit 56, and the network connection unit 57 are connected.

  Note that the information processing controller 13 omitted in FIG. 1 includes a main processor 21-3, sub processors 23-7, 23-8, 23-9, a DMAC (direct memory access controller) 25-3, and a DC (disk controller). 27-3 and the bus 29-3, the main processor 21-3 has an LS (local storage) 22-3, and the sub processors 23-7, 23-8, 23-9 are LS (Local storage) 24-7, 24-8, 24-9 are provided.

  FIG. 13 shows a software configuration of the information processing apparatus (PDA) 3, that is, the information processing controller 13. As shown in the figure, the control program includes an MS manager and a capability exchange program, and the function program includes a video / audio recording, video / audio reproduction, a phone book, a word processor, a spreadsheet program, and a web browser, As device drivers, programs for video output, audio output, camera video input, microphone audio input, and network input / output are provided.

  The information processing apparatus 4 including the information processing controller 14 is a portable CD player. FIG. 14 shows a hardware configuration of the portable CD player. In the illustrated example, the portable CD player is configured such that a CD (Compact Disc) can be mounted as the external recording unit 28-6 shown in FIG. 1 and is connected to the bus 29-4 of the information processing controller 14. 61, a liquid crystal display unit 62, an audio output unit 63, an operation button unit 64, and a network connection unit 65 are connected.

  Note that the information processing controller 14 omitted in FIG. 1 includes a main processor 21-4, sub processors 23-10, 23-11, 23-12, DMAC 25-4, DC 27-4, and a bus 29-4. The main processor 21-4 has an LS 22-4, and each of the sub processors 23-10, 23-11, 23-12 has an LS 24-10, 24-11, 24-12.

  FIG. 15 shows a software configuration of the information processing apparatus (portable CD player) 4, that is, the information processing controller 14. As shown in the figure, the control program includes an MS manager and a capability exchange program, the function program includes a program for music playback, and the device driver includes a program for audio output, CD control, and network input / output. .

  In the network system illustrated in FIG. 9, the information processing apparatuses 1, 3, and 4 are connected to the network 9, the information processing apparatus 1 is a master device (MS status = 0), and the information processing apparatuses 3 and 4 are slaves. Assume that the device (MS status = 1) is set.

  In this state, when the information processing apparatus 2 is newly connected to the network 9, the MS manager executed by the main processor 21-2 included in the information processing controller 12 in the information processing apparatus 2 is The other information processing devices 1, 3 and 4 are inquired about the MS status, recognizes that the information processing device 1 already exists as a master device, and sets its own device (information processing device 2) as a slave device (MS status = Set to 1). Further, the information processing device 1 set as the master device collects device information of each device including the newly added information processing device 2 and updates the device information table in the main memory 26-1.

  In this state, a case where an operation for making a recording reservation for a 2-hour broadcast program is performed by the information processing apparatus (PDA) 3 as a slave apparatus by the user will be described below.

  In this case, the information processing apparatus (PDA) 3 which is a slave apparatus receives input of recording reservation information including information such as a recording start time, a recording end time, a recording target broadcast channel, and recording quality from the user, and the recording reservation information A software cell including a recording reservation command as a DMA command is generated and transmitted to the information processing apparatus 1 which is a master apparatus.

  The main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that has received the software cell whose DMA command is the recording reservation command reads out the recording reservation command and also stores the apparatus information table in the main memory 26-1. The information processing apparatus that can execute the recording reservation command is specified.

  First, the main processor 21-1 reads information processing device type IDs of the information processing devices 1, 2, 3, and 4 included in the device information table and can execute a function program corresponding to the recording reservation command. Extract the device. Here, the information processing apparatuses 1 and 2 having the information processing apparatus type ID indicating the recording function are identified as candidate apparatuses, and the information processing apparatuses 3 and 4 are excluded from the candidate apparatuses.

  Next, the main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that is the master apparatus refers to the apparatus information table, and the processing capability of the main processor or sub-processor of the information processing apparatuses 1 and 2 Then, information related to the apparatus such as information related to the main memory is read, and it is determined whether or not the information processing apparatuses 1 and 2 satisfy the required specifications necessary for executing the function program corresponding to the recording reservation command. Here, it is assumed that the information processing apparatuses 1 and 2 satisfy the required specifications necessary for executing the function program corresponding to the recording reservation command.

  Further, the main processor 21-1 refers to the device information table, reads out information related to the external recording unit of the information processing devices 1 and 2, and determines that the free capacity of the external recording unit is sufficient for executing the recording reservation command. Determine if you are satisfied. Since the information processing apparatuses 1 and 2 are hard disk recorders, the difference between the total capacity and the usage amount of the hard disks 28-1 and 28-3 corresponds to the respective free capacity.

  In this case, the free capacity of the hard disk 28-1 of the information processing apparatus 1 is 10 minutes in terms of recording time, and the free capacity of the hard disk 28-3 of the information processing apparatus 2 is 20 hours in terms of recording time. Suppose that

  At this time, the main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that is the master apparatus is an information processing apparatus that can secure a free space for two hours necessary for execution of the recording reservation command. Identifies as an execution request destination slave device.

  As a result, only the information processing device 2 is selected as the execution request destination slave device, and the main processor 21-1 included in the information processing controller 11 in the information processing device 1 that is the master device receives the information processing device operated by the user. The recording reservation command including the recording reservation information transmitted from 3 is transmitted to the information processing device 2 to request execution of the recording reservation of the broadcast program for 2 hours.

  Then, the main processor 21-2 included in the information processing controller 12 in the information processing apparatus 2 analyzes the recording reservation command and sends a function program necessary for recording from the hard disk 28-3 as an external recording unit to the main memory. 26-2, and recording is performed according to the recording reservation information. As a result, the video / audio data of the 2-hour broadcast program reserved for recording is recorded in the hard disk 28-3 of the information processing apparatus 2.

  As described above, also in the network system of the example of FIG. 9, the user operates only one information processing apparatus, and operates a plurality of information processing apparatuses 1, 2, 2 without operating other information processing apparatuses. 3 and 4 can be operated as one virtual information processing apparatus 7.

B. Use of some sub-processors by other units in the same information processing apparatus As described above, in a grid computing system, a plurality of information processing apparatuses connected to a network perform distributed processing through cooperative operations, thereby virtually Operates as a single device. Each information processing apparatus constituting the system includes an information processing controller. The information processing controller is equipped with one or more sub processors capable of executing a sub processor program developed on its own local memory, and a main processor that instructs the sub processor to execute the sub processor program.

  The individual information processing apparatuses connected to the network have different performance required for each assigned application, but it is expensive and difficult to manufacture information processing controllers having different numbers of sub-processors accordingly. Further, the processing load distributed to each information processing apparatus on the network is not uniform, and the number of sub-processors required by the information processing controller in the apparatus is not uniform. Therefore, there is an information processing controller in the information processing apparatus that does not use all the sub processors, that is, no information processing controller that does not use all the sub processors in order to realize the scheduled processing. Could end up.

  Within each information processing controller, the main processor manages resources such as surplus processing capacity of each sub processor and can execute multiple functions simultaneously, but it is not necessary to use all sub processors. Absent. The information processing controller can use some of the sub processors for other purposes. For example, the information processing controller can permit other information processing units in the same information processing apparatus to use the surplus sub processors.

  Therefore, in the second embodiment of the present invention, in each information processing apparatus constituting the network system, the information processing controller in the apparatus assists some information processing units in the same information processing apparatus with some sub-processors. It was made to use as a processor.

  An information processing controller having a surplus sub-processor makes it possible for other information processing units in the same information processing apparatus to use the surplus sub-processor in a simple procedure, thereby enabling effective use of resources and overall system performance. Leads to improvement.

  FIG. 16 shows the configuration of an information processing apparatus according to the second embodiment of the present invention. The illustrated apparatus includes an information processing controller 111 equipped with a main processor and one or more sub-processors, and an information processing unit 170. Each of the information processing controller 111 and the information processing unit 170 is preferably configured as a single integrated circuit. The information processing controller 111 and the information processing unit 170 are connected via an external bus 167 and a bus bridge 168. The bus bridge 168 has a protection mechanism 169. The purpose of the protection mechanism 169 is to determine permission / prohibition for an access request from another unit such as the information processing unit 170 to the information processing controller 111, and to protect the sub processor or the local storage in the information processing controller 111. .

  As will be described later, the information processing controller 111 lends a part of the sub processors to the information processing unit 170, and the information processing unit 170 executes the sub processor program by the sub processors in the information processing controller 111. The sub processor lending mentioned here includes both regular lending and temporary lending.

  First, regular lending will be explained. In other words, the normal lending is a case where the sub-processor that the information processing controller 111 in the information processing apparatus 101 lends to the information processing unit 170 has already been determined from the apparatus design stage. As a result, if the information processing unit 170 makes an access request to the information processing controller 111 according to a predetermined procedure, it is confirmed that permission is granted. Normal lending may be called static lending.

  The information processing controller 111 includes a main processor 121-1, a DMAC (direct memory access controller) 125-1 for accessing the main memory 126-1, and a DC (for accessing the external recording units 128-1 and 128-2). Disk controller) 127-1, a plurality of sub-processors 123-1, 123-2, 123-3, and an external bus IF (interface) 166.

  The main processor 121-1 performs schedule management of processing of the sub processor program or data by the sub processors 123-1 to 123-3 and general management in the information processing controller 111. Further, the sub processors 123-1 to 123-3 execute sub processor program or data processing in parallel and independently under the control of the main processor 121-1.

  The main processor 121-1 and each of the sub-processors 123-1 to 123-3 have dedicated LS (local storage) 122-1 and 124-1 to 123, respectively, and execute processing programs developed on the LS. can do. However, the sub-processors 123-1 to 123-3 can start, stop, and interrupt the execution of the processing program only by the start instruction, stop instruction, and interrupt instruction from the main processor 121-1.

  The DMAC 125-1 is a dedicated controller that performs an access operation without the intervention of the main processor 121-1, with respect to a program or data stored in the main memory 126-1 in the information processing apparatus 101 constituted by a DRAM or the like. The DC 127-1 controls the access operation to the external recording units 128-1 and 128-2 connected to the information processing controller 111.

  The external bus IF 166 accesses the information processing unit 170 connected to the information processing controller 111 via the bus bridge 168 and accepts access from the information processing unit 170.

  The main processor 121-1, the DMAC 125-1, the DC 127-1, the sub-processors 123-1 to 123-1, and the external bus IF 166 are interconnected by an internal bus 129-1 of the information processing controller 111.

  The information processing unit 170 is connected to the information processing controller 111 via the external bus IF 166, the external bus 167, the bus bridge 168, and the external bus IF 174, and operates as an external unit of the information processing controller 111. The information processing unit 170 may have the same multiprocessor configuration as the information processing controller 111, but is not limited to this, and need not have a multiprocessor configuration. In FIG. 16, a processor 171, a main memory 172, a DMAC 173, and an external bus IF 174 for connecting to the information processing controller 111 are provided for simplifying the drawing. In the present embodiment, it is assumed that the information processing unit 170 has insufficient processor processing capacity for the performance required for the assigned application.

  The information processing controller 111 and the information processing unit 170 are preferably connected via the external bus 167 and the bus bridge 168, but may be directly connected without using the bus bridge 168. The bus protocol of the external bus IF 166 in the information processing controller 111 and the bus protocol of the external bus IF 174 in the information processing unit 170 may be the same or different. The bus bridge 168 absorbs the difference in the bus protocol and realizes an interface between the buses.

  In the present embodiment, some of the sub processors in the information processing controller 111 are lent out to the information processing unit 170 via the external bus IF 166. The sub-processor program on the information processing unit 170 side is loaded into the local storage of the lent sub-processor, and the sub-processor is used by another unit by the sub-processor executing the sub-processor program.

  As described above, since the local storage of the sub processor is used by other units such as the information processing unit 170 via the external bus IF 166, the local storage of the sub processor that is not permitted to be used is protected from access by other units. There is a need to. In addition, it is necessary to protect the local storage of the sub processor that is permitted to be used by other units from being accessed from inside the information processing controller 111.

  The bus bridge 168 includes a protection mechanism 169 for protecting the local storage from access via the external bus 167 by the information processing unit 170. In the present embodiment, the protection mechanism 169 uses an address conversion table.

  The address conversion table is preferably arranged in the main memory 126-1, and as shown in Table 1 below, each local storage in the information processing controller 111 is divided and managed as an entry. Each entry of this table includes correspondence information between them for converting a virtual entry address into a physical entry address, information (valid bit) indicating validity / invalidity of the corresponding entry, attribute information of the corresponding entry, and the like. The physical entry address is unique information indicating the start address of the entry, and the virtual entry address is temporary information used when another unit accesses the entry. The address conversion table may include a virtual / physical entry size and a virtual / physical entry end address in addition to the virtual / physical entry address. A part of the address translation table may be inside the protection mechanism 169. In the case of normal or static lending, the correspondence between the physical entry address and the virtual entry address is basically determined from the design stage of the information processing apparatus 101. The attribute information includes read / write enabled, write prohibited, read / write prohibited, and the like.

  When the information processing unit 170 makes an access request to the information processing controller 111, the virtual entry address is used instead of the physical entry address. The access request may be accompanied by a virtual entry size and a virtual entry end address. The conversion from the physical entry address to the virtual entry address is performed by the protection mechanism 169. That is, the information processing unit 170 knows only the virtual entry address, and the information processing controller 111 does not need to disclose the physical entry address to other units, and the information processing controller 111 itself has safety and confidentiality. Can be high.

  When an access request to a certain virtual entry address is made from the information processing unit 170, the protection mechanism 169 refers to the address conversion table and refers to the valid bit of the virtual entry address to confirm whether the entry is valid. At this time, the virtual entry size and the virtual entry end address may be confirmed. If the entry is invalid, an address translation error is notified to the information processing unit 170, and access is denied. On the other hand, if the entry is valid, the attribute information included in the entry is confirmed. Further, if the attribute information indicates write prohibition, write access is rejected, if read prohibition indicates read access, read / write access is rejected.

  Information relating to protection such as an address conversion table is set by a resource management program executed by the main processor 121-1.

  The resource management program executed by the main processor 121-1 of the information processing controller 111 has a function of allocating one or more sub processors and the local storage (LS) in the sub processors for the information processing unit 170 to use. Have. The resource management program has a resource management table on the main memory 126-1, and holds information indicating which sub-processors can be used.

  For example, as shown in Table 2, the resource management table prepares an entry for each sub-processor in the information processing controller 111, and each entry has a sub-processor ID and availability information of the associated sub-processor. Then, the sub processors assigned for use by the information processing unit 170 (that is, lent to other units) are set to be unavailable.

  When a program or other unit in the main processor 121-1 executes a sub-processor program in the sub-processor in the information processing controller 111, it is necessary to first select the sub-processor. For this purpose, a sub processor selection request is transmitted to the resource management program executed by the main processor 121-1. When the resource management program receives the sub-processor selection request, the resource management program refers to the resource management table, and when the sub-processor requested for selection is unusable, it returns a message that the use is rejected. When the use is permitted, the resource management table is updated according to the end of the use. As described above, in the case of normal or static lending, if the information processing unit 170 transmits a sub-processor selection request to the information processing controller 111 as one of the determined procedures, the access is made. Will be allowed. The resource management program also manages the above-described address conversion table and appropriately sets each entry in the address conversion table. As a result, even when a program in the main processor 121-1 or a plurality of access request sources such as other units make an access request to the same virtual entry address, an access permission / rejection is appropriately returned and the entry is used. By updating the address conversion table according to the situation, the exclusivity of each entry is realized and access collision is avoided. The resource management table is preferably set by information given in advance at the time of activation, but may be rewritten by a user operation.

  The information processing controller 111 as a multiprocessor chip lends some sub processors to the information processing unit 170 via the external IF 166. The information processing unit 170 is an image processing chip, for example, and uses a sub processor lent out from the information processing controller 111 because the processor capacity is insufficient to realize a desired image processing performance.

  FIG. 17 illustrates a state where some of the sub processors 123-3 of the information processing controller 111 are lent to the information processing unit 170 in the information processing apparatus 101 illustrated in FIG. In the illustrated example, normal operations of the information processing controller 111 such as operating system, GUI processing, and game application execution are executed using resources other than the lent sub-processor 123-3. On the other hand, the information processing unit 170 executes image processing using the sub processor 123-3 lent out from the information processing controller 111 in addition to the resource of the unit itself.

  The information processing unit 170 can freely execute the sub processor program with the lent sub processor. That is, the sub processor program on the information processing unit 170 side is loaded into the local storage of the lent sub processor, and the sub processor executes the sub processor program. On the information processing controller 111 side, the lent sub-processor is not used.

  When the sub processor is lent out by the information processing controller 111, the information processing unit 170 is permitted to access the local storage. For example, as shown in FIG. 18, the local storage to which access is permitted is mapped on the address space of the information processing unit 170, and can be written and read by the processor 171 and the DMAC 173 of the information processing unit 170. The information processing unit 170 writes the sub processor program to be executed and data associated therewith to the local storage of the sub processor to be used.

  The information processing unit 170 can freely write to and read from the local storage of the lent sub-processor. FIG. 19 illustrates a state in which the information processing unit 170 accesses the local storage to which access is permitted in the information processing apparatus 101 illustrated in FIG. 16. However, the protection mechanism 169 in the bus bridge 168 performs memory protection for access from the information processing unit 170 and prohibits access to other than the lent local storage.

  The start and stop of the execution of the sub processor program by the sub processors 123-1 to 123-3 are triggered by an instruction from the main processor 121-1. In other words, only the main processor 121-1 can cause the sub-processors 123-1 to 123-3 to start executing the sub-processor program, and the information processing unit 170 cannot directly activate the sub-processor to be used.

  Therefore, the information processing unit 170 writes a specific value in an external bus interrupt signal, a specific register or a memory area that is permitted to be written for notification, and notifies the main processor 121-1. 121-1 is requested to start or stop the execution of the sub processor program by the sub processor. Then, the main processor 121-1 instructs the sub processor program execution start or stop of the sub processor in response to the execution start or stop notification. In this way, the main processor 121-1 always controls all sub-processors including those lent out in the information processing controller 111, so that the operation of the entire information processing controller 111 can always be ensured. Here, when the information processing unit 170 uses the sub processor in the information processing controller 111, the above-described virtual entry address, virtual entry size, or virtual entry end address is used.

  FIG. 20 illustrates a state in which the information processing unit 170 in the information processing apparatus 101 illustrated in FIG. 16 executes the sub processor program by the lent sub processor. The information processing unit 170 requests the main processor 121-1 to start execution by a notification means such as an interrupt. The main processor 121-1 receives this request and instructs the sub processor to start execution.

  When the execution of the sub processor program by the sub processor is finished, the sub processor notifies the information processing unit 170 of the end of the execution through the external bus IF 166 by an interrupt.

  FIG. 21 illustrates a state in which the interrupt generated from the sub processor 123-3 is transferred to the information processing unit 170 using the sub processor in the information processing apparatus 101 illustrated in FIG. The sub processor 123-3 notifies the information processing unit 170 that the execution of the sub processor program has ended.

  In this way, in each information processing apparatus constituting the network system, the information processing controller in the apparatus can realize a mechanism that allows some sub-processors to be used as auxiliary processors by other units in the same information processing apparatus. it can.

  According to the mechanism described above, the sub processor is used with a simple procedure. Since the sub processor is lent out statically, the scheduling load on the main processor 121-1 can be reduced.

  In addition, since the local storage of the sub processor is mapped to the bus address space of another unit that uses the sub processor, programming of the other unit is easy. That is, since the sub processor program and data can be easily transferred and the local storage can be polled, the degree of freedom in programming is high.

  Further, in the information processing apparatus 101 illustrated in FIG. 16, a network interface is not necessary for other units using the sub processor, and heavy protocol processing such as TCP / IP is not necessary. Therefore, the delay is small compared to the case where the sub processor is lent out via the network. In other words, since the program can be transferred and the result can be obtained in a short time, it is easy to use and the performance is improved by a small overhead. Further, when the information processing unit 170 uses the sub processor in the information processing controller 111, the information processing controller 111 recognizes and uses only the virtual entry address, the virtual entry size, or the virtual entry end address. It is not necessary to disclose the address, physical entry size, or physical entry end address to other units, and the safety and confidentiality of the information processing controller 111 itself can be increased. The correspondence between the virtual entry address and the physical entry address, the correspondence between the virtual entry size and the physical entry size, and the correspondence between the virtual entry end address and the physical entry end address are determined from the device design stage. There is also an effect that a communication protocol for establishing is unnecessary. The above is a description of the regular lending procedure.

  Hereinafter, a temporary lending procedure will be described. Temporary lending means that the sub processor that the information processing controller 111 in the information processing apparatus 101 lends to the information processing unit 170 is not determined at the apparatus design stage, and is dynamically changed according to the processing status of the entire apparatus. This is the case. Temporary lending may be called dynamic lending. Naturally, when the information processing unit 170 requests access to the information processing controller 111, there is a great possibility that it is not permitted.

  FIG. 22 shows the processing operation of the information processing unit 170 that requests the sub processor lending in the form of a flowchart. This processing operation is realized in a form in which the processor 171 in the information processing unit 170 executes a predetermined program.

  First, a sub processor rental request is transmitted via the external bus 167 to the information processing controller 111 that may have a surplus sub processor, and also the location in the I / O space to which the local storage is desired to be allocated (step S1). .

  This sub processor lending request command may be transmitted in a packet, or may be notified by interruption by writing the command in a memory area for communication with the information processing controller 111.

  Subsequently, a response to the lending request is received from the information processing controller 111 as the request destination (step S2).

  This response may be notified by an interruption from the information processing controller 111, or the information processing unit 170 may detect a specific address on the information processing controller 111 side by polling.

  Then, based on this response, it is determined whether or not the sub processor lending request is accepted from the information processing controller 111 (step S3).

  When the sub processor lending request is accepted, the I / O address designated by the lending request command is mapped to the address space in the information processing unit 170 (step S4). 23 and 24 show the state of the address space in the information processing unit 170 before and after the local storage is lent out.

  Here, the I / O address may be the same as the physical address of the information processing unit 170. In this case, mapping may simply mean that the software will use the physical address. Alternatively, the address conversion table may be rewritten to map the corresponding physical address to the virtual address space so that the software can use it. If there is a mechanism for mutually converting the I / O address and the physical address of the information processing unit 170, the mechanism is appropriately set so that the information processing unit 170 can access the I / O address of the lent local storage. To.

  On the other hand, if the sub processor lending request is rejected, a predetermined error process is performed (step S5), and then the entire process routine is terminated.

  FIG. 25 shows the processing operation in the information processing controller 111 requested to lend out the sub processor in the form of a flowchart. This processing operation is realized in a form in which the main processor 121-1 in the information processing controller 111 executes a predetermined program.

  When a sub processor lending request is received from the information processing unit 170 (step S11), the resource management table is referred to and it is checked whether there is a sub processor that is not reserved (step S12).

  If there is a non-reserved sub-processor, one of them is selected as a sub-processor to be lent (step S13). For example, in the case of a resource management table as shown in Table 3 below, among the three subprocessors with IDs 0 to 2, the subprocessor with ID2 is unused, so it is selected as a subprocessor to be lent.

  Then, the resource management table is rewritten as shown in Table 4, and the selected sub-processor is reserved for another unit, that is, the information processing unit 170 (step S14).

  Then, the I / O page table is rewritten so that the information processing unit 170 can access the local storage of the selected sub processor (step S15). It is assumed that the I / O address assigned to the local storage is designated by the information processing unit 170 by the lending request command.

  If necessary, the main page table used for internal address translation is rewritten so that the program on the information processing controller 111 cannot access the local storage of the selected sub-processor (step S16).

  On the other hand, when all the sub-processors are all reserved (step S12), the rejection is notified to the information processing unit 170 that is the request source (step S17).

  For example, when the information processing controller 111 includes three sub-processors 123-1 to 123-3 as shown in FIG. 16, these local storages are mapped to the physical address space as shown in FIG. . Then, at the stage where none of the sub-processors is lent out to the outside, these local storages are mapped to the virtual address space as shown in FIG. Thereafter, when the sub processor 123-3 is lent to the information processing unit 170, the local storage is removed from the virtual address space of the information processing controller 111 and mapped to the address space of the information processing unit 170, as shown in FIG. (See FIG. 24). The information processing controller 111 cannot access the local storage of the sub processor 123-3 that has disappeared from the virtual address space.

  FIG. 29 shows an operation sequence for the information processing unit 170 to cause the sub processor 123-3 of the information processing controller 111 to execute the sub processor program in the information processing apparatus 101 shown in FIG.

  The information processing unit 170 writes the sub processor program to be executed in the local storage 124-3 of the sub processor 123-3 and the data associated with the program (S21).

  After completing the writing of the sub processor program, the information processing unit 170 requests the main processor 121-1 of the information processing controller 111 to execute the sub processor program (S22).

  The main processor 121-1 having received the request instructs the sub-processor 123-3 to execute the program (S23).

  The sub processor 123-3 instructed to execute executes the sub processor program.

  When the execution is completed, an execution completion notification of the requested sub processor program is sent to the information processing unit 170 (S25). The above is a description of a temporary, that is, dynamic lending procedure. In the case of temporary or dynamic lending, there is an effect that permission / rejection of use of the sub-processor can be determined flexibly according to the processing status of the entire apparatus.

  The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiment without departing from the gist of the present invention.

  In the present specification, the embodiment of the present invention has been described by taking as an example the case where the sub processor is lent out between the information processing controller and the information processing unit connected via the external bus in the information processing apparatus. The gist of the invention is not limited to this. For example, when a surplus subprocessor is used among three information processing controllers or information processing units, or when a surplus subprocessor is used among a plurality of information processing devices connected via a network other than an external bus, for example. Even if it is performed, the present invention can be similarly applied.

  In short, the present invention has been disclosed in the form of exemplification, and the description of the present specification should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims section described at the beginning should be considered.

FIG. 1 is a diagram showing a configuration of a network system according to an embodiment of the present invention. FIG. 2 is a diagram for explaining an access procedure from the sub processor 23 to the main memory 24. FIG. 3 is a diagram illustrating a configuration example of the software cell. FIG. 4 is a diagram showing a data area of the software cell when the DMA command is a status return command. FIG. 5 is a diagram illustrating a state in which a plurality of information processing apparatuses operate as one virtual information processing apparatus. FIG. 6 is a diagram illustrating an example of a software configuration of the information processing controller. FIG. 7 is a diagram illustrating a state in which four information processing apparatuses operate as one virtual information processing apparatus. FIG. 8 is a diagram showing an example of distributed processing in the system shown in FIG. FIG. 9 is a diagram illustrating a specific example of each information processing apparatus and system. FIG. 10 is a diagram showing a hardware configuration of the hard disk recorder in FIG. FIG. 11 is a diagram showing a software configuration of the hard disk recorder in FIG. FIG. 12 is a diagram showing a hardware configuration of the PDA in FIG. FIG. 13 is a diagram showing a software configuration of the PDA in FIG. FIG. 14 is a diagram showing a hardware configuration of the portable CD player in FIG. FIG. 15 is a diagram showing a software configuration of the portable CD player in FIG. FIG. 16 is a diagram showing the configuration of the information processing apparatus 101 according to the second embodiment of the present invention. FIG. 17 is a diagram illustrating a state in which some of the sub processors 123-3 of the information processing apparatus 101 are lent to the information processing unit 170. FIG. 18 is a diagram showing a state of mapping on the address space of the information processing unit 170. FIG. 19 is a diagram illustrating a state in which the information processing unit 170 accesses a local storage to which access is permitted. FIG. 20 is a diagram illustrating a state in which the information processing unit 170 executes the sub processor program by the lent sub processor. FIG. 21 is a diagram illustrating a state in which an interrupt generated from a sub processor is transferred to the information processing unit 170 using the sub processor. FIG. 22 is a flowchart showing the processing operation of the information processing unit 170 that requests the sub processor to lend. FIG. 23 is a diagram showing the state of the address space in the information processing unit 170 before the local storage is lent out. FIG. 24 is a diagram illustrating a state of the address space in the information processing unit 170 after the local storage is lent out. FIG. 25 is a flowchart showing the processing operation in the information processing controller 111 requested to rent a sub processor. FIG. 26 is a diagram illustrating a physical address space of the information processing controller 111. FIG. 27 is a diagram illustrating a virtual address space of the information processing controller 111 before the sub processor is lent. FIG. 28 is a diagram showing a virtual address space of the information processing controller 111 after the sub processor is lent out. FIG. 29 is a diagram illustrating an operation sequence for the information processing unit 170 to cause the sub processor 123-3 of the information processing controller 111 to execute a program.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 11, 12 ... Information processing apparatus 20 ... Virtual information processing apparatus 30 ... Local network 40 ... Communication network 50 ... Server 60 ... Function information database 61 ... Software database 71 ... Information processing apparatus function database 72 ... Function database 73 ... Cooperation function Database 101 ... Information processing device 111 ... Information processing controller 121-1 ... Main processor 122-1 ... LS in main processor
123-1-3... Sub-processor 124-1-3.
125-1 ... DMAC
126-1 ... main memory 127-1 ... DC
128-1-2 ... External recording unit 166 ... External bus IF
167 ... External bus 168 ... Bus bridge 169 ... Protection mechanism 170 ... Information processing unit 171 ... Processor 172 ... Main memory 173 ... DMAC
174 ... External bus IF

Claims (19)

An information processing apparatus included in an information processing system in which a plurality of information processing apparatuses connected to a network performs distributed processing by cooperative operation,
An information processing controller comprising one or more sub-processors capable of executing a program expanded on its own local storage; and a main processor that instructs the sub-processor to execute the program;
An information processing unit in the information processing apparatus using a part of the sub processors in the information processing controller;
Address mapping means for mapping the local storage of the sub processor to be used to the address space of the information processing unit;
Sub processor program placement means for placing a sub processor program that the information processing unit requests the sub processor to execute on a local storage of the sub processor used by the information processing unit;
An information processing apparatus comprising: Determining a sub-processor to be used by the information processing unit based on surplus processing capability of each sub-processor;
The information processing apparatus according to claim 1. The main processor starts, stops, or interrupts the sub processor program execution of the sub processor in response to a sub processor program execution start request, an execution stop request, or an interrupt request from the information processing unit.
The information processing apparatus according to claim 1. An information processing controller comprising one or more sub-processors capable of executing a program expanded on its own local storage, and a main processor that instructs the sub-processor to execute the program,
Resource management means for managing each sub-processor;
Connection means for connecting an information processing unit using a part of the sub-processor;
Use subprocessor determination means for determining a subprocessor used by the information processing unit;
Sub processor program placement means for placing a sub processor program that the information processing unit requests the sub processor to execute on a local storage of the sub processor used by the information processing unit;
An information processing controller comprising: The resource management means manages surplus processing capacity of each sub-processor;
The usage sub-processor determining means determines a sub-processor to be used by the information processing unit based on surplus processing capability of each sub-processor.
The information processing controller according to claim 4. The main processor starts, stops, and interrupts the sub processor program execution of the sub processor in response to a sub processor program execution start request, execution stop request, or interrupt request from the information processing unit via the connection means. Do,
The information processing controller according to claim 4. Information processing using resources of an information processing controller having one or more sub processors capable of executing a sub processor program developed on its own local storage and a main processor that instructs the sub processor to execute the sub processor program A unit,
Connection means for connecting the information processing controller;
Address mapping means for mapping the local storage of the sub processor to be used to its own address space;
Sub-processor program placement means for placing a sub-processor program that requests execution of the sub-processor on the local storage of the sub-processor to be used;
Sub processor program execution request means for requesting the main processor to start, stop, or interrupt a sub processor program execution by a sub processor to be used;
An information processing unit comprising: A means for receiving an interrupt from a sub-processor to be used via the connection means;
The information processing unit according to claim 7. One or more sub-processors capable of executing a sub-processor program developed on its own local storage, and a sub-processor of a part of an information processing apparatus controller including a main processor that instructs the sub-processor to execute the sub-processor program The information processing controller for processing the information processing unit to use the information processing unit, and the control method of the information processing apparatus including the information processing unit,
A resource management step for managing each sub-processor;
A sub-processor determining step for determining a sub-processor used by the information processing unit;
A sub processor program placement step of placing a sub processor program that the information processing unit requests the sub processor to execute on a local storage of the sub processor used by the information processing unit;
An information processing apparatus control method comprising: In the resource management step, the surplus processing capacity of each sub-processor is managed,
In the use subprocessor determination step, a subprocessor to be used by the information processing unit is determined based on the surplus processing capability of each subprocessor.
The information processing apparatus control method according to claim 9. The main processor further includes a step of starting, stopping, or interrupting the sub processor program execution of the sub processor in response to a sub processor program execution start request, an execution stop request, or an interrupt request from the information processing unit.
The information processing apparatus control method according to claim 9. An address conversion step of converting an access request using a virtual address from the information processing unit to the local storage of the sub processor into a physical address of the local storage of the sub processor;
The information processing apparatus control method according to claim 9. A protection step for prohibiting unauthorized access to the local storage of each sub-processor;
The information processing apparatus control method according to claim 9. In the protection step, access from the information processing unit to a local storage of a sub processor that is not permitted to be used by the information processing unit is prohibited.
The information processing apparatus control method according to claim 13. In the protection step, access inside the information processing controller to the local storage of the sub processor used by the information processing unit is prohibited.
The information processing apparatus control method according to claim 13. Information for using resources of an information processing controller having one or more subprocessors capable of executing a subprocessor program developed on its own local storage and a main processor that instructs the subprocessor to execute the subprocessor program A method for controlling a processing unit,
An address mapping step for mapping the local storage of the sub processor to be used to its own address space;
A sub processor program placement step for placing a sub processor program for requesting execution of the sub processor on the local storage of the sub processor to be used;
A sub processor program execution requesting step for requesting the main processor to start, stop, or interrupt an execution of a sub processor program by a sub processor to be used;
An information processing unit control method comprising: A step of accepting an interrupt from a sub-processor to be used via the connection means;
The information processing unit control method according to claim 16. Information on one or more subprocessors capable of executing a subprocessor program developed on its own local storage and a subprocessor of a part of an information processing controller having a main processor that instructs the subprocessor to execute the subprocessor program A computer program described in a computer-readable format so as to execute processing for use by a processing unit on an information processing controller,
A resource management step for managing each sub-processor;
A sub-processor determining step for determining a sub-processor used by the information processing unit;
A sub processor program placement step of placing a processing sub processor program that the information processing unit requests the sub processor to execute on a local storage of the sub processor used by the information processing unit;
In response to the sub processor program execution start request, execution stop request, or interrupt request from the information processing unit, starting, stopping, or interrupting the sub processor program execution of the sub processor;
A computer program comprising: Processing for using resources of an information processing controller having one or more subprocessors capable of executing a subprocessor program developed on its own local storage and a main processor that instructs the subprocessor to execute the subprocessor program A computer program written in a computer readable format to execute on the information processing unit,
An address mapping step for mapping the local storage of the sub processor to be used to its own address space;
A sub processor program placement step for placing a sub processor program for requesting execution of the sub processor on the local storage of the sub processor to be used;
A sub processor program execution requesting step for requesting the main processor to start, stop, or interrupt an execution of a sub processor program by a sub processor to be used;
A computer program comprising:

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