KR20060071069A - Information processing apparatus, information processing method, information processing system, and computer program for information processing - Google Patents

Abstract

It is possible to reliably and effectively perform distributed processing corresponding to a user's operation between a plurality of information processing apparatuses connected via a network.

The information processing controllers 11, 12, 13, and 14 in the information processing apparatuses 1, 2, 3, and 4 are the main processor 21, the subprocessor 23, and the DMAC (direct memory access controller) 25, respectively. And DC (disk controller) 27 are connected via bus 29. The main processor 21 writes information on the operation state of the own device as the device information into the main memory 26 connected to the information processing controller, and responds to requests from other devices. The device information is transmitted to the other device. Thereby, the arbitrary information processing apparatus sees the operation | movement state of itself and another information processing apparatus, selects the information processing apparatus which runs the program corresponding to a user's operation, and makes the apparatus run the said program.

Information processing unit, information processing controller, main processor

Description

Information processing apparatus, information processing method, information processing system and computer program for information processing {INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING SYSTEM, AND COMPUTER PROGRAM FOR INFORMATION PROCESSING}

1 is a diagram illustrating an example of a network system of the present invention.

It is a figure used for description of the information processing controller with which the information processing apparatus of this invention is equipped.

3 is a diagram illustrating an example of a software cell.

4 is a diagram showing a data area of a software cell when the DMA command is a status return command.

5 is a diagram showing how a plurality of information processing apparatuses operate as one virtual information processing apparatus.

6 is a diagram illustrating an example of a software configuration of the information processing controller.

7 is a diagram showing how four information processing apparatuses operate as one virtual information processing apparatus.

FIG. 8 is a diagram illustrating an example of distributed processing in the system of FIG. 7.

9 is a diagram illustrating a specific example of each information processing apparatus and system.

FIG. 10 is a diagram illustrating a hardware configuration of the hard disk recorder in FIG. 9.

FIG. 11 is a diagram showing the software configuration of the hard disk recorder in FIG.

12 is a diagram illustrating a hardware configuration of the PDA in FIG. 9.

FIG. 13 is a diagram showing the software configuration of the PDA in FIG.

FIG. 14 is a diagram illustrating a hardware configuration of the portable CD player in FIG. 9.

FIG. 15 is a diagram showing the software configuration of the portable CD player in FIG.

16 is a diagram illustrating another example of the network system of the present invention.

It is a figure used for description of the information processing controller with which the information processing apparatus of this invention is equipped.

18 is a diagram illustrating an internal structure of a DMAC.

19 is a diagram showing a command / response structure in the information processing apparatus.

20 is a diagram illustrating a sequence when the subprocessor accesses the main memory.

21 is a diagram illustrating an internal structure of the work memory.

22 is a diagram illustrating an internal structure of a subprocessor.

Fig. 23 shows the internal structure of a control register.

It is a figure which shows the state in which several information processing apparatuses operate as one virtual information processing apparatus.

FIG. 25 is a diagram showing how four information processing apparatuses operate as one virtual information processing apparatus. FIG.

FIG. 26 is a diagram illustrating an example of distributed processing in the system of FIG. 25.

27 is a diagram illustrating a specific example of each information processing apparatus and system.

FIG. 28 is a diagram showing the hardware configuration of the hard disk recorder in FIG.

FIG. 29 is a diagram showing the software configuration of the hard disk recorder in FIG.

30 is a diagram illustrating a hardware configuration of the PDA in FIG. 27.

FIG. 31 is a diagram showing the software configuration of the PDA in FIG.

32 is a diagram illustrating a hardware configuration of the portable CD player in FIG. 27.

33 is a view showing the software configuration of the portable CD player in FIG. 27.

Explanation of symbols for the main parts of the drawings

9: network

1, 2, 3 and 4: information processing unit

11: information processing controller

21-1: main processor

23-1, 23-2, 23-3: Subprocessor

25-1: DMAC (Direct Memory Access Controller)

27-1: Disk Controller

[Patent Document 1] Japanese Patent Laid-Open No. 2002-342165

[Patent Document 2] Japanese Patent Laid-Open No. 2002-351850

[Patent Document 3] Japanese Patent Application Laid-Open No. 2002-358289

[Patent Document 4] Japanese Patent Application Laid-Open No. 2002-366533

[Patent Document 5] Japanese Patent Application Laid-Open No. 2002-366534

[Patent Document 6] US Patent 6,587,906

[Patent Document 7] US Patent 6,667,920

[Patent Document 8] US Patent 6,728,845

[Patent Document 9] US Patent Publication 2004-0039895

[Patent Document 10] US Patent Publication 2004-0054880

[Patent Document 11] US Patent Publication 2004-0098496

The present invention relates to an information processing apparatus, an information processing method, an information processing system, and a computer program for information processing.

In recent years, grid computing has attracted attention. Grid computing is a technique for cooperatively operating a plurality of information processing apparatuses connected to a network to realize high computational performance.

For example, Patent Document 1 (Japanese Patent Laid-Open Publication No. 2002-342165), Patent Document 2 (Japanese Patent Laid-Open Publication No. 2002-351850), Patent Document 3 (Japanese Patent Laid-Open Publication No. 2002-358289), Patent In Document 4 (Japanese Patent Laid-Open Publication No. 2002-366533) and Patent Document 5 (Japanese Patent Laid-Open Publication No. 2002-366534), by using a uniform modular structure, a common computing module, and a uniform software cell, It is disclosed to realize a computer architecture for high speed processing.

In addition, Patent Document 6 (US Patent 6,587,906), Patent Document 7 (US Patent 6,667,920), Patent Document 8 (US Patent 6,728,845), Patent Document 9 (US Patent Publication 2004-0039895), Patent Document 10 (US Patent Publication 2004- 0054880 and Patent Document 11 (U.S. Patent Application Publication No. 2004-0098496) disclose speeding up a process by operating a plurality of processors in an information processing apparatus independently and in parallel.

However, in a network system in which a plurality of information processing apparatuses are connected via a network, each information processing apparatus or, in order to execute a process corresponding to an operation of the user's network system in a distributed manner throughout the network system, or It is necessary for the information processing apparatus which manages a network system to grasp | ascertain the operation state of another information processing apparatus.

Therefore, this invention makes it possible to reliably and effectively perform such distributed processing among a plurality of information processing apparatuses connected via a network.

An information processing apparatus of the present invention is connected to another information processing apparatus via a network, and performs information processing in accordance with a predetermined command, wherein the information processing apparatus collects information on an operation state from the other information processing apparatus. Information processing that can execute the command by comparing the capability exchange means for creating the information table with the information on the resources required for the execution of the command when the command is generated and the information on the operation state of the device information table. And device specifying means for specifying the device.

In the information processing apparatus of the present invention having the above configuration, when this is connected to another information processing apparatus via a network, information about the operation state is collected from the other information processing apparatus to create an apparatus information table, and the predetermined When a command is generated, the information on the resources required for the execution of the command is compared with the information on the operation state of the device information table, so that the information processing device capable of executing the command is identified. In the distributed processing is surely and effectively executed.

[One. Basic configuration of network systems and information processing devices: Part 1]

1 shows an example of the network system of the present invention, in which a plurality of information processing apparatuses 1, 2, 3, and 4 are connected via a network 9.

(1-1.Information Processing Unit and Information Processing Controller)

The information processing apparatuses 1, 2, 3 and 4 are various AV (Audio and Visual) apparatuses and portable apparatuses which will be described later, respectively.

Referring to the information processing apparatus 1, the information processing apparatus 1 includes an information processing controller 11 as a computer function unit. The information processing controller 11 includes a main processor 21-1, subprocessors 23-1, 23-2, and 23-3, a DMAC (direct memory access controller) 25-1, and a DC (disk controller). 27-1.

The main processor 21-1 includes schedule management of execution (data processing) of the subprocessor programs by the subprocessors 23-1, 23-2, and 23-3, and the information processing controller 11 (information processing device). General management of (1)) is performed. However, in the main processor 21-1, a program other than the program for management can also be configured to operate. In that case, the main processor 21-1 also functions as a subprocessor. The main processor 21-1 has an LS (local storage) 22-1.

Although one subprocessor may be sufficient, Preferably it is multiple. This example is the case of plural numbers.

Each of the subprocessors 23-1, 23-2, and 23-3 executes the subprocessor program in parallel and independently under the control of the main processor 21-1 to process data. In some cases, the program in the main processor 21-1 may be configured to operate in cooperation with the subprocessor program in the subprocessors 23-1, 23-2 or 23-3. The functional program described later is also a program operating in the main processor 21-1. Each subprocessor 23-1, 23-2 and 23-3 also has LS (local storage) 24-1, 24-2 and 24-3.

The DMAC 25-1 accesses programs and data stored in the main memory 26-1 made of DRAM (dynamic RAM) or the like connected to the information processing controller 11, and the DC 27-1. Accesses the external memory units 28-1 and 28-2 connected to the information processing controller 11.

The external memory units 28-1 and 28-2 may be fixed disks (hard disks) or removable disks, and optical disks such as MO, CD ± RW, DVD ± RW, memory disks, and SRAM (static). Various things, such as RAM) and ROM, can be used. Therefore, the DC 27-1 is called a disk controller, but is an external memory unit controller.

As in the example of FIG. 1, the information processing controller 11 can be configured such that a plurality of external memory units 28 can be connected to the information processing controller 11.

The main processor 21-1, each of the subprocessors 23-1, 23-2, and 23-3, the DMAC 25-1, and the DC 27-1 are connected by the bus 29-1. do.

The information processing controller 11 is assigned, as an information processing device ID, an identifier that can uniquely identify the information processing apparatus 1 including the information processing controller 11 through the entire network.

Similarly, for the main processor 21-1 and each of the subprocessors 23-1, 23-2, and 23-3, identifiers that can be specified are assigned as the main processor ID and the subprocessor ID.

It is preferable to configure the information processing controller 11 as a one-chip IC (integrated circuit).

The other information processing apparatuses 2, 3, and 4 are similarly configured. Here, units with the same parent number are assumed to have the same function, even if the branch numbers are different, unless otherwise specified. In addition, when a branch number is abbreviate | omitted in the following description, it is assumed that the difference by a branch number does not generate | occur | produce.

(1-2. Access to main memory from each subprocessor)

As described above, each subprocessor 23 in one information processing controller independently executes a subprocessor program to process data, but different subprocessors simultaneously read or read the same area in the main memory 26. In the case of writing, data mismatch can occur. Therefore, access to the main memory 26 from the subprocessor 23 is performed in the following procedure.

As shown in FIG. 2A, the main memory 26 is constituted by a plurality of addressable memory locations 0 to M. For each memory location, additional segments 0 to M for storing information indicating the state of data are allocated. The additional segment is supposed to include the F / E bit, the subprocessor ID, and the LS address (local storage address). Each memory location is also assigned access keys 0 to M described later. The F / E bit is defined as follows.

The F / E bit = 0 indicates that data is being processed by the subprocessor 23 or invalid data which is not the latest data because it is empty, and thus cannot be read. F / E bit = 0 indicates that data can be written to the memory location, and is set to 1 after writing.

F / E bit = 1 indicates that the data of the corresponding memory location is not read by the subprocessor 23 and is the latest unprocessed data. The data at that memory location is readable and is set to zero after being read by the subprocessor 23. In addition, the F / E bit = 1 indicates that the memory location is impossible to write data.

Further, in the state of the F / E bit = 0 (non-read / write value), it is possible to set a read reservation for the memory location. When a read reservation is made to a memory location of F / E bit = 0, the subprocessor 23 adds the subprocessor ID of the subprocessor 23 as read reservation information to an additional segment of the memory location where the read reservation is made. And the LS address.

Subsequently, when the data is written to the memory location reserved for reading by the sub-processor 23 on the data writing side, and is set to F / E bit = 1 (read / write impossible), it is added as read reservation information in advance. The subprocessor ID written in the segment and the LS address are read.

When data needs to be processed in multiple stages by a plurality of sub-processors, the sub-processor 23 which performs the previous stage of processing by the sub-processor 23 performing the previous stages is controlled by controlling the read / write of the data of each memory location. Immediately after writing to a predetermined address in the memory 26, a separate subprocessor 23 which performs the processing of the next step becomes able to read the data after the previous processing.

As shown in FIG. 2B, the LS 24 in each subprocessor 23 is also composed of a plurality of addressable memory locations 0 to L. For each memory location, additional segments 0 to L are similarly allocated. The additional segment will contain busy bits.

When the subprocessor 23 reads data in the main memory 26 to the memory location of its LS 24, the busy bit corresponding to the memory location of the read destination is set to 1 and reserved. No other data can be stored in the memory location where the busy bit is one. After reading the memory location of the LS 24, the busy bit becomes zero and can be used for any purpose.

As shown in FIG. 2A, the main memory 26 further connected to each information processing controller includes a plurality of sandboxes. The sandbox defines an area in the main memory 26. Each sandbox is assigned to each subprocessor 23, and the subprocessor can be used exclusively. That is, each subprocessor 23 can use the sandbox assigned to itself, but cannot access data beyond this area.

The main memory 26 is composed of a plurality of memory locations, but the sandbox is a collection of these memory locations.

In addition, in order for the main memory 26 to realize exclusive control, a key management table as shown in Fig. 2C is used. The key management table is stored in a relatively high speed memory such as SRAM in the information processing controller and is associated with the DMAC 25.

In the key management table, there is an entry equal to the number of subprocessors in the information processing controller, and each entry is stored in association with the subprocessor ID, the subprocessor key and the key mask corresponding thereto.

The process when the subprocessor 23 uses the main memory 26 is as follows. First, the subprocessor 23 transmits a read or write command to the DMAC 25. This command includes its subprocessor ID and the address of the main memory 26 as the access request destination.

The DMAC 25 checks the subprocessor key of the subprocessor 23 of the access request source by referring to the key management table before executing this command. Next, the DMAC 25 compares the subprocessor key of the examined access request source with the access key assigned to the memory location shown in FIG. 2A in the main memory 26 serving as the access request destination, and the two keys match. Only execute the above command.

In the key mask on the key management table shown in Fig. 2C, the arbitrary bit becomes 1, so that the corresponding bit of the subprocessor key associated with the key mask can be 0 or 1.

For example, suppose the subprocessor key is 1010. Typically, this subprocessor key only allows access to a sandbox with an access key of 1010. However, when the key mask associated with this subprocessor key is set to 0001, only the number of digits in which the bit of the key mask is set to 1 is matched with the subprocessor key and the access key, and this subprocessor key is masked. The 1010 enables access to a sandbox having an access key whose access key is either 1010 or 1011.

As described above, the exclusivity of the sandbox of the main memory 26 is realized. In other words, when it is necessary to process data in multiple stages by a plurality of subprocessors in one information processing controller, by configuring as described above, only the subprocessor performing the previous stage processing and the subprocessor performing the subsequent stage processing. The predetermined address of the main memory 26 can be accessed, thereby protecting data.

For example, use as follows is considered. First, immediately after the start of the information processing apparatus, the values of the key masks are all zero. It is assumed that a program in the main processor is executed to cooperate with the subprocessor program in the subprocessor. When the processing result data executed by the first subprocessor is to be stored in the main memory 26 and transmitted to the second sub processor, the corresponding main memory area is naturally accessible from either subprocessor. Should be. In such a case, the program in the main processor appropriately changes the value of the key mask to provide a main memory area accessible from a plurality of subprocessors, thereby enabling multi-step processing by the subprocessor.

More specifically, when the multi-step process is performed in the order of data from another information processing apparatus → processing by the first subprocessor → processing by the first sub memory → processing by the second sub processor → second main memory area,

Subprocessor key of the first subprocessor: 0100,

Access key of the first main memory area: 0100,

Subprocessor key of the second subprocessor: 0101,

Access key of the second main memory area: 0101,

As described above, the second subprocessor cannot access the first main memory area. Therefore, by setting the key mask of the second subprocessor to 0001, it is possible to enable access to the first main memory area by the second subprocessor.

(1-3. Creating and Configuring Software Cells)

In the network system of FIG. 1, software cells are transmitted between the information processing devices 1, 2, 3, and 4 for distributed processing between the information processing devices 1, 2, 3, and 4. That is, the main processor 21 included in the information processing controller in any information processing apparatus generates a software cell containing a command, a program, and data, and transmits the same to another information processing apparatus via the network 9. Can be dispersed.

3 shows an example of the configuration of the software cell. The software cell of this example is entirely composed of a transmission source ID, a transmission destination ID, a response destination ID, a cell interface, a DMA command, a program, and data.

In the transmission source ID, the network address and information processing device ID of the information processing device which is the transmission source of the software cell, and the identifier of the main processor 21 and each subprocessor 23 included in the information processing controller in the information processing device (main Processor ID and subprocessor ID).

The transmission destination ID and the response destination ID each include the same information about the information processing device that is the destination of the software cell and the information processing device that is the destination of the execution result of the software cell.

The cell interface is information required for use of the software cell, and is composed of a global ID, information of a necessary subprocessor, a sandbox size, and a previous software cell ID.

The global ID can uniquely identify the corresponding software cell throughout the network, and is created based on the source ID and the date and time (date and time) of the creation or transmission of the software cell.

The number of subprocessors required is set to the number of subprocessors required for the execution of the software cell. The sandbox size is set in the amount of memory in the main memory 26 and the LS 24 of the subprocessor 23 necessary for the execution of the software cell.

The last software cell ID is an identifier of the previous software cell in a group of software cells that require sequential execution of streaming data or the like.

The execution section of the software cell is composed of DMA commands, programs and data. The DMA command includes a series of DMA commands necessary for starting the program, and the program includes a subprocessor program executed by the subprocessor 23. Data here is data processed by the program containing this subprocessor program.

The DMA command also includes a loading command, a kick command, a function program execution command, a status request command, and a status reply command.

The loading command is a command for loading information in the main memory 26 into the LS 24 in the subprocessor 23, and includes, in addition to the loading command itself, a main memory address, a subprocessor ID, and an LS address. The main memory address indicates an address of a predetermined area in the main memory 26 which is the source of loading of information. The subprocessor ID and the LS address indicate an identifier of the subprocessor 23 which is the loading destination of the information and the address of the LS 24.

The kick command is a command for starting execution of a subprocessor program and includes, in addition to the kick command itself, a subprocessor ID and a program counter. The subprocessor ID identifies the subprocessor 23 to be kicked, and the program counter gives an address for the subprocessor program execution program counter.

The function program execution command is a command for which an arbitrary information processing apparatus requests execution of a function program to another information processing apparatus as described later. The information processing controller in the information processing apparatus that receives the function program execution command identifies the function program to be started by the function program ID described later.

The status request command is a command for requesting transmission of device information relating to the current operating state (situation) of the information processing apparatus indicated by the transmission destination ID to the information processing apparatus indicated by the response destination ID. Although a functional program is mentioned later, it is a program classified as a functional program in the block diagram of the software which the main memory 26 of the information processing apparatus shown in FIG. 6 stores. The function program is loaded into the main memory 26 and executed by the main processor 21.

The status reply command is a command in which the information processing apparatus that has received the status request command responds to the information processing apparatus whose device information is indicated by the response destination ID included in the status request command. The status reply command stores the device information in the data area of the execution section.

4 shows the structure of the data area of the software cell when the DMA command is a status return command.

The information processing apparatus ID is an identifier for identifying the information processing apparatus provided with the information processing controller, and represents the ID of the information processing apparatus which transmits the status reply command. When the power is turned on, the information processing device ID is set by the main processor 21 included in the information processing controller in the information processing device to the network address of the information processing device and the information processing controller in the information processing device. It is generated based on the number of subprocessors 23 included and the like.

The information processing apparatus type ID includes a value indicating a characteristic of the information processing apparatus. The characteristics of the information processing apparatus are, for example, a hard disk recorder, a PDA (Personal Digital Assistants), a portable CD (Compact Disc) player, and the like described later. In addition, the information processing apparatus type ID may represent the function of an information processing apparatus, such as video audio recording and video audio reproduction. The value indicating the feature or function of the information processing device is determined in advance, and the feature or function of the information processing device can be grasped by reading the information processing device type ID.

The MS (master / slave) status indicates whether the information processing device is operating as a master device or a slave device as described later. When this is set to 0, it indicates that it is operating as a master device. If set, this indicates that the device is operating as a slave device.

The main processor operating frequency represents the operating frequency of the main processor 21 in the information processing controller. The main processor utilization rate represents the utilization rate in the main processor 21 for all programs currently operating by the main processor 21. The main processor utilization rate is a value representing the ratio of the processing power in use to the total processing power of the target main processor, and is calculated as a unit, for example, MIPS, which is a unit for evaluating processor processing power, or in processor usage time per unit time. Calculated on the basis of The same applies to the subprocessor utilization rate described later.

The number of subprocessors represents the number of subprocessors 23 included in the information processing controller. The subprocessor ID is an identifier for identifying each subprocessor 23 in the information processing controller.

The subprocessor status indicates the state of each subprocessor 23, and there are states such as unused, reserved, and busy. unused indicates that the subprocessor is not currently being used or reserved for use. reserved indicates a state in which use is reserved although not currently used. busy indicates that it is currently in use.

The subprocessor utilization rate represents the utilization rate in the subprocessor for a subprocessor program currently being executed by the subprocessor or for which execution is reserved for the subprocessor. In other words, the subprocessor utilization rate indicates the current utilization rate when the subprocessor status is busy, and the estimated utilization rate that will be used later when the subprocessor status is reserved.

The subprocessor ID, the subprocessor status, and the subprocessor usage rate are set one set for one subprocessor 23, and are set by the number of sets of the number of subprocessors 23 in one information processing controller.

The main memory total capacity and the main memory usage amount represent the total capacity of the main memory 26 connected to the information processing controller and the capacity currently being used, respectively.

The number of external memory sections indicates the number of external memory sections 28 connected to the information processing controller. The external memory unit ID is information for uniquely identifying the external memory unit 28 connected to the information processing controller. The external memory unit type ID indicates the type of the external memory unit (for example, hard disk, CD ± RW, DVD ± RW, memory disk, SRAM, ROM, and the like).

The external memory unit total capacity and the external memory unit usage amount represent the total capacity of the external memory unit 28 identified by the external memory unit ID and the capacity currently being used, respectively.

The external memory section ID, the external memory section type ID, the external memory section total capacity, and the external memory section usage are set one set for one external memory section 28, and are connected to the information processing controller. Is set by the number of sets. That is, when a plurality of external memory units are connected to one information processing controller, each external memory unit is assigned a different external memory unit ID, and the external memory unit type ID, external memory unit total capacity, and external memory unit usage are also separately. Managed separately.

(1-4. Execution of the software cell)

The main processor 21 included in the information processing controller in the arbitrary information processing apparatus generates a software cell having the above-described configuration and transmits it to the other information processing apparatus and the information processing controller in the apparatus via the network 9. . The information processing apparatus of a transmission source, the information processing apparatus of a transmission destination, the information processing apparatus of a response destination, and the information processing controller in each apparatus are respectively identified by the said transmission source ID, a transmission destination ID, and a response destination ID.

The main processor 21 included in the information processing controller in the information processing apparatus that has received the software cell stores the software cell in the main memory 26. The main processor 21 of the transmission destination reads the software cell and processes the DMA commands included therein.

Specifically, the main processor 21 of the transmission destination first executes a loading command. As a result, information is loaded from the main memory address indicated by the loading command to a predetermined region of the LS 24 in the subprocessor specified by the subprocessor ID and the LS address included in the loading command. The information loaded here is a subprocessor program or data included in the received software cell, or other indicated data.

Next, the main processor 21 transmits the kick command to the subprocessor indicated by the subprocessor ID included therein, together with the program counter included in the kick command.

The indicated subprocessor executes the subprocessor program in accordance with the kick command and the program counter. After the execution result is stored in the main memory 26, the main processor 21 is notified that the execution is completed.

In addition, the processor which executes a software cell in the information processing controller in the information processing apparatus of a transmission destination is not limited to the subprocessor 23, The main memory program, such as a function program which the main processor 21 contains in a software cell, It is also possible to specify to run.

In this case, the information processing apparatus of the transmission source includes, in the information processing apparatus of the transmission destination, a main memory program and data processed by the main memory program instead of the subprocessor program, and the DMA command is a loading command. The cell is transmitted so that the main memory 26 stores the main memory program and the data processed by it.

Subsequently, the information processing apparatus of the transmission source, to the information processing apparatus of the transmission destination, a main processor ID for the information processing controller in the information processing apparatus of the transmission destination, a main memory address, a function program ID to be described later for identifying a program for the main memory, and the like And a program counter, the DMA command transmits a software cell which is a kick command or a function program execution command, and causes the main processor 21 to execute the main memory program.

As described above, in the network system of the present invention, the information processing apparatus of the transmission source transmits the subprocessor program or the main memory program to the information processing apparatus of the transmission destination by the software cell, and transmits the subprocessor program information of the transmission destination. The subprocessor 23 included in the information processing controller in the processing apparatus can be loaded, and the subprocessor program or the main memory program can be executed by the information processing apparatus of the transmission destination.

In the information processing controller in the information processing apparatus of the transmission destination, when the program included in the received software cell is a subprocessor program, the subprocessor program is loaded into the designated subprocessor. Then, the subprocessor program or the main memory program included in the software cell is executed.

Therefore, even if the user does not operate the information processing apparatus of the transmission destination, the subprocessor program or the main memory program can be automatically executed by the information processing controller in the information processing apparatus of the transmission destination.

In this way, when the information processing controller in the own apparatus does not have a main memory program such as a subprocessor program or a function program, the information processing apparatus can acquire them from another information processing apparatus connected to the network. have. In addition, data is transmitted between the subprocessors and the main memory by the DMA method, and by using the above-described sandbox, even if it is necessary to process data in multiple stages in one information processing controller, Security can be performed.

[2. Distributed Processing Part as Network System: 1]

As a result of the distributed processing by using the software cell, as shown in the upper end of FIG. 5, the plurality of information processing apparatuses 1, 2, 3, and 4 connected to the network 9 are shown in the lower end of FIG. 5. Similarly, it operates as one virtual information processing apparatus 7. However, for that purpose, the following processes need to be performed with the following structures.

(2-1.System Configuration and Program Loading)

6 shows a configuration of software stored in the main memory 26 of each information processing controller. These software (programs) are recorded in the external memory unit 28 connected to the information processing controller before power is supplied to the information processing apparatus.

Each program is classified into a control program, a function program, and a device driver by a function or a feature.

The control program is provided with the same information processing controllers, and is executed by the main processor 21 of each information processing controller, and includes an MS (master / slave) manager and a capability exchange program described later.

The function program is executed by the main processor 21, and the one corresponding to the information processing apparatus is provided for each information processing controller, such as for recording, reproducing, and material searching.

The device driver is provided for the input / output (transmission / reception) of the information processing controller (information processing apparatus) and corresponds to the information processing apparatus for each information processing controller such as broadcast reception, monitor output, bit stream input / output, network input / output, and the like.

When the information processing device is physically connected to the network 9 by the insertion of a cable or the like, the main power is supplied to the information processing device, and the information processing device is electrically and functionally connected to the network 9. The main processor 21 of the information processing controller of the processing apparatus loads each program belonging to the control program and each program belonging to the device driver into the main memory 26.

As the loading order, the main processor 21 first executes a read command to the DC 27 to read a program from the external memory unit 28 and then executes a write command to the DMAC 25. The program is written to the main memory 26.

Each program belonging to the functional program may be configured to load only necessary programs when necessary, or similarly to programs belonging to other categories, each program may be loaded immediately after the main power is turned on.

Each program belonging to the functional program does not need to be recorded in the external memory unit 28 of all the information processing apparatuses connected to the network, and if it is recorded in the external memory unit 28 of any one of the information processing apparatuses, Since it can be loaded from another information processing apparatus by one method, as a result, as shown at the bottom of FIG. 5, a functional program can be executed as one virtual information processing apparatus 7.

In addition, as described above, the functional program processed by the main processor 21 may cooperate with the subprocessor program processed by the subprocessor 23 in some cases. Therefore, when the main processor 21 reads the function program from the external memory unit 28 and writes it to the main memory 26, when there is a subprocessor program which cooperates with the target function program, The subprocessor program is also written in the same main memory 26. In this case, although there may be one subprocessor program which cooperates, there may exist several. In the case of plural numbers, all the subprocessor programs which operate in association are written into the main memory 26.

The subprocessor program written in the main memory 26 is then written into the LS 24 in the subprocessor 23 and cooperatively operates with the function program processed by the main processor 21.

As shown in the software cell of Fig. 3, an identifier capable of uniquely identifying a program for each program is assigned to the functional program as the functional program ID. The function program ID is determined from the creation date, the information processing apparatus ID, and the like in the step of creating the function program.

The subprocessor program ID is also assigned to the subprocessor program, whereby the subprocessor program can be uniquely identified. The subprocessor program ID to be allocated may be an identifier associated with the function program ID of the function program to be associated with the cooperative operation, for example, the function program ID is the parent number and the branch number is added at the end. For example, the identifier may be irrelevant to the function program ID of the function program that is the partnering operation.

In either case, when the functional program and the subprocessor program cooperate with each other, it is necessary to store the program ID, which is the identifier of the counterpart, in the own program. Even when a function program cooperates with a plurality of subprocessor programs, the function program stores all the subprocessor program IDs of the plurality of subprocessor programs.

The main processor 21 secures an area in the main memory 26 for storing device information (information on the operating state) of the information processing apparatus in which the main processor 21 operates, and records the information as the device information table of the own apparatus. do. The device information here is each information below the information processing device ID shown in FIG.

(2-2. Determination of Master / Slave in the System)

In the above-described network system, when the main power is supplied to any information processing apparatus, the main processor 21 of the information processing controller of the information processing apparatus supplies a master / slave manager (hereinafter referred to as MS manager) to the main memory 26. Load in and run

When the MS manager detects that the information processing apparatus on which it operates is connected to the network 9, the MS manager confirms the existence of another information processing apparatus connected to the same network 9. Here, "connection" or "existence" indicates that the information processing apparatus is not only physically connected to the network 9 but also electrically and functionally connected to the network 9 as described above.

In the following, the information processing apparatus on which it operates is called a child apparatus, and another information processing apparatus is called another apparatus. The device also refers to the information processing device.

The method by which the MS manager confirms the existence of another information processing apparatus connected to the same network 9 is shown below.

The MS manager generates a software cell in which the DMA command is a status request command, the sender ID and the destination ID are not specified in the information processing apparatus, and does not specify the sender ID, and transmits it on the network to which the information processing apparatus is connected. Set the timer for checking network connection. The timeout time of the timer is, for example, 10 minutes.

When another information processing apparatus is connected on the network system, the other apparatus receives a software cell of the status request command and issues a DMA to the information processing apparatus that issues a status request command specified by the response destination ID. The command is a status reply command and transmits a software cell containing device information of itself (other device) as data. The software cell of the status reply command includes at least information (information processing device ID, information on the main processor, information on the subprocessor, etc.) identifying the other device, and the MS status of the other device.

The MS manager of the information processing device which issued the status request command monitors the reception of the software cell of the status reply command sent from another device on the network until the network connection confirmation timer times out. As a result, when a status reply command indicating MS status = 0 (master device) is received, the MS status in the device information table of the own device is set to one. As a result, the device becomes a slave device.

On the other hand, when the status reply command is not received at all until the network connection confirmation timer is timed out, or when the status reply command indicating MS status = 0 (master device) is not received, The MS status in the device information table is set to zero. As a result, the device becomes a master device.

In other words, when no device is connected to the network 9 or no master device is present on the network 9, when a new information processing device is connected to the network 9, the device is automatically connected. It is set as a master device. On the other hand, when a new information processing apparatus is connected to the network 9 in a state where a master apparatus already exists on the network 9, the apparatus is automatically set as a slave apparatus.

In either of the master device and the slave device, the MS manager periodically monitors the status of other devices by sending status request commands to other devices on the network 9 to inquire the status information. As a result, the main power supply of the information processing device connected to the network 9 is cut off, or the information processing device is disconnected from the network 9, so that a status reply command is issued from a specific other device within a predetermined period set for determination in advance. When there is a change in the connection state of the network 9, such as when no reply is made or when a new information processing device is connected to the network 9, the information exchange program is notified of the information.

(2-3. Acquisition of Device Data in Master Device and Slave Device)

The main processor 21 executes the capability exchange program when the MS manager receives notification of the inquiry of other devices on the network 9 and the completion of setting of the MS status of the own device.

When the own device is the master device, the capability exchange program acquires device information of all other devices connected to the network 9, that is, device information of each slave device.

Acquiring the device information of the other device, as described above, generates a software cell whose DMA command is a status request command and transmits it to the other device, after which the DMA command is a status reply command and the device of the other device as data. It is possible by receiving a software cell containing information from another device.

Similar to the device information table of the child device which is the master device, the capability exchange program has an area for storing device information of all other devices (each slave device) connected to the network 9, and the main memory 26 of the child device. Is secured to the device information table as a device information table of another device (slave device).

That is, in the main memory 26 of the master device, device information of all information processing devices connected to the network 9 including the child device is recorded as the device information table.

On the other hand, when the child device is a slave device, the capability exchange program acquires device information of all other devices connected to the network 9, that is, device information of each slave device other than the master device and the child device. The information processing device ID and the MS status contained in the device information are recorded in the main memory 26 of the own device.

That is, in the main memory 26 of the slave device, the device information of the child device is recorded as a device information table, and the master device and the information processing device for each slave device connected to the network 9 other than the child device. The ID and MS status are recorded as separate device information tables.

In addition, in either of the master device and the slave device, the capability exchange program receives the device information of the information processing device when it is notified from the MS manager that the information processing device is newly connected to the network 9 as described above. Acquired and recorded in the main memory 26 as described above.

The MS manager and the capability exchange program are not limited to being executed by the main processor 21 but may be executed by any subprocessor 23. The MS manager and the capability exchange program are preferably resident programs that always operate while the main power supply of the information processing apparatus is turned on.

(2-4. When the information processing device is cut off from the network)

In either of the master device and the slave device, the capability exchange program, as described above, the main power supply of the information processing device connected to the network 9 is cut off from the MS manager, or the information processing device from the network 9. When it is notified that is separated, the device information table of the information processing device is deleted from the main memory 26 of the child device.

In addition, when the information processing apparatus cut | disconnected from the network 9 is a master apparatus, a master apparatus is newly determined by the following method.

Specifically, for example, the information processing apparatus not disconnected from the network 9 replaces the information processing apparatus IDs of the own apparatus and the other apparatus with numerical values, respectively, and replaces the information processing apparatus ID of the own apparatus with the information of the other apparatus. Compared with the processing device ID, when the information processing device ID of the own device is the minimum among the information processing fields not cut off from the network 9, the slave device moves to the master device and sets the MS status to 0. As the master device, as described above, device information of all other devices (each slave device) connected to the network 9 is acquired and recorded in the main memory 26.

(2-5. Distributed Processing Based on Device Information)

As shown in the lower part of Fig. 5, in order to operate the plurality of information processing apparatuses 1, 2, 3, and 4 connected to the network 9 as one virtual information processing apparatus 7, the master apparatus is a user. It is necessary to grasp the operation and operation status of the slave device.

7 shows how four information processing apparatuses operate as one virtual information processing apparatus 7. It is assumed that the information processing apparatus 1 is operating as the master apparatus, and the information processing apparatuses 2, 3, and 4 are slave apparatuses A, B, and C. FIG.

When the user operates the information processing apparatus connected to the network 9, if the operation target is the master device 1, the operation information is directly grasped by the master device 1, and the operation target is the slave device. The operation information is transmitted from the operated slave device to the master device 1. That is, regardless of whether the operation target of the user is either the master apparatus 1 or the slave apparatus, the operation information is always grasped in the master apparatus 1. The operation information is transmitted by, for example, a software cell in which the DMA command is an operation information transmission command.

And the main processor 21-1 contained in the information processing controller 11 in the master apparatus 1 selects the function program to run according to the operation information. At that time, if necessary, the main processor 21-1 included in the information processing controller 11 in the master device 1 may use the external memory unit 28-1 or 28-2 of the child device by the above method. The function program is loaded from the main memory 26-1 to the main memory 26-1, but another information processing device (slave device) may transmit the function program to the master device 1.

The functional program includes information on the apparatus such as the information processing apparatus type ID shown as each information shown in FIG. 4 required for each execution unit, processing capacity of the main processor or subprocessor, main memory usage, and conditions relating to the external memory unit. Requirement specifications are specified.

The main processor 21-1 included in the information processing controller 11 in the master device 1 reads out the above-mentioned specification required for each function program. Further, the device information of each information processing device is read with reference to the device information table recorded in the main memory 26-1 by the capability exchange program in advance. The device information herein indicates information below the information processing device ID shown in FIG. 4 and is information about a main processor, a subprocessor, a main memory, and an external memory unit.

The main processor 21-1 included in the information processing controller 11 in the master device 1 includes the device information of each information processing device connected on the network 9 and the above-mentioned information required for executing a function program. Compare the requirements specification sequentially.

For example, when the function program requires a recording function, only the information processing device having a recording function is identified and extracted based on the information processing device type ID. Further, a slave device capable of securing the processing capacity of the main processor or subprocessor, the main memory usage, and the external memory unit necessary to execute the function program is specified as the execution request candidate device. Here, when a plurality of execution request candidate devices are specified, one execution request candidate device is specified and selected from the candidate device.

When the slave device requesting execution is specified, the main processor 21-1 included in the information processing controller 11 in the master device 1, to the specified slave device, the information processing controller 11 in the child device. The device information table of the corresponding slave device recorded in the main memory 26-1 included in is updated.

In addition, the main processor 21-1 included in the information processing controller 11 in the master device 1 generates a software cell in which the DMA command is a function program execution command, and generates a software cell at the cell interface of the software cell. The required subprocessor information and sandbox size (see Fig. 3) related to the function program are set, and transmitted to the slave device requested to be executed.

The slave device requested to execute the function program executes the function program and updates the device information table of the own device. At that time, if necessary, the main processor 21 included in the information processing controller in the slave device is configured to perform a function program and the corresponding function program from the external memory unit 28 of the child device to the main memory 26 by the above-described method. Load a subprocessor program that operates in association.

If the necessary function program or the subprocessor program cooperatively operating with the function program is not recorded in the external memory unit 28 of the slave device that is requested to execute the function program, the other information processing apparatus may execute the function program or sub. The system may be configured to transmit the processor program to the functional program execution request slave device.

The subprocessor program may be executed by another information processing apparatus using the above-described loading command and kick command.

After the execution of the function program is finished, the main processor 21 included in the information processing controller in the slave device which executed the function program sends a termination notification to the main processor 21 included in the information processing controller 11 in the master device 1. -1) and the device information table of the own device is updated. The main processor 21-1 included in the information processing controller 11 in the master device 1 receives the end notification and updates the device information table of the slave device that executed the function program.

The main processor 21-1 included in the information processing controller 11 in the master device 1 is an information processing device capable of executing the corresponding function program from the reference result of the device information table of the own device and the other device. There may be times when you choose yourself. In that case, the master device 1 executes the function program.

In the example of FIG. 7, a case where a user operates slave device A (information processing device 2), and another slave device B (information processing device 3) executes a function program corresponding to the operation. 8 shows an example of the above dispersion processing.

In the example of FIG. 8, when the user operates the slave device A, distributed processing of the entire network system including the slave device A starts, and the slave device A first transmits the operation information to the master device 1 in step 81. Send to

In step 72, the master device 1 receives the operation information and proceeds to step 73, from the device information table of the child device and the other device recorded in the main memory 26-1 of the child device, The operation state of each information processing apparatus is examined to select an information processing apparatus capable of executing a function program corresponding to the received operation information. This example is a case where the slave device B is selected.

Next, in step 74, the master device 1 requests execution of a function program for the selected slave device B. FIG.

In step 95, the slave device B receives the execution request, and proceeds to step 96 to execute the execution requested function program.

As described above, the user operates only one information processing apparatus so that the plurality of information processing apparatuses 1, 2, 3, and 4 are virtually operated by one information processing apparatus 7 without operating the other information processing apparatus. Can be operated as.

(2-6. Specific example of each information processing apparatus and system)

The information processing apparatuses 1, 2, 3, and 4 interconnected via the network 9 basically perform information processing by the information processing controllers 11, 12, 13, and 14 as described above. Although one may be sufficient, the example is shown in FIG.

In this example, the information processing apparatus 1 including the information processing controller 11 is a hard disk recorder, as shown in FIG. 10, and as the hardware configuration, the external memory unit 28-1 shown in FIG. 1. ), A hard disk is built in, and an optical disk such as DVD ± R / RW, CD ± R / RW, Blu-rayDisc (registered trademark) or the like is mounted as the external memory unit 28-2 shown in FIG. In addition, the broadcast receiving unit 32-1, the video input unit 33-1, and the audio input unit 34 are connected to the bus 31-1 connected to the bus 29-1 of the information processing controller 11. -1), the video output unit 35-1, the audio output unit 36-1, the operation panel unit 37-1, the remote control light receiving unit 38-10 and the network connection unit 39-1 are connected. .

The broadcast receiving unit 32-1, the video input unit 33-1, and the audio input unit 34-1 receive a broadcast signal or input a video signal and an audio signal from the outside of the information processing apparatus 1, Each is converted into digital data of a predetermined format and sent to the bus 31-1 for processing by the information processing controller 11, and the video output unit 35-1 and audio output unit 36-1 To process the video data and audio data transmitted from the information processing controller 11 to the bus 31-1, convert them as digital data or convert them into analog signals and send them to the outside of the information processing apparatus 1. The remote control light receiving unit 38-1 receives the remote control (remote operation) infrared signal from the remote control transmitter 43-1.

9 and 10, the monitor display device 41 and the speaker device are provided in the video output unit 35-1 and the audio output unit 36-1 of the information processing apparatus (hard disk recorder) 1. 42 is connected.

The information processing apparatus 2 provided with the information processing controller 12 of the example of FIG. 9 is also a hard disk recorder, Comprising: Like the information processing apparatus 1, as shown with the reference number in brackets in FIG. will be. For example, as shown in FIG. 9, the monitor display device and the speaker device are not connected to the information processing device (hard disk recorder) 2.

As a software configuration of the information processing apparatuses (hard disk recorders) 1 and 2, that is, the information processing controllers 11 and 12, as shown in FIG. 11, the control program includes an MS manager and a capability exchange program, and functions. As a program, a program for video audio recording, video audio playback, location search, and program recording reservation is provided. As a device driver, a program for broadcast reception, video output, audio output, external memory input / output, and network input / output is provided. .

In the example of FIG. 9, the information processing apparatus 3 including the information processing controller 13 is a personal digital assistant (PDA). As shown in FIG. 12, the external memory shown in FIG. 1 is a hardware configuration. The unit 28-5 is configured to mount a memory card disk, and to the bus 51 connected to the bus 29-3 of the information processing controller 13, the liquid crystal display unit 52 and audio output. The unit 53, the camera unit 54, the audio input unit 55, the keyboard unit 56, and the network connection unit 57 are connected.

In addition, the information processing controller 13 which abbreviate | omitted the inside in FIG. 1 is the main processor 21-3, the subprocessors 23-7, 23-8, and 23-9, DMAC (direct memory access controller) 25 -3), DC (disk controller) 27-3, and bus 29-3, and the main processor 21-3 has LS (local storage) 22-3, and each The subprocessors 23-7, 23-8 and 23-9 have LS (local storage) 24-7, 24-8 and 24-9.

As the software configuration of the information processing apparatus (PDA) 3, that is, the information processing controller 13, as shown in FIG. 13, the control program is provided with an MS manager and a capability exchange program, and is a video and audio function as a function program. It has a program for recording, video audio playback, phone book, word processor and table calculation, and Web browser, and as a device driver, it has a program for video output, audio output, camera video input, microphone audio input and network input / output. do.

The information processing apparatus 4 provided with the information processing controller 14 of the example of FIG. 9 is a portable CD player, and as shown in FIG. 14, as a hardware structure, the external memory part 28- shown in FIG. 6), a CD (Compact Disc) can be mounted, and a liquid crystal display 62 and an audio output unit (B) 61 are connected to a bus 61 connected to the bus 29-4 of the information processing controller 14. 63), the operation button portion 64 and the network connection portion 65 are connected.

In addition, the information processing controller 14 which abbreviate | omitted the inside in FIG. 1 is the main processor 21-4, the subprocessors 23-10, 23-11, and 23-12, DMAC (direct memory access controller) 25 -4), a DC (disk controller) 27-4, and a bus 29-4, and the main processor 21-4 has an LS (local storage) 22-4, and each The subprocessors 23-10, 23-11, and 23-12 have LS (local storage) 24-10, 24-11, and 24-12.

As the software configuration of the information processing apparatus (portable CD player) 4, that is, the information processing controller 14, as shown in FIG. 15, the control program includes an MS manager and a capability exchange program, and as a function program, A program for music reproduction is provided, and as a device driver, a program for audio output, CD control, and network input / output is provided.

In the network system of the example of FIG. 9 described above, the information processing apparatuses 1, 3, and 4 are connected on the network 9, and the information processing apparatus 1 is a master apparatus (MS status = 0). It is assumed that the information processing apparatuses 3 and 4 are set as slave devices (MS status = 1).

In this state, when the information processing apparatus 2 is newly connected to the network 9, the main processor 21-2 included in the information processing controller 12 in the information processing apparatus 2 by the above-described method. The MS manager executed by the MS inquires the MS status to the other information processing apparatuses 1, 3, and 4, recognizes that the information processing apparatus 1 already exists as a master apparatus, and recognizes the child apparatus (information processing apparatus ( 2)) to the slave device (MS status = 1). In addition, the information processing apparatus 1 set in the master apparatus collects device information of each apparatus including the newly added information processing apparatus 2 and updates the apparatus information table in the main memory 26-1. do.

In this state, it shows the case where the recording reservation operation of the broadcast program for 2 hours is performed by the information processing apparatus (PDA) 3 which is a slave device by the user.

In this case, the information processing device (PDA) 3, which is a slave device, receives an input of recording reservation information including information such as recording start time, recording end time, recording target broadcast channel, recording quality, and the like from the user. A software cell containing the recording reservation information and the recording reservation command as the DMA command is generated and transmitted to the information processing device 1 which is the master device.

The main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that receives the software cell in which the DMA command is the recording reservation command reads the recording reservation command, and the main memory 26 reads the recording reservation command. With reference to the device information table in -1), an information processing device capable of executing the corresponding recording reservation command is specified.

First, the main processor 21-1 reads the information processing apparatus type ID of each of the information processing apparatuses 1, 2, 3, and 4 included in the device information table, and executes a function program corresponding to the recording reservation command. Extract possible information processing devices. Here, information processing apparatuses 1 and 2 having an information processing apparatus type ID indicating a recording function are specified as candidate apparatuses, and information processing apparatuses 3 and 4 are excluded from the candidate apparatuses.

Next, the main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that is the master device refers to the device information table, and the main processor of the information processing apparatuses 1 and 2 or Whether the information processing apparatuses 1 and 2 satisfy the requirement specification required for the execution of the function program corresponding to the recording reservation command by reading information about the apparatus such as the processing capacity of the subprocessor and the information about the main memory. Judge. Here, it is assumed that both the information processing apparatuses 1 and 2 satisfy the requirement specification required for the execution of the function program corresponding to the recording reservation command.

In addition, the main processor 21-1 reads the information about the external memory units of the information processing apparatuses 1 and 2 with reference to the device information table, so that the free space of the external memory unit is used to execute the recording reservation command. It is determined whether the required dose is satisfied. Since the information processing apparatuses 1 and 2 are hard disk recorders, the difference between the total capacity and the usage amount of the hard disks 28-1 and 28-3 corresponds to the respective blank capacities.

In this case, the free space of the hard disk 28-1 of the information processing device 1 is 10 minutes in terms of recording time, and the free space of the hard disk 28-3 of the information processing device 2 is recorded. Let's say it's 20 hours.

At this time, the main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that is the master device can secure a free space for two hours necessary for the execution of the recording reservation command. The information processing apparatus is identified as the execution request destination slave apparatus.

As a result, only the information processing device 2 is selected as the execution request destination slave device, and the main processor 21-1 included in the information processing controller 11 in the information processing device 1 as the master device is selected by the user. The recording reservation command including the recording reservation information transmitted from the operated information processing apparatus 3 is transmitted to the information processing apparatus 2, and the execution of the recording reservation of the two-hour broadcast program is requested.

Then, the main processor 21-2 included in the information processing controller 12 in the information processing apparatus 2 interprets the recording reservation command and transmits a function program necessary for recording to the hard disk 28-3, which is an external memory unit. ) Is loaded into the main memory 26-2, and recording is performed in accordance with the recording reservation information. As a result, the video and audio data of the broadcast program of two hours of recording reservation is recorded on the hard disk 28-3 of the information processing apparatus 2.

Thus, even in the network system of the example of FIG. 9, a user operates only one information processing apparatus, and virtually operates the several information processing apparatuses 1, 2, 3, and 4, without operating another information processing apparatus. It can operate as one information processing apparatus 7.

[3. Basic configuration of network systems and information processing devices: Part 2]

16 shows another example of the network system of the present invention, in which a plurality of information processing apparatuses 1001, 1002, 1003, and 1004 are connected through a network 1009. FIG.

(3-1.Information Processing Unit and Information Processing Controller)

The information processing apparatuses 1001, 1002, 1003, and 1004 are various AV (Audio and Visual) devices and portable devices as described later, respectively.

Referring to the information processing apparatus 1001, the information processing apparatus 1001 includes an information processing controller 1011 as a computer function unit. The information processing controller 1011 includes a main processor 1021-1, subprocessors 1023-1, 1023-2, and 1023-3, a direct memory access controller (DMAC) 1025-1, and a control register 1028-. 1), work memory 1029-1, and DC (disk controller) 1030-1.

The main processor 1021-1 includes schedule management of execution (data processing) of the subprocessor programs by the subprocessors 1023-1, 1023-2, and 1023-3, and an information processing controller 1011 (information processing device). (1001), overall management is performed. However, a program other than the program for management may be configured to operate in the main processor 1021-1. In that case, the main processor 1021-1 also functions as a subprocessor. The main processor 1021-1 has LS (local storage) 1022-1.

Although one subprocessor may be sufficient, Preferably it is multiple. This example is the case of plural numbers.

Each subprocessor 1023-1, 1023-2, and 1023-3 executes a subprocessor program in parallel and independently under the control of the main processor 1021-1 to process data. In some cases, the program in the main processor 1021-1 may be configured to operate in cooperation with the subprocessor program in the subprocessors 1023-1, 1023-2, or 1023-3. The functional program described later is also a program operating in the main processor 1021-1. Each subprocessor 1023-1, 1023-2, and 1023-3 also has LS (local storage) 1024-1, 1024-2, and 1024-3.

The DMAC 1025-1 includes a main memory 1026-1 made of DRAM (dynamic RAM) and the like and a sub memory 1027-1 made of SRAM (static RAM) and the like connected to the information processing controller 1011, respectively. It is for accessing programs and data stored in. By interposing the DMAC 1025-1, data transfer can be performed between the subprocessors and the main memory 1026-1 by the DMA system, thereby achieving high speed.

The control register 1028-1 determines which subprocessor processes which subprocessor program to be processed in the information processing controller 1011, and which of the following processing threads described below exist in the subprocessor. In addition, it is used to manage the progress of the subprocessor program execution by the subprocessor.

The work memory 1029-1 is a work memory composed of SRAM or the like included in the information processing controller 1011, and includes a main processor 1021-1 and subprocessors 1023-1, 1023-2, and 1023-3. Is accessed by

The DC 1030-1 accesses the external memory units 1031-1 and 1031-2 connected to the information processing controller 1011.

The external memory units 1031-1 and 1031-2 may be fixed disks (hard disks) or removable disks, and optical disks such as MO, CD ± RW, DVD ± RW, memory disks, and SRAM (static). Various things, such as RAM) and ROM, can be used. Therefore, although DC1030-1 is called a disk controller, it is an external memory part controller.

As in the example of FIG. 16, the information processing controller 1011 can be configured such that a plurality of external memory units 1031 can be connected to the information processing controller 1011.

Main processor 1021-1, each subprocessor 1023-1, 1023-2 and 1023-3, DMAC 1025-1, control register 1028-1, work memory 1029-1, and DC 1030-1 is connected by a bus 1032-1.

The information processing controller 1011 is assigned, as an information processing device ID, an identifier that can uniquely identify the information processing apparatus 1001 including the information processing controller 1011 through the entire network.

Similarly, for the main processor 1021-1 and each of the subprocessors 1023-1, 1023-2, and 1023-3, identifiers that can be specified are assigned as the main processor ID and the subprocessor ID.

The information processing controller 1011 is preferably configured as a single chip IC (integrated circuit).

The other information processing apparatuses 1002, 1003, and 1004 are similarly configured. Here, units with the same parent number are assumed to have the same function, even if the branch numbers are different, unless otherwise specified. In addition, when a branch number is abbreviate | omitted in the following description, it is assumed that the difference by a branch number does not generate | occur | produce.

(3-2. Access to main memory from each subprocessor)

As described above, each subprocessor 1023 in one information processing controller independently executes a subprocessor program to process data, but different subprocessors simultaneously read or read the same area in the main memory 1026. In the case of writing, data mismatch can occur. Therefore, access to the main memory 1026 from the subprocessor 1023 is performed in the following procedure.

Similarly with respect to the sub memory 1027 and the work memory 1029, different sub-processors are considered to access the same area at the same time, but the main memory 1026 is shown here.

As shown in FIG. 17A, the main memory 1026 is composed of a plurality of addressable memory locations 0 to N. For each memory location, additional segments 0 to N for storing information indicating the state of data are allocated. The additional segment is supposed to include the F / E bit, the subprocessor ID, and the LS address (local storage address). Each memory location is also assigned access keys 0 to N described later. The F / E bit is defined as follows.

The F / E bit = 0 indicates that data is being processed by the subprocessor 1023 or invalid data that is not the latest data because it is in an empty state and cannot be read. F / E bit = 0 indicates that data can be written to the memory location, and is set to 1 after writing.

F / E bit = 1 indicates that the data of the memory location is not read by the subprocessor 1023 and is the latest unprocessed data. The data in that memory location is readable and is set to zero after being read by the subprocessor 1023. In addition, the F / E bit = 1 indicates that the memory location is impossible to write data.

Further, in the state of the F / E bit = 0 (non-read / write value), it is possible to set a read reservation for the corresponding memory location. When a read reservation is made to a memory location of F / E bit = 0, the subprocessor 1023 adds the subprocessor ID of the subprocessor 1023 as read reservation information to an additional segment of the memory location where the read reservation is made. And the LS address.

Thereafter, when the data is written to the memory location reserved for reading by the subprocessor 1023 on the data writing side, and is set to F / E bit = 1 (read / write impossible), it is added as read reservation information in advance. The subprocessor ID written in the segment and the LS address are read.

When it is necessary to process data in multiple stages by a plurality of subprocessors, the subprocessor 1023 which performs the previous stage of processing by the sub-processor 1023 which performs the previous stages of the process by controlling the read / write of the data of each memory location in this way. Immediately after writing to the predetermined address in the memory 1026, a separate subprocessor 1023 which performs the processing of the next step becomes able to read the data after the previous processing.

As shown in FIG. 17B, the LS 1024 in each subprocessor 1023 is also configured by a plurality of addressable memory locations 0 to L. For each memory location, additional segments 0 to L are similarly allocated. The additional segment will contain busy bits.

When the subprocessor 1023 reads the data in the main memory 1026 to the memory location of its LS 1024, the busy processor corresponding to the memory location of the read destination is set to 1 and reserved. No other data can be stored in the memory location where the busy bit is one. After reading into the memory location of the LS 1024, the busy bit becomes 0, which can be used for any purpose.

As shown in FIG. 17A, the main memory 1026 further connected to each information processing controller includes a plurality of sandboxes. The sandbox defines an area in the main memory 1026, and each sandbox is assigned to each subprocessor 1023 so that the subprocessor can be used exclusively. That is, each subprocessor 1023 can use the sandbox assigned to itself, but cannot access data beyond this area.

The main memory 1026 is composed of a plurality of memory locations 0 to N, but the sandbox is a collection of these memory locations. That is, one sandbox is composed of one or a plurality of memory locations.

In addition, in order to realize exclusive control of the main memory 1026, a key management table as shown in Fig. 17C is used. The key management table is stored in a relatively high speed memory such as SRAM in the information processing controller and is associated with the DMAC 1025. However, the key management table may be stored in the work memory 1029.

In the key management table, there are entries equal to the number of subprocessors in the information processing controller, and each entry is stored in association with the subprocessor ID, the subprocessor key and the key mask corresponding thereto.

The process when the subprocessor 1023 uses the main memory 1026 is as follows. First, the subprocessor 1023 transmits a read or write command to the DMAC 1025. This command includes its subprocessor ID and an address in the main memory 1026 that is the access request destination.

Before executing this command, the DMAC 1025 checks the subprocessor key of the subprocessor 1023 of the access request source by referring to the key management table. Next, the DMAC 1025 compares the subprocessor key of the examined access request source with the access key assigned to the memory location shown in FIG. 17A in the main memory 1026 serving as the access request destination, and the two keys match. Only in case of executing the above command.

In the key mask on the key management table shown in Fig. 17C, any of the bits becomes 1, so that the corresponding bit of the subprocessor key associated with the key mask can be 0 or 1.

For example, suppose the subprocessor key is 1010. Typically, this subprocessor key only allows access to a sandbox with an access key of 1010. However, when the key mask associated with this subprocessor key is set to 0001, only the number of digits in which the bit of the key mask is set to 1 is matched with the subprocessor key and the access key, and this subprocessor key is masked. The 1010 enables access to a sandbox having an access key whose access key is either 1010 or 1011.

In this manner, the exclusivity of the sandbox of the main memory 1026 is realized. In other words, when it is necessary to process data in multiple stages by a plurality of subprocessors in one information processing controller, by configuring as described above, only the subprocessor performing the previous stage and the subprocessor performing the subsequent stage The predetermined address in the main memory 1026 can be accessed, thereby protecting data.

For example, use as follows is considered. First, immediately after the start of the information processing apparatus, the values of the key masks are all zero. It is assumed that a program in the main processor is executed to cooperate with the subprocessor program in the subprocessor. When the processing result data executed by the first subprocessor is to be stored in the main memory 1026 and transmitted to the second subprocessor, the corresponding main memory area is naturally accessible from either subprocessor. Should be. In such a case, the program in the main processor appropriately changes the value of the key mask to provide a main memory area that can be accessed from the plurality of subprocessors, thereby enabling multi-step processing by the subprocessor.

More specifically, when the multi-step processing is performed in the order of data from another information processing apparatus → processing by the first subprocessor → processing by the first sub memory → processing by the second sub processor → second main memory area. ,

Subprocessor key of the first subprocessor: 0100,

Access key of the first main memory area: 0100,

Subprocessor key of the second subprocessor: 0101,

Access key of the second main memory area: 0101,

As described above, the second subprocessor cannot access the first main memory area. Therefore, by setting the key mask of the second subprocessor to 0001, it is possible to enable access to the first main memory area by the second subprocessor.

(3-3. Access to main memory and sub memory from each sub processor)

Each subprocessor 1023 in one information processing controller can be read or written in the sub memory 1027 in the same manner as in the main memory 1026. However, some kinds of commands are considered for the command. Some may have priority. So, below, each subprocessor 1023 shows the structure and order for using the main memory 1026 and the sub memory 1027 correctly.

As shown in FIG. 18, the DMAC 1025 has a main memory control register 1033 and a sub memory control register 1034 therein. The main memory control register 1033 is for accessing the main memory 1026, and the sub memory control register 1034 is for accessing the sub memory 1027.

The main memory control register 1033 is composed of the following four blocks, and each stores a command for accessing the main memory 1026 as follows.

First, a plurality of commands having high priority are stored in the command block. The command is processed first.

The normal command block 1 stores a plurality of normal commands, and the normal command block 2 also stores a plurality of normal commands. Although there is no functional difference between the normal command block 1 and the normal command block 2, for example, the command before execution of access to the main memory 1026 is stored in one block, and the command after execution is stored in the other block. By doing so, there is an effect that the commands before execution and after execution can be processed intensively and continuously, respectively.

In the order command block, a plurality of commands to be processed in the correct order are stored. In other words, the commands from the subprocessors 1023 are stored together with the subprocessor IDs of the subprocessors of the command sender in the received order. As a result, the commands can be processed in the received order, and the execution results can be returned to the command sender subprocessor in the same order.

The sub memory control register 1034 is also composed of the following four blocks, and each stores a command for accessing the sub memory 1027 as follows.

First, a plurality of commands having high priority are stored in the command block. The command is processed first.

A plurality of read commands is stored in the read command block, and a plurality of write commands are stored in the write command block.

Although an attempt was made to access an arbitrary area in the sub memory 1027, the standby command block stores a plurality of commands in which the target area is locked and cannot be accessed. Upon unlocking, the command first moves to the command block.

Each subprocessor 1023 accesses the main memory 1026 or the sub memory 1027 by, for example, a command having a structure as shown in FIG. 19. The response of the execution result from the main memory 1026 or the sub memory 1027 after the access execution also has the same structure.

In this command / response structure, the command types are read and write. The priority command identifier indicates that the command is a high priority command. The normal command identifier is at the time of access to the main memory 1026, and indicates that the command is stored in the normal command block 1 or the normal command block 2.

The chain command identifier is also at the time of access to the main memory 1026, and indicates that the command requires continuous access with the command immediately before or after it. Alternatively, the serial number of consecutive command strings may be used. The command in which the chain command identifier is set is stored in the order command block, but the priority of the processing is first higher than the command in the command block.

The address here represents an address in the main memory 1026 or the sub memory 1027 for executing a command. Alternatively, the address may be an address in the work memory 1029.

The subprocessor identifier is a subprocessor ID of the subprocessor of the command transmission source. The processing thread identifier is an identifier of a processing thread, which will be described later, from the command sender.

OK / NG indicates the success / failure of the command. The data herein is read data included in the response at the time of executing the read command, or data written in the command at the time of executing the write command.

As shown in FIG. 18, in the DMAC 1025, the main memory control register 1033 and each subprocessor 1023 for accurately accessing the main memory 1026 to each of the above-described subprocessors 1023 are provided. In addition to the sub memory control register 1034 for accurately accessing the sub memory 1027, the main processor 1021 may store a plurality of read commands and write commands for accessing the main memory 1026 or the sub memory 1027, respectively. The read command block 1035 for the main processor and the write command block 1036 for the main processor may be provided. The address conversion register 1037 will be described later.

When the plurality of subprocessors transmit the memory access commands having the same priority to the DMAC 1025 at the same timing, the following procedure is assumed. In other words, the DMAC 1025 has a pointer indicating the last subprocessor that has successfully accessed the memory. When the DMAC 1025 receives memory access commands having the same priority from the plurality of subprocessors at the same timing, the DMAC 1025 has a higher value than the pointer. It is assumed that this larger command and the difference with the pointer have the smallest priority. In this case, the next largest pointer value is assumed to be the smallest pointer value.

(3-4. Access to sub memory for accurate access to main memory from each sub processor)

The main memory 1026 made of DRAM and the like, and the sub memory 1027 made of SRAM and the like, of course, differ in structure of each element, so that their purpose of use is also different.

Therefore, as an example of a method of using the main memory 1026 and the sub memory 1027 in combination, the sub memory 1027 is responsible for address translation when each sub processor 1023 accesses the main memory 1026. Is considered. The structure and procedure for that are shown using FIG.

As described above, the main memory 1026 is configured by a plurality of memory locations, and one sandbox is configured by one or a plurality of memory locations. Each subprocessor 1023 can exclusively use the sandbox assigned to itself.

For example, as illustrated in FIG. 20A, it is assumed that sandboxes 1, 2, and 3 in the main memory 1026 are allocated to an arbitrary subprocessor 1023. It is assumed that sandbox 1 is 0x800 to 0x8FF, sandbox 2 is 0x200 to 0x2FF, sandbox 3 is 0xF00 to 0xFFF, and each sandbox is identified by the head address. In other words, the sandboxes to be allocated may not have consecutive addresses.

The subprocessor 1023 first accesses the address conversion register 1037 in the DMAC 1025 when reading data from the sandboxes 1, 2, and 3.

The address translation register 1037 is a register that associates the subprocessor 1023 with the sandbox assigned to the subprocessor 1023 and is composed of an entry equal to the number of the subprocessors 1023. It is assumed here that the entry indicated by Q1 corresponds to the subprocessor 1023.

At this time, the subprocessor 1023 reads the value of Q1 corresponding to itself. Further, data 0x20 is read from the first address in the sub memory 1027, which is indicated by the read value Q1 (0x80).

The area of the sandbox 1 is specified based on the value of Q1. For example, a value obtained by multiplying the value of Q1 by 16 times indicates the head address of sandbox 1, and a value obtained by adding 255 to the head address indicates the end address of sandbox 1. Therefore, as described above, when the value of Q1 is 0x80, the area of the sandbox 1 is 0x800 to 0x8FF.

Further, the subprocessor 1023 reads data 0xF0 from the second address in the same sub memory 1027, which is represented by the data 0x20 read from the first address.

The area of the sandbox 2 is specified based on the data read out from this second address. Specifically, similarly to sandbox 1, a value 16 times the value of data read from the second address indicates the head address of sandbox 2, and a value obtained by adding 255 to the head address indicates the end address of sandbox 2. . Therefore, when the data read out from the second address is 0xF0 as described above, the area of the sandbox 2 is 0x200 to 0x2FF.

Further, the subprocessor 1023 reads data 0x00 from the third address in the same sub memory 1027 indicated by the data 0xF0 read from the second address. 0x00 indicates the end of the assigned sandbox.

The area of the sandbox 3 is specified based on the data read out from this third address. Specifically, similarly to sandboxes 1 and 2, a value 16 times the value of data read from the third address indicates the head address of sandbox 3, and a value obtained by adding 255 to the head address is the end address of sandbox 3 Indicates. Therefore, when the data read out from the third address is 0x00 as described above, the area of the sandbox 3 is 0xF00 to 0xFFF.

As described above, each subprocessor 1023 can accurately access the assigned sandbox even if the address of the sandbox assigned to it is discontinuous, and can reliably read data from the assigned sandbox.

Next, the same subprocessor 1023 writes data to a new sandbox in the main memory 1026 and sends the sandbox to a sandbox group managed by the entry corresponding to itself in the address translation register 1037. The procedure for adding is shown using FIG. 20B.

It is assumed that the subprocessor 1023 has written data in the sandbox 4 which is an area of 0x000 to 0x0FF in the main memory 1026. At this time, the subprocessor 1023 first reads the value of Q1 (the initial value of Q1, for example, 0x80 as described above).

Subsequently, the subprocessor 1023 writes a value (0x80) of Q1 that has been read first to an address in the sub memory 1027 that can identify the sandbox 4 into which data is newly written. For example, since data is written in the area of 0x000 to 0x0FF at this time, the value (0x80) of Q1 is written to the address in the sub memory 1027 indicated by 0x00 divided by 16 as the head address 0x000. Further, the address 0x00 in the sub memory 1027 in which the value of Q1 (0x80) is written is written to Q1 in the address conversion register 1037 as the value of the new Q1.

As described above, each subprocessor 1023 can add a new sandbox to an existing sandbox group. Even in this case, the address of each sandbox may be discontinuous. The above method can also be used when there is no existing sandbox group and the first sandbox is associated with the sub memory 1027 and the address translation register 1037.

(3-5. Accessing Work Memory from the Main Processor and Each Subprocessor)

As described above, since the main memory 1026 is constituted by a DRAM or the like and data is transferred by the DMA method, each subprocessor 1023 can use the large capacity main memory 1026 at high speed. . The sub memory 1027 is made of SRAM or the like, and can be used at high speed in the same manner.

In addition, the main processor 1021 and each subprocessor 1023 work memory 1029 included in the information processing controller together with the main memory 1026 and the sub memory 1027 connected to the information processing controller. As long as it can be used as a share, it is possible to realize higher speed.

In addition, if a simple numerical operation can be performed by the work memory 1029, it is efficient. Since the work memory 1029 is made of SRAM or the like as described above, a large capacity such as DRAM cannot be expected, but it is very fast.

The configuration and procedure in the case where the main processor 1021 and each subprocessor 1023 access the work memory 1029 are shown below.

As shown in FIG. 21, the work memory 1029 includes a controller 1038 and a RAM 1039. As the RAM 1039, an SRAM can be used, but is not limited thereto. The RAM 1039 is composed of a plurality of blocks. An address is assigned to each block, and data is stored.

The main processor 1021 and each subprocessor 1023 access the RAM 1039 through the controller 1038. Specifically, the main processor 1021 and each subprocessor 1023 transmit commands, addresses, data, and the like to the controller 1038, and the controller 1038 accesses the RAM 1039 accordingly.

After the execution of the process, the controller 1038 returns the command execution result to the main processor 1021 or the subprocessor 1023 of the command transmission source.

Commands when each subprocessor 1023 accesses the work memory 1029 are the same as those used when accessing the main memory 1026 or the sub memory 1027 as shown in FIG. 19, for example. . The response of the execution result from the work memory 1029 after the processing execution is also the same structure.

However, when the work memory 1029 is accessed, the priority command identifier, normal command identifier, chain command identifier, and processing thread identifier in the commands shown in FIG. 19 are not used basically. However, the work memory 1029 may be used as long as it can cope with these identifiers. As the command type, some are considered as shown below.

The first is a read command. This is used to read data in the work memory 1029. The main processor 1021 and each subprocessor 1023 also transmit the address of the block in the RAM 1039 that stores desired data together with the read command. The controller 1038 returns the read data as OK / NG indicating success / failure of the read command as the execution result.

The second is a write command. This is used to write data into the work memory 1029. The main processor 1021 and each subprocessor 1023 transmit a write command, data, and an address of a block in the RAM 1039 that stores the data. The controller 1038 returns an OK / NG indicating the success / failure of the write command as the execution result.

The third is an addition command. This is used to add data in the work memory 1029. The main processor 1021 and each subprocessor 1023 transmit an address of a block in the RAM 1039 that stores an addition command and data to be added. The controller 1038 adds 1 to the data in the block of the received address and overwrites it. As an execution result, OK / NG indicating the success / failure of the addition command is returned.

The fourth is a set command. This is used to manipulate data in the work memory 1029 bit by bit. The main processor 1021 and each subprocessor 1023 transmit a set command, an address of a block in the RAM 1039 that stores data to be operated, and mask data.

In contrast, the controller 1038 compares the received mask data with the data in the block of the received address, and compares the value of the bit in the data with the same position as the bit having the value 1 in the mask data. 1 As a result of execution, Completed indicating completion of the set command is returned. At this time, the data before execution of the set command may also be returned to confirm the success / failure of the command.

The fifth is a clear command. This is also used to manipulate data in the work memory 1029 in units of bits. The main processor 1021 and each subprocessor 1023 transmit a clear command, an address of a block in the RAM 1039 that stores data to be operated, and mask data.

In contrast, the controller 1038 compares the received mask data with the data in the block of the received address, and compares the value of the bit in the data with the same position as the bit having the value 1 in the mask data. 0. As a result of execution, Completed indicating completion of the clear command is returned. At this time, the data before the clear command is also returned, so that the success / failure of the command can be confirmed.

As described above, the main processor 1021 and each subprocessor 1023 can use the work memory 1029 in addition to the large capacity main memory 1026 and the high speed sub memory 1027. In addition, when the work memory 1029 is used as a cache of the main memory 1026 or the sub memory 1027, a higher speed can be expected.

(3-6. Processing Threads in Each Subprocessor)

As described above, each subprocessor 1023 in one information processing controller is independent in structure. Thus, each subprocessor 1023 independently executes a subprocessor program to process data. It is also contemplated that each subprocessor 1023 has a plurality of virtually independent processing threads therein. The structure is shown in FIG.

The subprocessor 1023 is connected to the bus 1032 through an arbiter 1040 included therein. The subprocessor 1023 also includes LS (local storage) 1024 and processing threads 1041, 1042, 1043 and 1044, and the arbiter 1040 notifies the appropriate processing thread of signals from the outside. Play a role.

In FIG. 22, each processing thread 1041, 1042, 1043, and 1044 is shown independently, but is virtually independent. The processing threads 1041, 1042, 1043 and 1044 are each assigned a processing thread identifier and can operate independently and in parallel.

Each processing thread 1041, 1042, 1043, and 1044 reliably addresses the processing thread of the command sender to independently access the main memory 1026, the sub memory 1027, or the work memory 1029. Make sure the fund is returned. The procedure for this is shown below.

The command when each processing thread 1041, 1042, 1043, and 10440 accesses each memory is the same as that used by each subprocessor 1023 when accessing the memory, for example, as shown in FIG. 19. Do. The response of the execution result from each memory after the processing execution is also the same structure.

Although the command / response structure of FIG. 19 has been described above, the subprocessor identifier is the subprocessor ID of the subprocessor of the command sender, and the processing thread identifier is for identifying which processing thread in the subprocessor is the command sender. .

The response from the main memory 1026, the sub memory 1027, or the work memory 1029 is first returned to the subprocessor 1023 of the command transmission source based on the subprocessor identifier. Further, based on the processing thread identifier, the arbiter 1040 in the subprocessor 1023 is returned to the processing thread of the command sender.

However, when any of a plurality of processing threads in the subprocessor, for example, when performing the same processing, it is possible to return the processing load to the light processing thread without the processing thread identifier. In addition, each time a response is received from the main memory 1026, the sub memory 1027, or the work memory 1029, one of the plurality of processing threads is sequentially selected, and the response is selected for the selected processing thread. You may reply.

As described above, even when a plurality of processing threads in each subprocessor 1023 independently access the main memory 1026, the sub memory 1027, or the work memory 1029, the processing threads of the command transmission source are provided. You can make sure that the response is returned.

(3-7. Subprocessor Program Management with Control Registers)

In the case where a plurality of subprocessors 1023 exist in one information processing controller and there are a plurality of processing threads in each subprocessor 1023, which processing thread needs to process a subprocessor program to be processed in the information processing controller. Determining whether or not to process the data processing module is important for realizing speeding up the information processing controller.

Thus, by using the control register 1028 shown in FIG. 16 below, a configuration and procedure for efficiently allocating the processing of the subprocessor program to each processing thread to efficiently operate the information processing controller are shown.

As shown in FIG. 23, the control register 1028 is comprised from the process waiting subprocessor program register 1045 and the subprocessor program process progress register 1046. As shown in FIG.

Referring to the processing wait subprocessor program register 1045, when the subprocessor program to be processed is generated in the information processing controller, the main processor 1021 is located in the processing wait subprocessor program register 1045. The address in the main memory 1026, the sub memory 1027, the work memory 1029, or the LS (local storage) 1022 or 1024 in which a program or data related thereto is stored is written.

In the state where there is no subprocessor program to be processed, the value of the processing waiting subprocessor program register 1045 is zero. All of the processing threads read the value of the processing wait subprocessor program register 1045 periodically or irregularly, as long as nothing is executing the subprocessor program, and as a result, processing that reads a non-zero value. It is assumed that the thread performs processing.

At the same time, the processing thread writes a zero value to the processing wait subprocessor program register 1045. The processing thread which performs the process reads and processes the subprocessor program or related data to be processed based on the value of the read waiting subprocessor program register 1045. At this time, the subprocessor program has already been read into the subprocessor 1023 having the corresponding processing thread, and the reading of the subprocessor program is also considered unnecessary.

In this way, the processing of the subprocessor program can be promptly assigned to the processing thread having a sufficient processing capacity not to execute the subprocessor program, and the information processing controller can be operated efficiently.

The subprocessor program processing progress register 1046 is a 2-bit (x, y) register for writing the processing progress status by the processing thread to which the processing of the subprocessor program is assigned. For example, (0, 0) represents unprocessed, (0, 1) represents step 1 in processing, (1, 0) represents step 2 in processing, and (1, 1) represents processing Indicates completion In addition, by writing the processing thread identifier together with these two bits, it is possible to indicate the processing thread to which the process is allocated.

Alternatively, a register for writing processing progress of the subprocessor program may be provided for each processing thread in the information processing controller.

The subprocessor program processing progress register 1046 is accessible to the main processor 1021, all subprocessors 1023, and all processing threads in the information processing controller, thereby accurately determining the progress of processing of the subprocessor program. Can be. In addition, in the case where a processing progress register is provided for each processing thread, the processing progress can be grasped even when a plurality of subprocessor programs are executed at the same time.

The above is an example of a processing thread management method in the case where each subprocessor 1023 has a plurality of virtually independent processing threads therein.

In addition, in the following, when a subprocessor performs some processing, it does not matter which processing thread in the said subprocessor processes, and the difference of the execution result by the difference of a processing thread does not arise. do. Therefore, the description of how the plurality of processing threads in the subprocessor share processing with respect to the processing contents of the subprocessor is omitted.

(3-8. Creating and Configuring Software Cells)

In the network system of FIG. 16, software cells are transmitted between the information processing apparatuses 1001, 1002, 1003, and 1004 for distributed processing between the information processing apparatuses 1001, 1002, 1003, and 1004. That is, the main processor 1021 included in the information processing controller in an arbitrary information processing apparatus generates a software cell containing a command, a program, and data, and transmits it to another information processing apparatus via the network 1009. The processing can be distributed.

3 shows an example of the configuration of the software cell. The software cell of this example is entirely composed of a transmission source ID, a transmission destination ID, a response destination ID, a cell interface, a DMA command, a program, and data.

The transmission source ID includes a network address and an information processing device ID of an information processing device which is a transmission source of a software cell, and an identifier of a main processor 1021 and each subprocessor 1023 included in the information processing controller in the information processing device (main processor ID and subprocessor ID).

The transmission destination ID and the response destination ID each include the same information about the information processing device that is the destination of the software cell and the information processing device that is the destination of the execution result of the software cell.

The cell interface is information necessary for the use of a software cell, and is composed of a global ID, information of a required subprocessor, a sandbox size, and a previous software cell ID.

The global ID can uniquely identify the corresponding software cell throughout the network, and is created based on the source ID and the date and time (date and time) of the creation or transmission of the software cell.

The number of subprocessors required is set to the number of subprocessors required for the execution of the software cell. The sandbox size is set in the amount of memory in the main memory 1026 and the LS 1024 of the subprocessor 1023 required for the execution of the software cell.

The last software cell ID is an identifier of the previous software cell in a group of software cells that require sequential execution of streaming data or the like.

The execution section of the software cell is composed of DMA commands, programs and data. The DMA command includes a series of DMA commands necessary for starting the program, and the program includes a subprocessor program executed by the subprocessor 1023. Data here is data processed by the program containing this subprocessor program.

The DMA command also includes a loading command, a kick command, a function program execution command, a status request command, and a status reply command.

The loading command is a command for loading information in the main memory 1026 into the LS 1024 in the subprocessor 1023 and includes a main memory address, a subprocessor ID, and an LS address in addition to the loading command itself. The main memory address indicates an address of a predetermined area in the main memory 1026 that is the source of loading the information. The subprocessor ID and the LS address indicate an identifier of the subprocessor 1023 which is the loading destination of the information and the address of the LS 1024.

The kick command is a command for starting execution of a subprocessor program and includes, in addition to the kick command itself, a subprocessor ID and a program counter. The subprocessor ID identifies the subprocessor 1023 to be kicked, and the program counter gives an address for the subprocessor program execution program counter.

The function program execution command is a command for requesting execution of a function program to another information processing apparatus from another information processing apparatus as described later. The information processing controller in the information processing apparatus that receives the function program execution command identifies the function program to be started by the function program ID described later.

The status request command is a command for requesting transmission of device information relating to the current operating state (situation) of the information processing apparatus indicated by the transmission destination ID to the information processing apparatus indicated by the response destination ID. Although a functional program is mentioned later, it is a program classified as a functional program in the block diagram of the software which the main memory 1026 of the information processing apparatus shown in FIG. 6 stores. The function program is loaded into the main memory 1026 and executed by the main processor 1021.

The status reply command is a command in which the information processing apparatus that has received the above status request command responds to the information processing apparatus whose device information is indicated by the response destination ID included in the status request command. The status reply command stores the device information in the data area of the execution section.

Fig. 4 shows the structure of the data area of the software cell when the DMA command is a status return command.

The information processing apparatus ID is an identifier for identifying the information processing apparatus provided with the information processing controller, and represents the ID of the information processing apparatus which transmits the status reply command. When the power is turned on, the information processing device ID is set by the main processor 1021 included in the information processing controller in the information processing device to the network address of the information processing device and the information processing controller in the information processing device. It is generated based on the number of subprocessors 1023 included.

The information processing apparatus type ID includes a value indicating a characteristic of the information processing apparatus. The characteristics of the information processing apparatus are, for example, a hard disk recorder, a PDA (Personal Digital Assistants), a portable CD (Compact Disc) player, and the like described later. In addition, the information processing apparatus type ID may represent the function of an information processing apparatus, such as video audio recording and video audio reproduction. The values indicating the features and functions of the information processing apparatus are determined in advance, and the characteristics and functions of the information processing apparatus can be grasped by reading the information processing apparatus type ID.

The MS (master / slave) status indicates whether the information processing device is operating as a master device or a slave device as described later. When this is set to 0, it indicates that it is operating as a master device. If set, this indicates that the device is operating as a slave device.

The main processor operating frequency indicates the operating frequency of the main processor 1021 in the information processing controller. The main processor utilization rate represents the utilization rate in the main processor 1021 for all programs currently operating by the main processor 1021. The main processor utilization rate is a value representing the ratio of the processing power in use to the total processing power of the target main processor, for example, calculated in units of MIPS which is a unit for evaluating processor processing power, or the processor usage time per unit time. Calculated based on The same applies to the subprocessor utilization described later.

The number of subprocessors represents the number of subprocessors 1023 included in the information processing controller. The subprocessor ID is an identifier for identifying each subprocessor 1023 in the information processing controller.

The subprocessor status indicates the state of each subprocessor 1023, and there are states such as unused, reserved, and busy. unused indicates that the subprocessor is not currently being used or reserved for use. reserved is a state which is not currently used but is reserved. busy indicates that it is currently in use.

The subprocessor utilization rate represents the utilization rate in the subprocessor for a subprocessor program currently being executed by the subprocessor or for which execution is reserved for the subprocessor. In other words, the subprocessor usage ratio indicates the current usage ratio when the subprocessor status is busy, and the estimated estimated usage ratio to be used later when the subprocessor status is reserved.

The subprocessor ID, the subprocessor status, and the subprocessor usage rate are set one set for one subprocessor 1023, and set by the number of sets of the number of subprocessors 1023 in one information processing controller.

The main memory total capacity and the main memory usage amount represent the total capacity and the currently used capacity of the main memory 1026 connected to the information processing controller, respectively.

The number of external memory sections indicates the number of external memory sections 1031 connected to the information processing controller. The external memory unit ID is information for uniquely identifying the external memory unit 1031 connected to the information processing controller. The external memory unit type ID indicates the type of the external memory unit (for example, hard disk, CD-RW, DVD-RW, memory disk, SRAM, ROM, and the like).

The external memory unit total capacity and the external memory unit usage amount represent the total capacity of the external memory unit 1031 and the capacity currently being used, respectively identified by the external memory unit ID.

The external memory unit ID1, the external memory unit type ID, the external memory unit total capacity, and the external memory unit usage amount are set one set for one external memory unit 1031, and are connected to the information processing controller 1031. Is set by the number of sets. That is, when a plurality of external memory units are connected to one information processing controller, each external memory unit is assigned a different external memory unit ID, and the external memory unit type ID, external memory unit total capacity, and external memory unit usage are also separately. Managed separately.

(3-9. Execution of the software cell)

The main processor 1021 included in the information processing controller in the arbitrary information processing apparatus generates a software cell having the above configuration and transmits it to the other information processing apparatus and the information processing controller in the apparatus via the network 1009. . The information processing apparatus of a transmission source, the information processing apparatus of a transmission destination, the information processing apparatus of a response destination, and the information processing controller in each apparatus are respectively identified by the said transmission source ID, a transmission destination ID, and a response destination ID.

The main processor 1021 included in the information processing controller in the information processing apparatus that has received the software cell stores the software cell in the main memory 1026. The main processor 1021 of the transmission destination reads the software cell and processes the DMA commands included therein.

Specifically, the main processor 1021 of the transmission destination first executes a loading command. As a result, information is loaded from the main memory address indicated by the loading command to a predetermined area of the LS 1024 in the subprocessor specified by the subprocessor ID and the LS address included in the loading command. The information loaded here is a subprocessor program or data included in the received software cell, or other indicated data.

Next, the main processor 1021 transmits the kick command to the subprocessor indicated by the subprocessor ID included therein, together with the program counter included in the kick command.

The indicated subprocessor executes the subprocessor program in accordance with the kick command and the program counter. After the execution result is stored in the main memory 1026, the main processor 1021 is notified that the execution is completed.

In addition, the processor which executes a software cell in the information processing controller in the information processing apparatus of a transmission destination is not limited to the subprocessor 1023, The program for main memory, such as a function program in which the main processor 1021 is contained in a software cell. It is also possible to specify to run.

In this case, the information processing apparatus of the transmission source includes, in the information processing apparatus of the transmission destination, a main memory program and data processed by the main memory program instead of the subprocessor program, and the DMA command is a loading command. The cell is transmitted so that the main memory 1026 stores the main memory program and the data processed by it.

Subsequently, the information processing apparatus of the transmission source, to the information processing apparatus of the transmission destination, a main processor ID for the information processing controller in the information processing apparatus of the transmission destination, a main memory address, a function program ID to be described later for identifying a program for the main memory, and the like. And a software counter, wherein the DMA command transmits a software cell which is a kick command or a function program execution command, and causes the main processor 1021 to execute the main memory program.

As described above, in the network system of the present invention, the information processing apparatus of the transmission source transmits the subprocessor program or the main memory program to the information processing apparatus of the transmission destination by the software cell, and transmits the subprocessor program information of the transmission destination. The subprocessor 1023 included in the information processing controller in the processing apparatus can be loaded to execute the subprocessor program or the main memory program in the information processing apparatus of the transmission destination.

In the information processing controller in the information processing apparatus of the transmission destination, when the program included in the received software cell is a subprocessor program, the subprocessor program is loaded into the designated subprocessor. Then, the subprocessor program or the main memory program included in the software cell is executed.

Therefore, even if the user does not operate the information processing apparatus of the transmission destination, the subprocessor program or the main memory program can be automatically executed by the information processing controller in the information processing apparatus of the transmission destination.

In this way, when the information processing controller in the own apparatus does not have a main memory program such as a subprocessor program or a function program, the information processing apparatus can acquire them from another information processing apparatus connected to the network. In addition, data transfer is performed between the subprocessors and the main memory by the DMA system, and by using the above-described sandbox, even when data must be processed in multiple stages in one information processing controller, high speed and high security Processing can be performed with

[4. Distributed Processing as a Network System 2

As a result of the distributed processing by using the software cell, as shown in the upper part of FIG. 24, the plurality of information processing apparatuses 1001, 1002, 1003, and 1004 connected to the network 1009 are shown in the lower part of FIG. 24. Similarly, it operates as one virtual information processing apparatus 1007. However, the following processes need to be performed with the following structures.

(4-1.System Configuration and Program Loading)

6 shows a configuration of software stored in the main memory 1026 of each information processing controller. These software (programs) are recorded in the external memory unit 1031 connected to the information processing controller before power is supplied to the information processing apparatus.

Each program is classified into a control program, a function program, and a device driver by a function or a feature.

The control program is provided with the same information processing controller, and is executed by the main processor 1021 of each information processing controller, and includes an MS (master / slave) manager and a capability exchange program described later.

The function program is executed by the main processor 1021, and is provided with an information processing apparatus corresponding to each information processing controller, such as recording, reproduction, and material search.

The device driver is provided for the input / output (transmission / reception) of the information processing controller (information processing apparatus) and corresponds to the information processing apparatus for each information processing controller such as broadcast reception, monitor output, bit stream input / output, network input / output, and the like.

When the information processing device is physically connected to the network 1009 by inserting a cable or the like, when the main power is supplied to the information processing device, and the information processing device is electrically and functionally connected to the network 1009, the information The main processor 1021 of the information processing controller of the processing apparatus loads each program belonging to the control program and each program belonging to the device driver into the main memory 1026.

As the loading order, the main processor 1021 first executes a read command to the DC 1030 to read a program from the external memory unit 1031, and then executes a write command to the DMAC 1025. The program is written to the main memory 1026.

Each program belonging to the functional program may be configured to load only necessary programs when necessary, or similarly to programs belonging to other categories, each program may be loaded immediately after the main power is turned on.

Each program belonging to the functional program does not need to be recorded in the external memory unit 1031 of all information processing apparatuses connected to the network, and if it is recorded in the external memory unit 1031 of any one information processing apparatus, Since it can be loaded from another information processing apparatus by one method, as a result, as shown at the bottom of FIG. 24, a functional program can be executed as one virtual information processing apparatus 1007. As shown in FIG.

In addition, as described above, the functional program processed by the main processor 1021 may cooperate with the subprocessor program processed by the subprocessor 1023 in some cases. Therefore, when the main processor 1021 reads the function program from the external memory unit 1031 and writes it to the main memory 1026, when there exists a subprocessor program which cooperates with the target function program, The subprocessor program is also written to the same main memory 1026. In this case, although there may be one subprocessor program which cooperates, there may be a plurality of subprocessor programs. In the case of plural numbers, all the subprocessor programs which operate in association are written into the main memory 1026.

The subprocessor program written in the main memory 1026 is then written into the LS 1024 in the subprocessor 1023 and cooperatively operates with the functional program processed by the main processor 1021.

As shown in the software cell of FIG. 3, an identifier capable of uniquely identifying a program for each program is assigned to the functional program as the functional program ID. The function program ID is determined from the creation date, the information processing device ID, and the like at the stage of the creation of the function program.

The subprocessor program ID is also assigned to the subprocessor program, whereby the subprocessor program can be uniquely identified. The subprocessor program ID to be allocated may be an identifier associated with the function program ID of the function program to be associated with the cooperative operation, for example, the function program ID is the parent number and the branch number is added at the end. For example, the identifier may be irrelevant to the function program ID of the function program that is the partnering operation.

In either case, when the functional program and the subprocessor program cooperate with each other, it is necessary to store the program ID, which is the identifier of the counterpart, in the child program. Even when a function program cooperates with a plurality of subprocessor programs, the function program stores all the subprocessor program IDs of the plurality of subprocessor programs.

The main processor 1021 secures an area in the main memory 1026 for storing device information (information on the operating state) of the information processing device in which the main processor 1021 operates, and records the information as a device information table of the own device. do. The device information here is the information below the information processing device ID shown in FIG.

(4-2. Determination of Master / Slave in the System)

In the above-described network system, when the main power is supplied to any information processing apparatus, the main processor 1021 of the information processing controller of the information processing apparatus is configured to supply a master / slave manager (hereinafter referred to as MS manager) to the main memory 1026. Load in and run

When the MS manager detects that the information processing apparatus on which it operates is connected to the network 1009, the MS manager confirms the existence of another information processing apparatus connected to the same network 1009. Here, "connection" or "existence" indicates that the information processing apparatus is not only physically connected to the network 1009, but also electrically and functionally connected to the network 1009 as described above.

In the following, the information processing apparatus on which it operates is called a child apparatus, and another information processing apparatus is called another apparatus. The device also refers to the information processing device.

A method of confirming the existence of another information processing apparatus connected to the same network 1009 by the MS manager is shown below.

The MS manager generates a software cell in which the DMA command is a status request command, the sender ID and the destination ID are not specified in the information processing apparatus, and does not specify the sender ID, and transmits it on the network to which the information processing apparatus is connected. Set the network connection verification timer. The timeout time of the timer is, for example, 10 minutes.

When another information processing apparatus is connected on the network system, the other apparatus receives a software cell of the status request command and issues a DMA to the information processing apparatus that issues a status request command specified by the response destination ID. The command is a status reply command and transmits a software cell containing device information of itself (other device) as data. The software cell of the status reply command includes at least information (information processing device ID, information on the main processor, information on the subprocessor, etc.) specifying the other device, and the MS status of the other device.

The MS manager of the information processing device which issued the status request command monitors the reception of the software cell of the status reply command sent from another device on the network until the network connection confirmation timer times out. As a result, when a status reply command indicating MS status = 0 (master device) is received, the MS status in the device information table of the own device is set to one. As a result, the device becomes a slave device.

On the other hand, when the status reply command is not received at all until the network connection confirmation timer is timed out, or when the status reply command indicating MS status = 0 (master device) is not received, The MS status in the device information table is set to zero. As a result, the device becomes a master device.

In other words, if no device is connected to the network 1009 or if no master device is present on the network 1009, the new information processing device is connected to the network 1009. Is set as the master device. On the other hand, in a state where a master device already exists on the network 1009, when a new information processing device is connected to the network 1009, the device is automatically set as a slave device.

In either of the master device and the slave device, the MS manager periodically monitors the status of other devices by sending status request commands to other devices on the network 1009 and inquiring status information. As a result, the main power supply of the information processing apparatus connected to the network 1009 is cut off, or the information processing apparatus is disconnected from the network 1009, so that a status reply command from a specific other device within a predetermined period set for determination in advance is obtained. Is not returned, or when there is a change in the connection state of the network 1009, such as when a new information processing device is connected to the network 1009, the information exchange program is notified of the information.

(4-3. Acquisition of Device Data in Master Device and Slave Device)

The main processor 1021 executes the capability exchange program when the MS manager receives notification of the inquiry of other devices on the network 1009 and the completion of setting of the MS status of the own device.

When the own device is the master device, the capability exchange program acquires device information of all other devices connected to the network 1009, that is, device information of each slave device.

Acquiring the device information of the other device, as described above, generates a software cell whose DMA command is a status request command and transmits it to the other device, after which the DMA command is a status reply command and the device of the other device as data. It is possible by receiving a software cell containing information from another device.

Similar to the device information table of the child device which is the master device, the capability exchange program has an area for storing device information of all other devices (each slave device) connected to the network 1009, and the main memory 1026 of the child device. Is secured to the device information table as a device information table of another device (slave device).

That is, in the main memory 1026 of the master device, device information of all information processing devices connected to the network 1009 including the child device is recorded as the device information table.

On the other hand, when the child device is a slave device, the capability exchange program acquires device information of all other devices connected to the network 1009, that is, device information of each slave device other than the master device and the child device. The information processing device ID and the MS status contained in the device information are recorded in the main memory 1026 of the own device.

That is, in the main memory 1026 of the slave device, the device information of the child device is recorded as a device information table, and the master device and the information processing device for each slave device connected to the network 1009 other than the child device. The ID and MS status are recorded as separate device information tables.

In addition, in either of the master device and the slave device, the capability exchange program receives the device information of the information processing device when it is notified from the MS manager that the information processing device is newly connected to the network 1009. Acquisition is performed and recorded in the main memory 1026 as described above.

The MS manager and the capability exchange program are not limited to being executed by the main processor 1021 but may be executed by any subprocessor 1023. The MS manager and the capability exchange program are preferably resident programs that always operate while the main power supply of the information processing apparatus is turned on.

(4-4. When the information processing device is cut off from the network)

In either of the master device and the slave device, as described above, the main power supply of the information processing device connected to the network 1009 is cut off from the MS manager, or the information processing device from the network 1009. When notified that is separated, the device information table of the information processing device is deleted from the main memory 1026 of the child device.

In addition, when the information processing apparatus cut | disconnected from the network 1009 in this way is a master apparatus, a master apparatus is newly determined by the following method.

Specifically, for example, the information processing apparatus not disconnected from the network 1009 replaces the information processing apparatus IDs of the own apparatus and the other apparatus with numerical values, respectively, and replaces the information processing apparatus ID of the own apparatus with the information of the other apparatus. Compared with the processing device ID, when the information processing device ID of the own device is the minimum among the information processing devices not disconnected from the network 1009, the slave device moves to the master device and sets the MS status to 0. As the master device, as described above, device information of all other devices (each slave device) connected to the network 1009 is obtained and recorded in the main memory 1026.

(4-5. Distributed Processing Based on Device Data)

As shown in the lower part of FIG. 24, in order to operate the plurality of information processing apparatuses 1001, 1002, 1003, and 1004 connected to the network 1009 as one virtual information processing apparatus 1007, the master apparatus is a user. It is necessary to grasp the operation and operation status of the slave device.

25 shows how four information processing apparatuses operate as one virtual information processing apparatus 1007. It is assumed that the information processing apparatus 1001 operates as the master apparatus, and the information processing apparatuses 1002, 1003, and 1004 operate as slave apparatuses A, B, and C. FIG.

When the user operates the information processing apparatus connected to the network 1009, if the operation target is the master device 1001, the operation information is directly grasped by the master device 1001, and the operation target is the slave device. The operation information is transmitted from the operated slave device to the master device 1001. That is, regardless of whether the operation target of the user is either the master device 1001 or the slave device, the operation information is always grasped by the master device 1001. The operation information is transmitted by, for example, a software cell in which the DMA command is an operation information transmission command.

The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 selects a function program to execute according to the operation information. At that time, if necessary, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 is configured to execute the external memory unit 1031-1 or 1031-2 of the child device by the above method. The function program is loaded from the main memory 1026-1 to the main memory 1026-1, but another information processing device (slave device) may transmit the function program to the master device 1001.

The function program includes apparatuses such as information processing apparatus type IDs shown as information shown in FIG. 4 required for each execution unit, processing capability of the main processor or subprocessor, main memory usage, and conditions relating to the external memory unit. The specification of requirements is specified.

The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 reads out the above-mentioned specification required for each function program. In addition, the device information of each information processing apparatus is read with reference to the device information table recorded in the main memory 1026-1 by the capability exchange program in advance. The device information herein indicates information below the information processing device ID shown in FIG. 4 and is information about a main processor, a subprocessor, a main memory, and an external memory unit.

The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 includes the device information of each information processing device connected on the network 1009 and the above-mentioned information required to execute a function program. Compare the requirements specification sequentially.

For example, when the function program requires a recording function, only the information processing device having a recording function is identified and extracted based on the information processing device type ID. Further, a slave device capable of securing the processing capacity of the main processor or subprocessor, the main memory usage, and the external memory unit necessary to execute the function program is specified as the execution request candidate device. Here, when a plurality of execution request candidate devices are specified, one execution request candidate device is specified and selected from the candidate device.

When the slave device requesting execution is specified, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 has an information processing controller 1011 in its own device with respect to the specified slave device. The device information table of the corresponding slave device recorded in the main memory 1026-1 included in the table is updated.

In addition, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 generates a software cell whose DMA command is a function program execution command, and generates a corresponding function on the cell interface of the software cell. The necessary subprocessor information and sandbox size (see Fig. 3) related to the program are set and transmitted to the slave device requested to be executed.

The slave device requested to execute the function program executes the function program and updates the device information table of the own device. At that time, if necessary, the main processor 1021 included in the information processing controller in the slave device is connected to the main memory 1026 from the external memory unit 1031 of the own device by the above method. Load a subprocessor program that operates in association.

If the necessary function program or the subprocessor program cooperatively operating with the function program is not recorded in the external memory unit 1031 of the slave device that is requested to execute the function program, the other information processing apparatus is the function program or sub. The system may be configured to transmit the processor program to the functional program execution request slave device.

The subprocessor program may be executed by another information processing apparatus using the above-described loading command and kick command.

After completion of the execution of the function program, the main processor 1021 included in the information processing controller in the slave device that executed the function program sends a termination notification to the main processor 1021 included in the information processing controller 1011 in the master device 1001. -1) and the device information table of the own device is updated. The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 receives the end notification and updates the device information table of the slave device that executed the function program.

The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 is an information processing device capable of executing the corresponding function program from the reference result of the device information table of the child device and the other device. There may be times when you choose yourself. In that case, the master device 1001 executes the function program.

In the example of FIG. 25, in the case where a user manipulates slave device A (information processing device 1002), and a separate slave device B (information processing device 1003) executes a function program according to the operation, 26 shows an example of the above dispersion processing.

In the example of FIG. 26, when the user operates the slave device A, the distributed processing of the entire network system including the slave device A starts, and the slave device A first transmits the operation information to the master device 1001 in step 1091. Send to

In step 1092, the master device 1001 receives the operation information and proceeds to step 1093, from the device information table of the child device and the other device recorded in the main memory 1026-1 of the child device, The operation state of each information processing apparatus is examined to select an information processing apparatus capable of executing a function program corresponding to the received operation information. This example is a case where the slave device B is selected.

Next, in step 1094, the master device 1001 requests execution of the function program for the selected slave device B. FIG.

In step 1095, the slave device B receives the execution request, and then proceeds to step 1096 to execute the execution requested function program.

As described above, the user operates only one information processing apparatus so that the plurality of information processing apparatuses 1001, 1002, 1003, and 1004 are virtually operated by one information processing apparatus 1007 without operating the other information processing apparatus. Can be operated as.

(4-6. Specific example of each information processing apparatus and system)

The information processing apparatuses 1001, 1002, 1003, and 1004 interconnected via the network 1009 basically perform information processing by the information processing controllers 1011, 1012, 1013, and 1014 as described above. Although one may be sufficient, the example is shown in FIG.

In this example, the information processing apparatus 1001 including the information processing controller 1011 is a hard disk recorder, and as shown in FIG. 28, the external memory unit 1031-1 shown in FIG. 16 is a hardware configuration. As an external memory unit 1031-2 shown in Fig. 16, an optical disc such as DVD ± R / RW, CD ± R / RW, Blu-rayDisc (registered trademark) can be mounted. In addition, the broadcast receiver 1052-1, the video input unit 1053-1, and the audio input unit 1054 are connected to the bus 1051-1 connected to the bus 1032-1 of the information processing controller 1011. 1), the video output unit 1055-1, the audio output unit 1056-1, the operation panel unit 1057-1, the remote control light receiving unit 1058-1, and the network connection unit 1059-1 are connected.

The broadcast receiving unit 1052-1, the video input unit 1053-1, and the audio input unit 1054-1 receive a broadcast signal or input a video signal and an audio signal from the outside of the information processing apparatus 1001, Each is converted into digital data of a predetermined format and sent to the bus 1051-1 for processing by the information processing controller 1011. The video output unit 1055-1 and the audio output unit 1056-1 To process the video data and audio data transmitted from the information processing controller 1011 to the bus 1051-1, convert them into digital data, or convert them into analog signals and send them to the outside of the information processing apparatus 1001. The remote control light receiver 1058-1 receives the remote control (remote operation) infrared signal from the remote control transmitter 1063-1.

As shown in FIG. 27 and FIG. 28, the monitor display device 1061 and the speaker device are provided in the video output unit 1055-1 and the audio output unit 1056-1 of the information processing apparatus (hard disk recorder) 1001. 1062 are connected.

The information processing apparatus 1002 provided with the information processing controller 1012 of the example of FIG. 27 is also a hard disk recorder, and is comprised similarly to the information processing apparatus 1001 as shown with the reference number in brackets in FIG. will be. For example, as shown in FIG. 27, the monitor display device and the speaker device are not connected to the information processing device (hard disk recorder) 1002.

As a software configuration of the information processing apparatuses (hard disk recorders) 1001 and 1002, that is, the information processing controllers 1011 and 1012, as shown in FIG. 29, the control program includes an MS manager and a capability exchange program. As a program, a program for video audio recording, video audio playback, location search, and program recording reservation is provided. As a device driver, a program for broadcast reception, video output, audio output, external memory input / output, and network input / output is provided. .

The information processing apparatus 1003 provided with the information processing controller 1013 of the example of FIG. 27 is PDA (Personal Digital Assistants), and as shown in FIG. 30, as a hardware structure, the external memory part shown in FIG. As a 1031-5, a memory card disk can be mounted, and a liquid crystal display 1072 and an audio output unit are provided on a bus 1071 connected to the bus 1032-3 of the information processing controller 1013. 1073, camera portion 1074, audio input portion 1075, keyboard portion 1076, and network connection portion 1077 are connected.

In addition, in FIG. 16, the information processing controller 1013 which has abbreviate | omitted the inside may include the main processor 1021-3, the subprocessors 1023-7, 1023-8, and 1023-9, DMAC (direct memory access controller) ( 1025-3, control register 1028-3, work memory 1029-3, DC (disk controller) 1030-3, and bus 1032-3, and the main processor 1021-3. ) Has LS (local storage) 1022-3, and each subprocessor 1023-7, 1023-8, and 1023-9 has LS (local storage) 1024-7, 1024-8, and 1024-. Has 9).

As the software configuration of the information processing apparatus (PDA) 1003, that is, the information processing controller 1013, as shown in FIG. 31, the control program is provided with an MS manager and a capability exchange program, and is a video and audio function. It has a program for recording, video audio playback, phone book, word processor and table calculation, and Web browser, and as a device driver, it has a program for video output, audio output, camera video input, microphone audio input and network input / output. do.

The information processing apparatus 1004 provided with the information processing controller 1014 of the example of FIG. 27 is a portable CD player, and as shown in FIG. 32, as a hardware configuration, the external memory part 1031 shown in FIG. 16 is shown. 6), a CD (Compact Disc) can be mounted, and a liquid crystal display (1082) and an audio output unit (2) on a bus 1081 connected to the bus 1032-4 of the information processing controller 1014. 1083, the operation button part 1084, and the network connection part 1085 are connected.

In addition, the information processing controller 1014 which has abbreviate | omitted the inside in FIG. 16 is the main processor 1021-4, the subprocessors 1023-10, 1023-11, and 1023-12, DMAC (direct memory access controller) 1025. -4), a control register 1028-4, a work memory 1029-4, a DC (disk controller) 1030-4, and a bus 1032-4, and the main processor 1021-4. Has LS (local storage) 1022-4, and each subprocessor 1023-10, 1023-11, and 1023-12 has LS (local storage) 1024-10, 1024-11, and 1024-12. Has

As a software configuration of the information processing apparatus (portable CD player) 1004, that is, the information processing controller 1014, as shown in FIG. 33, the control program includes an MS manager and a capability exchange program, and as a function program, A program for music reproduction is provided, and as a device driver, a program for audio output, CD control, and network input / output is provided.

In the network system of the example of FIG. 27 described above, the information processing apparatuses 1001, 1003, and 1004 are connected on the network 1009, and the information processing apparatus 1001 is the master apparatus (MS status = 0). It is assumed that the information processing apparatuses 1003 and 1004 are set as slave devices (MS status = 1).

In this state, when the information processing apparatus 1002 is newly connected to the network 1009, the main processor 1021-2 included in the information processing controller 1012 in the information processing apparatus 1002 by the method described above. The MS manager executed by the MS inquires the MS status to other information processing apparatuses 1001, 1003, and 1004, recognizes that the information processing apparatus 1001 already exists as a master device, and recognizes the child device (information processing apparatus ( 1002)) to the slave device (MS status = 1). In addition, the information processing apparatus 1001 set as the master device collects device information of each device including the newly added information processing device 1002 and updates the device information table in the main memory 1026-1. do.

In this state, it shows the case where the recording reservation operation of the broadcast program for 2 hours is performed by the information processing apparatus (PDA) 1003 which is a slave device by the user.

In this case, the information processing apparatus (PDA) 1003, which is a slave device, receives an input of recording reservation information including information such as recording start time, recording end time, recording target broadcast channel, recording quality, and the like from the user. A software cell including the recording reservation information and the recording reservation command as the DMA command is generated and transmitted to the information processing device 1001 which is the master device.

The main processor 1021-1 included in the information processing controller 1011 in the information processing apparatus 1001 that receives the software cell in which the DMA command is the recording reservation command reads the recording reservation command, and the main memory 1026. With reference to the device information table in -1), an information processing device capable of executing the corresponding recording reservation command is specified.

First, the main processor 1021-1 reads the information processing apparatus type IDs of the information processing apparatuses 1001, 1002, 1003, and 1004 included in the device information table, and executes a function program corresponding to the recording reservation command. Extract possible information processing devices. Here, information processing apparatuses 1001 and 1002 having an information processing apparatus type ID indicating a recording function are specified as candidate apparatuses, and information processing apparatuses 1003 and 1004 are excluded from the candidate apparatus.

Next, the main processor 1021-1 included in the information processing controller 1011 in the information processing device 1001 that is the master device refers to the device information table, and the main processor of the information processing devices 1001 and 1002 or Whether the information processing apparatuses 1001 and 1002 satisfy the requirements required for the execution of the function program corresponding to the recording reservation command by reading information about the apparatus such as the processing capacity of the subprocessor and the information on the main memory. Judge. Here, it is assumed that both of the information processing apparatuses 1001 and 1002 satisfy the requirement specification required for the execution of the function program corresponding to the recording reservation command.

In addition, the main processor 1021-1 reads information about the external memory units of the information processing apparatuses 1001 and 1002 with reference to the device information table, and the free space of the external memory unit is used for execution of the recording reservation command. It is determined whether the required dose is satisfied. Since the information processing apparatuses 1001 and 1002 are hard disk recorders, the difference between the total capacity and the usage amount of the hard disks 1031-1 and 1031-3 corresponds to the respective blank capacities.

In this case, the free space of the hard disk 1031-1 of the information processing apparatus 1001 is 10 minutes in terms of recording time, and the free space of the hard disk 1031-3 of the information processing apparatus 1002 records. Let's say it's 20 hours.

At this time, the main processor 1021-1 included in the information processing controller 1011 in the information processing apparatus 1001 serving as the master device can secure a free space for two hours necessary for executing the recording reservation command. The information processing apparatus is identified as the execution request destination slave apparatus.

As a result, only the information processing device 1002 is selected as the execution request destination slave device, and the main processor 1021-1 included in the information processing controller 1011 in the information processing device 1001 serving as the master device is provided to the user. The recording reservation command including the recording reservation information transmitted from the information processing apparatus 1003 operated by the transmission is sent to the information processing apparatus 1002, and the execution of the recording reservation of the two-hour broadcast program is requested.

Then, the main processor 1021-2 included in the information processing controller 1012 in the information processing apparatus 1002 interprets the recording reservation command, and transmits a function program required for recording to the hard disk 1031-3 serving as an external memory unit. ) Is loaded into the main memory 1026-2, and recording is performed in accordance with the recording reservation information. As a result, the video and audio data of the broadcast program of two hours of recording reservation is recorded on the hard disk 1031-3 of the information processing apparatus 1002.

Thus, even in the network system of the example of FIG. 27, the user operates only one information processing apparatus, thereby virtually operating the plurality of information processing apparatuses 1001, 1002, 1003, and 1004 without operating the other information processing apparatus. It can operate as one information processing apparatus 1007.

Those skilled in the art will understand that various modifications, combinations, subcombinations, changes, and the like may occur within the scope of the claims or equivalents thereof, depending on design requirements or other factors.

As described above, according to the present invention, distributed processing can be reliably and effectively performed between a plurality of information processing apparatuses connected via a network.

Claims (22)

An information processing apparatus which is connected to another information processing apparatus via a network and performs information processing in accordance with a predetermined command, Capability exchange means for collecting information on an operation state from said other information processing apparatus and creating a device information table; When the command is generated, device specifying means for specifying an information processing apparatus capable of executing the command by comparing the information on the resources necessary for the execution of the command with the information on the operation state of the device information table. Information processing apparatus comprising a. The method of claim 1, The capability exchange means collects and stores information processing capability data of the other information processing apparatus in the apparatus information table, And the device specifying means specifies an information processing device capable of executing the command by comparing the information processing capability required for executing the command with the information processing capability of the other information processing apparatus. The method of claim 1, The capability exchange means collects and stores the memory capacity data of the other information processing apparatus in the apparatus information table, And the device specifying means specifies an information processing device capable of executing the command by comparing a memory capacity required for the execution of the command with a memory capacity of the other information processing device. The method of claim 1, The capability exchange means collects and stores capacity data of the external recording means of the other information processing apparatus in the apparatus information table, The device specifying means specifies the information processing apparatus capable of executing the command by comparing the capacity of the external recording means necessary for the execution of the command with the capacity of the external recording means of the other information processing apparatus. Processing unit. The method of claim 1, The capability exchange means collects the information processing apparatus type identifiers capable of specifying the functions of the other information processing apparatus and stores them in the apparatus information table. And the device specifying means specifies an information processing device capable of executing the command by comparing a function necessary for executing the command with an information processing device type identifier of the other information processing device. The method of claim 1, And the capability exchanging means transmits and executes the command to the information processing apparatus specified by the apparatus specifying means. The method of claim 1, And the capability exchange means collects information on the operation state of the other information processing apparatus and updates the device information table when the connection between the other information processing apparatus and the network is changed. The method of claim 1, And the capability exchange means collects information on an operation state of the other information processing apparatus at predetermined time intervals and updates the device information table. The method of claim 1, The other information processing apparatus includes a plurality of processor means for processing the command, and the capability exchanging means collects information on an operating state of each of the plurality of processor means and stores them in the device information table. Information processing device. The method of claim 1, Manager means for determining whether or not another information processing apparatus is connected to the network; And if it is determined by the manager means that another information processing apparatus is connected to the network, the processing by the capability exchanging means is executed. An information processing method in which an information processing apparatus connected to another information processing apparatus via a network performs information processing according to a predetermined command, An ability exchange step of collecting information on an operation state from the other information processing device and creating a device information table; When the command is generated, the device specifying step of specifying an information processing device capable of executing the command by comparing the information on the resources necessary for the execution of the command with the information on the operation state of the device information table. Information processing method comprising a. The method of claim 11, And an execution request step of transmitting the command to the information processing apparatus specified in the device specifying step to execute execution request. The method of claim 11, The other information processing apparatus includes a plurality of processor means for processing the command, In the capability exchanging step, the information processing method collects information on an operating state of each of the plurality of processor means and stores it in the device information table. The method of claim 11, A management step of determining whether another information processing apparatus is connected to the network; And in the case where it is determined that another information processing apparatus is connected to the network in this management step, the capability exchange step is executed. In an information processing system in which one information processing device and another information processing device are connected via a network, and perform information processing according to a predetermined command, The one information processing device, Capability exchange means for collecting information on an operation state from said other information processing apparatus and creating a device information table; When the command is generated, device specifying means for specifying an information processing apparatus capable of executing the command by comparing the information on the resources necessary for the execution of the command with the information on the operation state of the device information table. Information processing system comprising a. The method of claim 15, And the capability exchanging means transmits and executes the command to the information processing apparatus specified by the apparatus specifying means. The method of claim 15, The other information processing apparatus includes a plurality of processor means for processing the command, And the capability exchange means collects information on an operation state of each of the plurality of processor means and stores the information in the device information table. The method of claim 15, The one information processing apparatus further includes manager means for determining whether another information processing apparatus is connected to the network, and when it is determined by the manager means that another information processing apparatus is connected to the network, An information processing system characterized by executing a process by said capability exchange means. In an information processing system in which one information processing device and another information processing device are connected via a network, a computer provided by the one information processing device is provided to perform information processing according to a predetermined command. An ability exchange means for collecting information on an operation state from the other information processing apparatus to create a device information table, and information on resources necessary for executing the command when the command is generated, and the device information table. An information processing computer program for comparing information relating to an operating state and functioning as a device specifying means for specifying an information processing apparatus that can execute the command. The method of claim 19, An information processing computer program, characterized in that the computer also functions as a means for transmitting the command and requesting execution to the specified information processing apparatus. The method of claim 19, The other information processing apparatus includes a plurality of processor means for processing the command, The information processing computer program causes the computer to function as a means for collecting information on an operating state of each of the plurality of processor means as the capability exchange means and storing the information in the device information table. Computer program for processing. The method of claim 19, The computer program for processing information also functions the computer as manager means for determining whether another information processing device is connected to the network, And when it is determined that another information processing apparatus is connected to the network by the function as the manager means, the computer functions as the capacity exchange means.

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