JP2005251163A - Information processing device, information processing method, information processing system and information processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely and effectively perform distributed processing between a plurality of information processing devices connected via a network in accordance with a user operation. <P>SOLUTION: Information processing controllers 11, 12, 13 and 14 in the information processing devices 1, 2, 3 and 4 are each composed by connecting, via a bus 29, a main processor 21, a sub-processor 23, a DMAC (direct memory access controller) 25 and a DC (disc controller) 27. The main processor 21 writes information on the operation state of an own device as device information in a main memory 26 connected to the information processing controller and transmits the device information to the other device according to a request from the another device. Thus, the information processing device references the operation state of the own and the other information processing device, selects an information processing device for executing a program in accordance with the user operation, and causes the device to execute the program. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus, an information processing method, an information processing system, and an information processing program.

  Recently, grid computing has attracted attention. Grid computing is a technology that realizes high computing performance by cooperating a plurality of information processing devices connected to a network.

  For example, Patent Document 1 (JP 2002-342165 A), Patent Document 2 (JP 2002-351850 A), Patent Document 3 (JP 2002-358289 A), Patent Document 4 (JP 2002-366533 A). And Patent Document 5 (Japanese Patent Laid-Open No. 2002-366534) realize a high-speed computer architecture by using a uniform modular structure, a common computing module, and a uniform software cell. It has been shown.

  In addition, Patent Document 6 (US Pat. No. 6,587,906), Patent Document 7 (US Pat. No. 6,667,920), Patent Document 8 (US Pat. No. 6,728,845), Patent Document 9 (US Pat. 0039895), Patent Document 10 (US Patent Publication No. 2004-0054880) and Patent Document 11 (US Patent Publication No. 2004-0098496), a plurality of processors existing in an information processing apparatus are operated independently and in parallel. Has been shown to speed up.

The prior art documents listed above are as follows.
JP 2002-342165 A JP 2002-351850 A JP 2002-358289 A JP 2002-366533 A JP 2002-366534 A US Pat. No. 6,587,906 US Patent 6,667,920 US Pat. No. 6,728,845 US 2004-0039895 US 2004-0054880 US 2004-0098496

  However, in a network system in which a plurality of information processing devices are connected via a network, in order to execute processing according to a user operation on the network system in a distributed manner throughout the network system, each information processing device, Alternatively, the information processing apparatus that manages the network system needs to grasp the operation status of other information processing apparatuses.

  Accordingly, the present invention is capable of reliably and effectively performing such distributed processing among a plurality of information processing apparatuses connected via a network.

The information processing apparatus of the present invention
An information processing apparatus connected to another information processing apparatus via a network and performing information processing according to a predetermined command,
Capability exchanging means for collecting information on the operating state from the other information processing apparatus and creating a device information table;
Device identification means for identifying information processing devices that can execute the command by comparing information regarding resources required to execute the command and information regarding an operation state of the device information table when the command occurs;
It is characterized by providing.

  In the information processing apparatus of the present invention configured as described above, when this is connected to another information processing apparatus via a network, information on the operation state is collected from the other information processing apparatus to create a device information table When a predetermined command occurs, the information related to the resource required to execute the command is compared with the information related to the operation state of the device information table to identify the information processing device that can execute the command. The distributed processing is reliably and effectively executed among the plurality of information processing apparatuses.

  As described above, according to the present invention, distributed processing can be reliably and effectively performed among a plurality of information processing apparatuses connected via a network.

[1. Basic configuration of network system and information processing apparatus 1]
FIG. 1 shows an example of a network system according to the present invention, in which a plurality of information processing apparatuses 1, 2, 3 and 4 are connected via a network 9.

(1-1. Information processing apparatus and information processing controller)
The information processing apparatuses 1, 2, 3 and 4 are various AV (Audio and Visual) devices and portable devices as will be described later.

  As for the information processing apparatus 1, the information processing apparatus 1 includes an information processing controller 11 as a computer function unit. The information processing controller 11 includes a main processor 21-1, sub processors 23-1, 23-2 and 23-3, a DMAC (direct memory access controller) 25-1, and a DC (disk controller) 27-1.

  The main processor 21-1 performs schedule management of execution (data processing) of the sub processor program by the sub processors 23-1, 23-2, and 23-3, and general management of the information processing controller 11 (information processing apparatus 1). And do. However, a program other than the management program may be operated in the main processor 21-1. In that case, the main processor 21-1 also functions as a sub processor. The main processor 21-1 has an LS (local storage) 22-1.

  There may be one sub-processor, but preferably there are a plurality of sub-processors. This example is a plurality of cases.

  Each of the sub processors 23-1, 23-2, and 23-3 executes the sub processor program and processes data in parallel and independently under the control of the main processor 21-1. Further, in some cases, the program in the main processor 21-1 can be configured to operate in cooperation with the sub processor program in the sub processor 23-1, 23-2 or 23-3. A function program described later is also a program that operates in the main processor 21-1. Each of the sub processors 23-1, 23-2, and 23-3 also has LS (local storage) 24-1, 24-2, and 24-3.

  The DMAC 25-1 accesses a program and data stored in a main memory 26-1 including a DRAM (dynamic RAM) connected to the information processing controller 11, and the DC 27-1 is used for the information processing controller 11. Is accessed to the external recording units 28-1 and 28-2.

  The external recording units 28-1 and 28-2 may be fixed disks (hard disks) or removable disks, and optical disks such as MO, CD ± RW, DVD ± RW, memory disks, SRAM (static RAM), ROM, etc. Various types can be used. Therefore, although DC27-1 is called a disk controller, it is an external recording unit controller.

  As in the example of FIG. 1, the information processing controller 11 can be configured so that a plurality of external recording units 28 can be connected to the information processing controller 11.

  The main processor 21-1, the sub processors 23-1, 23-2 and 23-3, the DMAC 25-1, and the DC 27-1 are connected by a bus 29-1.

  An identifier that can uniquely identify the information processing apparatus 1 including the information processing controller 11 throughout the entire network is assigned to the information processing controller 11 as an information processing apparatus ID.

  Similarly, identifiers that can identify the main processor 21-1 and the sub processors 23-1, 23-2, and 23-3 are assigned as the main processor ID and the sub processor ID.

  The information processing controller 11 is preferably configured as a one-chip IC (integrated circuit).

  The other information processing apparatuses 2, 3, and 4 are similarly configured. Here, units having the same parent number perform the same function even if the branch numbers are different, unless otherwise specified. Further, in the following description, when the branch number is omitted, it is assumed that the difference in the branch number does not occur.

(1-2. Access to main memory from each sub processor)
As described above, each sub-processor 23 in one information processing controller independently executes a sub-processor program and processes data, but different sub-processors can read or write simultaneously to the same area in the main memory 26. When writing is performed, data mismatch may occur. Therefore, access from the sub processor 23 to the main memory 26 is performed according to the following procedure.

  As shown in FIG. 2A, the main memory 26 is composed of a plurality of addressable memory locations 0 to M. Additional segments 0 to M for storing information indicating the state of the data are allocated to each memory location. The additional segment includes an F / E bit, a sub processor ID, and an LS address (local storage address). Further, access keys 0 to M described later are also assigned to each memory location. The F / E bit is defined as follows.

  The F / E bit = 0 indicates that the data being processed being read by the sub-processor 23 or invalid data that is not the latest data because it is empty and cannot be read. The F / E bit = 0 indicates that data can be written to the memory location, and is set to 1 after writing.

  The F / E bit = 1 indicates that the data at the memory location has not been read by the sub-processor 23 and is the latest unprocessed data. The data in the memory location can be read and set to 0 after being read by the sub-processor 23. Further, the F / E bit = 1 indicates that the memory location cannot write data.

  Furthermore, it is possible to set a read reservation for the memory location in the state where the F / E bit = 0 (read disabled / write enabled). When a read reservation is made for a memory location with the F / E bit = 0, the sub processor 23 adds the sub processor ID and LS of the sub processor 23 as read reservation information to an additional segment of the memory location where the read reservation is made. Write the address.

  Thereafter, when data is written to the memory location reserved for reading by the sub-processor 23 on the data writing side and the F / E bit is set to 1 (readable / not writable), it is added to the additional segment as read reservation information in advance. Read to the written sub-processor ID and LS address.

  When it is necessary to process data in multiple stages by a plurality of sub-processors, the sub-processor 23 that performs the process in the previous stage controls the read / write of the data in each memory location in this way. Immediately after the data is written at a predetermined address in the main memory 26, another sub-processor 23 that performs the subsequent processing can read the data after the preprocessing.

  As shown in FIG. 2B, the LS 24 in each sub-processor 23 is also composed of a plurality of addressable memory locations 0-L. Similarly, additional segments 0 to L are allocated to each memory location. The additional segment includes a busy bit.

  When the sub-processor 23 reads the data in the main memory 26 to the memory location of its own LS 24, it reserves by setting the busy bit corresponding to the memory location to be read to 1. No other data can be stored in the memory location where the busy bit is 1. After reading to the memory location of the LS 24, the busy bit becomes 0 and can be used for any purpose.

  As shown in FIG. 2A, the main memory 26 connected to each information processing controller further includes a plurality of sandboxes. The sandbox defines an area in the main memory 26, and each sandbox is assigned to each sub processor 23 and can be used exclusively by the sub processor. That is, each sub-processor 23 can use a sandbox assigned to itself, but cannot access data beyond this area.

  The main memory 26 is composed of a plurality of memory locations 0 to M, and the sandbox is a set of these memory locations. That is, one sandbox is composed of one or more memory locations.

  Further, in order to realize exclusive control of the main memory 26, a key management table as shown in FIG. The key management table is stored in a relatively high-speed memory such as SRAM in the information processing controller, and is associated with the DMAC 25.

  There are as many entries as the number of sub processors in the information processing controller in the key management table, and each entry stores a sub processor ID, a corresponding sub processor key, and a key mask in association with each other. .

  The process when the sub processor 23 uses the main memory 26 is as follows. First, the sub processor 23 transmits a read or write command to the DMAC 25. This command includes its own sub-processor ID and the address of the main memory 26 that is the access request destination.

  Before executing this command, the DMAC 25 refers to the key management table and checks the sub processor key of the access request source sub processor 23. Next, the DMAC 25 compares the checked access request source sub-processor key with the access key allocated to the memory location shown in FIG. Execute the above command only when two keys match.

  In the key mask on the key management table shown in FIG. 2C, when the arbitrary bit becomes 1, the corresponding bit of the sub-processor key associated with the key mask may become 0 or 1. it can.

  For example, assume that the sub-processor key is 1010. Normally, this sub-processor key only allows access to a sandbox with 1010 access keys. However, if the key mask associated with this sub-processor key is set to 0001, the match determination between the sub-processor key and the access key is masked only for the digit whose key mask bit is set to 1. The sub processor key 1010 enables access to a sandbox having an access key whose access key is either 1010 or 1011.

  As described above, the sandbox exclusivity of the main memory 26 is realized. That is, when it is necessary to process data in multiple stages by a plurality of sub-processors in one information processing controller, by configuring as described above, the sub-processor that performs the process in the previous stage and the process in the subsequent stage are processed. Only the sub processor that performs the access can access a predetermined address in the main memory 26, and data can be protected.

  For example, it can be used as follows. First, immediately after the information processing apparatus is activated, the values of the key masks are all zero. It is assumed that a program in the main processor is executed and operates in cooperation with the sub processor program in the sub processor. When the processing result data executed by the first sub-processor is temporarily stored in the main memory 26 and is transmitted to the second sub-processor, the corresponding main memory area can naturally be accessed from either sub-processor. There is a need. In such a case, the program in the main processor appropriately changes the value of the key mask and provides a main memory area that can be accessed from a plurality of sub processors, thereby enabling multi-stage processing by the sub processors. .

More specifically, it is a multi-step process in the order of data from another information processing apparatus → processing by the first sub processor → first main memory area → processing by the second sub processor → second main memory area. When processing is done,
Sub-processor key of the first sub-processor: 0100
First main memory area access key: 0100,
Sub-processor key of the second sub-processor: 0101,
Second main memory area access key: 0101,
If the setting is kept as described above, the second sub-processor cannot access the first main memory area. Therefore, by setting the key mask of the second sub processor to 0001, it is possible to allow the second sub processor to access the first main memory area.

(1-3. Generation and configuration of software cell)
In the network system of FIG. 1, software cells are transmitted between the information processing apparatuses 1, 2, 3, and 4 for distributed processing between the information processing apparatuses 1, 2, 3, and 4. That is, the main processor 21 included in the information processing controller in a certain information processing apparatus generates a software cell including a command, a program, and data, and transmits the software cell to another information processing apparatus via the network 9 to perform processing. Can be dispersed.

  FIG. 3 shows an example of the configuration of the software cell. The software cell in this example is composed of a transmission source ID, a transmission destination ID, a response destination ID, a cell interface, a DMA command, a program, and data as a whole.

  The transmission source ID includes the network address and information processing device ID of the information processing device that is the transmission source of the software cell, and the identifiers of the main processor 21 and each sub-processor 23 included in the information processing controller in the information processing device (main Processor ID and sub-processor ID).

  The transmission destination ID and the response destination ID include the same information about the information processing device that is the transmission destination of the software cell and the information processing device that is the response destination of the execution result of the software cell, respectively.

  The cell interface is information necessary for using the software cell, and includes a global ID, necessary sub-processor information, a sandbox size, and a previous software cell ID.

  The global ID can uniquely identify the software cell throughout the network, and is created based on the transmission source ID and the date and time (date and time) of creation or transmission of the software cell.

  In the necessary sub-processor information, the number of sub-processors necessary for executing the software cell is set. The sandbox size is set with the amount of memory in the main memory 26 and the LS 24 of the sub processor 23 necessary for executing the software cell.

  The previous software cell ID is an identifier of the previous software cell in a group of software cells that request sequential execution of streaming data or the like.

  The execution section of the software cell is composed of DMA commands, programs and data. The DMA command includes a series of DMA commands necessary for starting the program, and the program includes a sub processor program executed by the sub processor 23. The data here is data processed by a program including the sub processor program.

  Further, the DMA command includes a load command, a kick command, a function program execution command, a status request command, and a status return command.

  The load command is a command for loading information in the main memory 26 into the LS 24 in the sub processor 23, and includes a main memory address, a sub processor ID, and an LS address in addition to the load command itself. The main memory address indicates an address of a predetermined area in the main memory 26 from which information is loaded. The sub processor ID and the LS address indicate the identifier of the sub processor 23 to which information is loaded and the address of the LS 24.

  The kick command is a command for starting execution of the sub processor program, and includes a sub processor ID and a program counter in addition to the kick command itself. The sub processor ID identifies the sub processor 23 to be kicked, and the program counter gives an address for the program counter for executing the sub processor program.

  As will be described later, the function program execution command is a command for requesting execution of a function program from another information processing apparatus to another information processing apparatus. The information processing controller in the information processing apparatus that has received the function program execution command identifies a function program to be activated by a function program ID described later.

  The status request command is a command for requesting transmission of device information related to the current operation state (situation) of the information processing device indicated by the transmission destination ID to the information processing device indicated by the response destination ID. Although the function program will be described later, the program is categorized into the function program in the software configuration diagram stored in the main memory 26 of the information processing apparatus illustrated in FIG. 6. The function program is loaded into the main memory 26 and executed by the main processor 21.

  The status reply command is a command in which the information processing apparatus that has received the status request command responds to the information processing apparatus indicated by the response destination ID included in the status request command with its own apparatus information. The status reply command stores device information in the data area of the execution section.

  FIG. 4 shows the structure of the data area of the software cell when the DMA command is a status return command.

  The information processing device ID is an identifier for identifying the information processing device including the information processing controller, and indicates the ID of the information processing device that transmits the status reply command. The information processing apparatus ID is included in the information processing controller in the information processing apparatus by the main processor 21 included in the information processing controller in the information processing apparatus when the power is turned on. It is generated based on the number of sub processors 23 to be processed.

  The information processing device type ID includes a value representing the characteristics of the information processing device. The characteristics of the information processing apparatus include, for example, a hard disk recorder, a PDA (Personal Digital Assistant), a portable CD (Compact Disc) player, and the like, which will be described later. The information processing device type ID may represent a function of the information processing device such as video / audio recording or video / audio reproduction. It is assumed that values representing the characteristics and functions of the information processing apparatus are determined in advance, and it is possible to grasp the characteristics and functions of the information processing apparatus by reading the information processing apparatus type ID.

  The MS (master / slave) status indicates whether the information processing apparatus is operating as a master apparatus or a slave apparatus, as will be described later. When this is set to 0, it operates as a master apparatus. If it is set to 1, it indicates that it is operating as a slave device.

  The main processor operating frequency represents the operating frequency of the main processor 21 in the information processing controller. The main processor usage rate represents the usage rate in the main processor 21 for all programs currently running on the main processor 21. The main processor usage rate is a value representing the ratio of the processing capacity in use to the total processing capacity of the target main processor. For example, the main processor usage rate is calculated by using MIPS, which is a unit for evaluating the processor processing capacity, or per unit time. Calculated based on processor usage time. The same applies to the sub-processor usage rate described later.

  The number of sub-processors represents the number of sub-processors 23 included in the information processing controller. The sub processor ID is an identifier for identifying each sub processor 23 in the information processing controller.

  The sub processor status represents the state of each sub processor 23, and there are states such as “unused”, “reserved”, and “busy”. “unused” indicates that the sub-processor is not currently used and is not reserved for use. “reserved” indicates a state that is not currently used but reserved for use. Busy indicates that it is currently in use.

  The sub-processor usage rate represents the usage rate of the sub-processor for a sub-processor program that is currently being executed by the sub-processor or that is reserved for execution by the sub-processor. That is, the sub processor usage rate indicates the current usage rate when the sub processor status is busy, and indicates the estimated usage rate that is to be used later when the sub processor status is reserved.

  One set of sub-processor ID, sub-processor status, and sub-processor usage rate is set for one sub-processor 23, and is set for the number of sub-processors 23 in one information processing controller.

  The main memory total capacity and the main memory usage amount represent the total capacity and the currently used capacity of the main memory 26 connected to the information processing controller, respectively.

  The number of external recording units represents the number of external recording units 28 connected to the information processing controller. The external recording unit ID is information that uniquely identifies the external recording unit 28 connected to the information processing controller. The external recording unit type ID represents the type of the external recording unit (for example, hard disk, CD ± RW, DVD ± RW, memory disk, SRAM, ROM, etc.).

  The external recording unit total capacity and the external recording unit usage amount represent the total capacity and the currently used capacity of the external recording unit 28 identified by the external recording unit ID, respectively.

  An external recording unit ID, an external recording unit type ID, an external recording unit total capacity, and an external recording unit usage amount are set for one external recording unit 28 and connected to the information processing controller. The number of sets of the number of units 28 is set. That is, when a plurality of external recording units are connected to one information processing controller, a different external recording unit ID is assigned to each external recording unit, the external recording unit type ID, the external recording unit total capacity, and the external recording unit Department usage is also managed separately.

(1-4. Execution of software cell)
The main processor 21 included in the information processing controller in a certain information processing device generates a software cell having the above configuration and transmits it to the other information processing device and the information processing controller in the device via the network 9. . The transmission source information processing device, the transmission destination information processing device, the response destination information processing device, and the information processing controller in each device are identified by the transmission source ID, the transmission destination ID, and the response destination ID, respectively. .

  The main processor 21 included in the information processing controller in the information processing apparatus that has received the software cell stores the software cell in the main memory 26. Furthermore, the transmission destination main processor 21 reads the software cell and processes the DMA command included therein.

  Specifically, the transmission destination main processor 21 first executes a load command. As a result, information is loaded from the main memory address instructed by the load command into a predetermined area of the LS 24 in the sub processor specified by the sub processor ID and LS address included in the load command. The information loaded here is a sub-processor program or data included in the received software cell, or other designated data.

  Next, the main processor 21 transmits the kick command to the sub processor indicated by the sub processor ID included therein, together with the program counter included in the kick command.

  The instructed sub processor executes the sub processor program according to the kick command and the program counter. After the execution result is stored in the main memory 26, the main processor 21 is notified that the execution has been completed.

  Note that the processor that executes the software cell in the information processing controller in the information processing apparatus of the transmission destination is not limited to the sub-processor 23, but the main processor 21 executes a program for main memory such as a function program included in the software cell. It can also be specified to execute.

  In this case, the transmission source information processing apparatus includes a main memory program and data processed by the main memory program instead of the sub processor program, and the DMA command is sent to the transmission destination information processing apparatus. The software cell as a load command is transmitted, and the main memory 26 stores the main memory program and data processed thereby.

  Next, the transmission source information processing apparatus identifies the main processor ID, the main memory address, and the main memory program for the information processing controller in the transmission destination information processing apparatus for the transmission destination information processing apparatus. A software cell that includes an identifier such as a function program ID (to be described later) and a program counter and whose DMA command is a kick command or a function program execution command is transmitted to cause the main processor 21 to execute the main memory program.

  As described above, in the network system of the present invention, the transmission source information processing apparatus transmits the sub processor program or the main memory program to the transmission destination information processing apparatus by the software cell, and transmits the sub processor program to the transmission destination. It is possible to load the sub processor 23 included in the information processing controller in the information processing apparatus and cause the information processing apparatus of the transmission destination to execute the sub processor program or the main memory program.

  When the program included in the received software cell is a sub processor program, the information processing controller in the transmission destination information processing apparatus loads the sub processor program to the designated sub processor. Then, the sub processor program or the main memory program included in the software cell is executed.

  Therefore, even if the user does not operate the transmission destination information processing apparatus, the sub processor program or the main memory program can be automatically executed by the information processing controller in the transmission destination information processing apparatus.

  In this way, when the information processing controller in its own device does not have a main memory program such as a sub processor program or a function program, the information processing device can receive information from other information processing devices connected to the network. Can be obtained. Furthermore, data is transferred between each sub-processor and the main memory by the DMA method, and even when it is necessary to process data in multiple stages within one information processing controller by using the above-described sandbox. High-speed and high-security processing can be executed.

[2. Distributed processing as a network system 1]
As a result of distributed processing using software cells, a plurality of information processing apparatuses 1, 2, 3, and 4 connected to the network 9 as shown in the upper part of FIG. It operates as a single information processing device 7. However, for this purpose, the following processing needs to be executed by the following configuration.

(2-1. System software configuration and program loading)
FIG. 6 shows the configuration of software stored in the main memory 26 of each information processing controller. These software (programs) are recorded in the external recording unit 28 connected to the information processing controller before the information processing apparatus is turned on.

  Each program is categorized into a control program, a function program, and a device driver by function or feature.

  The control program is the same for each information processing controller, and is executed by the main processor 21 of each information processing controller, and includes an MS (master / slave) manager and a capability exchange program described later.

  The function program is executed by the main processor 21, and a function program corresponding to the information processing apparatus is provided for each information processing controller such as recording, reproduction, and material search.

  Device drivers are used for input / output (transmission / reception) of an information processing controller (information processing device), such as broadcast reception, monitor output, bit stream input / output, network input / output, etc. Provided.

  When the information processing apparatus is physically connected to the network 9 by plugging in a cable or the like, the main power supply is turned on and the information processing apparatus is electrically and functionally connected to the network 9. The main processor 21 of the information processing controller of the information processing apparatus loads each program belonging to the control program and each program belonging to the device driver into the main memory 26.

  As a loading procedure, the main processor 21 first reads a program from the external recording unit 28 by causing the DC 27 to execute a read command, and then causes the DMAC 25 to execute a write command to load the program into the main memory 26. Write to.

  As for each program belonging to the function program, it may be configured to load only the necessary program when necessary, or like the programs belonging to other categories, each program is loaded immediately after the main power is turned on. You may comprise as follows.

  Each program belonging to the function program does not need to be recorded in the external recording unit 28 of all information processing apparatuses connected to the network, but may be recorded in the external recording unit 28 of any one information processing apparatus. Since it can be loaded from another information processing apparatus by the above-described method, as a result, as shown in the lower part of FIG. 5, the function program can be executed as one virtual information processing apparatus 7.

  Further, as described above, the function program processed by the main processor 21 may cooperate with the sub processor program processed by the sub processor 23. Therefore, when the main processor 21 reads the function program from the external recording unit 28 and writes it to the main memory 26, if there is a sub processor program that operates in cooperation with the target function program, the sub processor program is also the same. Write to main memory 26. In this case, there may be one sub-processor program that operates in cooperation, but there may be a plurality of sub-processor programs. If there are a plurality of sub-processor programs that operate in cooperation, the sub-processor programs are written in the main memory 26.

  The sub processor program written in the main memory 26 is then written in the LS 24 in the sub processor 23 and operates in cooperation with the function program processed by the main processor 21.

  As shown in the software cell of FIG. 3, an identifier that can uniquely identify the program for each program is assigned to the function program as the function program ID. The function program ID is determined from the creation date and time, the information processing apparatus ID, and the like at the stage of creating the function program.

  A sub processor program ID is also assigned to the sub processor program, whereby the sub processor program can be uniquely identified. The assigned sub processor program ID may be an identifier related to the function program ID of the function program that is the partner of the cooperative operation, for example, an identifier with the function program ID as a parent number and a branch number added at the end. However, an identifier that is not related to the function program ID of the function program that is the partner of the cooperative operation may be used.

  In any case, when the function program and the sub processor program operate in cooperation, it is necessary to store the program ID, which is the other party's identifier, in the own program. Even when the function program operates in cooperation with a plurality of sub-processor programs, the function program stores all the sub-processor program IDs of the plurality of sub-processor programs.

  The main processor 21 secures an area for storing device information (information regarding the operation state) of the information processing device on which the main processor 21 operates in the main memory 26, and records the information as a device information table of the own device. The device information here is each piece of information below the information processing device ID shown in FIG.

(2-2. Determination of master / slave in the system)
In the network system described above, when the main power supply to a certain information processing apparatus is turned on, the main processor 21 of the information processing controller of the information processing apparatus loads a master / slave manager (hereinafter referred to as MS manager) into the main memory 26 and executes it. To do.

  When the MS manager detects that the information processing apparatus on which it operates is connected to the network 9, it confirms the existence of another information processing apparatus connected to the same network 9. The “connection” or “existence” here means that the information processing apparatus is not only physically connected to the network 9 but also electrically and functionally connected to the network 9 as described above. Indicates.

  Hereinafter, an information processing apparatus in which the device operates is referred to as an own device, and another information processing device is referred to as an other device. The apparatus also indicates the information processing apparatus.

  A method in which the MS manager confirms the existence of another information processing apparatus connected to the same network 9 will be described below.

  The MS manager generates a software cell in which the DMA command is a status request command, the transmission source ID and the response destination ID are the information processing apparatus, and the transmission destination ID is not specified, and the network manager is connected to the information processing apparatus. Set the timer for checking the network connection. The timeout time of the timer is, for example, 10 minutes.

  When another information processing apparatus is connected to the network system, the other apparatus receives the software cell of the status request command, and sends it to the information processing apparatus that has issued the status request command specified by the response destination ID. On the other hand, the DMA command is a status return command, and a software cell including device information of itself (other device) is transmitted as data. The software cell of this status reply command includes at least information for identifying the other device (information processing device ID, information on the main processor, information on the sub processor, etc.) and the MS status of the other device.

  The MS manager of the information processing apparatus that has issued the status request command monitors the reception of the software cell of the status reply command transmitted from another apparatus on the network until the timer for network connection confirmation times out. As a result, when the status reply command indicating the MS status = 0 (master device) is received, the MS status in the device information table of the own device is set to 1. As a result, the device becomes a slave device.

  On the other hand, if no status reply command is received before the network connection confirmation timer times out, or if no status reply command indicating MS status = 0 (master device) is received, The MS status in the device information table of the own device is set to 0. This makes the device a master device.

  That is, if no information processing apparatus is connected to the network 9 in a state where none of the apparatuses is connected to the network 9 or a master apparatus does not exist on the network 9, the apparatus automatically becomes the master apparatus. Set as On the other hand, when a new information processing apparatus is connected to the network 9 in a state where a master apparatus already exists on the network 9, the apparatus is automatically set as a slave apparatus.

  For both the master device and the slave device, the MS manager periodically monitors the status of the other device by sending a status request command to the other device on the network 9 and inquiring status information. As a result, the main power supply of the information processing apparatus connected to the network 9 is cut off or the information processing apparatus is disconnected from the network 9, so that the status from a specific other apparatus within a predetermined period set in advance for determination When there is a change in the connection state of the network 9, such as when a reply command is not returned or when a new information processing apparatus is connected to the network 9, the information is notified to the ability exchange program described later. .

(2-3. Acquisition of device information in master device and slave device)
When the main processor 21 receives an inquiry from another manager on the network 9 and a notification of completion of setting the MS status of the own apparatus from the MS manager, the main processor 21 executes the capability exchange program.

  When the own device is a master device, the capability exchange program acquires device information of all other devices connected to the network 9, that is, device information of each slave device.

  As described above, the device information of another device is generated by generating a software cell in which the DMA command is a status request command and transmitting it to the other device. Thereafter, the DMA command is a status return command and data of the other device. This is possible by receiving a software cell containing device information from another device.

  Similar to the device information table of the own device that is the master device, the capability exchange program sets an area for storing device information of all other devices (each slave device) connected to the network 9 as the main memory of the own device. This information is recorded in a device information table of another device (slave device).

  That is, the device information of all information processing devices connected to the network 9 including the device itself is recorded in the main memory 26 of the master device as a device information table.

  On the other hand, when the own device is a slave device, the capability exchange program obtains device information of all other devices connected to the network 9, that is, device information of each slave device other than the master device and the own device. The information processing device ID and the MS status included in the device information are recorded in the main memory 26 of the own device.

  That is, the device information of the own device is recorded as a device information table in the main memory 26 of the slave device, and the master device connected to the network 9 other than the own device and the information processing device ID for each slave device. And the MS status are recorded as another device information table.

  Further, in both the master device and the slave device, when the capability exchange program is notified from the MS manager that the information processing device is newly connected to the network 9, as described above, the device of the information processing device Information is acquired and recorded in the main memory 26 as described above.

  Note that the MS manager and the capability exchange program are not limited to being executed by the main processor 21, but may be executed by any of the sub processors 23. The MS manager and the capability exchange program are preferably resident programs that always operate while the main power supply of the information processing apparatus is turned on.

(2-4. When the information processing apparatus is disconnected from the network)
For both the master device and the slave device, the capability exchange program causes the MS manager to cut off the main power supply of the information processing device connected to the network 9 or disconnect the information processing device from the network 9 as described above. When it is notified, the apparatus information table of the information processing apparatus is deleted from the main memory 26 of the own apparatus.

  Further, when the information processing apparatus disconnected from the network 9 is a master apparatus, a new master apparatus is determined by the following method.

  Specifically, for example, each of the information processing apparatuses that are not disconnected from the network 9 replaces the information processing apparatus ID of the own apparatus and the other apparatus with a numerical value, and sets the information processing apparatus ID of the own apparatus to the information processing apparatus of the other apparatus. If the information processing device ID of the own device is the smallest among the information processing devices that are not disconnected from the network 9 as compared with the ID, the slave device moves to the master device and sets the MS status to 0, As described above, device information of all other devices (each slave device) connected to the network 9 is acquired as a master device and recorded in the main memory 26.

(2-5. Distributed processing based on device information)
As shown in the lower part of FIG. 5, in order for a plurality of information processing devices 1, 2, 3, and 4 connected to the network 9 to operate as a single virtual information processing device 7, the master device is a user. It is necessary to understand the operation of the slave device and the operating state of the slave device.

  FIG. 7 shows a state in which four information processing apparatuses operate as one virtual information processing apparatus 7. It is assumed that the information processing apparatus 1 is operating as a master apparatus and the information processing apparatuses 2, 3 and 4 are operating as slave apparatuses A, B and C.

  When the user operates an information processing device connected to the network 9, if the operation target is the master device 1, the operation information is directly grasped by the master device 1, and if the operation target is a slave device, The operation information is transmitted from the operated slave device to the master device 1. That is, regardless of whether the user's operation target is the master device 1 or the slave device, the operation information is always grasped by the master device 1. The operation information is transmitted, for example, by a software cell whose DMA command is an operation information transmission command.

  Then, the main processor 21-1 included in the information processing controller 11 in the master device 1 selects a function program to be executed according to the operation information. At that time, if necessary, the main processor 21-1 included in the information processing controller 11 in the master device 1 may transfer the main memory 26-1 from the external recording unit 28-1 or 28-2 of the own device by the above method. However, another information processing device (slave device) may transmit the function program to the master device 1.

  In the function program, information processing device type IDs represented as information shown in FIG. 4, main processor or sub-processor processing capacity, main memory usage, and conditions related to the external recording unit are required for each execution unit. The required specifications regarding the device are defined.

  The main processor 21-1 included in the information processing controller 11 in the master device 1 reads out the required specifications necessary for each function program. Also, the device information table of each information processing device is read by referring to the device information table recorded in the main memory 26-1 by the capability exchange program in advance. The device information here indicates each piece of information below the information processing device ID shown in FIG. 4, and is information relating to the main processor, sub processor, main memory, and external recording unit.

  The main processor 21-1 included in the information processing controller 11 in the master device 1 sequentially compares the device information of each information processing device connected on the network 9 with the required specifications necessary for executing the function program. To do.

  For example, when the function program requires a recording function, only the information processing apparatus having the recording function is specified and extracted based on the information processing apparatus type ID. Furthermore, a slave device that can secure the conditions regarding the processing capability of the main processor or sub processor, the amount of main memory used, and the external recording unit necessary for executing the function program is specified as an execution request candidate device. Here, when a plurality of execution request candidate devices are specified, one execution request candidate device is specified and selected from the candidate devices.

  When the slave device to be executed is specified, the main processor 21-1 included in the information processing controller 11 in the master device 1 sets the main memory included in the information processing controller 11 in the own device for the specified slave device. The device information table of the slave device recorded in 26-1 is updated.

  Further, the main processor 21-1 included in the information processing controller 11 in the master device 1 generates a software cell whose DMA command is a function program execution command, and the cell interface of the software cell needs a function program related to the function program. The sub-processor information and the sandbox size (see FIG. 3) are set and transmitted to the slave device requested to execute.

  The slave device requested to execute the function program executes the function program and updates the device information table of the own device. At that time, if necessary, the main processor 21 included in the information processing controller in the slave device, from the external recording unit 28 of the own device to the main memory 26 by the above method, the function program and the sub-operation that operates in cooperation with the function program. Load the processor program.

  When the required function program or the sub processor program that operates in cooperation with the function program is not recorded in the external recording unit 28 of the slave device requested to execute the function program, the other information processing apparatus Alternatively, the system may be configured so that the sub processor program is transmitted to the function program execution request destination slave device.

  The sub-processor program can be executed by another information processing apparatus using the aforementioned load command and kick command.

  After the execution of the function program, the main processor 21 included in the information processing controller in the slave device that has executed the function program transmits an end notification to the main processor 21-1 included in the information processing controller 11 in the master device 1. At the same time, the device information table of the own device is updated. The main processor 21-1 included in the information processing controller 11 in the master device 1 receives the end notification and updates the device information table of the slave device that has executed the function program.

  The main processor 21-1 included in the information processing controller 11 in the master device 1 identifies itself as an information processing device that can execute the function program from the reference result of the device information table of the own device and the other device. There is also a case of selecting. In that case, the master device 1 executes the function program.

  In the example of FIG. 7, the case where the user operates the slave device A (information processing device 2) and another slave device B (information processing device 3) executes a function program corresponding to the operation will be described with reference to FIG. An example of distributed processing is shown.

  In the example of FIG. 8, when the user operates the slave device A, distributed processing of the entire network system including the slave device A starts. First, in step 81, the slave device A transmits the operation information to the master device. 1 to send.

  In step 72, the master device 1 receives the operation information, and further proceeds to step 73, where each information processing is performed from the device information table of the own device and other devices recorded in the main memory 26-1 of the own device. The operating state of the apparatus is checked, and an information processing apparatus that can execute a function program corresponding to the received operation information is selected. This example is a case where the slave device B is selected.

  Next, in step 74, the master device 1 requests the selected slave device B to execute the function program.

  In step 95, the slave device B receives the execution request, and further proceeds to step 96 to execute the function program requested to be executed.

  As described above, by operating only one information processing apparatus, the user operates a plurality of information processing apparatuses 1, 2, 3, and 4 in a virtual one without operating other information processing apparatuses. The information processing apparatus 7 can be operated.

(2-6. Specific examples of information processing apparatuses and systems)
The information processing apparatuses 1, 2, 3 and 4 connected to each other via the network 9 are basically any ones that perform information processing by the information processing controllers 11, 12, 13 and 14 as described above. An example is shown in FIG.

  In this example, the information processing apparatus 1 including the information processing controller 11 is a hard disk recorder. As shown in FIG. 10, the hardware configuration is a built-in hard disk as the external recording unit 28-1 shown in FIG. As the external recording unit 28-2 shown in FIG. 1, an optical disc such as DVD ± R / RW, CD ± R / RW, Blu-ray Disc (registered trademark) can be mounted, and the information processing controller 11 The bus 31-1 connected to the bus 29-1 includes a broadcast receiving unit 32-1, a video input unit 33-1, an audio input unit 34-1, a video output unit 35-1, an audio output unit 36-1, The operation panel unit 37-1, the remote control light receiving unit 38-1, and the network connection unit 39-1 are connected.

  The broadcast receiving unit 32-1, the video input unit 33-1 and the audio input unit 34-1 receive a broadcast signal or input a video signal and an audio signal from the outside of the information processing apparatus 1, and each has a digital format of a predetermined format. The data is converted into data and sent to the bus 31-1 for processing by the information processing controller 11. The video output unit 35-1 and the audio output unit 36-1 are transferred from the information processing controller 11 to the bus 31-. The video data and the audio data sent to 1 are processed, converted into digital data or converted into analog signals, and sent to the outside of the information processing apparatus 1. The remote control (remote operation) infrared signal is received from the transmitter 43-1.

  As shown in FIGS. 9 and 10, a monitor display device 41 and a speaker device 42 are connected to the video output unit 35-1 and the audio output unit 36-1 of the information processing apparatus (hard disk recorder) 1.

  The information processing apparatus 2 including the information processing controller 12 in the example of FIG. 9 is also a hard disk recorder and is configured in the same manner as the information processing apparatus 1 as indicated by reference numerals in parentheses in FIG. is there. However, for example, as shown in FIG. 9, a monitor display device and a speaker device are not connected to the information processing device (hard disk recorder) 2.

  As shown in FIG. 11, the software configuration of the information processing apparatuses (hard disk recorders) 1 and 2, that is, the information processing controllers 11 and 12, includes an MS manager and a capability exchange program as control programs, and video and audio as function programs. Programs for recording, video / audio playback, material search and program recording reservation are provided, and programs for broadcast reception, video output, audio output, external recording unit input / output and network input / output are provided as device drivers.

  The information processing apparatus 3 including the information processing controller 13 in the example of FIG. 9 is a PDA (Personal Digital Assistant), and as illustrated in FIG. 12, the hardware configuration is the external recording unit 28-5 illustrated in FIG. The memory card disk is configured so that it can be mounted, and the liquid crystal display unit 52, the audio output unit 53, the camera unit 54, and the audio input unit 55 are connected to the bus 51 connected to the bus 29-3 of the information processing controller 13. The keyboard unit 56 and the network connection unit 57 are connected.

  1, the information processing controller 13 whose internals are omitted is a main processor 21-3, sub processors 23-7, 23-8 and 23-9, a DMAC (direct memory access controller) 25-3, a DC (disk controller). ) 27-3 and the bus 29-3, the main processor 21-3 has an LS (local storage) 22-3, and each of the sub processors 23-7, 23-8 and 23-9 has an LS (Local storage) 24-7, 24-8 and 24-9.

  As shown in FIG. 13, the software configuration of the information processing apparatus (PDA) 3, that is, the information processing controller 13, includes an MS manager and a capability exchange program as a control program, and video / audio recording and video / audio reproduction as function programs. , A phone book, a word processor and a spreadsheet program, and a Web browser, and device drivers include video output, audio output, camera video input, microphone audio input, and network input / output programs.

  The information processing apparatus 4 including the information processing controller 14 in the example of FIG. 9 is a portable CD player. As shown in FIG. 14, the hardware configuration is a CD as the external recording unit 28-6 shown in FIG. (Compact Disc) can be mounted, and the liquid crystal display unit 62, the audio output unit 63, the operation button unit 64, and the network connection unit 65 are connected to the bus 61 connected to the bus 29-4 of the information processing controller 14. Are connected.

  1, the information processing controller 14 whose interior is omitted is a main processor 21-4, sub processors 23-10, 23-11 and 23-12, a DMAC (direct memory access controller) 25-4, and a DC (disk controller). ) 27-4, and a bus 29-4, the main processor 21-4 has an LS (local storage) 22-4, and each of the sub processors 23-10, 23-11 and 23-12 has an LS (Local Storage) 24-10, 24-11 and 24-12.

  As shown in FIG. 15, the software configuration of the information processing apparatus (portable CD player) 4, that is, the information processing controller 14, includes an MS manager and a capability exchange program as a control program, and a function program for playing music. A program for audio output, CD control, and network input / output is provided as a device driver.

  In the network system of the example of FIG. 9 as described above, the information processing devices 1, 3 and 4 are connected to the network 9, and the information processing device 1 is the master device (MS status = 0). And 4 are set as slave devices (MS status = 1).

  In this state, when the information processing apparatus 2 is newly connected to the network 9, the MS manager executed by the main processor 21-2 included in the information processing controller 12 in the information processing apparatus 2 is The other information processing devices 1, 3 and 4 are inquired about the MS status, recognizes that the information processing device 1 already exists as a master device, and sets its own device (information processing device 2) as a slave device (MS status = Set to 1). Further, the information processing device 1 set as the master device collects device information of each device including the newly added information processing device 2 and updates the device information table in the main memory 26-1.

  In this state, a case where a user performs an operation for recording reservation of a broadcast program for 2 hours in the information processing apparatus (PDA) 3 as a slave apparatus is shown.

  In this case, the information processing apparatus (PDA) 3 which is a slave apparatus receives input of recording reservation information including information such as a recording start time, a recording end time, a recording target broadcast channel, and recording quality from the user, and the recording reservation information And a software cell including a recording reservation command as a DMA command is generated and transmitted to the information processing apparatus 1 which is a master apparatus.

  The main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that has received the software cell whose DMA command is the recording reservation command reads out the recording reservation command and also stores the apparatus information table in the main memory 26-1. The information processing apparatus that can execute the recording reservation command is specified.

  First, the main processor 21-1 reads information processing device type IDs of the information processing devices 1, 2, 3, and 4 included in the device information table and can execute a function program corresponding to the recording reservation command. Extract the device. Here, the information processing devices 1 and 2 having the information processing device type ID indicating the recording function are specified as candidate devices, and the information processing devices 3 and 4 are excluded from the candidate devices.

  Next, the main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that is the master apparatus refers to the apparatus information table, and the processing capability of the main processor or sub-processor of the information processing apparatuses 1 and 2. Then, information related to the device such as information related to the main memory is read out, and it is determined whether or not the information processing devices 1 and 2 satisfy the required specifications necessary for executing the function program corresponding to the recording reservation command. Here, it is assumed that both the information processing apparatuses 1 and 2 satisfy the required specifications necessary for executing the function program corresponding to the recording reservation command.

  Further, the main processor 21-1 refers to the device information table, reads information related to the external recording units of the information processing apparatuses 1 and 2, and determines that the free capacity of the external recording unit is necessary for executing the recording reservation command. Determine if you are satisfied. Since the information processing apparatuses 1 and 2 are hard disk recorders, the difference between the total capacity and the usage of the hard disks 28-1 and 28-3 corresponds to the respective free capacity.

  In this case, the free capacity of the hard disk 28-1 of the information processing apparatus 1 is 10 minutes in terms of recording time, and the free capacity of the hard disk 28-3 of the information processing apparatus 2 is 20 hours in terms of recording time. Suppose that

  At this time, the main processor 21-1 included in the information processing controller 11 in the information processing apparatus 1 that is the master apparatus is an information processing apparatus that can secure a free space for two hours necessary for execution of the recording reservation command. Identifies as an execution request destination slave device.

  As a result, only the information processing device 2 is selected as the execution request destination slave device, and the main processor 21-1 included in the information processing controller 11 in the information processing device 1 that is the master device receives the information processing device operated by the user. The recording reservation command including the recording reservation information transmitted from 3 is transmitted to the information processing device 2 to request execution of the recording reservation of the broadcast program for 2 hours.

  Then, the main processor 21-2 included in the information processing controller 12 in the information processing apparatus 2 analyzes the recording reservation command and sends a function program necessary for recording from the hard disk 28-3 as an external recording unit to the main memory. 26-2, and recording is performed according to the recording reservation information. As a result, the video / audio data of the 2-hour broadcast program reserved for recording is recorded in the hard disk 28-3 of the information processing apparatus 2.

  As described above, also in the network system of the example of FIG. 9, the user operates only one information processing apparatus, and operates a plurality of information processing apparatuses 1, 2, 2 without operating other information processing apparatuses. 3 and 4 can be operated as one virtual information processing apparatus 7.

[3. Basic configuration of network system and information processing apparatus 2]
FIG. 16 shows another example of the network system of the present invention, in which a plurality of information processing apparatuses 1001, 1002, 1003 and 1004 are connected via a network 1009.

(3-1. Information processing apparatus and information processing controller)
The information processing apparatuses 1001, 1002, 1003, and 1004 are various AV (Audio and Visual) devices and portable devices as described below.

  As for the information processing apparatus 1001, the information processing apparatus 1001 includes an information processing controller 1011 as a computer function unit. The information processing controller 1011 includes a main processor 1021-1, sub processors 1023-1, 1023-2, and 1023-3, a DMAC (direct memory access controller) 1025-1, a control register 1028-1, a work memory 1029-1, and A DC (disk controller) 1030-1 is included.

  The main processor 1021-1 performs schedule management of execution (data processing) of sub processor programs by the sub processors 1023-1, 1023-2, and 1023-3, and general management of the information processing controller 1011 (information processing apparatus 1001). And do. However, the main processor 1021-1 may be configured to operate a program other than the management program. In that case, the main processor 1021-1 also functions as a sub processor. The main processor 1021-1 has an LS (local storage) 1022-1.

  There may be one sub-processor, but preferably there are a plurality of sub-processors. This example is a plurality of cases.

  Each of the sub processors 1023-1, 1023-2, and 1023-3 executes the sub processor program and processes data in parallel and independently under the control of the main processor 1021-1. Further, in some cases, the program in the main processor 1021-1 may be configured to operate in cooperation with the sub processor program in the sub processor 1023-1, 1023-2, or 1023-3. A function program described later is also a program that operates in the main processor 1021-1. Each of the sub processors 1023-1, 1023-2, and 1023-3 also has LS (local storage) 1024-1, 1024-2, and 1024-3.

  The DMAC 1025-1 is a program and data stored in the main memory 1026-1 made of DRAM (dynamic RAM) and the sub memory 1027-1 made of SRAM (static RAM), etc., respectively connected to the information processing controller 1011. Is for accessing. Through the DMAC 1025-1, data can be transferred between each sub-processor and the main memory 1026-1 by the DMA method, and high speed can be realized.

  The control register 1028-1 determines which sub-processor program to be processed in the information processing controller 1011 is processed by which sub-processor, and moreover, a later-described processing thread existing in the sub-processor. And is used to manage the progress of the sub processor program execution by the sub processor.

  The work memory 1029-1 is a work memory including an SRAM included in the information processing controller 1011 and is accessed by the main processor 1021-1 and the sub processors 1023-1, 1023-2, and 1023-3.

  The DC 1030-1 accesses the external recording units 1031-1 and 1031-2 connected to the information processing controller 1011.

  The external recording units 1031-1 and 1031-2 may be fixed disks (hard disks) or removable disks, and optical disks such as MO, CD ± RW, DVD ± RW, memory disks, SRAM (static RAM), ROM, etc. Various types can be used. Therefore, the DC 1030-1 is called a disk controller, but is an external recording unit controller.

  As in the example of FIG. 16, the information processing controller 1011 can be configured such that a plurality of external recording units 1031 can be connected to the information processing controller 1011.

  The main processor 1021-1, the sub processors 1023-1, 1023-2, and 1023-3, the DMAC 1025-1, the control register 1028-1, the work memory 1029-1, and the DC 1030-1 are connected by a bus 1032-1. The

  An identifier capable of uniquely identifying the information processing apparatus 1001 including the information processing controller 1011 throughout the entire network is assigned to the information processing controller 1011 as the information processing apparatus ID.

  Similarly, identifiers that can specify the main processor 1021-1 and the sub processors 1023-1, 1023-2, and 1023-3 are assigned as the main processor ID and the sub processor ID.

  The information processing controller 1011 is preferably configured as a one-chip IC (integrated circuit).

  The other information processing apparatuses 1002, 1003 and 1004 are configured similarly. Here, units having the same parent number perform the same function even if the branch numbers are different, unless otherwise specified. Further, in the following description, when the branch number is omitted, it is assumed that the difference in the branch number does not occur.

(3-2. Access to main memory from each sub processor)
As described above, each sub-processor 1023 in one information processing controller independently executes a sub-processor program and processes data, but different sub-processors can read or write simultaneously to the same area in the main memory 1026. When writing is performed, data mismatch may occur. Therefore, access from the sub processor 1023 to the main memory 1026 is performed according to the following procedure.

  Similarly, regarding the sub memory 1027 and the work memory 1029, it is conceivable that different sub processors simultaneously access the same area. Here, the main memory 1026 is shown.

  As shown in FIG. 17A, the main memory 1026 includes a plurality of addressable memory locations 0 to N. For each memory location, additional segments 0 to N for storing information indicating the state of data are allocated. The additional segment includes an F / E bit, a sub processor ID, and an LS address (local storage address). In addition, access keys 0 to N described later are also assigned to each memory location. The F / E bit is defined as follows.

  The F / E bit = 0 indicates that data being processed being read by the sub-processor 1023 or invalid data that is not the latest data because it is empty, and cannot be read. The F / E bit = 0 indicates that data can be written to the memory location, and is set to 1 after writing.

  The F / E bit = 1 indicates that the data in the memory location is not read by the sub processor 1023 and is the latest unprocessed data. The data in the memory location can be read and set to 0 after being read by the sub processor 1023. Further, the F / E bit = 1 indicates that the memory location cannot write data.

  Furthermore, it is possible to set a read reservation for the memory location in the state where the F / E bit = 0 (read disabled / write enabled). When a read reservation is made for a memory location with the F / E bit = 0, the sub processor 1023 adds the sub processor ID and LS of the sub processor 1023 as read reservation information to an additional segment of the memory location where the read reservation is made. Write the address.

  Thereafter, when data is written to the memory location reserved for reading by the sub processor 1023 on the data writing side and the F / E bit is set to 1 (readable / not writable), it is added to the additional segment as read reservation information in advance. Read to the written sub-processor ID and LS address.

  When it is necessary to process data in multiple stages by a plurality of sub-processors, the sub-processor 1023 that performs the process in the previous stage can control the processed data by controlling the reading / writing of data in each memory location in this way. Can be read out at a predetermined address in the main memory 1026, and another sub-processor 1023 that performs the subsequent processing can read out the data after the preprocessing.

  As shown in FIG. 17B, the LS 1024 in each sub-processor 1023 is also configured by a plurality of addressable memory locations 0 to L. Similarly, additional segments 0 to L are allocated to each memory location. The additional segment includes a busy bit.

  When the sub processor 1023 reads the data in the main memory 1026 to the memory location of its own LS 1024, it reserves by setting the busy bit corresponding to the memory location of the read destination to 1. No other data can be stored in the memory location where the busy bit is 1. After reading to the memory location of LS1024, the busy bit will be 0 and can be used for any purpose.

  As shown in FIG. 17A, the main memory 1026 connected to each information processing controller further includes a plurality of sandboxes. The sandbox defines an area in the main memory 1026. Each sandbox is assigned to each sub processor 1023 and can be used exclusively by the sub processor. That is, each sub-processor 1023 can use a sandbox assigned to itself, but cannot access data beyond this area.

  The main memory 1026 is composed of a plurality of memory locations 0 to N, and the sandbox is a collection of these memory locations. That is, one sandbox is composed of one or more memory locations.

  Furthermore, in order to realize exclusive control of the main memory 1026, a key management table as shown in FIG. 17C is used. The key management table is stored in a relatively high-speed memory such as SRAM in the information processing controller, and is associated with the DMAC 1025. However, the key management table may be stored in the work memory 1029.

  There are as many entries as the number of sub processors in the information processing controller in the key management table, and each entry stores a sub processor ID, a corresponding sub processor key, and a key mask in association with each other. .

  The process when the sub processor 1023 uses the main memory 1026 is as follows. First, the sub processor 1023 transmits a read or write command to the DMAC 1025. This command includes its own sub processor ID and an address in the main memory 1026 that is an access request destination.

  Before executing this command, the DMAC 1025 refers to the key management table and checks the sub processor key of the access request source sub processor 1023. Next, the DMAC 1025 compares the sub-processor key of the checked access request source with the access key allocated to the memory location shown in FIG. 17A in the main memory 1026 that is the access request destination, Execute the above command only when two keys match.

  In the key mask on the key management table shown in FIG. 17C, when the arbitrary bit becomes 1, the corresponding bit of the sub processor key associated with the key mask may become 0 or 1. it can.

  For example, assume that the sub-processor key is 1010. Normally, only a sandbox having an access key of 1010 can be accessed by this sub-processor key. However, if the key mask associated with this sub-processor key is set to 0001, the match determination between the sub-processor key and the access key is masked only for the digit whose key mask bit is set to 1. The sub processor key 1010 enables access to a sandbox having an access key whose access key is either 1010 or 1011.

  As described above, the sandbox exclusivity of the main memory 1026 is realized. That is, when it is necessary to process data in multiple stages by a plurality of sub-processors in one information processing controller, by configuring as described above, the sub-processor that performs the process in the previous stage and the process in the subsequent stage are processed. Only the executing sub-processor can access a predetermined address in the main memory 1026, and data can be protected.

  For example, it can be used as follows. First, immediately after the information processing apparatus is activated, the values of the key masks are all zero. It is assumed that a program in the main processor is executed and operates in cooperation with the sub processor program in the sub processor. When processing result data executed by the first sub-processor is temporarily stored in the main memory 1026 and transmitted to the second sub-processor, the corresponding main memory area can be accessed from either sub-processor. There is a need. In such a case, the program in the main processor appropriately changes the value of the key mask and provides a main memory area that can be accessed from a plurality of sub processors, thereby enabling multi-stage processing by the sub processors. .

More specifically, it is a multi-step process in the order of data from another information processing apparatus → processing by the first sub processor → first main memory area → processing by the second sub processor → second main memory area. When processing is done,
Sub-processor key of the first sub-processor: 0100
First main memory area access key: 0100,
Sub-processor key of the second sub-processor: 0101,
Second main memory area access key: 0101,
If the setting is kept as described above, the second sub-processor cannot access the first main memory area. Therefore, by setting the key mask of the second sub processor to 0001, it is possible to allow the second sub processor to access the first main memory area.

(3-3. Access to main memory and sub memory from each sub processor)
Each sub processor 1023 in one information processing controller can read or write to the sub memory 1027 as well as the main memory 1026, but there are several types of commands. It is possible that there may be high and low priority. Therefore, a configuration and a procedure for each sub processor 1023 to use the main memory 1026 and the sub memory 1027 accurately will be described below.

  As shown in FIG. 18, the DMAC 1025 has a main memory control register 1033 and a sub memory control register 1034 inside. The main memory control register 1033 is for accessing the main memory 1026, and the sub memory control register 1034 is for accessing the sub memory 1027.

  The main memory control register 1033 is composed of the following four blocks, each storing a command for accessing the main memory 1026 as follows.

  In the priority command block, a plurality of commands with high priority are stored. The command is processed preferentially.

  The normal command block 1 stores a plurality of normal commands, and the normal command block 2 also stores a plurality of normal commands. Although there is no functional difference between the normal command block 1 and the normal command block 2, for example, a command before execution of access to the main memory 1026 is stored in one block, and a command after execution is stored in the other By storing in a block, there is an effect that commands before and after execution can be processed intensively and continuously, respectively.

  The order command block stores a plurality of commands that need to be processed in the correct order. That is, the commands from each sub-processor 1023 are stored in the order received, together with the sub-processor ID of the sub-processor that is the command transmission source. As a result, the commands can be processed in the order received, and the execution results can be returned to the command transmission source sub-processor in the same order.

  The sub memory control register 1034 is also composed of the following four blocks, and each stores a command for accessing the sub memory 1027 as follows.

  In the priority command block, a plurality of commands with high priority are stored. The command is processed preferentially.

  A plurality of read commands are stored in the read command block, and a plurality of write commands are stored in the write command block.

  The waiting command block stores a plurality of commands that are attempted to access any area in the sub memory 1027 but cannot be accessed because the target area is locked. When unlocked, the command moves to the priority command block.

  Each sub processor 1023 accesses the main memory 1026 or the sub memory 1027 by a command having a structure as shown in FIG. 19, for example. The response of the execution result from the main memory 1026 or the sub memory 1027 after the access execution has the same structure.

  In this command / response structure, the command type includes read and write. The priority command identifier indicates that the command has a high priority. The normal command identifier is for accessing the main memory 1026 and indicates that the command is stored in the normal command block 1 or the normal command block 2.

  The chain command identifier is also used when accessing the main memory 1026, and indicates that the command requires continuous access together with the command immediately before or after. Alternatively, it may be a serial number of consecutive command strings. The command in which the chain command identifier is set is stored in the order command block, but the processing priority is higher than the commands in the priority command block.

  The address here indicates an address in the main memory 1026 or the sub memory 1027 that executes the command. Alternatively, an address in the work memory 1029 may be used.

  The sub processor identifier is the sub processor ID of the sub processor of the command transmission source. The processing thread identifier is an identifier of a processing thread, which will be described later, which is a command transmission source.

  OK / NG indicates success / failure of the command. The data here is read data included in the response when the read command is executed, or data to be written included in the command when the write command is executed.

  As shown in FIG. 18, in the DMAC 1025, the above-mentioned main memory control register 1033 for each sub processor 1023 to access the main memory 1026 correctly, and each sub processor 1023 to access the sub memory 1027 correctly. In addition to the sub memory control register 1034, the main processor 1021 can store a plurality of read commands and write commands for accessing the main memory 1026 or the sub memory 1027, and a main processor read command block 1035 and a main processor write command. A block 1036 can also be provided. The address conversion register 1037 will be described later.

  Further, when a plurality of sub processors transmit memory access commands having the same priority to the DMAC 1025 at the same timing, the following procedure is followed. That is, the DMAC 1025 has a pointer indicating the last sub-processor that has succeeded in accessing the memory, and when a memory access command having the same priority is received from a plurality of sub-processors at the same timing, the value is larger than that of the pointer. The command having the smallest difference from the pointer is given priority. In this case, the smallest pointer value follows the largest pointer value.

(3-4. Access to sub memory for accurate access to main memory from each sub processor)
Naturally, the main memory 1026 composed of a DRAM and the like and the sub memory 1027 composed of an SRAM and the like naturally have different purposes and have different purposes of use.

  Therefore, as an example of a method of using the main memory 1026 and the sub memory 1027 in combination, it can be considered that the sub memory 1027 performs address conversion when each sub processor 1023 accesses the main memory 1026. The configuration and procedure for this are shown in FIG.

  As described above, the main memory 1026 is composed of a plurality of memory locations, and one sandbox is composed of one or a plurality of memory locations. Each sub-processor 1023 can exclusively use the sandbox assigned to itself.

  For example, as shown in FIG. 20A, it is assumed that sandboxes 1, 2, and 3 in the main memory 1026 are assigned to a certain sub processor 1023. The sandbox 1 is 0x800 to 0x8FF, the sandbox 2 is 0x200 to 0x2FF, the sandbox 3 is 0xF00 to 0xFFF, and each sandbox is identified by the head address. In other words, each assigned sandbox may not have consecutive addresses.

  When the sub processor 1023 reads data from these sandboxes 1, 2, and 3, it first accesses the address conversion register 1037 in the DMAC 1025.

  The address conversion register 1037 is a register that associates the sub processor 1023 with the sandbox assigned to the sub processor 1023, and includes the same number of entries as the number of sub processors 1023. Here, it is assumed that the entry indicated by Q1 corresponds to the sub-processor 1023.

  At this time, the sub processor 1023 reads the value of Q1 corresponding to itself. Further, data (0x20) is read from the first address in the sub memory 1027 indicated by the read Q1 value (0x80).

  The area of the sandbox 1 is specified based on the value of Q1. For example, a value obtained by multiplying the value of Q1 by 16 indicates the start address of the sandbox 1, and a value obtained by adding 255 to the start address indicates the end address of the sandbox 1. Therefore, when the value of Q1 is 0x80 as described above, the area of the sandbox 1 is 0x800 to 0x8FF.

  The sub processor 1023 reads data (0xF0) from the second address in the same sub memory 1027 indicated by the data (0x20) read from the first address.

  The area of the sandbox 2 is specified based on the data read from the second address. Specifically, like the sandbox 1, the value obtained by multiplying the value of the data read from the second address by 16 indicates the start address of the sandbox 2, and the value obtained by adding 255 to the start address is the sandbox. 2 indicates the end address. Therefore, when the data read from the second address is 0xF0 as described above, the area of the sandbox 2 is 0x200 to 0x2FF.

  Further, the sub processor 1023 reads data (0x00) from the third address in the same sub memory 1027 indicated by the data (0xF0) read from the second address. 0x00 indicates the end of the assigned sandbox.

  The area of the sandbox 3 is specified based on the data read from the third address. Specifically, like the sandboxes 1 and 2, the value obtained by multiplying the value of the data read from the third address by 16 indicates the head address of the sandbox 3, and the value obtained by adding 255 to the head address is Indicates the end address of the sandbox 3. Therefore, when the data read from the third address is 0x00 as described above, the area of the sandbox 3 is 0xF00 to 0xFFF.

  As described above, each sub-processor 1023 can accurately access the assigned sandbox even if the address of the sandbox assigned to the sub-processor 1023 is non-consecutive. It can be read reliably.

  Next, the same sub-processor 1023 writes data into a new sandbox in the main memory 1026 and adds the sandbox to a sandbox group managed by an entry corresponding to itself in the address translation register 1037. The procedure is shown with reference to FIG.

  It is assumed that the sub processor 1023 writes data to the sandbox 4 that is an area from 0x000 to 0x0FF in the main memory 1026. At this time, the sub-processor 1023 first reads the value of Q1 (the initial value of Q1, for example, 0x80 as described above).

  Next, the sub-processor 1023 writes the previously read Q1 value (0x80) to an address in the sub-memory 1027 that can identify the sandbox 4 in which data is newly written. For example, since data is written in the area from 0x000 to 0x0FF this time, the value of Q1 (0x80) is written to the address in the sub memory 1027 indicated by 0x00 obtained by dividing 0x000, which is the start address, by 16. Further, the address (0x00) in the sub memory 1027 in which the value of Q1 (0x80) has been written is written to Q1 in the address conversion register 1037 as a new value of Q1.

  As described above, each sub-processor 1023 can add a new sandbox to an existing sandbox group. Also in this case, the address of each sandbox may be discontinuous. Further, when there is no existing sandbox group and the first sandbox is associated with the sub memory 1027 and the address translation register 1037, the above method can be used.

(3-5. Access to work memory from main processor and each sub processor)
As described above, the main memory 1026 is configured by a DRAM or the like, and further, data is transferred by the DMA method. Therefore, each sub processor 1023 can use the large-capacity main memory 1026 at high speed. Further, the sub memory 1027 is constituted by an SRAM or the like and can be used at a high speed as well.

  Further, if the main processor 1021 and each sub-processor 1023 can share and use the work memory 1029 included in the information processing controller as a work memory together with the main memory 1026 and the sub memory 1027 connected to the information processing controller, High speed can be realized.

  In addition, it is efficient if a simple numerical calculation can be performed by the work memory 1029. Since the work memory 1029 is composed of SRAM or the like as described above, it cannot be expected to increase the capacity like a DRAM, but is very fast.

  The configuration and procedure in the case where the main processor 1021 and each sub processor 1023 access the work memory 1029 will be described below.

  As shown in FIG. 21, the work memory 1029 includes a controller 1038 and a RAM 1039. An SRAM can be used as the RAM 1039, but is not limited thereto. The RAM 1039 is composed of a plurality of blocks. Each block is assigned an address and stores data.

  The main processor 1021 and each sub processor 1023 access the RAM 1039 through the controller 1038. Specifically, the main processor 1021 and each sub-processor 1023 transmit a command, address, data, or the like to the controller 1038, and the controller 1038 accesses the RAM 1039 accordingly.

  After executing the process, the controller 1038 returns the command execution result to the main processor 1021 or sub-processor 1023 that is the command transmission source.

  The command used when each sub processor 1023 accesses the work memory 1029 is the same as that used when accessing the main memory 1026 or the sub memory 1027 as shown in FIG. 19, for example. The response of the execution result from the work memory 1029 after the process execution has the same structure.

  However, when accessing the work memory 1029, the priority command identifier, normal command identifier, chain command identifier, and processing thread identifier in the command shown in FIG. 19 are basically not used. However, it may be used if the work memory 1029 can handle these identifiers. There are several possible command types as shown below.

  The first is a read command. This is used to read data in the work memory 1029. The main processor 1021 and each sub-processor 1023 also transmit the address of the block in the RAM 1039 that stores the desired data together with the read command. The controller 1038 returns OK / NG indicating the success / failure of the read command and the read data as an execution result.

  The second is a write command. This is used to write data into the work memory 1029. The main processor 1021 and each sub-processor 1023 transmit a write command, data, and an address of a block in the RAM 1039 for storing the data. The controller 1038 returns OK / NG indicating the success / failure of the write command as the execution result.

  The third is an addition command. This is used to add data in the work memory 1029. The main processor 1021 and each sub-processor 1023 transmit the addition command and the address of the block in the RAM 1039 that stores the data to be added. The controller 1038 adds 1 to the data in the block of the received address and overwrites it. As an execution result, OK / NG indicating success / failure of the addition command is returned.

  The fourth is a set command. This is used to manipulate the data in the work memory 1029 in bit units. The main processor 1021 and each sub-processor 1023 transmit a set command, an address of a block in the RAM 1039 for storing data to be operated, and mask data.

  On the other hand, the controller 1038 compares the received mask data with the data in the block of the received address, and sets the value of the bit in the data at the same position as the bit whose value is 1 in the mask data. . Completed indicating completion of the set command is returned as an execution result. At this time, the success / failure of the command may be confirmed by returning data before execution of the set command.

  The fifth is a clear command. This is also used to manipulate the data in the work memory 1029 in bit units. The main processor 1021 and each sub-processor 1023 transmit a clear command, an address of a block in the RAM 1039 that stores data to be operated, and mask data.

  On the other hand, the controller 1038 compares the received mask data with the data in the block of the received address, and sets the value of the bit in the data at the same position as the bit whose value is 1 in the mask data to 0. . Completed indicating completion of the clear command is returned as the execution result. At this time, the success / failure of the command may be confirmed by returning the data before executing the clear command.

  As described above, the main processor 1021 and each sub-processor 1023 can use the work memory 1029 in addition to the large-capacity main memory 1026 and the high-speed sub-memory 1027. Further, if the work memory 1029 is used as a cache for the main memory 1026 or the sub memory 1027, further increase in speed can be expected.

(3-6. Processing thread in each sub-processor)
As described above, each sub-processor 1023 in one information processing controller is structurally independent. Therefore, each sub processor 1023 can independently execute a sub processor program and process data. Furthermore, each sub processor 1023 may have a plurality of virtually independent processing threads inside. The structure is shown in FIG.

  The sub processor 1023 is connected to the bus 1032 via an arbiter 1040 included therein. The sub-processor 1023 also includes an LS (local storage) 1024 and processing threads 1041, 1042, 1043, and 1044. The arbiter 1040 is responsible for notifying an appropriate processing thread of an external signal. Take on.

  In FIG. 22, the processing threads 1041, 1042, 1043 and 1044 are shown independently, but are virtually independent. Each of the processing threads 1041, 1042, 1043, and 1044 is assigned a processing thread identifier, and can operate independently and in parallel.

  Since each of the processing threads 1041, 1042, 1043 and 1044 independently accesses the main memory 1026, the sub memory 1027 or the work memory 1029, a response is surely returned to the processing thread of the command transmission source. It is necessary to make it. The procedure for this is shown below.

  The commands used when the processing threads 1041, 1042, 1043 and 1044 access the respective memories are the same as those used when the sub processors 1023 access the memories as shown in FIG. 19, for example. The response of the execution result from each memory after the process execution has the same structure.

  Although the command / response structure of FIG. 19 has been described above, the sub processor identifier is the sub processor ID of the sub processor of the command transmission source, and the processing thread identifier is any processing thread in the sub processor. This is for identifying whether the command is transmitted.

  A response from the main memory 1026, the sub memory 1027, or the work memory 1029 is first returned to the sub processor 1023 that is the command transmission source based on the sub processor identifier. Further, based on the processing thread identifier, the arbiter 1040 in the sub processor 1023 returns the command to the processing thread of the command transmission source.

  However, when any of the multiple processing threads in the sub-processor is used, such as when performing the same processing, the response is returned to the processing thread with a light processing load without using the processing thread identifier. You may make it do. Each time a response is received from the main memory 1026, the sub memory 1027, or the work memory 1029, one of a plurality of processing threads is selected in order, and the response is returned to the selected processing thread. You may make it do.

  As described above, even when a plurality of processing threads in each sub-processor 1023 access the main memory 1026, the sub memory 1027, or the work memory 1029 independently, the processing threads of the command transmission source A response can be surely returned.

(3-7. Management of sub processor program by control register)
When a plurality of sub-processors 1023 exist in one information processing controller and each of the sub-processors 1023 has a plurality of processing threads, which pre-processor program is to be processed in the information processing controller. Determining whether the processing thread is to perform processing is important in order to increase the speed of the information processing controller.

  Accordingly, a configuration and a procedure for efficiently allocating the processing of the sub processor program to each processing thread and operating the information processing controller efficiently by using the control register 1028 shown in FIG. .

  As shown in FIG. 23, the control register 1028 includes a processing waiting subprocessor program register 1045 and a subprocessor program processing progress register 1046.

  The processing waiting subprocessor program register 1045 will be described. When a subprocessor program to be processed in the information processing controller is generated, the main processor 1021 stores the subprocessor program or the processing waiting subprocessor program register 1045 in the processing waiting subprocessor program register 1045. The address in the main memory 1026, the sub memory 1027, the work memory 1029, or the LS (local storage) 1022 or 1024 in which related data is stored is written.

  In a state where there is no sub processor program to be processed, the value of the processing waiting sub processor program register 1045 is zero. All processing threads read the value of the waiting subprocessor program register 1045 periodically or non-periodically while they are not executing any subprocessor program, and as a result, read a non-zero value. It is assumed that the processing thread performs processing.

  At the same time, the processing thread writes a value of zero in the processing waiting subprocessor program register 1045. The processing thread that performs the processing reads and processes the sub-processor program or the related data to be processed based on the read value of the processing-waiting sub-processor program register 1045. At this time, the sub processor program has already been read out by the sub processor 1023 having the processing thread, and it may be unnecessary to read out the sub processor program.

  In this way, the processing of the sub processor program can be quickly assigned to a processing thread that does not execute the sub processor program and has sufficient processing capability, and the information processing controller can be operated efficiently. .

  The sub processor program processing progress register 1046 is a 2-bit (x, y) register for a processing thread assigned with processing of the sub processor program to write the processing progress status. For example, (0,0) indicates unprocessed, (0,1) indicates stage 1 being processed, (1,0) indicates stage 2 being processed, and (1,1) indicates completion of processing. Show. Further, a processing thread identifier may be written together with these 2 bits to indicate a processing thread to which processing is assigned.

  Alternatively, as shown as processing threads 0, 1, 2, and 3 in FIG. 23, a register for writing the processing progress status of the sub processor program may be provided for each processing thread in the information processing controller.

  The sub processor program processing progress register 1046 can be accessed by the main processor 1021, all sub processors 1023, and all processing threads in the information processing controller, thereby accurately grasping the processing progress of the sub processor program. can do. Further, when a processing progress register is provided for each processing thread, it is possible to grasp the processing progress status even when a plurality of sub-processor programs are executed simultaneously.

  The above is an example of a processing thread management method in the case where each sub processor 1023 has a plurality of virtually independent processing threads inside.

  In the following, when a sub processor performs some processing, any processing thread in the sub processor may perform processing, and the difference in execution results due to the difference in processing threads. Shall not occur. Therefore, the description of how the plurality of processing threads in the sub processor share the processing with respect to the processing contents of the sub processor will be omitted.

(3-8. Generation and configuration of software cell)
In the network system of FIG. 16, software cells are transmitted between the information processing apparatuses 1001, 1002, 1003, and 1004 for distributed processing between the information processing apparatuses 1001, 1002, 1003, and 1004. That is, the main processor 1021 included in the information processing controller in a certain information processing apparatus generates a software cell including a command, a program, and data, and transmits the software cell to another information processing apparatus via the network 1009 to perform processing. Can be dispersed.

  FIG. 3 shows an example of the configuration of the software cell. The software cell in this example is composed of a transmission source ID, a transmission destination ID, a response destination ID, a cell interface, a DMA command, a program, and data as a whole.

  The transmission source ID includes the network address and information processing device ID of the information processing device that is the transmission source of the software cell, and the identifiers of the main processor 1021 and each sub-processor 1023 included in the information processing controller in the information processing device (main Processor ID and sub-processor ID).

  The transmission destination ID and the response destination ID include the same information about the information processing device that is the transmission destination of the software cell and the information processing device that is the response destination of the execution result of the software cell, respectively.

  The cell interface is information necessary for using the software cell, and includes a global ID, necessary sub-processor information, a sandbox size, and a previous software cell ID.

  The global ID can uniquely identify the software cell throughout the network, and is created based on the transmission source ID and the date and time (date and time) of creation or transmission of the software cell.

  In the necessary sub-processor information, the number of sub-processors necessary for executing the software cell is set. As the sandbox size, the amount of memory in the main memory 1026 and the LS 1024 of the sub processor 1023 necessary for executing the software cell is set.

  The previous software cell ID is an identifier of the previous software cell in a group of software cells that request sequential execution of streaming data or the like.

  The execution section of the software cell is composed of DMA commands, programs and data. The DMA command includes a series of DMA commands necessary for starting the program, and the program includes a sub processor program executed by the sub processor 1023. The data here is data processed by a program including the sub processor program.

  Further, the DMA command includes a load command, a kick command, a function program execution command, a status request command, and a status return command.

  The load command is a command for loading information in the main memory 1026 to the LS 1024 in the sub processor 1023, and includes a main memory address, a sub processor ID, and an LS address in addition to the load command itself. The main memory address indicates an address of a predetermined area in the main memory 1026 from which information is loaded. The sub processor ID and the LS address indicate the identifier of the sub processor 1023 to which the information is loaded and the address of the LS 1024.

  The kick command is a command for starting execution of the sub processor program, and includes a sub processor ID and a program counter in addition to the kick command itself. The sub processor ID identifies the sub processor 1023 to be kicked, and the program counter gives an address for the program counter for executing the sub processor program.

  As will be described later, the function program execution command is a command for requesting execution of a function program from another information processing apparatus to another information processing apparatus. The information processing controller in the information processing apparatus that has received the function program execution command identifies a function program to be activated by a function program ID described later.

  The status request command is a command for requesting transmission of device information related to the current operation state (situation) of the information processing device indicated by the transmission destination ID to the information processing device indicated by the response destination ID. Although the function program will be described later, it is a program categorized into the function program in the software configuration diagram stored in the main memory 1026 of the information processing apparatus shown in FIG. The function program is loaded into the main memory 1026 and executed by the main processor 1021.

  The status reply command is a command in which the information processing apparatus that has received the status request command responds to the information processing apparatus indicated by the response destination ID included in the status request command with its own apparatus information. The status reply command stores device information in the data area of the execution section.

  FIG. 4 shows the structure of the data area of the software cell when the DMA command is a status return command.

  The information processing device ID is an identifier for identifying the information processing device including the information processing controller, and indicates the ID of the information processing device that transmits the status reply command. The information processing apparatus ID is included in the information processing controller in the information processing apparatus by the main processor 1021 included in the information processing controller in the information processing apparatus when the power is turned on. The number of sub processors 1023 to be generated is generated.

  The information processing device type ID includes a value representing the characteristics of the information processing device. The characteristics of the information processing apparatus include, for example, a hard disk recorder, a PDA (Personal Digital Assistant), a portable CD (Compact Disc) player, and the like, which will be described later. The information processing device type ID may represent a function of the information processing device such as video / audio recording or video / audio reproduction. It is assumed that values representing the characteristics and functions of the information processing apparatus are determined in advance, and it is possible to grasp the characteristics and functions of the information processing apparatus by reading the information processing apparatus type ID.

  The MS (master / slave) status indicates whether the information processing apparatus is operating as a master apparatus or a slave apparatus, as will be described later. When this is set to 0, it operates as a master apparatus. If it is set to 1, it indicates that it is operating as a slave device.

  The main processor operating frequency represents the operating frequency of the main processor 1021 in the information processing controller. The main processor usage rate represents the usage rate in the main processor 1021 for all programs currently running on the main processor 1021. The main processor usage rate is a value representing the ratio of the processing capacity in use to the total processing capacity of the target main processor. For example, the main processor usage rate is calculated by using MIPS, which is a unit for evaluating the processor processing capacity, or per unit time. Calculated based on processor usage time. The same applies to the sub-processor usage rate described later.

  The number of sub processors represents the number of sub processors 1023 provided in the information processing controller. The sub processor ID is an identifier for identifying each sub processor 1023 in the information processing controller.

  The sub processor status represents the state of each sub processor 1023, and there are states such as “unused”, “reserved” and “busy”. “unused” indicates that the sub-processor is not currently used and is not reserved for use. “reserved” indicates a reserved state that is not currently used. Busy indicates that it is currently in use.

  The sub-processor usage rate represents the usage rate of the sub-processor for a sub-processor program that is currently being executed by the sub-processor or that is reserved for execution by the sub-processor. That is, the sub processor usage rate indicates the current usage rate when the sub processor status is busy, and indicates the estimated usage rate that is to be used later when the sub processor status is reserved.

  One set of sub-processor ID, sub-processor status, and sub-processor usage rate is set for one sub-processor 1023, and is set for the number of sub-processors 1023 in one information processing controller.

  The main memory total capacity and the main memory usage amount represent the total capacity and the currently used capacity of the main memory 1026 connected to the information processing controller, respectively.

  The number of external recording units represents the number of external recording units 1031 connected to the information processing controller. The external recording unit ID is information for uniquely identifying the external recording unit 1031 connected to the information processing controller. The external recording unit type ID represents the type of the external recording unit (for example, hard disk, CD ± RW, DVD ± RW, memory disk, SRAM, ROM, etc.).

  The external recording unit total capacity and the external recording unit usage amount represent the total capacity and the currently used capacity of the external recording unit 1031 identified by the external recording unit ID, respectively.

  An external recording unit ID, an external recording unit type ID, an external recording unit total capacity, and an external recording unit usage amount are set for one external recording unit 1031 and connected to the information processing controller. The number of sets corresponding to the number of sections 1031 is set. That is, when a plurality of external recording units are connected to one information processing controller, a different external recording unit ID is assigned to each external recording unit, the external recording unit type ID, the external recording unit total capacity, and the external recording unit Department usage is also managed separately.

(3-9. Execution of software cell)
The main processor 1021 included in the information processing controller in a certain information processing device generates a software cell having the above-described configuration and transmits it to another information processing device and the information processing controller in the device via the network 1009. . The transmission source information processing device, the transmission destination information processing device, the response destination information processing device, and the information processing controller in each device are identified by the transmission source ID, the transmission destination ID, and the response destination ID, respectively. .

  The main processor 1021 included in the information processing controller in the information processing apparatus that has received the software cell stores the software cell in the main memory 1026. Further, the transmission destination main processor 1021 reads the software cell and processes the DMA command included therein.

  Specifically, the main processor 1021 of the transmission destination first executes a load command. As a result, information is loaded from the main memory address designated by the load command to a predetermined area of the LS 1024 in the sub processor specified by the sub processor ID and the LS address included in the load command. The information loaded here is a sub-processor program or data included in the received software cell, or other designated data.

  Next, the main processor 1021 transmits the kick command to the sub processor indicated by the sub processor ID included therein, together with the program counter included in the kick command.

  The instructed sub processor executes the sub processor program according to the kick command and the program counter. Then, after the execution result is stored in the main memory 1026, the main processor 1021 is notified that the execution has been completed.

  Note that the processor that executes the software cell in the information processing controller in the information processing apparatus of the transmission destination is not limited to the sub-processor 1023, and the main processor 1021 stores a program for main memory such as a function program included in the software cell. It can also be specified to execute.

  In this case, the transmission source information processing apparatus includes a main memory program and data processed by the main memory program instead of the sub processor program, and the DMA command is sent to the transmission destination information processing apparatus. A software cell as a load command is transmitted, and the main memory 1026 stores the main memory program and data processed thereby.

  Next, the transmission source information processing apparatus identifies the main processor ID, the main memory address, and the main memory program for the information processing controller in the transmission destination information processing apparatus for the transmission destination information processing apparatus. A software cell that includes an identifier such as a function program ID (to be described later) and a program counter and whose DMA command is a kick command or a function program execution command is transmitted to cause the main processor 1021 to execute the main memory program.

  As described above, in the network system of the present invention, the transmission source information processing apparatus transmits the sub processor program or the main memory program to the transmission destination information processing apparatus by the software cell, and transmits the sub processor program to the transmission destination. It is possible to load the sub-processor 1023 included in the information processing controller in the information processing apparatus and cause the information processing apparatus as the transmission destination to execute the sub-processor program or the main memory program.

  When the program included in the received software cell is a sub processor program, the information processing controller in the transmission destination information processing apparatus loads the sub processor program to the designated sub processor. Then, the sub processor program or the main memory program included in the software cell is executed.

  Therefore, even if the user does not operate the transmission destination information processing apparatus, the sub processor program or the main memory program can be automatically executed by the information processing controller in the transmission destination information processing apparatus.

  In this way, when the information processing controller in its own device does not have a main memory program such as a sub processor program or a function program, the information processing device can receive information from other information processing devices connected to the network. Can be obtained. Furthermore, data transfer is performed between each sub-processor and the main memory by the DMA method, and even when data needs to be processed in multiple stages in one information processing controller by using the above-described sandbox. High-speed and high-security processing can be executed.

[4. Distributed processing as a network system 2]
As a result of distributed processing using software cells, a plurality of information processing apparatuses 1001, 1002, 1003, and 1004 connected to the network 1009 as shown in the upper part of FIG. It operates as a single information processing apparatus 1007. However, for this purpose, the following processing needs to be executed by the following configuration.

(4-1. System software configuration and program loading)
FIG. 6 shows the configuration of software stored in the main memory 1026 of each information processing controller. These software (programs) are recorded in the external recording unit 1031 connected to the information processing controller before the information processing apparatus is turned on.

  Each program is categorized into a control program, a function program, and a device driver by function or feature.

  The control program is the same for each information processing controller, and is executed by the main processor 1021 of each information processing controller, and includes an MS (master / slave) manager and a capability exchange program described later.

  The function program is executed by the main processor 1021, and is provided for each information processing controller, such as for recording, for reproduction, and for material search, according to the information processing apparatus.

  Device drivers are used for input / output (transmission / reception) of an information processing controller (information processing device), such as broadcast reception, monitor output, bit stream input / output, network input / output, etc. Provided.

  When the information processing apparatus is physically connected to the network 1009 by plugging in a cable or the like, the main power supply is turned on and the information processing apparatus is electrically and functionally connected to the network 1009. The main processor 1021 of the information processing controller of the information processing apparatus loads each program belonging to the control program and each program belonging to the device driver into the main memory 1026.

  As a loading procedure, the main processor 1021 first reads a program from the external recording unit 1031 by causing the DC 1030 to execute a read command, and then causes the DMAC 1025 to execute a write command to load the program into the main memory 1026. Write to.

  As for each program belonging to the function program, it may be configured to load only the necessary program when necessary, or like the programs belonging to other categories, each program is loaded immediately after the main power is turned on. You may comprise as follows.

  Each program belonging to the function program does not need to be recorded in the external recording unit 1031 of all information processing apparatuses connected to the network, and may be recorded in the external recording unit 1031 of any one information processing apparatus. Since it can be loaded from another information processing apparatus by the above-described method, as a result, as shown in the lower part of FIG. 24, the function program can be executed as one virtual information processing apparatus 1007.

  Further, as described above, the function program processed by the main processor 1021 may operate in cooperation with the sub processor program processed by the sub processor 1023. Therefore, when the main processor 1021 reads out the function program from the external recording unit 1031 and writes it into the main memory 1026, if there is a sub processor program that operates in cooperation with the target function program, the sub processor program is also the same. Write to main memory 1026. In this case, there may be one sub-processor program that operates in cooperation, but there may be a plurality of sub-processor programs. If there are a plurality of sub-processor programs, all sub-processor programs operating in cooperation are written in the main memory 1026.

  The sub processor program written in the main memory 1026 is then written in the LS 1024 in the sub processor 1023 and operates in cooperation with the function program processed by the main processor 1021.

  As shown in the software cell of FIG. 3, an identifier that can uniquely identify the program for each program is assigned to the function program as the function program ID. The function program ID is determined from the creation date and time, the information processing apparatus ID, and the like at the stage of creating the function program.

  A sub processor program ID is also assigned to the sub processor program, whereby the sub processor program can be uniquely identified. The assigned sub processor program ID may be an identifier related to the function program ID of the function program that is the partner of the cooperative operation, for example, an identifier with the function program ID as a parent number and a branch number added at the end. However, an identifier that is not related to the function program ID of the function program that is the partner of the cooperative operation may be used.

  In any case, when the function program and the sub processor program operate in cooperation, it is necessary to store the program ID, which is the other party's identifier, in the own program. Even when the function program operates in cooperation with a plurality of sub-processor programs, the function program stores all the sub-processor program IDs of the plurality of sub-processor programs.

  The main processor 1021 secures an area in the main memory 1026 for storing device information (information relating to the operation state) of the information processing device on which the main processor 1021 operates, and records the information as a device information table of the own device. The device information here is each piece of information below the information processing device ID shown in FIG.

(4-2. Determination of master / slave in the system)
In the network system described above, when the main power supply to a certain information processing apparatus is turned on, the main processor 1021 of the information processing controller of the information processing apparatus loads a master / slave manager (hereinafter referred to as MS manager) into the main memory 1026 and executes it. To do.

  When the MS manager detects that the information processing apparatus on which it operates is connected to the network 1009, the MS manager confirms the existence of another information processing apparatus connected to the same network 1009. Here, “connection” or “existence” means that the information processing apparatus is not only physically connected to the network 1009 but also electrically and functionally connected to the network 1009 as described above. Indicates.

  Hereinafter, an information processing apparatus in which the device operates is referred to as an own device, and another information processing device is referred to as an other device. The apparatus also indicates the information processing apparatus.

  A method in which the MS manager confirms the existence of another information processing apparatus connected to the same network 1009 will be described below.

  The MS manager generates a software cell in which the DMA command is a status request command, the transmission source ID and the response destination ID are the information processing apparatus, and the transmission destination ID is not specified, and the network manager is connected to the information processing apparatus. Set the timer for checking the network connection. The timeout time of the timer is, for example, 10 minutes.

  When another information processing apparatus is connected to the network system, the other apparatus receives the software cell of the status request command, and sends it to the information processing apparatus that has issued the status request command specified by the response destination ID. On the other hand, the DMA command is a status return command, and a software cell including device information of itself (other device) is transmitted as data. The software cell of this status reply command includes at least information for identifying the other device (information processing device ID, information on the main processor, information on the sub processor, etc.) and the MS status of the other device.

  The MS manager of the information processing apparatus that has issued the status request command monitors the reception of the software cell of the status reply command transmitted from another apparatus on the network until the timer for network connection confirmation times out. As a result, when the status reply command indicating the MS status = 0 (master device) is received, the MS status in the device information table of the own device is set to 1. As a result, the device becomes a slave device.

  On the other hand, if no status reply command is received before the network connection confirmation timer times out, or if no status reply command indicating MS status = 0 (master device) is received, The MS status in the device information table of the own device is set to 0. This makes the device a master device.

  That is, when no information processing apparatus is connected to the network 1009 or a new information processing apparatus is connected to the network 1009 in a state where no master apparatus exists on the network 1009, the apparatus automatically becomes the master apparatus. Set as On the other hand, when a new information processing apparatus is connected to the network 1009 in a state where a master apparatus already exists on the network 1009, the apparatus is automatically set as a slave apparatus.

  For both the master device and the slave device, the MS manager periodically monitors the status of the other device by sending a status request command to the other device on the network 1009 and inquiring status information. As a result, the main power supply of the information processing apparatus connected to the network 1009 is cut off or the information processing apparatus is disconnected from the network 1009, so that the status from a specific other apparatus is determined within a predetermined period set in advance for determination. When there is a change in the connection state of the network 1009, such as when a reply command is not returned or when a new information processing apparatus is connected to the network 1009, the information is notified to a capability exchange program described later. .

(4-3. Acquisition of device information in master device and slave device)
When the main processor 1021 receives from the MS manager the inquiry of other devices on the network 1009 and the notification of completion of setting of the MS status of the own device, the main processor 1021 executes the capability exchange program.

  When the own device is a master device, the capability exchange program acquires device information of all other devices connected to the network 1009, that is, device information of each slave device.

  As described above, the device information of another device is generated by generating a software cell in which the DMA command is a status request command and transmitting it to the other device. Thereafter, the DMA command is a status return command and data of the other device. This is possible by receiving a software cell containing device information from another device.

  Similar to the device information table of the own device that is the master device, the capability exchange program sets an area for storing device information of all other devices (each slave device) connected to the network 1009 as the main memory of the own device. These information is recorded as a device information table of another device (slave device).

  That is, device information of all information processing devices connected to the network 1009 including the device itself is recorded in the main memory 1026 of the master device as a device information table.

  On the other hand, when the own device is a slave device, the capability exchange program acquires device information of all other devices connected to the network 1009, that is, device information of each slave device other than the master device and the own device. The information processing apparatus ID and the MS status included in the apparatus information are recorded in the main memory 1026 of the own apparatus.

  That is, the device information of the own device is recorded in the main memory 1026 of the slave device as a device information table, and the master device connected to the network 1009 other than the own device and the information processing device ID for each slave device. And the MS status are recorded as another device information table.

  Further, in both the master device and the slave device, when the capability exchange program is notified from the MS manager that the information processing device is newly connected to the network 1009 as described above, the device of the information processing device Information is acquired and recorded in the main memory 1026 as described above.

  Note that the MS manager and the capability exchange program are not limited to being executed by the main processor 1021, but may be executed by any of the sub processors 1023. The MS manager and the capability exchange program are preferably resident programs that always operate while the main power supply of the information processing apparatus is turned on.

(4-4. When the information processing apparatus is disconnected from the network)
For both the master device and the slave device, the capability exchange program causes the MS manager to cut off the main power supply of the information processing device connected to the network 1009 or disconnect the information processing device from the network 1009 as described above. When it is notified, the device information table of the information processing device is deleted from the main memory 1026 of the own device.

  Furthermore, when the information processing apparatus disconnected from the network 1009 is a master apparatus, a new master apparatus is determined by the following method.

  Specifically, for example, each of the information processing apparatuses that are not disconnected from the network 1009 replaces the information processing apparatus ID of the own apparatus and the other apparatus with a numerical value, and sets the information processing apparatus ID of the own apparatus to the information processing apparatus of the other apparatus. If the information processing device ID of the own device is the smallest among the information processing devices that are not disconnected from the network 1009, the slave device moves to the master device and sets the MS status to 0, As described above, device information of all other devices (each slave device) connected to the network 1009 is acquired as a master device and recorded in the main memory 1026.

(4-5. Distributed processing based on device information)
As shown in the lower part of FIG. 24, in order for a plurality of information processing apparatuses 1001, 1002, 1003, and 1004 connected to the network 1009 to operate as one virtual information processing apparatus 1007, the master apparatus is a user. It is necessary to understand the operation of the slave device and the operating state of the slave device.

  FIG. 25 illustrates how four information processing apparatuses operate as one virtual information processing apparatus 1007. It is assumed that the information processing apparatus 1001 is operating as a master apparatus, and the information processing apparatuses 1002, 1003, and 1004 are operating as slave apparatuses A, B, and C.

  When the user operates an information processing apparatus connected to the network 1009, if the operation target is the master apparatus 1001, the operation information is directly grasped in the master apparatus 1001, and if the operation target is a slave apparatus, The operation information is transmitted from the operated slave device to the master device 1001. That is, regardless of whether the user's operation target is the master device 1001 or the slave device, the operation information is always grasped by the master device 1001. The operation information is transmitted, for example, by a software cell whose DMA command is an operation information transmission command.

  Then, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 selects a function program to be executed according to the operation information. At this time, if necessary, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 can transmit the main memory 1026-1 from the external recording unit 1031-1 or 1031-2 of the own device by the above method. However, another information processing apparatus (slave apparatus) may transmit the function program to the master apparatus 1001.

  In the function program, information processing device type IDs represented as information shown in FIG. 4, main processor or sub-processor processing capacity, main memory usage, and conditions related to the external recording unit are required for each execution unit. The required specifications regarding the device are defined.

  The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 reads out the required specifications necessary for each function program. Further, the device information table of each information processing device is read by referring to the device information table previously recorded in the main memory 1026-1 by the capability exchange program. The device information here indicates each piece of information below the information processing device ID shown in FIG. 4, and is information relating to the main processor, sub processor, main memory, and external recording unit.

  The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 sequentially compares the device information of each information processing device connected on the network 1009 with the required specifications necessary for executing the function program. To do.

  For example, when the function program requires a recording function, only the information processing apparatus having the recording function is specified and extracted based on the information processing apparatus type ID. Furthermore, a slave device that can secure the conditions regarding the processing capability of the main processor or sub processor, the amount of main memory used, and the external recording unit necessary for executing the function program is specified as an execution request candidate device. Here, when a plurality of execution request candidate devices are specified, one execution request candidate device is specified and selected from the candidate devices.

  When the slave device to be requested for execution is specified, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 determines the main memory included in the information processing controller 1011 in the own device for the specified slave device. The device information table of the slave device recorded in 1026-1 is updated.

  Furthermore, the main processor 1021-1 included in the information processing controller 1011 in the master device 1001 generates a software cell whose DMA command is a function program execution command, and the cell interface of the software cell requires a function related to the function program. The sub-processor information and the sandbox size (see FIG. 3) are set and transmitted to the slave device requested to execute.

  The slave device requested to execute the function program executes the function program and updates the device information table of the own device. At this time, if necessary, the main processor 1021 included in the information processing controller in the slave device causes the function program and the sub-program that operates in cooperation with the function program from the external recording unit 1031 of the own device to the main memory 1026 by the above method. Load the processor program.

  When the required function program or the sub processor program that operates in cooperation with the function program is not recorded in the external recording unit 1031 of the slave device requested to execute the function program, the other information processing apparatus Alternatively, the system may be configured so that the sub processor program is transmitted to the function program execution request destination slave device.

  The sub-processor program can be executed by another information processing apparatus using the aforementioned load command and kick command.

  After the execution of the function program, the main processor 1021 included in the information processing controller in the slave device that has executed the function program transmits an end notification to the main processor 1021-1 included in the information processing controller 1011 in the master device 1001. At the same time, the device information table of the own device is updated. The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 receives the end notification and updates the device information table of the slave device that has executed the function program.

  The main processor 1021-1 included in the information processing controller 1011 in the master device 1001 identifies itself as an information processing device that can execute the function program from the reference result of the device information table of the own device and the other device. There is also a case of selecting. In that case, the master device 1001 executes the function program.

  In the example of FIG. 25, the case where the user operates slave device A (information processing device 1002) and another slave device B (information processing device 1003) executes a function program corresponding to the operation will be described with reference to FIG. An example of distributed processing is shown.

  In the example of FIG. 26, when the user operates the slave device A, distributed processing of the entire network system including the slave device A starts. First, in step 1091, the slave device A transmits the operation information to the master device. 1001 is transmitted.

  The master device 1001 receives the operation information in step 1092, further proceeds to step 1093, and processes each information processing from the device information table of the own device and other devices recorded in the main memory 1026-1 of the own device. The operating state of the apparatus is checked, and an information processing apparatus that can execute a function program corresponding to the received operation information is selected. This example is a case where the slave device B is selected.

  Next, in step 1094, the master device 1001 requests the selected slave device B to execute the function program.

  The slave device B receives the execution request in step 1095, and further proceeds to step 1096 to execute the function program requested to be executed.

  As described above, by operating only one information processing apparatus, the user operates a plurality of information processing apparatuses 1001, 1002, 1003, and 1004 as a virtual one without operating other information processing apparatuses. The information processing apparatus 1007 can be operated.

(4-6. Specific examples of information processing apparatuses and systems)
Any of the information processing apparatuses 1001, 1002, 1003, and 1004 connected to each other via the network 1009 basically performs information processing by the information processing controllers 1011, 1012, 1013, and 1014 as described above. An example is shown in FIG. 27.

  In this example, the information processing apparatus 1001 including the information processing controller 1011 is a hard disk recorder, and as shown in FIG. 28, the hardware configuration is a built-in hard disk as the external recording unit 1031-1 shown in FIG. The external recording unit 1031-2 shown in FIG. 16 is configured so that an optical disk such as a DVD ± R / RW, a CD ± R / RW, or a Blu-ray Disc (registered trademark) can be mounted, and an information processing controller 1011. The bus 1051-1 connected to the bus 1032-1 is connected to the broadcast receiving unit 1052-1, the video input unit 1053-1, the audio input unit 1054-1, the video output unit 1055-1, the audio output unit 1056-1, Operation panel unit 1057-1, remote control light receiving unit 1058-1, and network connection unit 1059-1 are connected. It was continued.

  The broadcast receiving unit 1052-1, the video input unit 1053-1, and the audio input unit 1054-1 receive a broadcast signal or input a video signal and an audio signal from the outside of the information processing apparatus 1001, and each has a digital format of a predetermined format. This data is converted into data and sent to the bus 1051-1 for processing by the information processing controller 1011. The video output unit 1055-1 and the audio output unit 1056-1 are sent from the information processing controller 1011 to the bus 1051-. The video data and the audio data sent to 1 are processed, converted into digital data or converted into analog signals, and sent to the outside of the information processing apparatus 1001. A remote control (remote operation) infrared signal is received from the transmitter 1063-1.

  As shown in FIGS. 27 and 28, a monitor display device 1061 and a speaker device 1062 are connected to the video output unit 1055-1 and the audio output unit 1056-1 of the information processing device (hard disk recorder) 1001.

  The information processing apparatus 1002 including the information processing controller 1012 in the example of FIG. 27 is also a hard disk recorder, and is configured in the same manner as the information processing apparatus 1001 as indicated by reference numerals in parentheses in FIG. is there. However, for example, as shown in FIG. 27, a monitor display device and a speaker device are not connected to the information processing device (hard disk recorder) 1002.

  As shown in FIG. 29, the software configuration of the information processing apparatuses (hard disk recorders) 1001 and 1002, that is, the information processing controllers 1011 and 1012 includes an MS manager and a capability exchange program as control programs, and video and audio as function programs. Programs for recording, video / audio playback, material search and program recording reservation are provided, and programs for broadcast reception, video output, audio output, external recording unit input / output and network input / output are provided as device drivers.

  The information processing apparatus 1003 including the information processing controller 1013 in the example of FIG. 27 is a PDA (Personal Digital Assistant). As illustrated in FIG. 30, the hardware configuration is the external recording unit 1031-5 illustrated in FIG. And a memory card disk, and a bus 1071 connected to the bus 1032-3 of the information processing controller 1013 is connected to a liquid crystal display unit 1072, an audio output unit 1073, a camera unit 1074, and an audio input unit 1075. The keyboard unit 1076 and the network connection unit 1077 are connected.

  Note that the information processing controller 1013 whose interior is omitted in FIG. 16 includes a main processor 1021-3, sub processors 1023-7, 1023-8 and 1023-9, a DMAC (direct memory access controller) 1025-3, and a control register 1028-. 3, a work memory 1029-3, a DC (disk controller) 1030-3, and a bus 1032-3, the main processor 1021-3 has an LS (local storage) 1022-3, and each sub processor 1023- 7, 1023-8 and 1023-9 have LS (local storage) 1024-7, 1024-8 and 1024-9.

  As shown in FIG. 31, the software configuration of the information processing apparatus (PDA) 1003, that is, the information processing controller 1013 includes an MS manager and a capability exchange program as control programs, and video / audio recording and video / audio reproduction as function programs. , A phone book, a word processor and a spreadsheet program, and a Web browser, and device drivers include video output, audio output, camera video input, microphone audio input, and network input / output programs.

  The information processing apparatus 1004 including the information processing controller 1014 in the example of FIG. 27 is a portable CD player. As shown in FIG. 32, the hardware configuration is a CD as the external recording unit 1031-6 shown in FIG. (Compact Disc) and a bus 1081 connected to the bus 1032-4 of the information processing controller 1014 are connected to a liquid crystal display unit 1082, an audio output unit 1083, an operation button unit 1084, and a network connection unit 1085. Are connected.

  Note that the information processing controller 1014 omitted in FIG. 16 includes a main processor 1021-4, sub processors 1023-10, 1023-11 and 1023-12, a DMAC (direct memory access controller) 1025-4, and a control register 1028-. 4, a work memory 1029-4, a DC (disk controller) 1030-4, and a bus 1032-4, the main processor 1021-4 has an LS (local storage) 1022-4, and each sub processor 1023- 10, 1023-11 and 1023-12 have LS (local storage) 1024-10, 1024-11 and 1024-12.

  As shown in FIG. 33, the software configuration of the information processing apparatus (portable CD player) 1004, that is, the information processing controller 1014 includes an MS manager and a capability exchange program as a control program, and a function program for playing music. A program for audio output, CD control, and network input / output is provided as a device driver.

  In the network system of the example of FIG. 27 as described above, the information processing apparatuses 1001, 1003, and 1004 are connected to the network 1009, and the information processing apparatus 1001 is the master apparatus (MS status = 0). And 1004 are set as slave devices (MS status = 1).

  In this state, when the information processing apparatus 1002 is newly connected to the network 1009, the MS manager that is executed by the main processor 1021-2 included in the information processing controller 1012 in the information processing apparatus 1002 is The other information processing apparatuses 1001, 1003, and 1004 are inquired about the MS status, recognizes that the information processing apparatus 1001 already exists as a master apparatus, and sets its own apparatus (information processing apparatus 1002) as a slave apparatus (MS status = Set to 1). Also, the information processing apparatus 1001 set as the master apparatus collects apparatus information of each apparatus including the newly added information processing apparatus 1002 and updates the apparatus information table in the main memory 1026-1.

  In this state, a case where a user performs an operation for recording reservation of a broadcast program for 2 hours in an information processing apparatus (PDA) 1003 which is a slave apparatus is shown.

  In this case, the information processing apparatus (PDA) 1003 that is a slave apparatus receives input of recording reservation information including information such as a recording start time, a recording end time, a recording target broadcast channel, and recording quality from the user, and the recording reservation information A software cell including a recording reservation command as a DMA command is generated and transmitted to the information processing apparatus 1001 that is a master apparatus.

  The main processor 1021-1 included in the information processing controller 1011 in the information processing apparatus 1001 that has received the software cell whose DMA command is the recording reservation command reads out the recording reservation command and also stores the apparatus information table in the main memory 1026-1. The information processing apparatus that can execute the recording reservation command is specified.

  First, the main processor 1021-1 reads information processing device type IDs of the information processing devices 1001, 1002, 1003, and 1004 included in the device information table, and performs information processing that can execute a function program corresponding to the recording reservation command. Extract the device. Here, the information processing apparatuses 1001 and 1002 having the information processing apparatus type ID indicating the recording function are specified as candidate apparatuses, and the information processing apparatuses 1003 and 1004 are excluded from the candidate apparatuses.

  Next, the main processor 1021-1 included in the information processing controller 1011 in the information processing apparatus 1001 that is the master apparatus refers to the apparatus information table, and the processing capability of the main processor or sub-processor of the information processing apparatuses 1001 and 1002 Then, information related to the device such as information related to the main memory is read, and it is determined whether or not the information processing devices 1001 and 1002 satisfy the required specifications necessary for executing the function program corresponding to the recording reservation command. Here, it is assumed that both the information processing apparatuses 1001 and 1002 satisfy the required specifications necessary for executing the function program corresponding to the recording reservation command.

  Further, the main processor 1021-1 refers to the device information table, reads out information related to the external recording units of the information processing devices 1001 and 1002, and determines that the free capacity of the external recording unit is necessary for executing the recording reservation command. Determine if you are satisfied. Since the information processing apparatuses 1001 and 1002 are hard disk recorders, the difference between the total capacity and the usage amount of the hard disks 1031-1 and 1031-3 corresponds to the respective free capacity.

  In this case, the free capacity of the hard disk 1031-1 of the information processing apparatus 1001 is 10 minutes in terms of recording time, and the free capacity of the hard disk 1031-3 in the information processing apparatus 1002 is 20 hours in terms of recording time. Suppose that

  At this time, the main processor 1021-1 included in the information processing controller 1011 in the information processing apparatus 1001 that is the master apparatus sets up an information processing apparatus that can secure a free space for two hours necessary for executing the recording reservation command. Identifies as an execution request destination slave device.

  As a result, only the information processing apparatus 1002 is selected as the execution request destination slave apparatus, and the main processor 1021-1 included in the information processing controller 1011 in the information processing apparatus 1001 that is the master apparatus is the information processing apparatus operated by the user. The recording reservation command including the recording reservation information transmitted from 1003 is transmitted to the information processing apparatus 1002 to request execution of recording reservation of the broadcast program for 2 hours.

  Then, the main processor 1021-2 included in the information processing controller 1012 in the information processing apparatus 1002 analyzes the recording reservation command and sends a function program necessary for recording from the hard disk 1031-3 serving as an external recording unit to the main memory. 1026-2, and recording is performed according to the recording reservation information. As a result, the video / audio data of the 2-hour broadcast program reserved for recording is recorded in the hard disk 1031-3 of the information processing apparatus 1002.

  As described above, also in the network system of the example of FIG. 27, the user operates only one information processing apparatus, and operates a plurality of information processing apparatuses 1001, 1002, without operating other information processing apparatuses. 1003 and 1004 can be operated as one virtual information processing apparatus 1007.

It is a figure which shows an example of the network system of this invention. It is a figure with which it uses for description of the information processing controller with which the information processing apparatus of this invention is provided. It is a figure which shows an example of a software cell. It is a figure which shows the data area of a software cell when a DMA command is a status reply command. It is a figure which shows a mode that a some information processing apparatus operate | moves as one virtual information processing apparatus. It is a figure which shows an example of the software configuration of an information processing controller. It is a figure which shows a mode that four information processing apparatuses operate | move as one virtual information processing apparatus. It is a figure which shows the example of the distributed process in the system of FIG. It is a figure which shows the specific example of each information processing apparatus and a system. It is a figure which shows the hardware constitutions of the hard-disk recorder in FIG. It is a figure which shows the software structure of the hard disk recorder in FIG. It is a figure which shows the hardware constitutions of PDA in FIG. It is a figure which shows the software structure of PDA in FIG. It is a figure which shows the hardware constitutions of the portable CD player in FIG. FIG. 10 is a diagram showing a software configuration of the portable CD player in FIG. 9. It is a figure which shows the other example of the network system of this invention. It is a figure with which it uses for description of the information processing controller with which the information processing apparatus of this invention is provided. It is a figure which shows the internal structure of DMAC. It is a figure which shows the command / response structure in information processing apparatus. It is a figure which shows the procedure at the time of a sub processor accessing main memory. It is a figure which shows the internal structure of a work memory. It is a figure which shows the internal structure of a subprocessor. It is a figure which shows the internal structure of a control register. It is a figure which shows a mode that a some information processing apparatus operate | moves as one virtual information processing apparatus. It is a figure which shows a mode that four information processing apparatuses operate | move as one virtual information processing apparatus. FIG. 26 is a diagram illustrating an example of distributed processing in the system of FIG. 25. It is a figure which shows the specific example of each information processing apparatus and a system. It is a figure which shows the hardware constitutions of the hard-disk recorder in FIG. It is a figure which shows the software structure of the hard disk recorder in FIG. It is a figure which shows the hardware constitutions of PDA in FIG. It is a figure which shows the software structure of PDA in FIG. It is a figure which shows the hardware constitutions of the portable CD player in FIG. It is a figure which shows the software structure of the portable CD player in FIG.

Explanation of symbols

  Since all the main parts are described in the figure, they are omitted here.

Claims (22)

An information processing apparatus connected to another information processing apparatus via a network and performing information processing according to a predetermined command,
Capability exchanging means for collecting information on the operating state from the other information processing apparatus and creating a device information table;
When the command occurs, device identification means for identifying information processing devices capable of executing the command by comparing information regarding resources required to execute the command and information regarding an operation state of the device information table;
An information processing apparatus comprising: The capability exchanging means collects the information processing capability of the other information processing device and stores it in the device information table,
The device specifying means compares an information processing capability required for executing the command with an information processing capability of the other information processing device, and specifies an information processing device that can execute the command. The information processing apparatus according to claim 1. The capability exchanging means collects the memory capacity of the other information processing device and stores it in the device information table,
The apparatus specifying unit specifies an information processing apparatus capable of executing the command by comparing a memory capacity required for executing the command with a memory capacity of the other information processing apparatus. The information processing apparatus according to 1. The capability exchanging means collects the capacity of the external recording means of the other information processing apparatus and stores it in the apparatus information table;
The apparatus specifying means specifies an information processing apparatus capable of executing the command by comparing the capacity of the external recording means required for executing the command and the capacity of the external recording means of the other information processing apparatus. The information processing apparatus according to claim 1. The capability exchanging means collects an information processing device type identifier capable of specifying the function of the other information processing device and stores it in the device information table,
The device specifying unit compares the function required for executing the command with an information processing device type identifier of the other information processing device, and specifies an information processing device that can execute the command. The information processing apparatus according to claim 1.   The information processing apparatus according to claim 1, wherein the capability exchange unit transmits the command to the information processing apparatus specified by the apparatus specifying unit and requests execution thereof.   The capability exchanging means collects information related to an operation state of the other information processing apparatus and updates the apparatus information table when the connection of the other information processing apparatus to the network is changed. The information processing apparatus according to claim 1.   The information processing apparatus according to claim 1, wherein the capability exchanging unit collects information related to an operation state of the other information processing apparatus at a predetermined time interval and updates the apparatus information table.   The other information processing apparatus includes a plurality of processor means for processing the command, and the capability exchanging means collects information on the operation state of each of the plurality of processor means and stores the information in the apparatus information table. The information processing apparatus according to claim 1. The information processing apparatus according to claim 1, further comprising manager means for determining whether another information processing apparatus is connected to the network.
2. The information processing apparatus according to claim 1, wherein when the manager means determines that another information processing apparatus is connected to the network, the processing by the capability exchange means is executed. An information processing method in which an information processing apparatus connected to another information processing apparatus via a network performs information processing according to a predetermined command,
Capability exchanging step of collecting information on the operating state from the other information processing device and creating a device information table;
When the command occurs, a device identification step for identifying an information processing device capable of executing the command by comparing information regarding resources required for execution of the command and information regarding an operation state of the device information table;
An information processing method comprising:   The information processing method according to claim 11, further comprising an execution requesting step of transmitting the command to the information processing device specified in the device specifying step to request execution. .   The other information processing apparatus includes a plurality of processor means for processing the command. In the capability exchanging step, information on an operation state of each of the plurality of processor means is collected and stored in the apparatus information table. The information processing method according to claim 11, wherein: The information processing method further includes a management step of determining whether another information processing apparatus is connected to the network.
12. The information processing method according to claim 11, wherein if it is determined that another information processing apparatus is connected to the network in the management step, the capability exchange step is executed. An information processing system in which one information processing apparatus and another information processing apparatus are connected via a network and perform information processing according to a predetermined command,
The one information processing apparatus collects information on the operation state from the other information processing apparatus and creates a device information table, and when the command occurs, the resource required for executing the command An information processing system comprising: device specifying means for comparing information and information relating to an operation state of the device information table to specify an information processing device capable of executing the command.   The information processing system according to claim 15, wherein the capability exchanging unit transmits the command to the information processing apparatus specified by the apparatus specifying unit and requests execution thereof.   The other information processing apparatus includes a plurality of processor means for processing the command, and the capability exchanging means collects information on the operation state of each of the plurality of processor means and stores the information in the apparatus information table. The information processing system according to claim 15, characterized in that:   The one information processing apparatus further includes manager means for determining whether another information processing apparatus is connected to the network, and the other information processing apparatus is connected to the network by the manager means. The information processing system according to claim 15, wherein if it is determined, processing by the capability exchanging means is executed. In order to perform information processing according to a predetermined command in an information processing system in which one information processing device and another information processing device are connected via a network, a computer included in the one information processing device is provided.
Capability exchanging means for collecting information on operation status from the other information processing apparatus and creating a device information table, information on resources required for execution of the command when the command is generated, and the device information table Device specifying means for comparing the information on the operation state of the information processing device to specify the information processing device capable of executing the command,
Program for information processing to function as.   20. The information processing program according to claim 19, further causing the computer to function as means for transmitting the command to the identified information processing apparatus and requesting execution.   The other information processing apparatus includes a plurality of processor means for processing the command, and the information processing program collects information about an operation state of each of the plurality of processor means as the computer and the capability exchange means. The information processing program according to claim 19, wherein the information processing program is made to function as means for storing in the device information table.   The information processing program causes the computer to function as manager means for determining whether or not another information processing apparatus is connected to the network, and other information processing is performed on the network by the function as the manager means. The information processing program according to claim 19, wherein when it is determined that a device is connected, the computer is caused to function as the capability exchange unit.

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