JP2001188749A - Bus controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus controller for performing access to plural slave devices, and performing efficient access without any buffer for absorbing the difference of latency. SOLUTION: A bus controller 1 is provided with a master I/F 51 for controlling a request from a master device and slave I/F 52 and 53 for controlling access to slave devices for each slave device. At the time of receiving an access request, the master I/F 51 judges that the request is a write access in a step 103, or judges that the access is not being performed at present in a step 104, and asserts the request to the slave I/F 52 or 53 in a step 110 when the destination of the requested access is made coincident with that which is being accessed at present in a step 105, and requests the start of the access control. Thus, it is possible to realize efficient access without any buffer for absorbing the difference of the wait cycles of the different slave devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the field of computers and digital products, and more specifically to a bus controller for accessing a plurality of slave devices. It is a bus controller that aims at.

[0002]

2. Description of the Related Art FIG. 15 shows a system for accessing a memory from a CPU using a conventional bus controller. The system consists of a bus controller 1001, a CPU 100
2, a memory 1003 and a memory 1004. The bus controller 1001 receives a read request 1010 or a write request 101 from the CPU 1002.
1, the access control is performed on the memory pointed to by the address 1012. The bus controller 1001 returns data from the memory to the CPU 1002 in the order requested by the CPU 1002.

[0003]

However, the above-mentioned prior art has the following problems.

For example, when the memory 1003 is an SDRAM, read access to the memory 1003 is performed as shown in FIG.
As shown in the figure, an address A0 and a command C0 are issued, and the corresponding data D00, D01, D02 and D03 are stored in the memory 100.
The next address A1 and command
By issuing C1, it is possible to reduce the access waiting time and increase the transfer efficiency.

However, the memory 1003 and the memory 1
Considering the case where read access is performed in the order of 004,
After the access to the memory 1003 is started, the memory 1
When the access to the memory 004 is started, the data is read from the memory 1004 before the data in the memory 1003 depending on the access wait cycle of the memory 1004. Therefore, in order to guarantee the order of the data to the CPU 1002, The data from 1004 needs to be stored temporarily.

In order to avoid an increase in the circuit size because the size of data to be accessed at one time is large, if this buffer is not provided, the next access must be started after the previous access is completed. This is disadvantageous in terms of transfer efficiency.

In view of the above problems, the present invention relates to a bus controller which improves transfer efficiency while reducing the number of buffers and the circuit size.

[0008]

According to a first aspect of the present invention, there is provided a bus controller having address determining means for determining a match between a slave device indicated by an address of an access request from a master device and a currently accessed slave device. When there is an access request from the master device, the timing for starting the access request is determined from the address of the access request.

According to a second aspect of the present invention, in the bus controller, the address judging means for judging a match between the slave device indicated by the address of the access request from the master device and the currently accessed slave device is provided. If there is a read access by the request of the master device and the slave device that is accessing does not match the slave device indicated by the address of the access request from the master device, the slave device indicated by the address of the access request Prohibit access start.

According to a third aspect of the present invention, there is provided a bus controller having address determining means for determining a match between a slave device indicated by an address of an access request from a master device and a currently accessed slave device. During the period when it is determined that the read access is performed according to the request of the master device and the accessing slave device does not match the slave device indicated by the address of the access request from the master device, an access wait cycle of each slave device is performed. If the wait cycle of the slave device indicated by the address of the access request indicated by the wait register indicating is greater than or equal to the wait cycle of the accessing slave device, the If the wait cycle of the slave device indicated by the address of the access request indicated by the wait register is less than the wait cycle of the accessing slave device, the start of access to the slave device indicated by the address is prohibited. I do.

According to a fourth aspect of the present invention, a bus controller controls an access request from a master device.
F and a plurality of slave I / Fs for controlling access to the slave device. The master I / F operates as a slave based on the address of the access request from the master device.
Determine the timing of the access request to the I / F.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a system for accessing a memory from a CPU using the bus controller of the present invention. This system includes a bus controller 1, a CPU 2, a memory 3, and a memory 4. The bus controller 1
When the read request (negative logic) 10 from the CPU 2 is asserted, it is determined that there is a memory data read request from the CPU 2 and the acceptance of the request is notified to the CPU 2 by asserting the request acknowledge (negative logic) 20. . Similarly, a write request from CPU 2 (negative logic)
When 11 is asserted, it is determined that there is a data write request from the CPU 2 to the memory, and the CPU 2 is notified that the request is accepted by asserting a request acknowledge (negative logic) 20.

The bus controller 1 determines that the address 12 in the cycle in which the read request 10 or the write request 11 is asserted is the address of the access destination requested by the CPU 2, and based on this address,
An access is made to either the memory 3 or the memory 4. If the burst request (negative logic) 13 is asserted in this cycle, burst access is performed. Here, it is assumed that the burst access is 16 bytes and the non-burst single access is 4 bytes.

The bus controller 1 uses a control signal 30, an address 31, and data 32 for the memory 3,
The memory 4 is accessed using the control signal 40, the address 41, and the data 42. Memory 3 is SD
Like a RAM, an access can be performed by inputting a next access address and a command by a control signal before returning data from the memory. The memory 4 is, for example, SR
It is assumed that the address and the control signal are continuously output during the access to the memory like the AM.

The bus controller 1 outputs data read from the memories 3 and 4 to the CPU 2 through data 15. The CPU 2 further asserts a read acknowledge (negative logic) 22 to notify that the data 15 is valid data.

In the case of a write access, in a single write, the data 14 in the cycle in which the write request 11 is asserted is used as write data.
The data after the second is the cycle in which the bus controller 1 asserts the write acknowledge (negative logic) 23,
U2 is supplied by outputting to data 15.

FIG. 2 shows the configuration of the bus controller 1.
The bus controller 1 has a master I / F 51 and a slave I / F 5
2, 53 and the address buffers 61, 62,
Write data buffers 63 and 64, data selector 65
It consists of.

The master I / F 51 is a block for interfacing with a master device (the CPU 2 in the present embodiment).
3 to control the access requested by the CPU 2.

The slave I / Fs 52 and 53 are blocks for interfacing with the memories 3 and 4, respectively. When the requests 71 and 72 from the master I / F 51 are asserted, respectively, the grants 73 and 74 are asserted and the master I / F 5
1 is notified of the acceptance, and access control to the memories 3 and 4 is started. In addition, a read / write signal 75 and a burst signal 77 are output from the master I / F 51, respectively, and access end signals 80, 81 and read acknowledges 82, 8 are output from the slave I / Fs 52, 53, respectively.
3. Write acknowledges 84 and 85 are output.

The address buffers 61 and 62 are respectively
This buffer stores access addresses to the memories 3 and 4, and latches the address 12 in the cycle in which the address latch enables 91 and 92 from the slave I / Fs 52 and 53 are asserted, respectively.

The write data buffers 63 and 64 are buffers for storing write data to the memories 3 and 4, respectively. In the cycle in which the write data latch enables 93 and 94 from the slave I / Fs 52 and 53 are asserted, respectively. The data 14 is latched.

The data selector 65 selects one of the data from the slave device and the data 32 or 42, and selects the select signal 9 output from the master I / F 51.
5 is selected.

The master I / F 51 has an access flag 20
1, 202, and slave device flags 203, 204.

The access flags 201 and 202 are flags indicating that access is currently being performed based on a request from the master device.
The access corresponding to 1 has been received before the access flag 202.

Slave device flags 203, 204
Are flags corresponding to the access flags 201 and 202, respectively, indicating which slave device is being accessed. In the present embodiment, it is assumed that the memory 3 is 0 and the memory 4 is 1 for each.

FIG. 3 shows a flowchart for request control of the master I / F 51.

In step 101, it is determined whether there is a request from the master device. If the read request 10 or the write request 11 has been asserted, it is determined that a request has been made, and the process proceeds to step 102.
If neither is asserted, the process waits at step 101.

In step 102, the bus controller 1
Is in a state where it can accept the request. If the access flag 202 has been set, the request is no longer accepted and it is determined that control cannot be performed, and the process proceeds to step 101. Access flag 202
If is not set, the process proceeds to step 103 and access control is continued.

In step 103, it is determined whether the access is a read or a write. In step 101,
If the read request 10 has been asserted, the process proceeds to step 104. If the write request 11 has been asserted, the process proceeds to step 110.

In step 104, it is determined whether or not access is currently being performed. If the access flag 201 is set, it is determined that access is in progress and step 10
If it is not set to 5, the process proceeds to step 110.

In step 105, as the address determination means, it is checked based on the address 12 from the CPU 2 whether the device requesting access by the master device matches the device currently being accessed. If the slave device in the memory 3 or the memory 4 indicated by the slave device flag 203 matches the slave device indicated by the address 12, the process proceeds to step 10. Otherwise, the process proceeds to step 110.

In step 110, a request 71 or 72 is asserted for one of the slave I / Fs 52 and 53 corresponding to the slave device indicated by the address 10, and an access request to the slave by the slave I / F is issued. The process proceeds to step 111. At this time, the read / write signal 75 is asserted for read access in response to a request from the master, and the burst signal 77 is asserted for burst access.

In step 111, it is determined whether the grant from the slave I / F has been asserted and the slave I / F has accepted the request. If the request 71 has been asserted and the grant 73 has been asserted, and if the request 72 has been asserted and the grant 74 has been asserted, it is determined that the request has been accepted, the request acknowledge 20 is asserted, and the access flag 201 is set. If it is set, the access flag 202 is set, and the slave device flag 204 is set to the value of the device to be accessed. If the access flag 201 is not set, the access flag 201 is set, and the slave device flag 203 is set to the value of the device to be accessed. If the grant has not been asserted, the process waits at step 111.

In the master I / F 51, when the access end signals 80 and 81 from the slave I / F are asserted, the slave device flag 203 or 204 corresponds to the one set to the value of the corresponding slave device by the slave device flag 203 or 204. The access flag 201 or 202 is cleared.

The access flags 201 and 202 are both set, and the slave device flags 203 and 20 are set.
If 4 is set to the same value, the access flag 201 is cleared. When the access flag 201 is cleared, the value of the access flag 202 is shifted to the access flag 201 and the value of the slave device flag 204 is shifted to the slave device flag 203 immediately.

When the read acknowledgment 82 or 83 is asserted from the slave I / F, the master I / F 51 asserts the read acknowledgment 22 to notify valid read data, and the write acknowledgment 84 or 85 is asserted. If so, the write acknowledge 23 is asserted to notify the next data output timing.

For the read data, the device indicated by the slave device flag 203 is selected by the select signal 95.

The slave I / F 52 has an access flag 21
1, 212, busy flag 213, read access flag 214, and slave I / F 53 access flag 22
1, 222, a busy flag 223, and a read access flag 224.

FIG. 4 is a flowchart for request control of the slave I / Fs 52 and 53.

In step 151, it is determined whether there is a request from the master I / F. Request 71 if slave I / F 52, request 7 if slave I / F 53
If 2 is asserted, the process proceeds to step 152; otherwise, the process waits at step 151.

In step 152, it is determined whether a request from the master I / F can be accepted. Slave
I / Fs 52 and 53 are busy flags 213 and 22 respectively.
3 is not set and the access flag 212,
When 222 is not set and slave I / F
In the case of 52, both the access flag 211 and the read access flag 214 are set, and the read / write signal 75 is 0
If not a combination of (write), slave I / F53
Access flag 221 and read access flag 2
If both are set and the read / write signal 75 is not a combination of 0 (write), it is determined that the request can be accepted. If the slave I / F 52, the grant 73 is used. If the slave I / F 53, the grant 73 is used. If it is, the grant 74 is asserted for one cycle. If it is the slave I / F 52, the busy flag 213 is set.
If 11 is not set, the access flag 21
If the access flag 211 is set, the access flag 212 is set. If the slave I / F 53, the busy flag 223 is asserted. If the access flag 221 is not set, the access flag 2 is set.
When the access flag 221 is set to 21, the access flag 222 is set, and the process proceeds to step 153. If not, it waits in step 152.

In step 153, an access sequence corresponding to the slave device to be accessed is started in accordance with the read / write signal 75 and the burst signal 77 from the master I / F, and the process proceeds to step 151. At this time, the slave I / Fs 52 and 53 assert the address latch enable 91 and 92, respectively, and in the case of write access, assert the write data latch enable 93 and 94. The slave I / Fs 52 and 53 perform access control such as command issuance by control signals 30 and 40 according to the access sequence, respectively.

The slave I / Fs 52 and 53 clear the busy flags 213 and 223, respectively, after outputting the control signal and data to the slave, and assert the access end signals 80, 81 for one cycle when the access is completed. If the slave I / F 52, the value of the access flag 212 is shifted to the access flag 211 to clear the access flag 212, and if the slave I / F 52, the value of the access flag 212 is shifted to the access flag 211. , The access flag 212 is cleared.

FIGS. 5 to 12 show timing charts for explaining the operation of the bus controller of the present invention.

FIG. 5 shows a case where read access is continuously made to the same slave.

In the example of FIG. 5, a request 71 is asserted in a cycle 0 in response to a read request 10, and a read access to the memory 3 is started in a cycle 1. Further, the access according to the next read request 10 from the cycle 2 is started in the cycle 3 earlier than the read data of the previous access is returned. In the cycle in which the read data is returned, the read data acknowledge 22
Is asserted to notify the data read timing.

FIG. 6 shows a case where read access is continuously made to different slaves.

In the example of FIG. 6, a request 71 is asserted in a cycle 0 in response to a read request 10, and a read access to the memory 3 is started in a cycle 1. The request 71 corresponding to the next read request 10 from the cycle 2 is a cycle in which the access to the memory 3 is completed.
Asserted at 4 and access starts at cycle 5.

FIG. 7 shows a case where the same slave is continuously accessed for write.

In the example of FIG. 7, a request 71 is asserted in response to a write request 11 in cycle 0, and write access to the memory 3 is started in cycle 1. Further, the request 71 is asserted in response to the next write request 11 from the cycle 2. Since the bus is busy in the cycle 2, the grant 73 is asserted in the cycle 4 and the access is started in the cycle 5 Becomes

FIG. 8 shows a case in which write access is continuously made to different slaves.

In the example of FIG. 8, a request 71 is asserted in a cycle 0 in response to a write request 11, and a write access to the memory 3 is started from a cycle 1. Further, the request 71 is asserted in response to the next write request 11 from cycle 2, and since the bus is not busy, the grant 73 is asserted in cycle 2, and the access starts in cycle 3.

FIG. 9 shows a case where the same slave is accessed in the order of read and write.

In the example of FIG. 9, a request 71 is asserted in a cycle 0 in response to a read request 10, and a read access to the memory 3 is started in a cycle 1. Further, the request 71 is asserted in the cycle 2 in response to the next write request 11 from the cycle 2, but the grant 73 is asserted in the cycle 4 in which the read access is completed, and the access starts in the cycle 5. Is done.

FIG. 10 shows a case where different slaves are accessed in the order of read and write.

In the example of FIG. 10, a request 71 is asserted in a cycle 0 in response to a read request 10, and a read access to the memory 3 is started from a cycle 1. Further, in response to the next write request 11 from the cycle 2, the request 71 is asserted in the cycle 2, and the write access to the memory 4 is started from the cycle 5.

FIG. 11 shows a case where the same slave is accessed in the order of write and read.

In the example of FIG. 11, a request 71 is asserted in response to a write request 11 in cycle 0, and write access to the memory 3 is started in cycle 1. Further, in response to the next read request 10 from the cycle 2, the request 71 is asserted in the cycle 2, but the grant 73 is asserted in the cycle 4 in which the write access is completed, and the read access to the memory 3 is performed. Is started from cycle 5.

FIG. 12 shows a case where different slaves are accessed in the order of write and read.

In the example of FIG. 12, a request 71 is asserted in a cycle 0 in response to a write request 11, and a write access to the memory 3 is started from a cycle 1. Further, in response to the next read request 10 from the cycle 2, the request 72 is asserted in the cycle 2, and the read access to the memory 4 is started from the cycle 5.

FIG. 13 shows a flowchart in the case where the master I / F 51 performs request control based on the wait cycle information of the slave device. What is different from the one in the figure is that if it is determined in step 105 that the devices to be accessed do not match, the process proceeds to step 106, and it is determined whether the request can be made from the relationship of the weight. The master I / F 51 has a wait cycle register, and stores the wait cycle of the access for each slave device. In step 106, the wait cycle of the slave device indicated by the slave device flag 203 is compared with the wait cycle of the requested slave device. If the requested one is larger or equal, the process proceeds to step 110; Transitions to step 101.

FIG. 14 is a timing chart in the case of following the flowchart control of FIG.

Following the read request 10 to the memory 3 from the cycle 0, the read request 10 to the memory 4 from the cycle 2
Reading to a different slave is performed after the previous access is completed.However, since the wait cycle is larger than the previous access, the access completion does not overtake the previous access completion. 71 is asserted and is accessible from cycle 3. This makes it possible to eliminate useless waiting cycles.

[0065]

According to the bus controller of the first aspect, the access destination is determined based on the address and the access start timing is changed, so that data collision or the like occurs due to a difference in the wait cycle of the access destination device. This has the effect of avoiding the problem described above.

According to the bus controller of the second aspect, at the time of continuous read access, the access start timing is changed in accordance with the coincidence or non-coincidence of the access destination, thereby providing a buffer for absorbing a difference in wait cycle. There is an effect that the transfer is performed without reducing the transfer efficiency to the same slave device while making it unnecessary.

According to the bus controller of the third aspect, by changing the access start timing according to the wait cycle of the access destination, an unnecessary wait cycle is generated in the access in which the order of the read data is maintained. There is an effect that disappears.

According to the bus controller of the fourth aspect, the master I / F determines the access destination based on the address and changes the timing of the access request,
Slave I / F with different configuration for each slave device
In this case, there is no need to control access start timing, and the bus controller can be flexibly configured.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a system using a bus controller of the present invention.

FIG. 2 is a diagram showing a configuration example of a bus controller of the present invention.

FIG. 3 is a control flowchart of a master I / F 51;

FIG. 4 is a control flowchart of slave I / Fs 52 and 53.

FIG. 5 is a timing chart when continuous read access is performed to the same slave.

FIG. 6 is a timing chart when continuous read access is performed to different slaves;

FIG. 7 is a timing chart when continuous write access is performed to the same slave.

FIG. 8 is a timing chart when continuous write access is performed to different slaves;

FIG. 9 is a timing chart when an access is performed to the same slave in the order of read and write

FIG. 10 is a timing chart in the case of performing access to different slaves in the order of read and write

FIG. 11 is a timing chart in the case where access is performed to the same slave in the order of writing and reading;

FIG. 12 is a timing chart when performing access to different slaves in the order of write and read

FIG. 13 shows a master I / F 51 having a wait register.
Control flowchart

14 is a timing chart in the case where continuous read access is performed to different slaves according to the control flowchart of FIG. 13;

FIG. 15 is a diagram showing an example of a system using a conventional bus controller.

FIG. 16 is a timing chart of continuous access to SDRAM.

[Explanation of symbols]

 1 Bus controller 2 CPU 3, 4 Memory 10 Read request 11 Write request 12 Address 13 Burst request 14 Data input 15 Data output 20 Request acknowledge 22 Read acknowledge 23 Write acknowledge 30, 40 Control signal 31, 41 Address 32, 42 Data 51 Master I / F 52, 53 Slave I / F 61, 62 Address buffer 63, 64 Write data buffer 65 Data selector 71, 72 Request 73, 74 Grant 75 Read / write signal 77 Burst signal 80, 81 Access end signal 82, 83 Read Acknowledge 84, 85 Write acknowledge 91, 92 Address latch enable 93, 94 Write data latch enable 95 Select signal

Claims (4)

[Claims] Claims: 1. Based on a request from a master device,
A bus controller for controlling access to a plurality of slave devices, comprising: a slave device indicated by an address of an access request from the master device; and an address determination unit configured to determine a match between a slave device that is currently performing access, A bus controller that determines a timing to start accessing the slave device based on an address of an access request from the master device. 2. When a read access request is issued from the master device, the bus controller performs a read access according to the request from the master device, and the accessing slave device determines an address of an access request from the master device. 2. The device according to claim 1, wherein the address determination unit prohibits the start of access to the slave device indicated by the address of the access request during a period in which the access request does not match the slave device indicated by the address.
Bus controller as described. 3. A bus controller having a wait register indicating a wait cycle of an access of each slave device, wherein the master device receives a read access request, and performs a read access according to the request of the master device, and performs the address determination. During a period in which the means determines that the accessing slave device does not match the slave device indicated by the address of the access request from the master device, the wait cycle of the slave device indicated by the address of the access request indicated by the wait register indicates the access cycle. If the wait cycle is greater than or equal to the wait cycle of the slave device performing the access, the access to the slave device indicated by the address is permitted to start, and the address of the access request indicated by the wait register is indicated. If the wait cycles of the slave devices is below a wait cycle of the slave devices that are accessing the bus controller of claim 1, wherein the prohibiting starting access to the slave device indicated by the access request address. 4. A master I / F for controlling an access request from a master device, and a plurality of slave I / Fs for controlling an access to a slave device.
Wherein a timing of an access request to a slave I / F is determined based on an address of an access request from the master device.