JP2001282704A - Device, method and system for processing data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device, a method and a system for processing data which can reduce the scale and cost of the data processing system and can realize high-speed data processing. SOLUTION: Concerning the data processor for exchanging data between an SDRAM 5 connected to an SDRAM bus 13 for storing data and an external bus mater 17 connected to a general bus 15 for processing data, a data processor 20 equipped with a transmission control part 29 for assessing the SDRAM 5 corresponding to a request from the external bus master 17 and the data processing system equipped with this data processor 20 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device, a data processing method, and a data processing system.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional operation having a synchronous dynamic random access memory (SDRAM) capable of reading and writing data at high speed, and a bus for the SDRAM for realizing access to the SDRAM. FIG. 2 is a diagram illustrating a configuration of a processing system.

As shown in FIG. 1, this arithmetic processing system includes a first central processing unit (CPU) 1, a second central processing unit (CPU) 3, an SDRAM 5, and a read-only memory (ROM). 7, a random access memory (RAM) 9, an input / output buffer (I / O) 11,
An SDRAM bus 13 and a general-purpose bus 15 are provided.

Here, the first CPU 1 and the second CPU 3 are connected by an SDRAM bus 13 and a general-purpose bus 15. The ROM 7 and the RAM 9 are connected to the general-purpose bus 15.
And various resources of the I / O 11 are connected, and access from both the first and second CPUs 1 and 3 is possible. Similarly, the SDRAM bus 13 has an SDRAM 5
Are connected, and access from both the first and second CPUs 1 and 3 is possible.

However, in general, the SDRAM bus 1
The CPU which exchanges data via the CPU 3 has a problem that it becomes expensive because the function becomes complicated and the number of terminals provided is increased. Also, as shown in FIG. 1, in order to use a memory area constituted by one SDRAM 5 or a plurality of SDRAMs by a plurality of CPUs (for example, the first and second CPUs 1 and 3), the
Since it is necessary to connect the RAM bus 13 from the SDRAM to the plurality of CPUs, there is a problem that the transmission path of the SDRAM bus becomes complicated.

Further, the SDRAM 5 can operate at a high speed at an operating frequency of 100 MHz or more. However, as described above, the transmission path of the SDRAM bus becomes complicated, which causes a problem of lowering the operating frequency. is there.

When one memory area on the SDRAM is used by a plurality of CPUs, when the SDRAM bus is used, arbitration between the CPUs as to which CPU uses the SDRAM bus preferentially. Since an operation is required, there is a problem that means (comprising software and hardware) for controlling the plurality of CPUs becomes complicated.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to reduce the size and cost of a data processing system and realize a high-speed data processing. It is an object to provide a processing method and the data processing system.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for transferring data between a storage means connected to a first bus for storing data and an external data processing means connected to a second bus for processing data. The present invention is attained by providing a data processing device for exchanging data, wherein the data processing device includes an access control unit for accessing a storage unit in response to a request from an external data processing unit. According to such means, it is possible to avoid access conflicts that occur when a plurality of external data processing means access the storage means.

The access control means supplies the data read from the storage means by the access to the external data processing means via the second bus, or supplies the data read from the external data processing means via the second bus. If the supplied data is to be written into the accessed storage means,
The transmission path connected to the storage means is a one-to-one connection with the data processing device, and the speed of data input / output to the storage means can be increased.

The access control means includes a bus right granting means for granting preferential use of the second bus in response to a request from the external data processing means, wherein the bus right granting means gives priority to the external data processing means. If the access is permitted, the storage means can be accessed via the first bus except when an access request to the storage means is made by the external data processing means. Can be controlled independently of the operation of the external data processing means.

Further, when the external data processing means or storage means accesses the external device, if the request is made by the external data processing means, it is determined which of the external access and the request is to be executed with priority. By further providing arbitration means for determining, the efficiency of data processing can be increased.

The access control means, if the data transfer rate on the first bus is different from the data transfer rate on the second bus, is adapted to the specifications of the storage means and the external data processing means. Data transfer can be realized.

[0014] Another object of the present invention is to provide a data transfer means for storing data connected to a first bus and storing data therein, and an external data processing means connected to a second bus for processing data. This is achieved by providing a data processing method, characterized by accessing a storage unit in response to a request from an external data processing unit.

Another object of the present invention is a data processing system having a storage means connected to a first bus for storing data, and a second data processing means connected to a second bus for processing data. Connected to the first and second buses, access the storage means in response to a request from the second data processing means, and process the data obtained by the access via the second bus for the second data processing. Data processing means for supplying data to the storage means or writing data supplied by the second data processing means via the second bus to the accessed storage means. This is achieved by providing a system. According to such means, it is possible to avoid contention of the access which occurs when the first and second data processing means access the storage means, and directly from the second data processing means. A circuit for accessing the storage means becomes unnecessary.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. [First Embodiment] FIG. 2 is a diagram showing a configuration of an arithmetic processing system according to a first embodiment of the present invention. As shown in FIG. 2, the arithmetic processing system according to the first embodiment includes:
Synchronous dynamic random access memory (SDRA
M) 5, a read only memory (ROM) 7, a random access memory (RAM) 9, and an input / output buffer (I
/ O) 11, SDRAM bus 13, and general-purpose bus 15
, An external bus master 17 and a central processing unit (CP
U) 20.

The central processing unit 20 has a CP
U core 21, data buffer unit (DBUF) 23,
DMA (Direct Memory Access) control unit (DMAC) 2
5, an SDRAM control unit 27, and an external bus control unit 28
, An internal bus 33, and an external clock signal (CLK) input terminal 34. The external bus control unit 28 includes a transmission control unit (BTC) 29 and a general-purpose bus control unit 31. Also,
The general-purpose bus control unit 31 includes an access source determination unit 32, and includes a data buffer unit (DBUF) 23 and a DMA control unit (DM
The AC 25 and the transmission control unit (BTC) 29 include internal bus control units 24, 26, and 30, respectively.

Here, the SDRAM 5 and the SDRAM control unit 27 are connected by the SDRAM bus 13, and the external bus master 17 and the external bus control unit 28 are connected by the general-purpose bus 15. The general-purpose bus 15 is connected to the ROM 7, the RAM 9, and the I / O 11.

In the CPU 20, the data buffer unit 23, the DMA control unit 25, the SDRAM control unit 27, and the external bus control unit 28 are all connected to the internal bus 33. The CPU core 21 is connected to the data buffer unit 23, and the external clock signal CLK supplied to the CLK input terminal 34 is supplied to the SDRAM control unit 27 and the external bus control unit 28.

Next, an outline of the operation of the arithmetic processing system having the above configuration will be described. The most significant feature of the arithmetic processing system according to the present embodiment is that the CPU 20 has a bus transmission function. Here, the “bus transparent function” means that, for example, when an external bus master 17 connected to the general-purpose bus 15 makes an access request to the SDRAM 5 via the general-purpose bus 15, the CPU 20
A function of accessing the SDRAM 5 using the AM bus 13.

Then, for example, the external bus master 17
When using data stored in the DRAM 5, C
The PU 20 is requested to access the SDRAM 5 through the general-purpose bus 15. At this time, the CPU 20
The RAM bus 13 is driven to access the SDRAM 5.

The external bus master 17 sends the SDRA
If a write request to M5 has been made, the CPU
20 writes the data supplied from the external bus master 17 into the area of the SDRAM 5 designated by the external bus master 17. On the other hand, the SDRA
If a read request has been made from M5, CP
U20 is the SDR specified by the external bus master 17.
Data is read from the area of AM5, and the data is supplied to the external bus master 17 via the general-purpose bus 15.

As described above, since the CPU 20 has the bus transmission function, the external bus master 17
Even when it is necessary to access the external bus 5, the SDRAM bus 13 does not need to be connected to the external bus master 17 and only the general-purpose bus 15 needs to be connected, so that the cost of the external bus master 17 can be reduced. .

Further, as shown in FIG.
5 is connected only to the CPU 20, the transmission path of the SDRAM bus 13 becomes simple, and it becomes easy to realize the high-speed operation of the SDRAM 5 on the arithmetic processing system.

Further, only the CPU 20 executes the SDRA
Since M5 is accessed, the SDRAM bus 1
In using No. 3, arbitration between a plurality of CPUs is not required. Therefore, the means (comprising software and hardware) for controlling the entire arithmetic processing system is simplified. In addition, the SDRA of the CPU 20 itself is used.
Switching between the access to the M5 and the access to the SDRAM 5 requested from the external bus master 17 or the like via the general-purpose bus 15 is realized by hardware as described later.

Hereinafter, the operation of the arithmetic processing system according to the first embodiment shown in FIG. 2 will be described in detail.
In the following, a signal activated at a low level is denoted by “#”.

The CPU 20 operates as a so-called bus master that uses the general-purpose bus 15 in a leading manner,
When a resource (external bus master 17) that can become a bus master in place of U20 is connected to the general-purpose bus 15, the use right (bus right) of the general-purpose bus 15 is changed in response to the general-purpose bus release request from the external bus master 17. Hand over.
Here, the state in which the general-purpose bus 15 is released by the CPU 20 is referred to as a “bus grant state”.

More specifically, when the external bus master 17 requests the release of the general-purpose bus 15, the bus request signal BREQ # having a low level shown in FIG.
Is supplied from the external bus master 17 to the external bus control unit 28 via the general-purpose bus 15. At this time, when the external bus control unit 28 determines that the general-purpose bus 15 can be released, the external bus control unit 28 outputs a bus grant signal BGRNT #, which is activated at time T1 shown in FIG. It is supplied from the control unit 28 to the external bus master 17. Note that, as shown in FIG. 3, the general-purpose bus 15 is released in a period Tbg from the time T1 to the time T5 when the bus grant signal BGRNT # is activated.

As described above, the CPU 20 is connected to the general-purpose bus 15.
The external bus master 17 can access all the resources connected to the general-purpose bus 15 in the bus grant state in which the access is released. SDRAM5
Is a dedicated SDRAM bus 13 different from the general-purpose bus 15
, It is impossible for the external bus master 17 to directly access the SDRAM 5 even in the bus grant state.

When it becomes necessary to use the general-purpose bus 15 after releasing the general-purpose bus 15, as shown in FIG. 3D, the CPU 20 activates the activated low-level processor bus request. The signal PBREQ # is supplied to the external bus master 17 to request the external bus master 17 to stop using the general-purpose bus 15. The processor bus request signal PBREQ # is the bus grant signal B
After the time T1 when GRNT # is activated and the CPU 20
Is activated to a low level at an arbitrary time when it becomes necessary to use the general-purpose bus 15, but FIG. 3D shows a case where it is activated at a time T3 as an example.

The external bus master 17 is connected to the external bus master 17 shown in FIG.
At time T4 when the use of the general-purpose bus 15 is completed, the bus request signal BREQ # deactivated to a high level is supplied to the external bus control unit 28 as shown in FIG. Thus, after confirming that the high-level bus request signal BREQ # has been supplied, the external bus control unit 28 inactivates the bus grant signal BGRNT # at time T5 as shown in FIG. Thus, the release of the general-purpose bus 15 is completed, and the use of the general-purpose bus 15 is started.

In the above, the CPU 20 supports the function of the external bus master 17 accessing the SDRAM 5 via the CPU 20 in the bus grant state. In the following, such a function is referred to as "access transparent function".
And a mode for realizing the access transparent function is called an “access transparent mode” or simply a “transparent mode”.
The transparent access to the SDRAM 5 is simply referred to as “transparent access”. In addition, the above-mentioned access transparent function,
This is realized in the single mode or the burst mode in which the burst length is 4 or 8, depending on the type of access.

The operation of the external bus master 17 writing data to the SDRAM 5 via the general-purpose bus 15 will be described below with reference to the waveform diagram of FIG.

The external bus master 17 starts using the general-purpose bus 15 when the activated bus grant signal BGRNT # is supplied. When the access to the SDRAM 5 is necessary, the external bus master 17 outputs the address strobe signal AS # and the SDRAM select signal SDSEL #, for example, at a time as shown in FIGS. 4 (e) and 4 (f). It is activated to a low level at T2 and supplied to the external bus control unit 28. Thereby, the transmission control unit (BTC)
29 detects that the external bus master 17 has accessed the SDRAM 5. At this time, BTC2
Reference numeral 9 denotes an effective address signal for specifying an access destination in the SDRAM 5 during a period from time T2 to time T3 when the address strobe signal AS # is activated to a low level, as shown in FIG. AD
Capture by R.

The BTC 29 is connected to the external bus master 1
7 to read or write data to or from the SDRAM 5 according to the logical level of the read / write signal RDWR # supplied from. That is, as shown in FIG. 4 (g), for example, during the period from time T2 when the address strobe signal AS # is activated to the low level to time T3, the low-level read / write activated by the external bus master 17 is performed. When the signal RDWR # is supplied, the BTC 29 writes data to the SDRAM 5. Note that the high-level read / write signal RDWR
When # is supplied, the BTC 29 reads data from the SDRAM 5.

Here, since the logic level of the read / write signal RDWR # is referred to by the BTC 29 between the time T2 and the time T3 when the address strobe signal AS # is activated, it is shown in FIG. At time T3
In the subsequent predetermined period, the logic level may be either high or low.

Then, the external bus master 17
In the case of writing data to M5, FIG.
As shown in (l), the address strobe signal AS #
Is activated to a low level, at the same time (time T2), transfer of the write data D to the SDRAM 5 is started.

At this time, the BTC 29 transfers the data with the data length uniquely determined by the following Table 1 according to the combination of the logic levels of the supplied burst transfer request signal BMREQ # and the burst length designation signal BLEN8 #. I do.

[0039]

[Table 1] That is, for example, as shown in FIGS. 4H and 4N, the burst transfer request signal BMREQ # is low (L) between the time T2 when the address strobe signal AS # is activated and the time T3. Level and the burst length designation signal BLEN8 # is at a high (H) level,
As shown in Table 1 above, the external bus master 17
Data is transferred to DRAM 5 by four bursts. When a request for burst transfer is made by the external bus master 17 and the external bus control unit 28 is in a state where the request can be permitted, the external bus control unit 28 activates the low-level signal as shown in FIG. The burst transfer permission signal BMACK # is supplied to the external bus master 17.

The CPU 20 is connected to the external bus master 17
Therefore, when a request for burst transfer is made, the request is not canceled, so that the burst transfer permission signal BMACK # is always supplied to the external bus master 17. Since the logic level of the burst transfer request signal BMREQ # is referred to by the BTC 29 between the time T2 and the time T3 when the address strobe signal AS # is activated, as shown in FIG. During the period from T3 to the time when the burst transfer permission signal BMACK # is supplied to the external bus master 17, the logical level is arbitrary.

On the other hand, when writing data to the SDRAM 5, the external bus control unit 28 fetches the data from the general-purpose bus 15 and simultaneously outputs the byte valid signals BE0 # -7 # as shown in FIG. Then, only the byte corresponding to the byte valid signal BE0 # -7 # whose logic level is low (L) level is written to the SDRAM 5.

As shown in FIG. 4 (m), the external bus control unit 28 outputs a low-level bus cycle end signal from the time when the data D is fetched from the external bus master 17.
RDYOUT # is supplied to the external bus master 17 to notify that the data D is effectively taken in.

In the above description, the external bus master 17
When the data is transferred to the SDRAM 5 in four bursts, the lower 2 bits of the address of the data are set to 0, and the CPU 20 writes the data to the SDRAM 5 by sequentially incrementing the address of the lower 2 bits. Similarly, when data is transferred by 8 bursts, the lower 3 bits of the address of the data are set to 0, and the CPU 20 sequentially increments the address of the lower 3 bits to thereby transfer the data transferred by the 8 bursts. Is written to the SDRAM 5.

On the other hand, when the address strobe signal AS # is activated in the above, the burst transfer request signal BM
When REQ # is at a high (H) level and burst length designation signal BLEN8 # is also at a high (H) level, a single write operation of writing one data to SDRAM 5 is performed.

Next, the external bus master 17
The operation of reading data from the SDRAM 5 via the interface will be described with reference to the waveform diagram of FIG.

The external bus master 17 starts using the general-purpose bus 15 when the activated bus grant signal BGRNT # is supplied. When the access to the SDRAM 5 is necessary, the external bus master 17 transmits the address strobe signal AS # and the SDRAM select signal SDSEL # to, for example, a time as shown in FIGS. 5B and 5C. It is activated to a low level at T2 and supplied to the external bus control unit 28. Thereby, the transmission control unit (BTC)
29 detects that the external bus master 17 has accessed the SDRAM 5. At this time, BTC2
Reference numeral 9 denotes a valid address signal which designates an access destination in the SDRAM 5 during a period from time T2 to time T3 when the address strobe signal AS # is activated to a low level, as shown in FIG. AD
Capture by R.

In the period from time T2 to time T3 when the address strobe signal AS # is activated to the low level, for example, as shown in FIG. When the read / write signal RDWR # is supplied, the BTC 29
Reads data from the SDRAM 5.

At this time, the BTC 29 transfers the data with a data length uniquely determined by Table 1 according to the combination of the logic levels of the supplied burst transfer request signal BMREQ # and burst length designation signal BLEN8 #. .

That is, for example, FIG.
As shown in (f), the address strobe signal AS #
When the burst transfer request signal BMREQ # is at the low (L) level and the burst length designation signal BLEN8 # is at the low (L) level between the time T2 and the time T3 when As shown, SDR
Data is transferred from the AM 5 to the external bus master 17 in eight bursts. When a request for burst transfer is made by the external bus master 17 and the external bus control unit 28 is in a state where the request can be permitted, the external bus control unit 28 activates the low-level signal as shown in FIG. The burst transfer permission signal BMACK # is supplied to the external bus master 17.

Note that the CPU 20 is connected to the external bus master 17.
Therefore, when a request for burst transfer is made, the request is not canceled, so that the burst transfer permission signal BMACK # is always supplied to the external bus master 17. Since the logic level of the burst transfer request signal BMREQ # is referred to by the BTC 29 between the time T2 and the time T3 when the address strobe signal AS # is activated, as shown in FIG. During the period from T3 to the time when the burst transfer permission signal BMACK # is supplied to the external bus master 17, the logical level is arbitrary.

When reading data from the SDRAM 5, all bytes are read from the SDRAM 5 without selection, regardless of the logic level of the byte valid signals BE0 # -7 #.

As shown in FIG. 5 (h), the external bus control unit 28 sets the data read from the SDRAM 5 to the external bus master 17 via the general-purpose bus 15 at time T4 when it is ready to send the data. Along with the active data D, the activated low-level bus cycle end signal RD
YOUT # is supplied to the external bus master 17.

In the above, when data is transferred from SDRAM 5 to external bus master 17 in four bursts, the lower two bits of the address of the data are set to 0, and CPU 20 sequentially increments the lower two bits of the address. Thus, data is read from the SDRAM 5, and the 4-burst transfer is executed.

Similarly, when data is transferred by 8 bursts, the lower 3 bits of the address of the data are set to 0, and the CPU 20 reads data from the SDRAM 5 by sequentially incrementing the address of the lower 3 bits. , 8 burst transfer.

On the other hand, when the address strobe signal AS # is activated in the above, the burst transfer request signal BM
When REQ # is at a high (H) level and burst length designation signal BLEN8 # is also at a high (H) level, a single read operation of reading one data from SDRAM 5 is performed.

Next, the operation in the CPU 20, particularly the operation over the right to use the internal bus 33 will be described in detail. The following operations regarding the right to use the internal bus 33 are performed by the internal bus control unit 24 included in the data buffer unit 23, the DMA control unit 25, and the transmission control unit 29, respectively.
26 and 30. The general-purpose bus control unit 3
The access source determination unit 32 included in 1 will be described later.

With respect to the internal bus 33 shown in FIG.
The data buffer unit 23, the DMA control unit 25, and the transmission control unit 29 can operate as a bus master.
The DRAM control unit 27 and the general-purpose bus control unit 31 operate as a bus slave. The state of the internal bus 33 is composed of three phases: an arbitration phase, an access request phase, and a data transfer phase. Here, the bus master is determined in the arbitration phase, and the state transits to the access request phase and the data transfer phase. After the access request phase, the data transfer phase is always performed.

First, in the arbitration phase,
The data buffer unit 23 determines the right to use the internal bus 33. At this time, the priority in using the internal bus 33 is in the data buffer unit 23. The determination of the right to use the internal bus 33, that is, arbitration, is performed by the internal bus control unit 2 included in the data buffer unit 23.
4 and the internal bus control unit 26 included in the DMA control unit 25.

In the data transfer on the internal bus 33,
Burst read and single write are basic, but D
The data read out by the MA control unit 25 via the SDRAM control unit 27 is again transferred to the S
Burst transfer is performed in an operation of writing to the DRAM 5 or a write request by the transmission control unit 29.

Next, regarding the above arbitration,
This will be described with reference to the waveform diagram of FIG. As shown in FIG. 6, the DMA control unit 25 from time T2 to time T4, and the data buffer unit 2 from time T4 to time T6.
3. The transmission control unit 29 operates as a bus master from time T6 to time T8, and the data buffer unit 23 operates after time T8.

Data buffer unit 23 and DMA control unit 25
Arbitration of the bus right is performed by the internal bus request signal BIREQ # shown in FIG. 6B and the internal bus acknowledge signal BIACK # shown in FIG. 6C.
The arbitration of the bus right between the data buffer unit 23 and the transmission control unit 29 is performed by using the internal bus use signal BIUSE # shown in FIG. 6D and the internal bus use signal shown in FIG. This is performed by the processor bus request signal BIPBR # and the internal bus release request signal BIREL # shown in FIG. The internal bus address strobe signal BIAS # shown in FIG. 6G is a signal indicating that the bus master issues an access request to the slave.

As shown in FIG. 6B, the DMA control unit 25 requests the data buffer unit 23 to use the internal bus by activating the internal bus request signal BIREQ #. Then, as shown in FIG. 6C, at time T1, the data buffer unit 23 activates the internal bus acknowledge signal BIACK # to low level, and permits the DMA control unit 25 to use the internal bus 33 ( In the figure). If it becomes necessary for the data buffer unit 23 to use the internal bus 33 while the DMA control unit 25 uses the internal bus 33, the internal buffer 33 is used at time T3 as shown in FIG. The bus acknowledge signal BIACK # is deactivated to a high level, and the internal bus processor bus request signal BIPBR # is activated as shown in FIG. Further, the DMA control unit 25 deactivates the internal bus request signal BIREQ # when the use of the internal bus 33 is finished (in the figure).

In the period from time T4 to time T6 when the internal buffer 33 is used, the data buffer unit 23 uses the internal bus use signal BIUS as shown in FIG.
E # is activated, and the internal bus processor bus request signal BIPBR # is deactivated as shown in FIG. 6 (e) (in the figure).

When data transmission is requested via the general-purpose bus 15, the transmission control unit 29 transmits the internal bus release request signal BIRE at time T 5 as shown in FIG.
Activate L # and request the data buffer unit 23 to release the internal bus 33. Then, the data buffer unit 23 responds to the activation of the internal bus release request signal BIREL #, as shown in FIG.
At the time when the use of No. 3 is completed, the internal bus use signal BIUSE # is deactivated (in the figure).

When it becomes necessary to use the internal bus 33, the data buffer unit 23 outputs an internal bus processor bus request signal as shown in FIG.
Activate BIPBR #, and the transmission control unit 29
At time T7 when the use of the internal bus release request signal BIREL # is deactivated as shown in FIG. 6 (f) (in the figure). Then, the data buffer unit 23 operates at time T after the internal bus release request signal BIREL # is deactivated.
At 8, the internal bus use signal BIUSE # is activated as shown in FIG. 6D, and the internal bus processor bus request signal BIPBR # is inactivated (FIG. 6D).

Next, control in the access request phase will be described with reference to a waveform diagram shown in FIG.
As shown in FIG. 7B, internal bus address strobe signal BI activated to a low level at time T1.
When the AS # is supplied from the bus master to the slave, an access request to the slave is made by the bus master. At this time, as shown in FIG. 7C, an address space specifying signal BI for specifying the address space of the access destination is provided.
ASI is supplied from the bus master to the slave.

The bus master inhibits the output of the address space specifying signal BIASI in phases other than the access request phase and in the access request phase when there is no access right in order to avoid contention in using the internal bus 33.

As shown in FIG. 7D, at time T1, the internal bus address signal BIADR is supplied from the bus master to the slave. The output of the internal bus address signal BIADR is also prohibited in phases other than the access request phase and in the access request phase when there is no access right in order to avoid contention in using the internal bus 33.

Also, at the same time T1, FIG.
As shown in (e), the internal bus read / write signal
BIRW is supplied from the bus master to the slave, and this signal notifies the slave that read access is performed when the signal is high and write access is performed when the signal is low. Accordingly, in the example shown in FIG. 7E, read access is instructed at time T1, write access is instructed at time T2, and read access is instructed at time T3.

At time T1, the internal bus block transfer signal BIBLK is supplied from the bus master to the slave, as shown in FIG. 7 (f). Sometimes the slave is notified that it is a single transfer.
Accordingly, in the example shown in FIG.
Indicates a block transfer, a single transfer at time T2, and a block transfer at time T3.

At time T1, an internal bus slave selection signal BISEL is supplied from the bus master to the slave as shown in FIG. 7 (g). When the access is at the low level, the slave is notified that the access is to the address area of the memory connected to the general-purpose bus 15. Therefore, in the example shown in FIG. 7 (g), at time T1, access to the memory connected to the general-purpose bus 15 is requested, and at time T2 and time T2.
3, the request for access to the SDRAM 5 is notified.

As shown in FIG. 7 (h), at time T1, the internal bus data type signal BIDTYPE is supplied from the slave to the general-purpose bus control unit 31. The size (effective bit width) of the data to be transmitted is notified. Then, as shown in FIG. 7 (i), at time T1, a bus width signal BIWIDTH is supplied from the slave to the general-purpose bus control unit 31, and this signal causes a bus specific to each resource connected to the general-purpose bus 15 to be transmitted. The width is notified.

Next, the control in the data transfer phase will be described with reference to the waveform diagrams shown in FIGS. Here, in FIG. 8 and FIG.
10 shows an operation when data is read from the memory cell. In FIG. 10, an operation for writing data to the SDRAM 5 is shown. 8 to 10, a case where the burst length is 4 is shown.

The internal bus 33 handles only data having a width of 64 bits. For an external interface of less than 64 bits, the SDRAM control unit 27 and the general-purpose bus control unit 31 respectively operate the bus width of the external interface. Perform data conversion according to.

As shown in FIGS. 8A and 8B, for example, in synchronization with the so-called rising edge of the external clock signal CLK, the signal S is output from time T1 to time T4.
Data signal BIDATA is read from DRAM 5. Although the data signal BIDATA is a signal for transferring data, the bus master avoids contention in the use of the internal bus 33. Therefore, the data signal BIDATA is used in an access request phase when there is no access right with a phase other than the access request phase. Inhibit BIDATA output.

At this time, as shown in FIG. 8C, the internal bus data enable signal BIDIEN is activated to a low level. This internal bus data enable signal BI
DIEN is a signal indicating that the read data is output to the internal bus 33 in the next cycle.
The M control unit 27 outputs the internal bus data enable signal BIDIEN at the same time as outputting the data to the internal bus 33.
To the transfer destination.

As shown in FIG. 8D, from time T1 to time T4, the internal bus write enable signals BIBE0-7 at low level or high level are supplied from the bus master to the SDRAM control unit 27. This signal indicates whether writing is permitted for each bit area (byte) when the data to be transferred is divided into eight bits from 0 to 63 bits. More specifically, writing is permitted for a byte corresponding to the internal bus write enable signal set to high level, and writing is prohibited for a byte corresponding to the internal bus write enable signal set to low level.

As shown in FIG. 8E, from time T1 to time T4, the internal bus abnormality detection signal BIMEXC # is at a low level or a high level, respectively. Here, the internal bus abnormality detection signal BIMEXC # is, for example, the address of the SDRAM 5 specified at the time of a load or store request from the external bus master 17.
This signal is activated when an error is detected when the address exceeds the address range held by the external bus master 17 or as a result of a parity check of the data requested to be loaded by the external bus master 17. Activated in units.

The waveform diagram shown in FIG.
The operation when the bus width of the M bus 13 is 64 bits will be described. The operation when the bus width of the SDRAM bus 13 is 32 bits is shown in FIG. That is, SDRAM
When the bus width of the bus 13 is set to 32 bits, FIG.
At time T1, T3, T5, T7, data is transferred, and the internal bus data enable signal BIDIEN, the internal bus write enable signal BIBE0-7, and the internal bus abnormality detection signal BIMEXC # are activated. You. That is, when the bus width of the SDRAM bus 13 is 32 bits, the data transfer rate is halved compared to when the bus width of the SDRAM bus 13 is 64 bits.

FIG. 10 shows an SDRAM as described above.
5, a single write is performed at time T1, and a burst write with a burst length of 4 is performed at time T2. First, as shown in FIG. 10B, at time T1, the internal bus address strobe signal BIAS # is activated to a low level, and the bus master issues an access request to the SDRAM control unit 27 operating as a slave. At the same time T1, as shown in FIG. 10C, a low-level internal bus block transfer signal BIBLK is supplied from the bus master to the SDRAM control unit 27, and single transfer of data is instructed.

At time T1, as shown in FIG. 10D, a low-level internal bus read / write signal BIRW is supplied to the SDRAM 5 to notify that it is a write access, and FIG. As shown,
One piece of data is supplied to the SDRAM 5 via the internal bus 33. Further, at time T1, a valid low-level or high-level internal bus write enable signal BIBE
0-7 are supplied to the SDRAM 5, and only the byte corresponding to the internal bus write enable signal which is set to the high level is in the SDR5.
It is written to AM5.

At time T2, the operation is the same as at time T1, but as shown in FIG. 10C, a high-level internal bus block transfer signal BIBLK is supplied from the bus master to the SDRAM control unit 27. , FIG.
As shown in (e), data is burst-transferred and SD
The data is written to the RAM 5.

The above is the description of the operation in the data transfer phase. Hereinafter, two specific examples of the operation of the CPU 20 over the internal bus 33 will be described. Here, the first specific example will be described with reference to the waveform diagram of FIG. The internal bus busy signal BIBSY shown in FIG.
# Is a signal indicating that an access request from the bus master is not accepted.

First, at time T1, as shown in FIGS. 11 (g) and 11 (j), the activated internal bus address strobe signal BIAS # and internal bus slave selection signal BISEL are transmitted from the data buffer unit 23 to the SDRAM. The data is supplied to the control unit 27, and access to the SDRAM 5 is requested. 11 (h) and 11 (i) at the same time.
As shown in FIG. 3, the high-level internal bus read / write signal BIRW and internal bus block transfer signal BIBLK
Since the data is supplied to the RAM control unit 27, a burst read is required. Then, the SDRAM control unit 27 operates at time T1.
The address is sequentially incremented according to the internal bus address signal BIADR shown in FIG. 11 (k) sent from the data buffer unit 23, and the data read from the SDRAM 5 as shown in FIG. 11 (l). Is transferred to the data buffer unit 23 by four bursts.

Further, as shown in FIG.
When the activated internal bus request signal BIREQ # is supplied from the MA control unit 25 to the data buffer unit 23 and the use of the internal bus 33 is requested (in the figure), the transfer operation to the data buffer unit 23 is performed. When performed, FIG. 1
As shown in FIG. 1 (m), the inactive internal bus busy signal BIBSY # is supplied from the SDRAM control unit 27 to the data buffer unit 23. Then, as shown in FIG. 11C, in response to the signal, the data buffer unit 23 converts the activated internal bus acknowledge signal BIACK # into a DMA signal.
This is supplied to the control unit 25 to notify the permission of use of the internal bus 33. In addition, as shown in FIG. 11D, the data buffer unit 23 simultaneously inactivates the internal bus use signal BIUSE # (in the figure).

As described above, at time T2, the master module operating as a bus master for internal bus 33 transmits data from DMA buffer 25 to DMA controller 25.
To replace

Then, at time T3, as shown in FIGS. 11 (g) and 11 (j), the activated internal bus address strobe signal BIAS # and the deactivated internal bus slave selection signal BISEL are The access from the DMA control unit 25 to the general-purpose bus control unit 31 to the memory connected to the general-purpose bus 15 is requested. At the same time,
As shown in FIGS. 11H and 11I, since the high-level internal bus read / write signal BIRW and internal bus block transfer signal BIBLK are supplied to the general-purpose bus control unit 31, a burst read is requested. Is done.

Then, as shown in FIG. 11 (k),
The general-purpose bus control unit 31 sequentially increments the address according to the internal bus address signal BIADR sent from the DMA control unit 25 at time T3, and is connected to the general-purpose bus 15 as shown in FIG. The data read from the memory is transferred to the DMA controller 25 by four bursts.

As shown in FIG. 11E, when the activated internal bus processor bus request signal BIPBR # is output from the data buffer unit 23,
When the above-described transfer operation to the DMA control unit 25 is performed, the internal bus busy signal BIBSY # deactivated from the general-purpose bus control unit 31 is transmitted to the DMA control unit 25 and the data buffer unit as shown in FIG. 23. Then, as shown in FIG.
The control unit 25 controls the inactivated internal bus request signal.
BIREQ # is supplied to the data buffer unit 23 (in the figure).

Then, the data buffer unit 23
As shown in (d) and FIG. 11 (e), the internal bus use signal BIUSE # is activated and the internal bus processor bus request signal BIPBR # is deactivated (in the figure).
Thus, at time T4, the master module
The A control unit 25 replaces the data buffer unit.

Then, at time T5, as shown in FIGS. 11 (g) and 11 (j), the activated internal bus address strobe signal BIAS # and the internal bus slave selection signal BISEL are sent from the data buffer unit 23. SDRA
It is supplied to the M control unit 27, and an access to the SDRAM 5 is requested. At the same time, FIG.
As shown in (i), a low-level internal bus read / write signal BIRW and an internal bus block transfer signal BIBLK
Is supplied to the SDRAM control unit 27, so that a single write is required. Then, the SDRAM control unit 27
FIG. 11 transmitted from the data buffer unit 23 at time T5
In response to the internal bus address signal BIADR shown in (k), one data shown in FIG. 11 (l) supplied at the same time T5 is written to the SDRAM 5.

The above is the description of the CPU 20 with respect to the internal bus 33.
Is a first specific example of the operation of the following, in the following,
A second specific example will be described with reference to the waveform diagram of FIG.

First, at time T1, as shown in FIGS. 12 (h) and 12 (k), the activated internal bus address strobe signal BIAS # and the internal bus slave selection signal BISEL are transmitted from the data buffer unit 23 to the SDRAM. The data is supplied to the control unit 27, and access to the SDRAM 5 is requested. At the same time, FIGS. 12 (i) and 12 (j)
As shown in FIG. 3, the high-level internal bus read / write signal BIRW and internal bus block transfer signal BIBLK
Since the data is supplied to the RAM control unit 27, a burst read is required. Then, the SDRAM control unit 27 operates at time T1.
The address is sequentially incremented in response to the internal bus address signal BIADR shown in FIG. 12 (l) sent from the data buffer unit 23, and the data read from the SDRAM 5 as shown in FIG. Is transferred to the data buffer unit 23 by four bursts.

Further, as shown in FIG. 12 (g), the internal bus release request signal BI
REL # is supplied to the data buffer unit 23 and the internal bus 3
3 is requested, the data buffer unit 23
12 (n), the inactive internal bus busy signal BIBSY # is supplied from the SDRAM control unit 27 to the data buffer unit 23 as shown in FIG. Then, as shown in FIG. 12E, the data buffer unit 23 inactivates the internal bus use signal BIUSE # (in the figure).

In this way, as shown in FIG. 12B, the master module operating as a bus master for the internal bus 33 replaces the transmission control unit 29 from the data buffer unit 23 at time T2.

Then, at time T3, as shown in FIGS. 12 (h) and 12 (k), the activated internal bus address strobe signal BIAS # and the deactivated internal bus slave selection signal BISEL are The signal is supplied from the transmission control unit 29 to the general-purpose bus control unit 31 (shown in the figure).
Access to the memory connected to 5 is required. At the same time, as shown in FIGS. 12 (i) and 12 (j), the high-level internal bus read / write signal BIRW and internal bus block transfer signal BIBLK are supplied to the general-purpose bus controller 31.
, A burst read is required.

Then, as shown in FIG.
The general-purpose bus control unit 31 sequentially increments the address according to the internal bus address signal BIADR transmitted from the transmission control unit 29 at time T3, and is connected to the general-purpose bus 15 as shown in FIG. The data read from the memory is transferred to the transmission control unit 29 by four bursts.

At time T4, internal bus release request signal BIRE activated as shown in FIG.
When L # is output from the transmission control unit 29 to the data buffer unit 23 (in the figure), when the above-described transfer operation to the transmission control unit 29 is performed, the next operation by the transmission control unit 29 starts.

At time T5, as shown in FIGS. 12 (h) and 12 (k), the activated internal bus address strobe signal BIAS # and the internal bus slave selection signal BISEL are transmitted from the transmission control unit 29 to the transmission control unit 29. The data is supplied to the SDRAM control unit 27, and an access to the SDRAM 5 is requested. At the same time, as shown in FIGS. 12 (i) and 12 (j), the internal bus read / write signal BIRW at low level and the internal bus block transfer signal BI at high level
Since BLK is supplied to the SDRAM control unit 27, a burst write is required. Then, the SDRAM control unit 27
FIG. 12 transmitted from the transmission control unit 29 at time T5
In response to the internal bus address signal BIADR shown in (l), the burst data shown in FIG. 12 (m) supplied from the same time T5 is written to the SDRAM 5.

The above is the description of the CPU 20 with respect to the internal bus 33.
In the operation processing system according to the first embodiment as described above, in the bus grant state in which the external bus master 17 has started using the general-purpose bus 15, the general-purpose bus 15 It may be logically separated from the CPU 20. That is, in this case, the access source determination unit 32 included in the general-purpose bus control unit 31 determines the access request source, and when it is determined that the access request has been made from the data buffer unit 23,
An internal bus busy signal BIBSY # is issued to the data buffer unit 23 to notify that the access request cannot be satisfied.

As a result, the data buffer unit 23 suspends access to the general-purpose bus control unit 31 and performs only access to the SDRAM control unit 27 via the path 35. Further, the external bus master 17 communicates with the general-purpose bus 1 via the path 36.
ROM 5 or RAM 9 or I / O 1 connected to
Access 1

Therefore, when the external bus master 17
ROM 5 or RAM 9 or I / O 1 connected to
When the use of the general-purpose bus 15 is started to access the general-purpose bus 15, the general-purpose bus 15 is logically separated from the CPU 20 as described above, so that the external bus master 17 can use the general-purpose bus 15 while using the general-purpose bus 15. Even if there is, the access from the bus master in the CPU 20 to the SDRAM control unit 27 can be performed independently of the operation of the external bus master 17.

As described above, according to the arithmetic processing system according to the first embodiment, the operation of the arithmetic processing system is speeded up by providing the CPU 20 having the bus transmission function and realizing high-speed arithmetic processing. The size and cost of the system can be reduced. [Second Embodiment] FIG. 14 shows a structure of a main part in a central processing unit (CPU) according to a second embodiment of the present invention. As shown in FIG. 14, CPU 40 according to the second embodiment has the same configuration as CPU 20 according to the first embodiment shown in FIG.
7 is further provided.

Here, the PLL circuit 37 doubles the external clock signal CLK supplied to the external clock signal (CLK) input terminal 34 to generate an internal clock signal (int.CLK).
And the SDRAM control unit 39 and the external bus control unit 4
4 and generates an external clock valid signal, which will be described later, to generate an input / output register 41 included in the transmission control unit 43.
Supply to The exchange of data between the SDRAM 5 and the internal bus 33 is performed via a buffer 38 included in the SDRAM control unit 39.

Hereinafter, the CPU 4 shown in FIG.
0 when the frequency of the external clock signal CLK is 50 M
The case of Hz will be described as an example with reference to the waveform diagram of FIG. As shown in FIG.
An external clock signal CLK having a frequency of 50 MHz shown in FIG. Then, the external clock signal C
LK is doubled by the PLL circuit 37, and FIG.
An internal clock signal int.CLK having a frequency of 100 MHz shown in (b) is generated. The internal clock signal i
Due to the frequency of nt.CLK, the operating frequency of the CPU 40 becomes 10
0 MHz.

At this time, SDRAM bus 13 operates at 100 MHz which is the same as the frequency of internal clock signal int.CLK. On the other hand, the operating frequency of the general-purpose bus 15 operates at 50 MHz, which is the same as the frequency of the external clock signal CLK.

As described above, PLL circuit 37 multiplies input external clock signal CLK by a specified clock speed (twice in this case) to generate internal clock signal int. Shown in FIG. 15B. CLK, and at time T
An external clock valid signal shown in FIG. 15C showing the so-called rising timing of the external clock signal CLK from 1 to time T4 or the like is generated and supplied to the input / output register 41.

Here, the data read from the SDRAM 5 and supplied to the external bus control unit 44 via the internal bus 33 is temporarily held in a buffer 42 included in the transmission control unit 43, and triggers an external clock valid signal. To the input / output register 41 which operates as Therefore, even when the operating frequency in the CPU 40 is different from the frequency of the external clock signal CLK, the data is supplied to the external bus master 17 via the general-purpose bus 15 as data synchronized with the external clock signal CLK.

On the other hand, the data to be written to the SDRAM 5 is held in the input / output register 41 after being sent from the external bus master 17. Thereafter, the data is stored in the buffer 42 in the transmission control unit 43, and writing to the SDRAM 5 is performed.

The general-purpose bus 15 can have a bus width of 8, 16, 32, or 64 bits depending on the type of device to be connected, and the bus width is variable.
The bus width of the internal bus 33 in 40 is set to 64 bits, and is a fixed value. Therefore, when the bus width of the internal bus 33 is different from that of the general-purpose bus 15, the data is stored in the buffer 42 included in the transmission control unit 43, and the stored data is divided and transferred on the general-purpose bus 15. You.

As described above, the CPU 4 according to the second embodiment
According to 0, even when the frequency of the external clock signal CLK is different from the operating frequency or the bus width of the internal bus 33 and the general-purpose bus 15 is different, the CPU 20 according to the first embodiment shown in FIG. The same effect as described above can be obtained.

In the description of the first and second embodiments, the arithmetic processing system using the SDRAM 5 capable of reading and writing data at a high speed has been described. Data rate (DDR) SDRAM or Rambus D
It goes without saying that the present invention can be similarly applied to an arithmetic processing system using a RAM or the like.

[0113]

As described above, according to the present invention, it is possible to avoid access conflicts that occur when a plurality of external data processing means access the storage means.

Also, since it is not necessary for each external data processing means to have means for accessing the storage means,
The system can be constructed at low cost.

Further, according to the present invention, since the transmission path connected to the storage means is simple, data can be input / output to / from the storage means more quickly than in the case of a complicated transmission path. Can be speeded up.

Further, since the access to the storage means by the data processing device itself can be controlled independently of the operation of the external data processing means, the efficiency of data processing by parallel processing can be realized.

Further, the efficiency of data processing can be improved and the reliability of operation can be obtained.

Also, since data transfer according to the specifications of the storage means and the external data processing means can be realized, the degree of freedom in system design, that is, the versatility can be increased.

Further, it is possible to avoid contention of the access which occurs when the first and second data processing means access the storage means, and to directly access the storage means from the second data processing means. Since a circuit for accessing the memory unit is unnecessary, the speed of access to the storage unit can be increased, and the scale and cost of the data processing system can be reduced.

Finally, means for solving the problem of the present invention will be additionally described. (1) A data processing device for exchanging data with a storage unit connected to a first bus for storing data and an external data processing unit connected to a second bus for processing data, A data processing apparatus, comprising: an access control unit that accesses a storage unit in response to a request from the processing unit. (2) The access control means includes read data storage means for storing data read from the storage means, and performs external data processing on the data stored in the read data storage means in accordance with the bus width of the second bus. The data processing device according to (1), which supplies the data to the means. (3) A data processing method for exchanging data between a storage means connected to the first bus for storing data and an external data processing means connected to the second bus for processing data, the method comprising: A data processing method comprising accessing a storage unit in response to a request from the processing unit. (4) The data read from the storage means is stored in the read data storage means, and the data stored in the read data storage means is supplied to the external data processing means according to the bus width of the second bus (3) ).

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a conventional arithmetic processing system.

FIG. 2 is a diagram showing a configuration of an arithmetic processing system according to the first embodiment of the present invention.

FIG. 3 is a first waveform diagram illustrating an operation of the arithmetic processing system shown in FIG. 2;

FIG. 4 is a second waveform diagram illustrating an operation of the arithmetic processing system shown in FIG. 2;

FIG. 5 is a third waveform diagram for explaining the operation of the arithmetic processing system shown in FIG. 2;

FIG. 6 is a first waveform chart showing an operation of the central processing unit shown in FIG. 2;

FIG. 7 is a second waveform diagram showing an operation of the central processing unit shown in FIG. 2;

FIG. 8 is a third waveform diagram showing an operation of the central processing unit shown in FIG. 2;

FIG. 9 is a fourth waveform diagram showing an operation of the central processing unit shown in FIG. 2;

FIG. 10 is a fifth waveform chart showing an operation of the central processing unit shown in FIG. 2;

11 is a first waveform diagram showing a specific example of the operation of the central processing unit shown in FIG.

12 is a second waveform diagram showing a specific example of the operation of the central processing unit shown in FIG.

FIG. 13 is a diagram illustrating the operation of the arithmetic processing system shown in FIG. 2;

FIG. 14 is a diagram showing a configuration of a main part in a central processing unit according to Embodiment 2 of the present invention.

15 is a waveform chart illustrating an operation of the central processing unit shown in FIG.

[Explanation of symbols]

1 First Central Processing Unit (CPU) 3 Second Central Processing Unit (CPU) 5 Synchronous Dynamic Random Access Memory (SD
RAM) 7 Read-only memory (ROM) 9 Random access memory (RAM) 11 I / O buffer (I / O) 13 SDRAM bus 15 General-purpose bus 17 External bus master 20, 40 Central processing unit 21 CPU core 23 Data buffer unit (DBUF) ) 24, 26, 30 Internal bus control unit 25 DMA (Direct Memory Access) control unit (DMA
C) 27, 39 SDRAM control unit 28, 44 External bus control unit 29, 43 Transmission control unit (BTC) 31 General-purpose bus control unit 32 Access source determination unit 33, 45, 46 Internal bus 34 External clock signal (CLK) input terminal 35, 36 path 37 PLL circuit 38, 42 buffer 41 input / output register

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasushi Yasuno 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu Limited (Reference) 5B060 CD15 MB03 MM03

Claims (10)

[Claims] 1. A data processing device for exchanging data with a storage means connected to a first bus for storing data and an external data processing means connected to a second bus for processing data, A data processing apparatus comprising: an access control unit that accesses the storage unit in response to a request from the external data processing unit. 2. The access control means supplies the data read from the storage means by the access to the external data processing means via the second bus.
2. The data processing apparatus according to claim 1, wherein said data supplied from said external data processing means via said second bus is written into said accessed storage means. 3. The external data processing means includes a bus right granting means for granting preferential use of the second bus in response to a request from the external data processing means. On the other hand, when the priority use is permitted, it is possible to access the storage unit via the first bus except when an access request to the storage unit is made by the external data processing unit. The data processing device according to claim 1. 4. If the request is made by the external data processing means when externally accessing the external data processing means or the storage means, any one of the external access and the request is executed with priority. 2. The data processing device according to claim 1, further comprising an arbitration unit that determines whether the data processing is performed. 5. The data processing apparatus according to claim 1, wherein said access control means makes a transfer rate of said data on said first bus different from a transfer rate of said data on said second bus. . 6. A data processing method for exchanging data with storage means connected to a first bus and storing data, and external data processing means connected to a second bus and processing data. A data processing method comprising accessing the storage means in response to a request from the external data processing means. 7. The data read from the storage means by the access is supplied to the external data processing means via the second bus, or the external data processing means supplies the data to the second bus. 7. The data processing method according to claim 6, wherein the data supplied via the storage unit is written into the storage unit accessed. 8. When the priority use of the second bus is granted in response to a request from the external data processing means, except when an access request to the storage means is made by the external data processing means. 7. The data processing method according to claim 6, wherein said storage means can be accessed via said first bus. 9. The data processing method according to claim 6, wherein a transfer rate of said data on said first bus is different from a transfer rate of said data on said second bus. 10. A data processing system comprising: storage means connected to a first bus for storing data; and second data processing means connected to a second bus for processing data. Connected to the second bus, accessing the storage means in response to a request from the second data processing means, and transferring the data obtained by the access to the second data via the second bus. A first data processing unit for supplying the data to the processing unit or writing the data supplied by the second data processing unit via the second bus to the storage unit to which the access has been made; A data processing system characterized by the following.