JPS6054065A - Synchronous controller - Google Patents

Abstract

PURPOSE:To request the access without deciding whether a memory device is already operated or not with a micro instruction, by preventing the generation of a wasteful latency time when the memory device whose access time is not constant is accessed. CONSTITUTION:A latency control signal 17 and an operating indication signal 18 are outputted by an access contol 302 in a buffer storage 4 or an access control 303 in a main storage 5. That is, the access control 302 sets the signal 17 to logical ''1'' if data cannot be read out from a high-speed memory 102 in the buffer 4, and the access control 302 sets the signal 17 to logical ''0'' if data can be read. The access control 303 sets the signal 17 to logical ''1'' during the reference time of a low-speed memory 103 and sets the signal 18 to logical ''1'' when the main storage 5 is operated. AND between this signal 18 and an access start field value is operated by an AND gate, and OR between the signal 17 and this AND is operated by an OR gate to generate a latency signal. Thus, the generation of a wasteful queuing time is prevented, and the access is requested without deciding whether the memory device is already operated or not with a micro instruction in a basic processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprogram control type information processing device, and more particularly to a synchronization control device for a basic processing device and a memory device in the information processing device.

[Background of the invention]

A conventional information processing device referred to a memory with a configuration as shown in FIG. The basic processing unit 1 sets a reference address on the address bus 2 and activates the access using the activation signal 3. The buffer memory 4 uses a hit judgment 101 to determine whether data at a designated address exists in the buffer memory, and if the data exists, the data is read out from the high speed memory 102. The signal line 6 notifies the main memory 5 that the data does not exist, and reads the data from the low-speed memory 103. The read data is sent to the basic processing unit 1 via the data bus 7. The synchronization signal 8 is for notifying that data has been established on the data bus 7. In a 4-hour information processing device including such a buffer storage 4, data may be read from a high-speed memory or from a low-speed memory. Therefore, it is necessary to extend the timing clock inside the basic processing device 1 by an appropriate amount of time according to the data reference time. FIG. 2 shows this situation. TMO, TMI, TM2 and TM3 are basic clocks inside the basic processing unit 1. This example shows a case where TM3 is extended when the data reference time is long. It takes one machine cycle to switch from TMO to TM3. Main memory address is time T O
When access activation 3 is output at T1, T
Step 2 confirms the data. This is a case where no data exists in the buffer memory 4 and data is read from the main memory 5. When the data is determined at T2, the synchronization signal 8 is set at T3. Seeing this, the extended basic clock TM3 is reset (time T4).

At this timing, the data on the data bus 7 is input to the internal register. At the same time, access activation 3 is reset. FIG. 2 shows the case of continuous reference. At time T4, the next address is set, and at III5, access activation 3 is set. At this time, the synchronization signal 8 is reset. This access indicates a case where data exists in the buffer memory 4. When the data is determined at time T6, a synchronizing signal 8t- is set at time T7. The rest is the same as last time.

In this way, in the conventional method, even if the data is determined at T2 or T6, the data is taken into the internal register at T4.
'! , or T8, resulting in wasted time.

[Purpose of the invention]

An object of the present invention is to prevent wasted waiting time from occurring when accessing a memory device whose access time is not constant, so that a microinstruction must determine whether the memory device is already in operation or not. The main reason for this is that there is no provision of a synchronous control circuit that can issue access requests without requesting access.

[Summary of the invention]

In the present invention, the memory device does not return a response when the access time is the fastest, returns a response signal only when it cannot respond with the fastest access time for some reason, and extends the basic clock inside the basic processing unit. A feature of the present invention is that even when the memory device cannot be accessed due to data transfer with an input/output device, the microprogram automatically extends the set of access activation signals without being aware of this.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 3 shows a schematic configuration of the present invention. Conventional synchronization signal 8
In contrast, the waiting control signal 17 and the in-operation display signal 18 are used as response signals.

The wait control signal 17 and the in-operation display signal 18 are outputted by the access control 302 in the buffer memory 4 or the access control 303 in the main memory 5.

Access control 302 accesses high speed memory 1 in buffer storage 4
When data cannot be read from the high-speed memory 102, the wait control 1h number 17 is set to logic "I I+" during the reference time for outputting data from the main memory 5. When data can be read from the high-speed memory 102, it is set to logic "0". Also, while the buffer memory 4 is operating, the in-operation display signal 18 is set to logic "1".The access control 303 sets the wait control signal 17 to logic "1" during the reference time of the low-speed memory 103 of the main memory 5. 1". Also, while the main memory 5 is operating, the operating display signal 18 is set to logic "".
Set it to 1”.

The synchronization control circuit 301 in the basic processing unit 1 starts memory access based on the access activation signal 3, and waits for the wait control signal 1.
7. When receiving the operating display signal 18, Mi controls the basic tally within the processing device 1.

FIG. 4 shows details of the synchronous control circuit 301.

Control memory 9 stores microprograms. The microinstruction read from control memory 9 is set in microinstruction register 10. This microinstruction has an access activation field 11, and this bit is logic ``11''.
The clock control circuit 12 outputs a three-phase basic clock.The clock control circuit 12 may be a circuit as shown in FIG. 5, for example.When the wait signal 13 is a logic TMO when it is 0”.

Each basic clock of TMI and 'I'M'2 is output repeatedly. When the wait signal 13 becomes logic "1", TM2 is extended with logic "1".
stores the value of the access activation field 11, performs a logical AND operation with the inversion of the basic clock TMO by the AND gate 15, and outputs the result as the activation signal 3. A wait control signal 17 and an operating indicator 4H"r18 are returned from the memory device. When starting an access, the memory address register 1 is sent back.
An address is set in 9 and output to address bus 2. Data read from main memory 5 or buffer memory 4 is set in memory data register 22 via data bus 7. FIG. 6 shows the time relationship of these signals. In FIG. 6, the address to be read is set on the address bus 2 at time TO, and the activation signal 3 is set at time Tl. Buffer memory 4 hit judgment 10
1 determines whether or not the requested data exists in the high-speed memory 102, and if it does not exist, it is notified to the p main memory 5 through the signal line 6. This example shows a case where data does not exist in the high speed memory 102. Therefore, the wait control signal 17 is set at time T2. Seeing this, the clock control circuit 12 basically extends TM2. When the data is established on the data bus 7 (time T3), the wait control signal 17 is reset.

Thereby, the extension of the basic clock TM2 is stopped at the timing of pT4, and the normal cycle returns. At this time, the memory data register 22 takes in the data.

Figure 6 shows the case of continuous access.
The third time shows a case where data exists in the high-speed memory 102 in the buffer storage 4.

At time T4, set the next address to address bus 2,
Start signal 3 is set at time T5. Since data exists in the high-speed memory 102 this time, the hit determination 101 does not set the wait control signal 17. Then, since the clock control circuit 12 does not extend the basic clock TM2, the cycle ends in a normal cycle. Therefore, data is taken into the memory data register 22 at time T6.

As described above, according to the present invention, there is almost no wasted time and access can be made without having to change accesses.

In addition, logic ``1'' is added when the memory device is active and the base processing unit should not initiate access from the memory device.
The AND gate 23 performs a logical product of the in-operation display signal 18 and the value of the access activation field 11, and the OR gate 24 performs a logical OR with the wait control signal 17 to obtain the wait signal 1.
3, the basic processing unit can issue a memory access request without determining whether the memory device is in operation.

The wait signal 13 becomes logic "1" when the basic processing unit attempts to issue an access request during memory operation.

Therefore, the basic clock TM2 is extended. Waiting signal 1
3 becomes logic "O" when the operating display signal 1B becomes logic "0"
``When the extension of the basic clock TM2 is stopped and the normal cycle is resumed, the value of the access activation field 11 is set in the flip-flop 14, and the memory access that has been awaited is executed.

In this way, a microinstruction that initiates a memory access can request a memory access without having to determine the state of the memory device.

〔Effect of the invention〕

According to the present invention, data can be read without unnecessary waiting time even when the access time of a memory device is not constant.

Furthermore, a microinstruction that issues a memory access request can issue an access request without being aware of whether the memory device is already in operation or dead.

[Brief explanation of the drawing]

Fig. 1 is an outline of the entire information processing system, Fig. 2 is a timing chart of a conventional example, Fig. 3 is a schematic configuration of the present invention, Fig. 4 is a synchronization control circuit, the fifth area is a clock control circuit, and the sixth
The figure shows a timing chart.

Claims (1)

[Claims] 1. Consisting of a basic processing device that performs information processing, a main storage device through which the basic processing device accesses data, and a buffer storage device provided to speed up data access time. In the information processing device, if the data requested by the basic processing device exists in the buffer storage device and can be read within a specified time, the logic 60 is ``Yes''; otherwise, the logic is ``60'' for the time necessary for access. 1", and an internal basic clock control circuit controlled by the wait control signal. 2. In the synchronous control device, the buffer storage device or the main Internal basic clock control controlled by the output of a logic circuit that combines an in-operation display signal that becomes logic "1" when the storage device is in operation and an access request signal inside the basic processing unit. % that the circuit was installed
The synchronous control device of item 1, which is characterized by: