JPH09153009A - Arbitration method for hierarchical constitution bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to give a device on a bus of low order the same right to use a bus of high order as a device on the bus of high order by providing the arbitration means of the bus of high order a means which sets connection information on the bus of low order and information regarding the priority of arbitration. SOLUTION: A system which has a secondary PCI bus connected to a primary PCI bus 111 through a PCI bus bridge is provided with registers 201 and 202 for determining whether or not the secondary PCI bus is connected and the priority of arbitration of a device on the secondary PCI bus in an arbitrator 103 which arbitrates the primary PCI bus 111. Then an arbitration circuit 205 performs arbitration according to the set priority by referring to the contents of the control registers 201 and priority register 202 when there is a request for the right to use the PIC bus 111 from the device on the primary or secondary PCI bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration method suitable for a small information processing device such as a personal computer or a workstation.

[0002]

2. Description of the Related Art Generally, I / O of a personal computer
O-bus is a high-speed data transfer from a CPU bus, host bus, or system bus via a bus bridge.
It is hierarchically connected to an I / O bus, a medium speed I / O bus, and a low speed I / O bus via a bus bridge. However, in recent years, due to the expansion of the number of slots in the high-speed I / O bus, etc., a configuration method has emerged in which an I / O bus having the same data transfer rate and bus protocol is connected to the high-speed I / O bus via a bus bridge. It was In this method, since the lower I / O bus connected via the bus bridge has the same bus protocol as the upper I / O bus, the upper I / O is apparently used.
It looks like the bus has been expanded.

As described above, the I / O bus having the same protocol can be expanded through the bus bridge. A PCI Special Interest Group which is an industry group in the US
Known as the PCI local bus (hereinafter abbreviated as PCI bus), the specifications of which are formulated and published.

FIG. 3 shows a primary PCI bus and a secondary P bus.
PCI with CI bus connected via PCI to PCI bus bridge
1 shows a block diagram of a conventional system with a bus. Primary PCI bus 111 is host bus / PCI bus bridge 102
Is connected to the host bus 101 via. Primary P
Multiple PCI devices are connected to the CI bus 111,
Each PCI device has an arbitration signal for acquiring the bus use right of the PCI bus, and is connected to the primary PCI bus arbiter 103.

For example, the PCI device 104 is a primary PCI
A request signal REQ_1a123 is output in order to acquire the bus use right of the bus 111 (hereinafter abbreviated as bus right). The primary PCI bus arbiter 103 permits the PCI device 104 to use the primary PCI bus 111 by performing arbitration of the bus right request signal transmitted from each PCI device and then outputting the bus use permission signal ACK_1a124. . Request signals for other PCI devices
In order to perform handshake of the bus use permission signal, a signal required for handshake is defined for each device and each slot in the PCI bus, and an arbiter for arbitrating the bus right exists for each PCI bus.

In FIG. 3, the PCI slot 107 and the PCI slot 108 are respectively REQ_1b125, ACK_1b126, and R as signals of the bus right arbitration handshake.
EQ_1c127 and ACK_1c128 are connected between the primary PCI bus arbiter 103. In addition, a signal for requesting the bus right of the primary PCI bus 111 from the host bus 101 side, Ho
st_REQ121 and Host_ACK122 are connected to the host bus / PCI bus bridge 102. Here, the secondary PCI bus 112 is connected to the primary PCI bus 111 via the secondary PCI bus bridge 105. The secondary PCI bus bridge 105 has a function of electrically buffering the bus signal of the primary PCI bus 111 and buffering the same bus protocol as that of the primary PCI bus 111. The bus right request signal of each PCI device on the secondary PCI bus 112 is input to the secondary PCI bus bridge 105, the secondary PCI bus bridge 105 performs the bus right arbitration in the secondary PCI bus, and further, the primary PC
When requesting the bus right of the I bus 111, the bus right request signal REQ_2nd129 and ACK_2nd1 which is the bus use permission signal
At 30, a handshake of the bus right arbitration is performed with the primary PCI bus arbiter 103.

Next, FIG. 7 shows a conventional operation example of the primary PCI bus arbiter 103 shown in FIG. When there is no master using the PCI bus, the PCI bus arbiter 103 is in the bus idle state 170, and when each PCI device requests the bus right at the same time, the primary PCI bus arbiter 103 becomes the device on the primary PCI bus. To give the bus right, one of the bus use permission signals, ACK_1a, is output (171). In addition, the PCI bus arbiter in turn grants bus rights to devices on the primary PCI bus (172,173,174),
When the bus right reaches all PCI devices including the secondary PCI bus bridge 105, it makes a round and goes back to the primary PC.
Give bus right to I device.

As described above, the primary PCI bus arbiter 1
03 is the secondary PCI bus bridge 105 is the primary PCI
If you have 111 connections on the bus, set this to the primary P
Bus arbitration is performed assuming that it is one of the PCI devices on the CI bus 111.

Further, all PCI devices have an I / O area called a PCI configuration space for describing information such as device attributes, and acquire information described in this PCI configuration space. By doing so, it is possible to obtain certain information about the device.

Regarding the PCI bus protocol, electrical specifications, and specific bus arbitration method that have been mentioned, "PCI SYSTEM ARCHITECTURE THIRD EDITION" issued by ADDISON-WESLEY PUBLISHING COMPANY in the United States (19
Published in February 1995). Below are the pages describing each technology.

-Specifications of the PCI bus, pages 39 to 76.

Arbitration of the PCI bus, pages 77 to 112.

· PCI bus configuration space
From page 327 to page 356.

• PCI to PCI bridge configuration, pages 375 to 452.

For more detailed specifications on the PCI bus, "PCI Local Bus Specification Revision 2.0" issued by the PCI Special Interest Group in the United States.
(Published April 30, 1993).

[0016]

The prior art has the following problems.

That is, in the conventional example shown in FIG. 3, the bus right request signal of each PCI device connected to the secondary PCI bus 112 is temporarily arbitrated by the secondary PCI bus bridge 105 in the secondary PCI bus 112. . As a result, when the device that has acquired the bus right of the secondary PCI bus 112 further requests the bus use right of the primary PCI bus 111, the secondary PCI bus bridge 105 outputs the bus right request signal REQ_2nd129 to the primary PCI bus arbiter 103. However, it is necessary to wait for the primary PCI bus arbiter 103 to output the bus right use permission signal ACK_2nd130 and to be given the bus right.

Here, the primary PCI bus arbiter 103
However, if the devices requesting the bus right of the primary PCI bus 111 are equally arbitrated, the PCI devices on the secondary CI bus 112 are
Compared to the PCI device on 11, the chance of obtaining the bus right of the primary PCI bus 111 is significantly reduced.

For example, three primary PCI buses 111
It is assumed that there are PCI devices, and there are three PCI devices on the secondary PCI bus 112, and each device outputs an access request to the host bus / PCI bus bridge. The PCI device on the primary PCI bus 111 inputs the bus right request signal directly to the primary PCI bus arbiter 103, while the PCI device on the secondary PCI bus receives the primary PCI bus arbiter 103 via the secondary PCI bus bridge 105. Request bus right. Therefore, if the three PCI devices on the primary PCI bus 111 acquire the bus right once, the secondary PC
The I-bus bridge 105 can also obtain the bus right once. Therefore,
While the PCI device on the primary PCI bus 111 acquires the bus right three times, the PCI device on the secondary PCI bus 112 needs the bus right arbitration in the secondary PCI bus 112, and thus the bus right is given only once. Cannot be acquired.

Thus, the secondary PCI bus 112 is connected to the secondary PCI bus 112 on the lower side via the secondary PCI bus bridge.
Since the PCI device has a significantly low chance of acquiring the access right to the primary PCI bus 111, it may not be able to operate normally depending on the type of the PCI device.

For example, by connecting a plurality of PCI devices including a LAN card to the secondary PCI bus,
When another PCI device is mounted on the bus 111, the following problems occur. LAN on secondary PCI bus 112
Since the card has a low probability of acquiring the bus right, the time interval between the operations for acquiring the bus right and performing the data transfer becomes several times as compared with the case where the same LAN card is mounted on the primary PCI bus 111. For this reason, if this LAN card does not have enough buffer on the card to temporarily store communication data, the contents of the buffer will be waited during the waiting time before getting the right to use the bus. There is a possibility that problems such as loss of communication data may occur due to overflow of data.

In this way, when a device requesting the right to use the upper I / O bus is mounted on the I / O bus extended to the lower side via the bus bridge, the bus right on the upper side is acquired. There is a problem that the opportunity is significantly lower than that of the device mounted on the upper bus.

An object of the present invention is an I / O bus system having a hierarchical structure extended via a bus bridge, and even for devices on an I / O bus extended to a lower side, an upper side I / O Higher-level I / O equivalent to the device attached to the O bus
It is to provide an improved arbitration method for granting bus usage rights.

Another object of the present invention is a system in which a plurality of PCI buses are hierarchically configured via bridges.
To provide an arbitration method capable of giving the right to use the lower and upper I / O buses at a timing suitable for each device according to the function of the PCI device connected to the bus and the lower PCI bus. is there.

Still another object of the present invention is to provide an optimum bus arbitration for PCI devices on the secondary PCI bus in a system having a primary PCI bus and a secondary PCI bus connected via a bus bridge. , PCI bus arbitration method and arbitration means.

[0026]

In order to achieve the object of the present invention, the arbitration means for performing the bus right arbitration of the upper side bus is provided with the connection information of the lower side bus and the information regarding the priority in the arbitration. Means were provided. Furthermore, when the arbitration means performs arbitration for the upper bus, it determines the bus arbitration rate based on the information about whether the lower bus is connected and the setting information about the arbitration order of the device connected to the lower bus. I decided to do it.

Specifically, in a system having a primary PCI bus and a secondary PCI bus connected via a PCI bus bridge, whether or not the secondary PCI bus is connected inside the arbiter that arbitrates the primary PCI bus, A register is provided to set the arbitration priority of the device on the secondary PCI bus. Also, the arbitration circuit inside the arbiter of the primary PCI bus refers to the setting value of the register for setting the priority when performing the arbitration of the bus right, and the device on the primary PCI bus and the device on the secondary PCI bus are referenced. I changed the ratio of giving the bus right to.

Further, the configuration information written in the PCI configuration space of the PCI device is read, and the register for setting the arbitration priority provided in the PCI bus arbiter is set.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an explanatory diagram of a PCI bus arbiter in a first embodiment of the present invention.

In FIG. 1, the primary PCI bus arbiter 10 is shown.
3 is the primary P by PCI bus interface 200
It is connected to the CI bus 111. The internal control register 201, the priority register 202, and the arbitration circuit 205 are connected to each other via an internal bus 207. When setting values in two registers, the PCI bus interface 200 Set from bus 111. For the specifications to map the registers to the I / O space of the PCI bus, refer to the PCI Bus Specification “PCI Local Bus Specif
ication Revision 2.0 "(PCI Special Interest Group
Since it was published in April 30, 1993), etc., it is omitted here.

The arbitration circuit 205 uses REQ / for inputting / outputting a bus right handshake signal from the PCI bus.
Bus right request signal Host_REQ121 and bus specification enable signal H from the host bus bridge via the ACK signal input / output port 206
Input / output of signals such as ost_ACK122, a bus right request signal REQ_2nd129, a bus use permission signal ACK_2nd130 and the like from the lower secondary PCI bus. Also, the primary PCI arbiter 1
The connection between 03 and the devices on the primary PCI bus and secondary PCI bus is shown in FIG. 3 described in the conventional example.
Since it is the same as the connection diagram of the PCI arbiter, its explanation is omitted here.

In FIG. 1, the arbitration circuit 205 is
Primary PCI bus 111 or secondary PC in Figure 3
When the PCI device on the I bus 112 requests the bus right of the PCI bus 111 through the REQ / ACK signal input / output port 206, the contents of the control register 201 and the priority register 202 are referred to and the two registers are registered. Arbitrate according to the set arbitration priority.

FIG. 2 further shows details of two registers inside the primary PCI arbiter 103.

FIG. 2A shows the bit configuration of the control register 201.

Bit 0: Host_REQ priority control (0 = fixed, 1 = rotation) This bit is a bit for controlling the priority of a signal for requesting the bus right of the primary PCI bus from the host bus 101 side in FIG. Yes, fixed priority and rotation can be set.

When fixed priority is set,
Arbitration is performed by setting the priority order set in the priority register 202 as an absolute priority order. On the other hand, when the rotation is set, the rotation order is determined and the arbitration is performed based on the priority setting of each bus right request signal which is also set in the priority register 202.

Bit 1: REQ_1 * priority control (0 = fixed, 1 = rotation) This bit collectively sets the arbitration priority (fixed priority / rotation) for the bus right handshake signal from each PCI device on the primary PCI bus 111. It is a bit to decide. The other parts are the same as bit 0 and will not be described.

Bit 2: PCI bus hierarchical structure (0 = with secondary PCI bus, 1 = without) This bit disables the secondary PCI bus 112 due to the presence or absence of the secondary PCI bus 112 or the disabling of the secondary PCI bus bridge 105. Set information such as conversion. When this bit is set to 2, the arbitration ratio information set in bit 3 becomes invalid.

Bits 3 and 4: Arbitration ratio (Primary bus: Secondary bus) This bit is used when the arbitration circuit 205 arbitrates a bus request from each PCI device.
The ratio of giving the bus right of the primary PCI bus to the PCI device on 11 and the PCI device on the secondary PCI bus 112 is set. According to the set value of this bit, the arbitration circuit 205 performs arbitration so that the PCI device on the secondary PCI bus 112 is appropriately given the opportunity to acquire the bus right.

Bits 5, 6 and 7 are unused reserved bits.

Next, (b) the bit configuration of the priority register 202 will be described.

Bit 0: host priority (0 =
Host_REQ> REQ_1 *, 1 = REQ_1 *> Host_REQ) This bit sets the arbitration priority order between the bus right request from the host bus 101 side and the PCI device on the primary PCI bus. This bit is set in the control register 20
The arbitration method of the arbitration circuit 205 is determined in combination with 1 bits 0 and 1.

Bits 1 and 2: Priority setting This register is a bit that determines the arbitration priority among the device on the primary PCI bus 111 in FIG. 3, the PCI device 104, the PCI slot 107, and the PCI slot 108.

The setting value of this bit is also combined with the setting values of bits 0 and 1 of the control register 201 to determine the arbitration method of the arbitration circuit 205.

Bits 3, 4, 5, 6, 7: Reserved bits that have not been used.

As for the devices on the primary PCI bus, the example of three devices has been described except the host bus / PCI bus bridge 102 and the secondary PCI bus bridge 105. However, when the number of PCI device connections is increased, this reserved bit is used. Allows you to set the arbitration priority for PCI devices except for the two bus bridges.

Next, referring to FIG. 4, the PC of the first embodiment
A first operation example of the I-bus arbiter will be described. When 03h is set in the control register 201 and 00h is set in the priority register 202 shown in FIG. 2, all bus right request signals are rotated (Host_REQ>REQ_1a>REQ_1b> RE).
Arbitration circuit 20 to arbitrate in Q_1c) and to give the bus right to the PCI device on the primary PCI bus 111 and the device on the secondary PCI bus 112 at a ratio of 1: 1.
5 works.

That is, the arbitration circuit shown in FIG.
A case where all the bus right request signals in FIG. 3 are output when 205 is in the bus idle state (147) will be described. The arbitration circuit 205 has a control register 201.
Then, based on the setting value of the priority register 202, first, the bus right is given to the host bus / PCI bus bridge 102 (140). After that, ACK_1a is output to give the bus right to the device on the primary PCI bus 111 (141). Further, in order to give the bus right to the device on the secondary PCI bus 112, the ACK_1nd signal is output after the output of ACK_1a is stopped. In this way, when the bus right is given to all the PCI devices while alternately giving the bus right to the device on the primary PCI bus and the PCI device on the secondary PCI bus (143, 144, 145, 146), the host bus / PCI bus goes round. Give bus right again to the bridge.

Regarding the timing of output stop and output of the bus use permission signal from the device currently using the bus to the device which gives the next bus right, the arbitration circuit 205 uses a timer or the like at an arbitrary timing. It may be performed, or the device currently using the bus may be switched when the output of the bus right request signal is stopped.

In this way, by alternately granting the bus use permission to the secondary PCI bus side and the primary PCI bus side, the PCI device attached to the lower side of the secondary PCI bus bridge is also on the primary PCI bus. PCI
Primary bus usage rights can be granted as often as devices. At this time, in the secondary PCI bus 112, the secondary PCI bus bridge 105 may similarly give the bus right to the devices on the secondary PCI bus 112 by rotation.

Next, FIG. 6 shows another operation example of the PCI bus arbiter of the first embodiment.

In the two register settings of the PCI bus arbiter described with reference to FIG. 4, bits 3 and 4 of the control register 201 are changed to 01 and set, and the arbitration ratio of the bus right is set to the PCI device on the primary PCI bus. For two times,
A case where the PCI device on the secondary PCI bus is set to be once will be described.

In FIG. 6, a case will be described in which the bus right requests are issued from all the PCI devices when the primary PCI bus arbiter 103 is in the bus idle state (170). The primary PCI bus arbiter 103 first outputs a Host_ACK signal according to the settings of the control register 201 and the priority register 202 to give the bus right to the host bus / PCI bus bridge (161). After granting the bus right to the device on the primary PCI bus 111 twice in succession (161, 162), the PC on the secondary PCI bus 112
The ACK_2nd signal is output to give the bus right to the I device (163).

Subsequently, the device on the primary PCI bus is twice (164, 165 and 167, 168) to the device on the secondary PCI bus (166, 169) once, to the host bus / PCI bus bridge. While giving the bus right,
It makes a round and returns to the bus idle (170) or the bus right (161) to the host bus / PCI bus bridge.

The bus right is arbitrated once per device on the secondary PCI bus with respect to twice on the primary PCI bus. By the way, by acquiring the configuration information of the PCI configuration space of the PCI device and setting the control register 201 and the priority register 202 based on this information, the PCI attached to the primary / secondary PCI bus Depending on the capabilities of the device
It becomes possible to provide an optimal arbitration method.

For example, a plurality of PCI-LAN cards may be mounted on the primary PCI bus, and a PCI-S card may be mounted on the secondary PCI bus.
When a CSI card is installed, the LAN card is
Since it is desirable that the waiting time until the bus right is acquired is shorter, the control register 201 and the priority register 202 are set so that the PCI device on the primary PCI bus is given priority to the PCI device. It is possible to provide a bus arbitration method.

Such reading of device information from the PCI configuration space may be performed by a BIOS supporting the PCI bus, or by the system user using a tool program at arbitrary timing. Is also good.

As described above, the arbitration method according to the first embodiment has been described with reference to the drawings. Regarding the operation when the maximum number of PCI devices are not mounted on each of the primary PCI bus and the secondary PCI bus, ,
Although not described in the figure, a bus right request signal to which no PCI device is attached is never output.
Therefore, when the PCI device is not mounted on the primary PCI bus and the secondary PCI bus, the corresponding arbitration is skipped by the arbitration operation shown in FIGS. 4 and 6, and the bus right is given to the next PCI device. Passed.

Further, the above description is all about the case where the bus right arbitration is performed by the rotation method. When fixed priority is set, the priority set in the priority register is used as an absolute priority, and a PCI device having a higher request priority can always preferentially acquire the bus right.

Next, FIG. 5 shows the PCI of the second embodiment of the present invention.
The connection diagram of a bus arbiter is shown.

In the second embodiment shown in FIG. 5, the primary
PCI common to PCI bus 111 and secondary PCI bus 112
The arbiter 151 is provided to collectively arbitrate bus right requests from all PCI devices.

9 and 10 show the register configuration of the PCI bus arbiter 151 of the second embodiment.

As shown in FIG. 9, the PCI bus arbiter 151
In comparison with the first embodiment shown in FIG. 1, the priority register is divided into a primary bus and a secondary bus, and a primary PCI priority register 203 and a secondary PCI priority register 204 are provided respectively.

The bit configuration of each register will be described with reference to FIG.

The (a) control register and the (b) primary PCI priority register of FIG. 10 are respectively the control register 201 and the control register 201 in the first embodiment.
Since it has the same bit configuration as that of the priority register 202, its explanation is omitted here.

The (c) secondary priority register of FIG. 10 is a register for setting the priority of the PCI device on the secondary PCI bus 112 of the second embodiment shown in FIG. Bit 0 and bits 3 to 7 are unused reserved bits. Use bits 1 and 2 for the secondary PC.
Set the priority of bus mastership arbitration for PCI devices on the I bus.

Finally, the PCI of the second embodiment will be described with reference to FIG.
The operation of the bus arbiter 151 will be described.

Of the registers shown in FIG. 10, the control register 201 has 03h, the primary PCI priority register 203 has 01h, and the secondary PCI priority register 2
04 is set to 00h, all bus right requests are adjusted by rotation, and the bus right arbitration ratio between the device on the primary PCI bus and the device on the secondary PCI bus is 1:
The case of setting to 1 will be described with reference to FIG.

When the PCI bus arbiter 151 is in the bus idle state (188) and there is a bus right request from each PCI device, according to the settings of the control register 201, the primary PCI priority register 203 and the secondary PCI priority register 204, Perform arbitration operation.

First, in order to give the bus right to the host bus / PCI bus bridge, Host_ACK 122 is output (181). Next, in order to alternately give the bus right to the PCI device on the primary PCI bus 111 and the PCI device on the secondary PCI bus, the bus use permission signal corresponding to each device is output (183,184,185,186,187,188).

In this way, when the bus right is given to all the PCI devices, the operation is completed. The operation of the other parts related to the second embodiment is the same as that of the first embodiment, and the description thereof is omitted here.

[0072]

According to the present invention, in bus arbitration in a system having a hierarchical bus structure, an I / O device mounted on a lower I / O bus via a bus bridge can be connected to an upper I / O device. As in the case of being attached to the bus, the bus access right to the upper I / O bus can be given.

Further, the bus arbiter can arbitrarily set the arbitration ratio between the device mounted on the upper I / O bus and the device mounted on the lower I / O bus, and each I / O Since the arbitration priority among devices can be set, an optimum bus arbitration method can be set according to the function of the attached I / O device.

Specifically, the primary PCI bus and PCI /
In a system having a secondary PCI bus via a PCI bus bridge, a device attached to the secondary PCI bus can be given the same primary PCI bus access right as the PCI device attached to the primary PCI bus. PCI due to mounting on the PCI bus
It is possible to prevent malfunction of the device and deterioration of system performance.

Further, based on the configuration information read from the PCI configuration space,
You can set the optimal arbitration method.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a PCI bus arbiter according to a first embodiment of this invention.

FIG. 2 is an explanatory diagram of registers of a PCI bus arbiter.

FIG. 3 is a connection diagram of a conventional PCI bus arbiter.

FIG. 4 is an explanatory diagram of a first operation example of the PCI bus arbiter of the first embodiment.

FIG. 5 is a connection diagram of a PCI bus arbiter according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a second operation example of the PCI bus arbiter of the first embodiment.

FIG. 7 is an explanatory diagram of a conventional operation example of a PCI bus arbiter.

FIG. 8 is an explanatory diagram of an operation example of the PCI bus arbiter of the second embodiment.

FIG. 9 is an explanatory diagram of a PCI bus arbiter according to a second embodiment.

FIG. 10 is an explanatory diagram of registers of the PCI bus arbiter according to the second embodiment.

[Explanation of symbols]

103 ... Primary PCI bus arbiter, 111 ... Primary PCI bus, 121 ... Bus right request signal, 122 ... Bus use permission signal, 129 ... Bus right request signal, 130 ... Bus use permission signal, 200 ... PCI bus interface,
201 ... Control register, 202 ... Priority register, 205 ... Arbitration circuit, 206
… REQ / ACK signal input / output port.

Claims (6)

[Claims] 1. A hierarchical bus system including a first bus, a second bus, and a bus bridge that hierarchically connects the bus from the first bus to the second bus. Arbitrating a right to use request for the first bus transmitted from a plurality of devices connected to the bus and a right to use request for the first bus transmitted by the bridge, and obtaining the right to use the first bus by the plurality of devices. Arbitrating the bus access right given to any one of the device or the bridge, wherein the arbiter is the first arbiter that is transmitted by a device connected to the second bus via the bridge. The arbiter has means for setting the arbitration priority of the right to use one bus, and the arbiter also has the information set in the means for setting the arbitration priority. Zui, the hierarchical configuration bus arbitration method characterized in that it is capable of changing the algorithm of the bus arbitration operation that arbitrates bus access requests from a plurality of devices and the bridge which connects to the first bus. 2. The bus between the at least one device connected to the second bus and the at least one device connected to the first bus as the means for setting the arbitration priority. Rights Arbitration method for a hierarchical bus that stores information about priority. 3. The bus right arbitration priority setting means according to claim 1, wherein the bus right is given to a bus device connected to the first bus and a bus device connected to the second bus. Arbitration method for hierarchical bus storing information about frequency-frequency ratio. 4. The hierarchical arbitration bus according to claim 1, wherein the arbitration priority setting means sets the arbitration priority based on unique configuration information of devices mounted on the first bus and the second bus. Arbitration method. 5. The hierarchical arbitration method according to claim 1, wherein the first bus and the second bus are buses having the same physical and logical specifications and bus transfer protocol. 6. At least a first bus and a second bus,
In a hierarchical bus system including a bus bridge that hierarchically connects buses from the first bus to the second bus, use of the first bus sent by a plurality of devices connected to the first bus Bus access right that arbitrates the right request and the first bus usage right request sent from the bridge, and gives the first bus usage right to any one of the plurality of devices or the bridge. Arbitrating the arbitration, the arbiter has means for setting whether or not a device is connected to the second bus via the bridge, and the arbiter is set to the setting means. If a device is connected to the second bus based on the information, the algorithm of the bus usage right arbitration operation of the first bus is changed. Hierarchical configuration bus arbitration method of that.