JP2000243042A - Clock recovery device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable wide cap challenge and improving the accuracy of a clock by deciding whether an analog reproduced signal is in a frequency lock state with a reproducing clock or not, oscillating a reproducing clock synchronizing with a frequency of a reproduced signal when it is not in a lock state, and oscillating a reproducing clock synchronizing with a phase synchronizing signal when it is in a lock state. SOLUTION: A phase error detector 101 detects the quantity of phase error, a frequency error detector 102 calculates the quantity of a frequency error and the quantity of an initial frequency error using the quantity of phase error. A switch 105 performs phase pull-in by turning off a circuit at the time of frequency pull-in and turning on a circuit after frequency clock by a frequency clock signal from a frequency clock detector 103. Analog quantity converted by D/A converters 107, 108 of which the gain is different from each other are added by an analog adder 110, inputted to a VCO 111, a clock having a frequency in accordance with an input signal is oscillated, after high speed frequency pull-in is performed, a phase is locked.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery device, for example, in an information recording / reproducing device such as a hard disk device or an optical disk, using a phase synchronization signal pre-recorded on a recording medium and using a reproducing head. The present invention relates to an apparatus for reproducing a clock synchronized with an analog reproduction signal read from a recording medium, the apparatus having a high-speed frequency pull-in function.

[0002]

2. Description of the Related Art In recent years, as a data reproducing apparatus of a data recording / reproducing system such as a hard disk drive (HDD) or a DVD, a PRML (Partial Response) has been developed.
A device using a reproduction signal processing circuit of the Maximum Likelihood (Maximum Likelihood) method has been developed. The PRML method is a reproduction signal processing method combining a PR encoding method and a maximum likelihood decoding method (for example, Viterbi decoding). In the case of such a reproduction signal processing circuit using the PRML method,
Extract the clock signal from the signal recorded on the recording medium,
Self-synchronization for reproducing digital data using the extracted clock signal is often used.

FIG. 2 shows an example of a reproduction signal processing circuit using PRML signal processing. In FIG. 2, reference numeral 4 denotes an AGC amplifier (hereinafter referred to as VGA) for amplifying an analog reproduction signal reproduced from a recording medium of a data recording / reproducing system. 5)
Is an A / D converter for converting an analog signal output from the LPF 5 into a digital signal, 2 is an A / D converter, and 3 is an A / D converter 2. PR equalizer that performs waveform equalization on the digital signal output from the PDP by a PR (Partial Response) method, 6 denotes a Viterbi decoder that performs Viterbi decoding on the digital signal that has been subjected to waveform equalization by the PR equalizer 3 Reference numeral 1 denotes a clock recovery that extracts a clock signal using the output of the PR equalizer 3 and supplies the clock signal to the A / D converter 2. Reference numeral 7 denotes a decoder that decodes the output of the Viterbi decoder 6.

Next, the operation will be described. VGA4 is
An amplifier having an automatic gain adjustment function (AGC) for controlling a dynamic range of an amplitude value of an analog reproduced signal read from a head or a pickup (hereinafter, referred to as a head system) of a data reproducing apparatus. The read analog reproduction signal is amplified. The LPF 5 removes an extra high frequency component from the amplified reproduced signal,
Improve the N (signal to noise) ratio. The A / D converter 2
The clock from clock recovery 1 is used as a sampling pulse, and an analog reproduction signal is converted into a digital signal. The PR equalizer 3 equalizes the signal by performing a convolution operation according to the Nyquist filter and the PR method. The Viterbi decoder 6 detects the most probable data sequence as decoded data from the PR-encoded data sequence based on the Viterbi algorithm. The decoder 7 decodes data modulated at the time of recording into original data before modulation. The clock recovery 1 performs frequency / phase pull-in according to a sync (synchronization) pattern recorded on a recording medium, and generates a clock synchronized with a reproduction signal.

[0005] With the above arrangement, recorded digital data is extracted from an analog reproduction signal provided from the head system. In such a system, clock recovery uses the output of the PR equalizer to calculate the amount of phase error. FIG. 3 shows an example of a configuration of a conventional clock recovery apparatus. A loop filter 107 for removing high-frequency components; a D / A converter 107 for converting a digital signal output from the loop filter 106 into an analog signal;
Reference numeral 11 denotes a voltage controlled oscillator (hereinafter, referred to as a VCO) that oscillates at a frequency corresponding to the analog signal output from the D / A converter 107.

Next, the operation will be described. The phase error detector 101 calculates a phase error amount using the output of the PR equalizer 3. This phase error detector, as shown in FIG.
For example, the sine wave shown in FIG. 4A is originally sampled at the sampling point shown in FIG. 4B, but the phase error PE caused by sampling the sine wave at the sampling point shown in FIG. 4C is estimated. is there. PR equalizer 3
As an example of the configuration of the phase error detector using the output of
ST TIMING RECOVERY FOR PA
RITAL-RESPONSE SIGNALING
SYSTEMS "(F. Dolivo, W. Schott)
t, G. Ungerbox; IEEE EConf. o
n Comm. , Boston pp 573-577,
June 1989). The phase error calculated here is calculated using the data after Nyquist equalization and PR equalization in the PR equalizer 3. Therefore, since a clock delay occurs in the PR equalizer, the pull-in time becomes longer in the conventional clock recovery device shown in FIG.

The amount of phase error calculated by the phase error detector 101 is passed through a loop filter 106 to the D / A converter 10.
7 and is converted by the D / A converter 107 into an analog amount such as a current. The VCO 111 oscillates at a frequency corresponding to the output of the D / A converter 107 and the A / D converter 2
This oscillated clock is supplied to the other digital signal processing units. The VCO 111 initially oscillates at the same frequency as during recording and sequentially changes to a frequency that compensates for the phase error on the reproducing side.

FIG. 5 shows an example of the output of the phase error detector 101 at the time of phase pull-in. The horizontal axis is the time axis, and the vertical axis corresponds to the phase error amount. The fact that the phase error amount changes stepwise is due to the influence of the quantization error at the time of A / D conversion. This figure shows a state in which feedback control by clock recovery starts at a point having a certain phase error, and the phase error gradually approaches “0” to lock the phase.

[0009]

FIG. 6 shows a recording format of a general magnetic recording / reproducing apparatus. As described above, the recording format includes the specific pattern data (hereinafter, referred to as a specific pattern) IP and the user data UD, and the specific pattern is used for clock phase synchronization, byte synchronization, AGC pull-in, and the like. Since the area where this specific pattern is recorded is not an area that can be used by the user, the shorter this area is, the longer the original user data area can be, and the more usable recording capacity can be increased. Since the length of the specific pattern is determined by the time required for clock phase synchronization, high-speed clock phase synchronization is desired to increase storage capacity.

By the way, as the processing speed of the data reproducing apparatus increases, the digital signal processing unit such as the PR equalizer
By realizing high-speed operation by parallelization and pipeline processing, it is possible to cope with an increase in processing speed. The pipeline processing is a method of dividing the processing of the circuit so that the processing can be performed with one clock. In the clock recovery device of FIG. Can be.

However, in a device that forms a feedback loop such as a clock recovery, unlike an open loop circuit, a clock delay increases due to parallel processing or pipeline processing, so that the loop characteristics deteriorate rather. In particular, in the configuration of the conventional clock recovery device as described above, the time required for phase lock is long and the range in which the frequency can be pulled in becomes narrow, so that the clock reproduction itself becomes difficult.

In order to cope with this, a frequency error is detected by a frequency comparator and a frequency pull-in is performed to widen a frequency pull-in range. For example, Japanese Patent Application Laid-Open No. 10-107623 discloses a “converter and Method and PLL operation device and method ". The frequency comparator used therein calculates the frequency error by counting the output of the phase comparator generated when the phase rotates by 2π. However, in this method and configuration, since a pulse generated every time the phase rotates 2π is used, the loop gain cannot be increased,
It becomes difficult to increase the speed of pulling in the frequency.

As a method of detecting a frequency error,
2. Description of the Related Art Conventionally, there is a "frequency comparator" disclosed in, for example, Japanese Patent Application Laid-Open No. 52-36072, in which a pulse having a reference frequency and a pulse (clock) having an unknown frequency are input to these two comparators. The input signals are compared, and the difference between the frequencies is output as an analog amount.

The feature of this method is that when the phase difference of the input signal reaches a predetermined value, a signal having a voltage value proportional to the phase difference entering the differentiating circuit is cut off for a short time, and the phase of one input signal is changed. In this case, a high-speed switch is required during high-speed operation, and it is difficult to obtain accuracy.

The purpose of this method is to simply compare the frequencies of two signals, and use one of the signals inverted. Therefore, this method cannot be used in the clock recovery apparatus of the present invention. The present invention has been made in view of the above-mentioned problems of the related art, and has a wide capture range, high accuracy of a reproduced clock,
It is another object of the present invention to realize a clock recovery device having a short pull-in time.

[0016]

According to a first aspect of the present invention, there is provided a clock recovery apparatus which uses a phase synchronization signal recorded in advance on a recording medium to synchronize a clock synchronized with an analog reproduction signal read from the recording medium. And a digital signal processing circuit for determining whether or not the analog reproduced signal is in a frequency locked state with the reproduced clock, wherein the frequency lock is detected by the frequency lock detecting means. A first oscillation control means for controlling an oscillating means to oscillate a reproduction clock frequency-synchronized with the analog reproduction signal when it is detected that the frequency lock is not detected, and a digital signal processing circuit; Means for detecting that the frequency is in the locked state by the means. The phase synchronization signal contained is obtained by so and a second oscillation control means for controlling the oscillation means to oscillate the phase-synchronized with the recovered clock.

The clock recovery apparatus according to the first aspect of the present invention comprises frequency lock detecting means for determining whether or not an analog reproduced signal is in a frequency locked state with the reproduced clock, and a digital signal processing circuit. ,
First oscillation control means for controlling an oscillation means so as to oscillate a reproduction clock frequency-synchronized with the analog reproduction signal when the frequency lock detection means detects that the frequency lock state is not established, and a digital signal processing circuit And controlling the oscillating means so as to oscillate a reproduction clock phase-synchronized with a phase synchronization signal included in the analog reproduction signal when the frequency lock detection means detects that the frequency is locked. With the above oscillation control means, the frequency pull-in range can be expanded, and the clock reproduction time can be shortened.

According to a second aspect of the present invention, there is provided a clock recovery apparatus for reproducing a clock synchronized with an analog reproduction signal read out from a recording medium using a phase synchronization signal recorded in advance on the recording medium. A recovery unit that calculates a value proportional to a phase error between the analog reproduction signal and the clock and outputs the calculated value as a digital value; and a phase synchronization unit that synchronizes the analog reproduction signal based on an output of the phase error detection unit. Phase synchronization means for oscillating the clock, and frequency error detection means for calculating a value proportional to a frequency error between the analog reproduction signal and the clock using the output of the phase error detection means as input data and outputting the value as a digital value And using the output of the frequency error detection means as input data to detect whether or not the frequency is locked. And the wave number lock detecting means is obtained by so and a frequency pull means performs frequency pull using the detected frequency error by the frequency error detecting means when not in the frequency-locked state.

According to a second aspect of the present invention, there is provided a clock recovery apparatus which calculates a value proportional to a phase error between an analog reproduction signal and the clock and outputs the value as a digital value; A phase synchronization unit that oscillates the clock phase-synchronized with the analog reproduction signal based on an output of the detection unit, and an output of the phase error detection unit as input data which is proportional to a frequency error between the analog reproduction signal and the clock. Frequency error detecting means for calculating a value and outputting it as a digital value; frequency lock detecting means for detecting whether or not the frequency error detecting means is in a frequency locked state with the output of the frequency input means as input data; and Frequency pull-in means for performing frequency pull-in using the frequency error detected by the error detection means. By, it is possible to widen the frequency acquisition range, making it possible to shorten the clock regeneration time.

According to a third aspect of the present invention, there is provided a clock recovery apparatus for reproducing a clock synchronized with an analog reproduction signal read from a recording medium by using a phase synchronization signal recorded in advance on the recording medium. In the recovery device, a phase error detection unit that calculates a value proportional to a phase error between the analog reproduction signal and the clock and outputs the result as a digital value, and an output of the phase error detection unit as input data and the analog reproduction signal. Frequency error detecting means for calculating a value proportional to the frequency error between the clocks and outputting as a digital value, and a frequency lock detecting means for detecting whether or not the output of the frequency error detecting means is input data and a frequency locked state And the output signal of the frequency error detecting means, using the output signal of the frequency lock detecting means as a control signal. A data holding unit for holding, a switch for turning on / off an output signal of the phase error detection unit based on an output signal of the frequency lock detection unit, a digital loop filter using an output of the switch as input data, and the digital loop filter And a clock regenerating means for regenerating the clock using the phase component and the frequency component output from the controller and the output of the data holding means as input data.

According to a third aspect of the present invention, there is provided a clock recovery apparatus for detecting a frequency error based on phase error information from a phase error detecting means, and performing frequency pull-in using the frequency error. Frequency lock detecting means for detecting whether or not the frequency error detecting means is in a frequency locked state with the output of the frequency error detecting means as input data,
A data holding unit that holds an output signal of the frequency error detecting unit using an output signal of the frequency lock detecting unit as a control signal, and turns on / off an output signal of the phase error detecting unit based on an output signal of the frequency lock detecting unit. It has a switch and a digital loop filter that uses the output of the switch as input data.Since these are digital circuits, high-precision frequency error detection and high-speed frequency pull-in are possible, and the frequency pull-in range is reduced. The clock reproduction time can be shortened.

According to a fourth aspect of the present invention, there is provided a clock recovery apparatus for reproducing a clock synchronized with an analog reproduction signal read from a recording medium using a phase synchronization signal recorded in advance on the recording medium. In the recovery device, a phase error detection unit that calculates a value proportional to a phase error between the analog reproduction signal and the clock and outputs the result as a digital value, and an output of the phase error detection unit as input data and the analog reproduction signal. Frequency error detecting means for calculating a value proportional to the frequency error between the clocks and outputting as a digital value, and a frequency lock detecting means for detecting whether or not the output of the frequency error detecting means is input data and a frequency locked state The output signal of the frequency error detecting means, using the output signal of the frequency lock detecting means as a control signal. A data holding unit for holding, a switch for turning on / off an output signal of the phase error detection unit based on an output signal of the frequency lock detection unit, a digital loop filter using an output of the switch as input data, and the digital loop filter Clock recovery means for recovering the clock using the phase component and frequency component output from the controller and the output of the data holding means as input data, and correcting the oscillation frequency of the clock recovery means using the output of the data holding means as input data. Frequency correction means for performing the correction.

A clock recovery apparatus according to a fourth aspect of the present invention includes a frequency error detecting means for detecting a frequency error based on the phase error information from the phase error detecting means, and a frequency pull-in using the frequency error. Frequency lock detection means for detecting whether or not the output of the frequency error detection means is a frequency lock state as input data,
A data holding unit that holds an output signal of the frequency error detecting unit using an output signal of the frequency lock detecting unit as a control signal, and turns on / off an output signal of the phase error detecting unit based on an output signal of the frequency lock detecting unit. It has a switch and a digital loop filter that uses the output of the switch as input data.Since these are digital circuits, high-precision frequency error detection and high-speed frequency pull-in are possible, and the frequency pull-in range is reduced. It is possible to extend the clock recovery time, and to reduce the clock recovery time, and to provide a frequency correction unit that corrects the oscillation frequency of the clock recovery unit when the next clock recovery is started from the frequency error amount. This makes it possible to reduce clock recovery later.

According to a fifth aspect of the present invention, there is provided a clock recovery apparatus according to the third or fourth aspect, wherein the frequency error detecting means includes a difference of a value proportional to a phase error in a certain fixed time. The digital value is calculated, and only when the absolute value of the difference value is smaller than a predetermined value, cumulative calculation is performed to calculate a value proportional to the frequency error.

In a clock recovery apparatus according to a fifth aspect of the present invention, the frequency error detecting means digitally calculates a difference value of a value proportional to a phase error at a certain time, and determines the absolute value of the difference value to be a predetermined value. By providing means for performing cumulative calculation only when the value is smaller than the value and calculating a value proportional to the frequency error, the frequency error can be detected with high accuracy.

According to a sixth aspect of the present invention, in the clock recovery apparatus according to the third or fourth aspect, the frequency error detecting means includes a difference of a value proportional to a phase error in a certain time. The digital value is calculated, and only when the difference value is smaller than a predetermined maximum value and larger than a predetermined minimum value, the cumulative calculation is executed to calculate a value proportional to the frequency error.

In the clock recovery device according to the invention of claim 6 of the present application, the frequency detecting means digitally calculates a difference value of a value proportional to the phase error in a certain time, and the difference value becomes larger than a predetermined maximum value. Providing a means for accumulating and calculating a value proportional to the frequency error only when the value is small and larger than a predetermined minimum value makes it possible to detect the frequency error with high accuracy.

According to a seventh aspect of the present invention, in the clock recovery apparatus according to the third or fourth aspect, the frequency error detecting means includes a difference of a value proportional to a phase error in a certain time. Digitally calculating the value, performing a predetermined correction corresponding to the characteristic of the phase error detecting means on the difference value by the sign of the difference value, and calculating the difference value or the corrected value selected by an external control signal. Only when the absolute value is smaller than a predetermined value, cumulative calculation is executed and a value proportional to the frequency error is calculated.

In the clock recovery device according to the invention of claim 7 of the present application, the frequency detecting means digitally calculates a difference value of a value proportional to the phase error in a certain time, and converts the difference value into a difference value by a sign of the difference value. A predetermined correction corresponding to the characteristic of the phase error detecting means is performed on the difference, and only when the difference value selected by the external control signal or the absolute value of the corrected value is smaller than the predetermined value, the cumulative calculation is performed and the value proportional to the frequency error is calculated. Is provided, it is possible to accurately detect the frequency error.

The clock recovery device according to the invention of claim 8 of the present application is the clock recovery device according to claim 4, wherein the frequency correction means includes a data proportional to a frequency error output from the frequency error detection means. Is larger than a predetermined value, the oscillation frequency of the clock recovery means is corrected at the start of clock recovery.

In the clock recovery apparatus according to the present invention, when the absolute value of the data proportional to the frequency error outputted from the frequency error detecting means is larger than a predetermined value, By correcting the oscillation frequency of the clock recovery means at the start of the clock recovery, it is possible to reduce the corrected frequency pull-in time.

According to a ninth aspect of the present invention, in the clock recovery apparatus according to the fourth aspect of the present invention, the frequency correction means includes a data proportional to a frequency error output from the frequency error detection means. Is larger than a predetermined maximum value or smaller than a predetermined minimum value, the oscillation frequency of the clock reproducing means is corrected at the start of clock reproduction.

A clock recovery device according to a ninth aspect of the present invention provides a clock recovery device, wherein when the data proportional to the frequency error output from the frequency error detecting means is larger than a predetermined maximum value or smaller than a predetermined minimum value, By correcting the oscillation frequency of the clock recovery means at the start of clock recovery, it is possible to shorten the corrected frequency pull-in time.

According to a tenth aspect of the present invention, in the clock recovery device according to the third or fourth aspect, the clock recovery means includes a phase component output from the digital loop filter and the data component. Digital adding means for adding the output of the holding means;
A first D / A converter for converting an output of the digital adder into an analog signal, a second D / A converter for converting a frequency component output from the digital loop filter into an analog signal, An analog adding means for adding an output signal of the first converting means and an output signal of the second D / A converting means; and a clock generating means for generating the clock according to the output of the analog adding means. It was done.

In the clock recovery device according to the tenth aspect of the present invention, the clock recovery means separates the digital signal of the phase component and the digital signal of the frequency component into separate digital signals.
After conversion into analog signals by the A-converter, these signals are added, so that it is not necessary to use a wide-range D / A converter as the D / A converter, and it is possible to eliminate a factor of cost increase.

The clock recovery device according to the invention of claim 11 of the present application is the clock recovery device according to claim 3 or 4, wherein the clock recovery means includes a phase component output from the digital loop filter and the data component. First digital adding means for adding the output of the holding means, second digital adding means for adding the output of the first digital adding means and the frequency component output from the digital loop filter, and Digital clock generating means for generating the clock according to the output of the digital adding means.

In a clock recovery apparatus according to an eleventh aspect of the present invention, in a clock recovery means, a phase component and a frequency component are added as a digital signal as it is, and a clock is generated by a digital clock generation means at a frequency corresponding to the added value. Is generated, it is not necessary to provide a D / A conversion means, and the scale of the clock recovery means can be reduced.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. In the first embodiment, by using the frequency error detector that accurately detects the frequency error even at the time of high-speed operation, a wide capture range, a highly accurate reproduction clock can be obtained, and the pull-in can be performed in a short pull-in time. This realizes a simple clock recovery device, and corresponds to the inventions of claims 1, 2, 3, 5, 6, 7, and 10.

FIG. 1 is a block diagram showing a clock recovery device according to the first embodiment of the present invention. In the figure, reference numeral 101 denotes a phase error detector as a phase error detector 601 for calculating a phase error amount using an output of a PR equalizer (not shown). Reference numeral 102 denotes a frequency error amount using an output of the phase error detector 101. Frequency error detector 103 as frequency error detector 603; frequency lock detector 103 as frequency lock detector 502 for detecting whether or not the output of frequency error detector 102 is locked to a target frequency; A detector 104; a data holder for holding the output of the frequency error detector 102; 105 a phase error detector 10 according to the output of the frequency lock detector 103;
1 is a switch for switching whether or not to transmit the output of 1 to a loop filter 106; 106 is a filter for filtering the output of the phase error detector 101; a loop filter realized by a digital filter; 107 and 108 are digital adders 109 to be described later D / A converter for converting the output of the loop filter 106 and one output of the loop filter 106 into analog signals, respectively.
109 is a digital adder for adding the output of the data holding unit 104 and the other output of the loop filter 106;
0 is an analog adder that adds the outputs of the D / A converters 107 and 108, and 111 is a voltage controlled oscillator (hereinafter, referred to as VCO) that oscillates at a frequency corresponding to the output of the analog adder 110 and outputs a reproduced clock. It is.

In FIG. 1, the phase error detector 101, frequency error detector 102, frequency lock detector 103, data holder 104, switch 105, loop filter 106, and digital adder 109 are constituted by digital circuits. The switch 105, the loop filter 106, and the D / A converter 108 control the phase synchronization means 602.
This is based on the output of the phase error detection means 601, the clock phase-synchronized with the analog reproduction signal, V
It is generated in CO111. Further, the phase synchronization means 602 constitutes a second oscillation control means 501 together with the phase error detector 101 as the phase error detection means 601, which is detected by the frequency lock detection means 502 to be in a frequency locked state. Occasionally, the VCO as the oscillating means 505 oscillates a reproduction clock phase-synchronized with a phase synchronization signal included in an analog reproduction signal (corresponding to a digital signal input to the phase error detector 101).
111 is controlled.

The data holding unit 104, the digital adder 109 and the D / A converter 107 constitute a frequency pull-in means 604, which is a frequency error detected by the frequency error detection means 603 when the frequency is not locked. Is used to perform frequency pull-in. The frequency pull-in means 604 constitutes a first oscillation control means 503 together with the frequency error detection means 603. When the frequency lock detection means 502 detects that the frequency lock state is not established, an analog oscillation control means 503 is provided. The VCO 111 as the oscillating means 505 is controlled so as to oscillate a reproduction clock frequency-synchronized with the reproduction signal. Further, a digital adder 109, a D / A converter 107, a D / A converter 108, an analog adder 110
The VCO 111 and the VCO 111 constitute a clock regenerating means 605. The clock regenerating means 605 receives the phase component and the frequency component output from the loop filter 106 and the output of the data retainer 104 as inputs and reproduces a clock.

Next, the operation will be described. An analog reproduction waveform read out by a reproduction head from a recording medium in which a phase synchronization signal is recorded in advance is A / D-converted, and a phase error detector 101 is obtained from a digital signal processed as necessary.
Calculates the amount of phase error. The frequency error detector 102 is
The frequency error amount and the initial frequency error amount are calculated using the phase error amount. Here, the frequency error is a value proportional to the frequency error of the data input to the frequency error detector 102, and the initial frequency error is a value proportional to the frequency error at the start of the frequency pull-in. I have.

The data holding unit 104 holds the initial frequency error amount in synchronization with the clock at the time of frequency pull-in, and does not update the data while holding the initial frequency error amount at the time of frequency pull-in completion at the time of phase pull-in. The frequency lock detector 103 determines whether or not the frequency lock-in has been completed based on the frequency error amount calculated by the frequency error detector 102, and outputs a frequency lock signal indicating whether or not the frequency lock-in has been completed to the data retainer 104. It outputs these control signals to the error detector 102 and the switch 105.

The switch 105 is connected to the frequency lock detector 1
The phase lock signal is turned off when the frequency is locked and turned on after the frequency lock by the frequency lock signal from 03, thereby starting the phase lock. When the phase is pulled in, switch 1
05 obtained through the loop filter 10
6, the phase component is converted into a frequency component and a frequency component. The phase component is added to the output of the data holding unit 104 by the adder 109, and is converted into an analog quantity by the D / A converter 107. Further, the frequency component calculated by the loop filter 106 is converted into an analog amount by the D / A converter 108. The use of two D / A converters in this way is
Since the magnitude of the phase component and the frequency component calculated by the loop filter 106 are significantly different (phase component / frequency component = 1000 or more), if this is to be processed by one D / A converter, a considerably wide range is covered. D / A
This is because a converter is required, which causes an increase in cost. Therefore, processing is performed using two D / A converters having different gains.

D / A converter 107 and D / A converter 108
Are added by the adder 110 and input to the VCO 111. The VCO 111 oscillates a clock having a frequency according to the input signal. By adopting such a configuration, the frequency lock loop operates first to perform high-speed frequency pull-in,
Since the phase locked loop operates and locks the phase, the frequency pull-in range can be widened and the clock recovery time can be reduced.

FIG. 7 shows a phase error detection characteristic of a specific pattern of the phase error detector. The phase error detector calculates and outputs a value proportional to the magnitude of the phase error. FIG. 7 shows the output of the phase error detector when the VCO oscillates a clock having a certain frequency error with respect to the data transfer speed in the phase error detector having such characteristics. The horizontal axis is the time axis, and the vertical axis corresponds to the phase error amount.

FIG. 8 shows a case where a certain frequency error exists in the specific pattern data (that is, a case where the clock oscillated from the VCO oscillates at a certain frequency having a frequency error compared to the data transfer speed). 3 shows the output of the phase error detector of FIG. The horizontal axis is the time axis,
The vertical axis corresponds to the phase error amount. (A) in the figure shows the phase error detector output when the frequency error is larger than that in (b). This is because the difference between the phase error at a certain sampling point and the phase error at the next sampling point increases as the frequency error increases. As a result, the amount of change in the amount of phase error increases, and the slope of the output of the phase error detector increases. Therefore, the magnitude of the frequency error amount is proportional to the phase error difference value for a certain period of time.

However, at the time points T, 2T, and T 'in FIG. 4A, the phase error amount rapidly changes from the plus side to the minus side. At this point, the phase is 2
Indicates that the rotation is π, but if this phase rotation occurs when calculating the difference value of the phase error, a value proportional to the frequency error must be obtained unless the difference value of this part is excluded. Can not.

FIG. 9 shows a first configuration example of the frequency error detector in the clock recovery device according to the first embodiment. In the figure, 1021a is a delay element that delays the phase error PE detected by the phase error detector, 1022 is a subtractor that subtracts the output of the delay element 1021a from the phase error,
Reference numeral 1023 denotes an absolute value calculator for calculating the absolute value of the output of the subtractor 1022, and 1024a denotes a threshold value TV and an absolute value calculator 10
A comparator for comparing the output of the comparator 23 with the output of the comparator 1
224a and the ground potential and the subtractor 1022
Selector 1021b for selecting and outputting one of the outputs
Is a delay element for delaying the output of the adder 1026,
Is an adder for adding the output of the selector 1025a and the output of the delay element 1021b.

Next, the operation will be described. The frequency error is obtained by calculating the slope of the phase error on the time axis. Therefore, first, the subtracter 10 uses the phase error amount PE given as a digital value and the phase error amount delayed by one clock by the delay element 1021a.
The difference value is calculated by 22. This difference value corresponds to the frequency error between the digital signal input to the clock recovery device and the reproduced clock. Next, the absolute value of the difference is obtained by the absolute value calculator 1023, and this value is compared with the threshold value TV by the comparator 1024a. If the absolute value of the difference is larger than a predetermined value given from the outside, it is determined that the phase has rotated by 2π, and the selector 1025a
To select the ground potential, that is, "0". As a result, portions where the phase is inverted, such as T and 2T in FIG. 8A, are removed. When the difference is smaller than the predetermined value, the difference is selected by the selector 1025a as the adder 1026 and the frequency error FE, and is output to a frequency lock detector (not shown). The adder 1026 accumulates this value to calculate the initial frequency error amount IFE. This means that the frequency error at each timing is calculated as Yn-Yn-
1, Yn-1-Yn-2, Yn-2-Yn-3, ...
By accumulating these, (Yn−Yn−1) + (Y
n−1−Yn−2) + (Yn−2−Yn−3) +... + (Yn−m
This is because Yn-Yn-m in (−1−Yn-m), that is, the initial frequency error amount IFE remains.

As described above, since the difference value generated when the phase is rotated by 2π is not input to the adder 1026, the output of the adder 1026 becomes a value proportional to the initial frequency error amount IFE. Further, by setting the delay amount of one clock when calculating the difference value to two clocks, it becomes possible to reduce the operation clock of the frequency error detector to half. This is because even when the interleave processing is performed, the adder 102
This is because the output of No. 6 is a value proportional to the frequency error amount when considered in the time axis direction. With such a configuration, it is possible to calculate a difference value of the phase error on the time axis and calculate a value corresponding to the frequency error. By using this, the present clock recovery device enables high-speed and accurate frequency pull-in.

FIG. 10 shows a second configuration example of the frequency error detector in the clock recovery device according to the first embodiment. 7, the same reference numerals as those in FIG. 7 denote the same or corresponding components, and 1024a is a comparator for comparing the output of the subtractor 1022 with a threshold value (maximum value) TVX. 1024b is an output of the subtractor 1022 and a threshold value (minimum value). Comparators for comparing TVN, 1027 are comparators 1024a, 1024b
A logical product circuit 1025a for generating a logical product of the outputs of the AND circuits 1025a is a selector for selecting and outputting either the ground potential or the output of the subtractor 1022 in accordance with the output of the logical product circuit 1027.

Next, the operation will be described. First, the phase error amount given as a digital value and the delay element 102
A difference value is calculated by the subtractor 1022 using the phase error amount PE delayed by one clock by 1a. This difference value corresponds to a frequency error. Next, the difference value is compared with a maximum value TVX and a minimum value TVN respectively given as thresholds from outside using comparators 1024a and 1024b. When the difference value is larger than the maximum value given from the outside, or when the difference value is smaller than the minimum value given from the outside, it is determined that the phase has rotated by 2π, and the selector 1025a sets the ground potential, that is, “0” to the ground potential. select. Otherwise, the difference value itself is selected by the selector 1025a.
And outputs it to an adder 1026 and a frequency lock detector (not shown) as a frequency error amount. Adder 1
026, this value is set to 1 by the delay element 1021b.
The values obtained by adding the clock-delayed values are integrated to calculate an initial frequency error amount IFE.

As described above, since the difference value generated when the phase is rotated by 2π is not input to the adder 1026, the output of the adder 1026 becomes a value proportional to the initial frequency error amount IFE. Further, by setting the delay amount of one clock when calculating the difference value to two clocks, it becomes possible to reduce the operation clock of the frequency error detector to half. This is because, even when the interleave processing is performed, the output of the adder 1026 becomes a value proportional to the frequency error amount when considered in the time axis direction. With such a configuration, it is possible to calculate a difference value of the phase error on the time axis and calculate a value corresponding to the frequency error. Further, by setting the maximum value and the minimum value of the difference value, it is possible to cope with a case where the characteristics of the phase error detector are not good, and for example, the gains are different between the plus side and the minus side of the frequency error amount. By using this, the clock recovery device can perform high-speed and accurate frequency pull-in.

FIG. 11 shows a third configuration example of the frequency error detector in the clock recovery device according to the first embodiment of the present invention. In the figure, 1021a is a delay element that delays the phase error PE, 1022 is a subtractor that subtracts the output of the delay element 1021a from the phase error PE, 1029 is a sign determiner that determines the sign of the output of the subtractor 1022, 1025
b is a coefficient 1 CF1 according to the output of the sign decision unit 1029.
And a coefficient for selecting coefficient 2 CF2, 1028 is a multiplier for multiplying the output of the subtractor 1022 by the coefficient selected by the selector 1025b, and 1025c is an external control signal C.
A selector for selecting an output of the multiplier 1028 and an output of the subtractor 1022 in accordance with the TL, an absolute value circuit 1023 for generating an absolute value of an output of the selector 1025c, and a reference numeral 1024a for an externally applied threshold TV and the absolute value The comparator 1025a for comparing the output of the circuit 1023 is a comparator 1024
A selector 1026 for selecting and outputting either the output of the subtractor 1022 or the ground value in accordance with the output of a, and an adder 1026 for adding the output of the selector 1025a and a value obtained by delaying the output by the delay element 1021b. is there.

Next, the operation will be described. First, the phase error PE given as a digital value and the delay
The difference value, that is, the frequency error is calculated by the subtracter 1022 using the phase error amount obtained by delaying this by one clock by 21a. Next, the sign of this difference value is
9 to determine whether the slope of the difference is positive or negative. A selector 102 that uses the output of the code determiner 1029 as a determination signal.
Coefficient 1 CF1 or Coefficient 2 CF selected in 5b
2 is multiplied by a multiplier 1028 with the above difference value. Then, the difference value and the multiplier 1028 are selected by the selector 1025c that uses the control signal CTL from the outside as a determination signal.
, And the absolute value is obtained by the absolute value circuit 1023. If this value is larger than a predetermined threshold value TV externally given by the comparator 1024a, it is determined that the phase has rotated by 2π. Ground potential, ie, “0”
Is output to the adder 1026, and the frequency error FE as an output of the selector 1025c is output to the adder 1026 to remove the phase-inverted portion. Adder 1
At 026, the initial frequency error IFE is output by adding the input and the output of the delay unit 1021b for delaying the output of the adder 1026. When the difference value is selected by the selector 1025c, the multiplier 1028 that multiplies the difference value by the coefficient selected by the sign of the difference value does not operate.

By adopting such a configuration, the difference value of the phase error on the time axis can be calculated, and the value corresponding to the frequency error can be calculated. In addition, the threshold value used in the calculation can be reduced to one. it can. Further, by multiplying the difference value by a coefficient according to the sign of the difference value, it is possible to cope with a case where the phase error detector has a characteristic in which the gain is different between the plus side and the minus side of the frequency error amount. Further, when the characteristics of the phase error detector are good, power consumption can be reduced by not operating the multiplier. By using this, the clock recovery device can perform high-speed and accurate frequency pull-in.

As described above, according to the first embodiment, the frequency lock loop constituted by the digital circuit is added, and the frequency is locked in high speed and high accuracy in advance.
Since the clock is reproduced by performing phase pull-in in the phase locked loop, it is possible to perform phase synchronization of the clock at a high speed, and to perform phase synchronization with a specific pattern having a short pattern length. It is possible to increase the area that can be used by the user.

Embodiment 2 In the first embodiment, an analog clock is obtained as a reproduced clock.
As shown in the above, a digital one may be obtained, and this case corresponds to the inventions of claims 1, 2, 3, 5, 6, 7, and 11.

In FIG. 15, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. , The frequency component output from the loop filter 106 and the output from the digital adder 109 are added. Reference numeral 121 denotes a digital VCO provided in place of the VCO 111 in FIG.

The switch 105 and the loop filter 106 constitute a phase synchronizing means 612.
The digital VCO 121 generates a clock phase-synchronized with the analog reproduction signal based on the output of the phase error detection means 601. Also, this phase synchronization means 612
Is the phase error detector 10 as the phase error detection means 601
1 together with the second oscillation frequency control means 511,
This is an analog reproduction signal (corresponding to a digital signal input to the phase error detector 101) when the frequency lock detection unit 502 detects that the frequency is locked.
The digital VC as the oscillating means 515 oscillates a reproduction clock phase-synchronized with the phase synchronization signal
O121 is controlled.

The data holding unit 104 and the digital adder 109 constitute a frequency pull-in unit 614, which performs frequency pull-in using the frequency error detected by the frequency error detection unit 603 when the frequency is not locked. Things. The frequency pull-in means 614 constitutes a first oscillation control means 513 together with the frequency error detection means 603. When the frequency lock detection means 502 detects that it is not in the frequency locked state, the frequency lock-in means 614 The digital VCO 121 as the oscillating means 515 is controlled so as to oscillate a reproduction clock frequency-synchronized with the reproduction signal.

Further, the digital adder 109 and the digital adder 120 constitute a clock recovery means 615 which receives the phase component and the frequency component output from the loop filter 106 and the output of the data holder 104 as inputs. The clock is reproduced.

Next, the operation will be described. An analog reproduction waveform read out by a reproduction head from a recording medium in which a phase synchronization signal is recorded in advance is A / D-converted, and a phase error detector 101 is obtained from a digital signal processed as necessary.
Calculates the amount of phase error. The frequency error detector 102 is
The frequency error amount and the initial frequency error amount are calculated using the phase error amount. Here, the frequency error is a value proportional to the frequency error of the data input to the frequency error detector 102, and the initial frequency error is a value proportional to the frequency error at the start of the frequency pull-in. I have.

The data retainer 104 holds the initial frequency error amount in synchronization with the clock at the time of frequency pull-in, and does not update the data while retaining the initial frequency error amount at the time of frequency pull-in completion at the time of phase pull-in. The frequency lock detector 103 determines whether or not the frequency lock-in has been completed based on the frequency error amount calculated by the frequency error detector 102, and outputs a frequency lock signal indicating whether or not the frequency lock-in has been completed to the data retainer 104. It outputs these control signals to the error detector 102 and the switch 105.

The switch 105 is connected to the frequency lock detector 1
The phase lock signal is turned off when the frequency is locked and turned on after the frequency lock by the frequency lock signal from 03, thereby starting the phase lock. When the phase is pulled in, switch 1
05 obtained through the loop filter 10
The signal is converted into a phase component and a frequency component by 6, and the phase component is added to the output of the data holding unit 104 by the adder 109. Further, the frequency component calculated by the loop filter 106 is added to the output of the adder 109 by the adder 120 and input to the digital VCO 121. Digital V
The CO 121 oscillates a clock having a frequency according to the input signal.

With such a configuration, the frequency pull-in range can be expanded, and the clock reproduction time can be shortened. Further, since the reproduction clock is generated as it is as a digital signal, a D / A converter is not required, and the circuit scale can be reduced and the signal processing can be performed with higher accuracy.

As described above, according to the second embodiment, after the frequency lock loop constituted by the digital circuit is added and the frequency is locked in high speed and high accuracy in advance,
The clock is recovered by performing phase pull-in in the phase-locked loop, and the clock is also recovered by a digital circuit, so that phase synchronization of the clock can be performed at high speed. It becomes possible to perform phase synchronization with a specific pattern, not only to increase the area of the recording / reproducing medium that can be used by the user, but also to reduce the circuit scale.

Embodiment 3 Third Embodiment A third embodiment of the present invention realizes a clock recovery device capable of shortening a frequency pull-in time by providing a frequency corrector and setting a frequency of a VCO.
This corresponds to the inventions of 5, 6, 7, 8, 9, and 10.

FIG. 12 is a block diagram showing a clock recovery device according to the third embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. A frequency correction unit 606 performs frequency correction based on the output of the data holding unit 104 and the RG signal (that is, a read gate signal indicating data reading), and outputs the corrected signal to the VCO 111. Of the frequency compensator.

In FIG. 12, the phase error detector 101, frequency error detector 102, frequency lock detector 103, data holder 104, switch 105, loop filter 106, digital adder 109, and frequency corrector 112 The switch 105, the loop filter 106, and the D / A converter 108 constitute a phase synchronization unit 602, which is a digital circuit. The phase synchronization unit 602 is a clock synchronized with the analog reproduction signal based on the output of the phase error detection unit 601. Is generated in the VCO 111. Further, the phase synchronization means 602 constitutes a second oscillation control means 501 together with the phase error detector 101 as the phase error detection means 601, which is detected by the frequency lock detection means 502 to be in a frequency locked state. Sometimes, the VCO 111 as the oscillating means 505 is controlled so as to oscillate a reproduction clock phase-synchronized with a phase synchronization signal included in an analog reproduction signal (corresponding to a digital signal input to the phase error detector 101). .

The data holding unit 104, the digital adder 109, and the D / A converter 107 constitute a frequency pull-in means 604, which is a frequency error detected by the frequency error detection means 603 when the frequency is not locked. Is used to perform frequency pull-in. The frequency pull-in means 604 constitutes a first oscillation control means 503 together with the frequency error detection means 603. When the frequency lock detection means 502 detects that the frequency lock state is not established, an analog oscillation control means 503 is provided. The VCO 111 as the oscillating means 505 is controlled so as to oscillate a reproduction clock frequency-synchronized with the reproduction signal.

Further, digital adder 109, D / A converter 107, D / A converter 108, analog adder 11
Clock recovery means 605 is constituted by 0 and the VCO 111. The clock recovery means 605 receives the phase component and the frequency component output from the loop filter 106 and the output of the data retainer 104 as inputs and reproduces a clock.

Next, the operation will be described. An analog reproduction waveform read out by a reproduction head from a recording medium in which a phase synchronization signal is recorded in advance is A / D converted, and a phase error detector 101 calculates a phase error amount from a digital signal processed as necessary. The frequency error detector 102 calculates a frequency error amount and an initial frequency error amount using the phase error amount. Here, the frequency error is a value proportional to the frequency error of the data input to the frequency error detector 102, and the initial frequency error is a value proportional to the frequency error at the start of the frequency pull-in. I have.

The data holding unit 104 holds the initial frequency error amount from the frequency error detector 102 in synchronization with the clock at the time of frequency pull-in, and keeps the initial frequency error amount at the time of frequency pull-in completion at the time of phase pull-in. Do not update data. The frequency lock detector 103 is
It is determined from the frequency error amount calculated by the frequency error detector 102 whether or not the frequency lock-in has been completed.
Are output as control signals.

The switch 105 is connected to the frequency lock detector 1
The phase lock signal is turned off when the frequency is locked and turned on after the frequency lock by the frequency lock signal from 03, thereby starting the phase lock. When the phase is pulled in, switch 1
05 is input to the loop filter 1
06, the phase component is converted into a phase component and a frequency component.
9 and converted into an analog quantity by the D / A converter 107. Further, the frequency component calculated by the loop filter 106 is converted into an analog amount by the D / A converter 108. The use of the two systems of D / A converters as described above uses a large difference between the phase component and the frequency component calculated by the loop filter 106 (phase component / frequency component = 1000 or more). D
This is because if the processing is performed by the / A converter, a D / A converter covering a considerably wide area is required, which causes an increase in cost. Therefore, two D / s with different gains
Processing is performed using A converters 107 and 108. D
The analog amounts converted by the / A converter 107 and the D / A converter 108 are added by the adder 110, and the VCO 111
Is input to The VCO 111 oscillates a clock having a frequency according to the input signal.

The frequency compensator 112 is used to
4 is an input. The output of the data retainer 104 when the frequency is locked represents an initial frequency error at the time of starting the frequency pull-in. If this value is equal to or larger than a certain value, it indicates that there is a certain error between the frequency at the time of data recording and the frequency at the time of reproduction. At this time, if the recording frequency changes for each zone as in zone bit recording, there is a high possibility that a certain percentage of frequency error will appear for each zone.
In order to perform frequency pull-in at high speed, it is desirable that the initial frequency error is small. When setting the oscillation frequency, the VCO 111 corrects the center oscillation frequency by the amount corresponding to the initial frequency error amount and oscillates at the time of starting the next frequency pull-in.

When the initial frequency error is large, the number of data used for the frequency acquisition becomes large, so that it takes time to acquire the frequency, and it may be impossible to complete the phase acquisition with a given specific pattern. In this case as well, by correcting the center oscillation frequency of the VCO 111 at the start of the retry, it is possible to complete the phase acquisition in a specific pattern. With such a configuration, it is possible to further widen the frequency pull-in range, shorten the frequency pull-in time, and shorten the clock reproduction time.

FIG. 13 shows a first configuration example of the frequency corrector in the clock recovery device according to the third embodiment of the present invention. In the figure, 1121 is an initial frequency error IF
An absolute value calculator 1122 for calculating the absolute value of E is a sign determiner 1123 for determining the sign of the initial frequency error IFE.
a is a comparator for comparing the output of the absolute value calculator 1121 with the threshold value TV, 1124a is a selector for selecting one of the set value 1 SV1 and the set value 2 SV2 according to the output of the sign determiner 1122, and 1124b is a comparator. Selector 1125 for selecting either the output of the selector 1124a or the ground potential according to the output of the selector 1123a, and an adder 1126 for adding the output of the selector 1124b and the output of the latch 1126.
Is a latch that receives the output of the adder 1125 as an input, 1124
c is a selector that selects one of the output of the latch 1126 and the ground potential according to the value of RG and outputs this as a correction value CV.

Next, the operation will be described. First, the absolute value of the initial frequency error amount IFE given as a digital value is calculated by the absolute value calculator 1121, and this absolute value is compared with a predetermined value (threshold) TV by the comparator 1123a. When the comparator 1123a determines that the absolute value of the initial frequency error is larger than a predetermined value, the selector 1123a
The correction value from the outside (set value 1 SV1,
Set value 2 SV2) is selected by the value selected by the selector 1124a, otherwise, the ground potential, that is,
“0” is selected by the selector 1124b. Selector 11
The output of 24b is input to the adder 1125,
126 is added to the output. The latch 1126 latches the output of the adder 1125 when the RG signal changes from ON to OFF. It is to be noted that the adder 112
The feedback to 5 is provided for the case where a larger correction amount is required at the time of the second correction. The RG signal is a mode control signal. When the RG signal is turned on, the read mode is set, and clock reproduction and data reproduction are started. Selector 1124c
Selects the output of the latch 1126 when the RG signal is ON, selects and outputs the ground potential, ie, “0”, as a correction amount when the RG signal is OFF, and controls the VCO at the start of the next clock reproduction. Correct the voltage by changing it.

With such a configuration, the VCO
Can be corrected even if the center oscillation frequency of the clock recovery device is deviated by a certain amount or more, and the clock recovery device can perform high-speed frequency pull-in.

FIG. 14 shows a second configuration example of the frequency corrector in the clock recovery device according to the third embodiment of the present invention. In the figure, 1122 is an initial frequency error IF
1123a is a comparator for comparing the initial frequency error IFE with a threshold (maximum value) TVX, 1123b is a comparator for comparing the initial frequency error IFE with a threshold (minimum value) TVN, and 1127 is An AND circuit for generating the logical product of the outputs of the comparators 1123a and 1123b, 1124a is a selector for selecting one of the set value 1 SV1 and the set value 2 SV2 in accordance with the output of the sign determiner 1122, and 1124b is a logical device. A selector for selecting and outputting either the output of the selector 1124a or the ground potential according to the output of the integration circuit 1127, and 1125 for the selector 112
4b and an output of the latch 1126,
A latch 1126 receives an output of the adder 1125 as an input,
A selector 1124c selects one of the output of the latch 1126 and the ground potential according to the value of RG.

Next, the operation will be described. First, the initial frequency error amount IFE given as a digital value and 2
The two thresholds are compared by the comparators 1123a and 1123b. The two thresholds represent the maximum and minimum thresholds of the initial frequency error, respectively. When the comparators 1123a and 1124b determine that the initial frequency error is outside the predetermined range (that is, larger than the maximum value or smaller than the minimum value), the output value of the selector 1124a, that is, the sign determination A value obtained by selecting a correction amount from the outside (set value 1 SV1, set value 2 SV2) by the selector 1124a based on the sign determined by the unit 1122, and if the correction amount is within the range, the ground potential is set as the correction amount. That is, selection is made by the selector 1124b so as to select "0". Selector 112
4b is input to the adder 1125,
26 output. The latch 1126 latches the output of the adder 1125 when the RG signal changes from ON to OFF. The selector 1124c selects the output of the latch 1126 when the RG signal is ON, and selects and outputs the ground potential, that is, “0” as the correction amount when the RG signal is OFF, at the time of starting the next clock reproduction. The control voltage of the VCO is changed and corrected.

With such a configuration, the VCO
Can be corrected even if the center oscillation frequency of the clock recovery device is deviated by a certain amount or more, and the clock recovery device can perform high-speed frequency pull-in. As described above, according to the third embodiment, a frequency locked loop constituted by a digital circuit is added, and a frequency lock is performed in advance at a high speed and with high accuracy, and then a phase lock is performed by the phase lock loop to recover a clock. And VC
Since the initial oscillation frequency of O can be set externally, clock phase synchronization can be performed at high speed, phase synchronization can be performed with a specific pattern having a short pattern length, and the user can use it in a recording / reproducing medium. The possible range can be increased, and even if the oscillation frequency of the VCO is largely shifted, the frequency can be quickly pulled in.

Embodiment 4 In the third embodiment, an analog clock is obtained as a reproduced clock.
It is also possible to obtain a digital one as shown in FIG.
This corresponds to the inventions of 9 and 11. 16, the same reference numerals as those in FIG. 12 indicate the same or corresponding parts. In FIG. 16, the switch 105 and the loop filter 106 constitute a phase synchronizing means 612. The phase synchronizing means 612 synchronizes a clock phase-synchronized with the analog reproduction signal based on the output of the phase error detecting means 601 with the digital VCO1.
21. The phase synchronization means 612 constitutes a second oscillation control means 511 together with the phase error detector 101 as the phase error detection means 601.
When the frequency lock detecting unit 502 detects that the frequency is locked, a reproduction clock phase-synchronized with a phase synchronization signal included in an analog reproduction signal (corresponding to a digital signal input to the phase error detector 101) is oscillated. The digital VCO 12 as the oscillating means 515
1 is controlled.

The data holding unit 104 and the digital adder 109 constitute a frequency pull-in means 614, which performs frequency pull-in using the frequency error detected by the frequency error detection means 603 when the frequency is not locked. Things. The frequency pull-in means 614 constitutes a first oscillation control means 513 together with the frequency error detection means 603. When the frequency lock detection means 502 detects that it is not in the frequency locked state, the frequency lock-in means 614 The digital VCO 121 as the oscillating means 515 is controlled so as to oscillate a reproduction clock frequency-synchronized with the reproduction signal.

Further, the digital adder 109, the digital adder 120 and the digital VCO 121 constitute a clock recovery means 615, which converts the phase component, the frequency component output from the loop filter 106 and the output of the data holder 104. The clock is reproduced as an input.

Next, the operation will be described. An analog reproduction waveform read out by a reproduction head from a recording medium in which a phase synchronization signal is recorded in advance is A / D converted, and a phase error detector 101 calculates a phase error amount from a digital signal processed as necessary. The frequency error detector 102 calculates a frequency error amount and an initial frequency error amount using the phase error amount. Here, the frequency error is a value proportional to the frequency error of the data input to the frequency error detector 102, and the initial frequency error is a value proportional to the frequency error at the start of the frequency pull-in. I have.

The data holding unit 104 holds the initial frequency error amount from the frequency error detector 102 in synchronization with the clock at the time of frequency acquisition, and retains the initial frequency error amount at the time of completion of the frequency acquisition at the time of phase acquisition. Do not update data. The frequency lock detector 103 is
It is determined from the frequency error amount calculated by the frequency error detector 102 whether or not the frequency lock-in has been completed.
Are output as control signals.

The switch 105 is connected to the frequency lock detector 1
The phase lock signal is turned off when the frequency is locked and turned on after the frequency lock by the frequency lock signal from 03, thereby starting the phase lock. When the phase is pulled in, switch 1
05 is input to the loop filter 1
06, the phase component is converted into a phase component and a frequency component.
9 is added. Further, the frequency component calculated by the loop filter 106 is added to the output of the digital adder 109 by the digital adder 120. The output of the digital adder 120 is input to the digital VCO 121, and the digital VCO 121 oscillates a clock having a frequency according to the input signal.

The frequency compensator 112 is used to
4 is an input. The output of the data retainer 104 when the frequency is locked represents an initial frequency error at the time of starting the frequency pull-in. If this value is equal to or larger than a certain value, it indicates that there is a certain error between the frequency at the time of data recording and the frequency at the time of reproduction. At this time, if the recording frequency changes for each zone as in zone bit recording, there is a high possibility that a certain percentage of frequency error will appear for each zone.
In order to perform frequency pull-in at a high speed, it is desirable that the initial frequency error be small.
12 detects a certain initial frequency error amount, the VCO 121 at the time of starting the next frequency pull-in.
Is corrected by the center oscillation frequency corresponding to the initial frequency error amount, and is oscillated.

When the initial frequency error is large, the number of data used for frequency acquisition becomes large, so that it may not be possible to complete the phase acquisition with a given specific pattern. Also in this case, by correcting the center oscillation frequency of the digital VCO 121 at the start of the retry, it is possible to complete the phase pull-in in a specific pattern. With such a configuration, it is possible to further widen the frequency pull-in range, shorten the frequency pull-in time, and shorten the clock reproduction time. Further, since the reproduction clock is generated as it is as a digital signal, a D / A converter is not required, and the circuit scale can be reduced and the signal processing can be performed with higher accuracy.

As described above, according to the fourth embodiment, the frequency lock loop constituted by the digital circuit is added, and the frequency is locked in high speed and high accuracy in advance.
The clock is recovered by performing phase pull-in by the phase locked loop, and the clock recovery is performed by a digital circuit, and the initial oscillation frequency of the VCO can be set from the outside. Phase synchronization can be performed at a high speed, phase synchronization can be performed with a specific pattern having a short pattern length, the area that can be used by the user in the recording / reproducing medium can be increased, and the oscillation frequency of the VCO can be increased. , It is possible not only to quickly pull in the frequency, but also to reduce the circuit scale.

[0094]

As described above, according to the clock recovery apparatus according to the first aspect of the present invention, the analog reproduction signal read from the recording medium is read using the phase synchronization signal recorded in advance on the recording medium. A clock recovery device for recovering a synchronized clock, comprising: a frequency lock detection unit for determining whether or not the analog reproduction signal is in a frequency locked state with the reproduction clock; and a digital signal processing circuit; A first oscillation control means for controlling an oscillation means so as to oscillate a reproduction clock frequency-synchronized with the analog reproduction signal when it is detected that the analog reproduction signal is not in a frequency locked state, and a digital signal processing circuit, When the frequency lock detecting means detects that the frequency is in the locked state, the analog restart is performed. Since the phase synchronization signal included in the signal to and a second oscillation control means for controlling the oscillation means to oscillate the phase-synchronized with a reproduction clock,
Even if a clock delay occurs due to digital processing during high-speed operation, the frequency pull-in range can be widened, and the time required for phase lock can be shortened by performing high-speed frequency pull-in. is there.

Further, according to the clock recovery apparatus of the second aspect of the present invention, a clock synchronized with an analog reproduction signal read from the recording medium is reproduced by using a phase synchronization signal recorded in advance on the recording medium. A clock recovery device that calculates a value proportional to a phase error between the analog reproduced signal and the clock, and outputs a digital value as a digital value. A phase synchronization means for oscillating the phase-synchronized clock, and a frequency error for calculating a value proportional to a frequency error between the analog reproduction signal and the clock using the output of the phase error detection means as input data and outputting the value as a digital value Detection means and the output of the frequency error detection means as input data to detect whether or not the frequency is locked. Frequency lock detecting means, and the frequency locking means for performing frequency locking using the frequency error detected by the frequency error detecting means when not in the frequency locked state. Even if a clock delay occurs, it is possible to obtain a wide frequency pull-in range, and it is possible to shorten the time until phase lock by performing the frequency pull-in at a high speed.

According to the clock recovery device of the third aspect of the present invention, a clock synchronized with an analog reproduction signal read from the recording medium is reproduced using a phase synchronization signal recorded in advance on the recording medium. A phase error detecting means for calculating a value proportional to a phase error between the analog reproduction signal and the clock and outputting the calculated value as a digital value; Frequency error detecting means for calculating a value proportional to the frequency error between the signal and the clock and outputting the calculated value as a digital value; and frequency lock detection for detecting whether or not a frequency lock state is established by using the output of the frequency error detecting means as input data. Means, and an output signal of the frequency error detecting means, using an output signal of the frequency lock detecting means as a control signal. A data holding means for holding over data,
A switch for turning on / off an output signal of the phase error detecting means according to an output signal of the frequency lock detecting means;
A digital loop filter that uses the output of the switch as input data; and a clock recovery unit that recovers the clock using the phase component and frequency component output from the digital loop filter and the output of the data holding unit as input data. Therefore, even if a clock delay occurs due to digital processing during high-speed operation, it is possible to widen the frequency pull-in range, and the time required for phase lock can be reduced by performing high-speed frequency pull-in. The effect is as follows.

According to the clock recovery apparatus of the present invention, a clock synchronized with an analog reproduction signal read from the recording medium is reproduced using a phase synchronization signal recorded in advance on the recording medium. A phase error detecting means for calculating a value proportional to a phase error between the analog reproduction signal and the clock and outputting the calculated value as a digital value; Frequency error detecting means for calculating a value proportional to the frequency error between the signal and the clock and outputting the calculated value as a digital value; and frequency lock detection for detecting whether or not a frequency lock state is established by using the output of the frequency error detecting means as input data. Means, and an output signal of the frequency error detecting means, using an output signal of the frequency lock detecting means as a control signal. A data holding means for holding over data,
A switch for turning on / off an output signal of the phase error detecting means according to an output signal of the frequency lock detecting means;
A digital loop filter that uses the output of the switch as input data, a clock recovery unit that uses the phase component and frequency component output from the digital loop filter and the output of the data holding unit as input data to recover the clock, Frequency correction means for correcting the oscillation frequency of the clock recovery means using the output of the holding means as input data, so that a wide frequency pull-in range can be obtained even if a clock delay occurs due to digital processing during high-speed operation. It is possible to shorten the time required for phase lock by performing frequency pull-in at a high speed, and shorten the time required for phase lock-in by reducing the frequency pull-in time. There is.

According to the clock recovery device of the present invention, in the clock recovery device according to the third or fourth aspect, the frequency error detecting means may include a value proportional to a phase error in a certain fixed time. Is calculated digitally, and only when the absolute value of the difference value is smaller than a predetermined value is cumulative calculation performed to calculate a value proportional to the frequency error. There is an effect that accurate and high-speed frequency pull-in can be performed by using the inclination of.

According to the clock recovery device of the invention of claim 6 of the present application, in the clock recovery device of claim 3 or 4, the frequency error detection means is configured to set a value proportional to a phase error in a certain time. Digital calculation of the difference value, and only when the difference value is smaller than a predetermined maximum value and larger than a predetermined minimum value, the cumulative calculation is executed to calculate a value proportional to the frequency error. There is an effect that accurate and high-speed frequency pull-in can be performed using the gradient of the phase error amount on the axis.

According to the clock recovery apparatus of claim 7 of the present application, in the clock recovery apparatus according to claim 3 or 4, the frequency error detection means has a value proportional to a phase error in a certain fixed time. Is digitally operated, a predetermined correction corresponding to the characteristic of the phase error detecting means is performed on the difference value by the sign of the difference value, and the difference value or the corrected value selected by an external control signal is obtained. Accumulation calculation is performed only when the absolute value of the value is smaller than a predetermined value, and a value proportional to the frequency error is calculated. There is an effect that the frequency pull-in can be performed.

According to the clock recovery device of the present invention, in the clock recovery device according to the fourth aspect, the frequency correction means is proportional to the frequency error output from the frequency error detection means. If the absolute value of the obtained data is larger than a predetermined value, the oscillation frequency of the clock recovery means is corrected at the start of clock recovery, so that the frequency pull-in speed after correction can be improved. The effect is as follows.

Further, according to the clock recovery device of the ninth aspect of the present invention, in the clock recovery device of the fourth aspect, the frequency correction means is proportional to the frequency error output from the frequency error detection means. If the obtained data is larger than a predetermined maximum value or smaller than a predetermined minimum value, it is assumed that the oscillation frequency of the clock reproducing means is corrected at the start of clock reproduction. There is an effect that can be improved.

According to the clock recovery device of the invention of claim 10 of the present application, in the clock recovery device of claim 3 or 4, the clock recovery means includes a phase component output from the digital loop filter and Digital adding means for adding the output of the data holding means, first D / A converting means for converting the output of the digital adding means into an analog signal, and converting the frequency component output from the digital loop filter into an analog signal A second D / A conversion means for converting, an analog addition means for adding an output signal of the first conversion means and an output signal of the second D / A conversion means, And a clock generating means for generating the clock. It is possible to perform the D / A converter without using switch means, there is an effect that can configure devices without increasing the cost.

According to the clock recovery apparatus of the present invention, in the clock recovery apparatus according to the third or fourth aspect, the clock recovery means may include a phase component output from the digital loop filter and a phase component output from the digital loop filter. First digital addition means for adding the output of the data holding means, second digital addition means for adding the output of the first digital addition means and the frequency component output from the digital loop filter, And a digital clock generating means for generating the clock in accordance with the output of the digital adding means of (2), so that the clock reproducing means can reproduce the clock without using the D / A converting means. This has the effect of reducing the size of the device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a clock recovery device according to the present invention.

FIG. 2 is a diagram illustrating a configuration example of a conventional PRML reproduction signal processing circuit.

FIG. 3 is a diagram illustrating a configuration example of a conventional clock recovery device.

FIG. 4 is a diagram showing a phase error amount.

FIG. 5 is a diagram showing a phase error detector output at the time of phase pull-in.

FIG. 6 is a diagram showing a general recording format of a magnetic recording / reproducing apparatus.

FIG. 7 is a diagram showing a phase error detection characteristic of a specific pattern of the phase error detector.

FIG. 8 is a diagram illustrating an output of a phase error detector when a certain frequency error exists.

FIG. 9 is a diagram illustrating a first configuration example of a frequency detection unit according to the present invention.

FIG. 10 is a diagram showing a second configuration example of the frequency detection means in the present invention.

FIG. 11 is a diagram showing a third configuration example of the frequency detection means in the present invention.

FIG. 12 is a block diagram of a clock recovery device according to a third embodiment of the present invention.

FIG. 13 is a diagram illustrating a first configuration example of a frequency correction unit according to the present invention.

FIG. 14 is a diagram showing a second configuration example of the frequency correction means in the present invention.

FIG. 15 is a block diagram of a clock recovery device according to a second embodiment of the present invention.

FIG. 16 is a block diagram of a clock recovery device according to a fourth embodiment of the present invention.

[Explanation of symbols]

 1 Clock Recovery 101 Phase Error Detector 102 Frequency Error Detector 1021a, 1021b Delay Element 1022 Subtractor 1023 Absolute Value Calculator 1024a, 1024b, 1024c Selector 1026 Adder 1027 Sign Judge 1028 Multiplier 103 Frequency Lock Detector 104 Data Holder 105 Switch 106 Loop filter 107, 108 D / A converter 109 Digital adder 110 Analog adder 111 VCO 112 Frequency corrector 1121 Absolute value calculator 1122 Sign determiner 1123a, 1123b, 1123c Comparator 1124a, 1124b, 1124c Selector 1125 Adder 1126 Latch 2 A / D converter 3 PR equalizer 4 AGC 5 LPF 6 Viterbi decoder 7 Decoder 501, 511 Second oscillation control means 502 Frequency lock detection means 503, 513 First oscillation control means 505, 515 Oscillation means 601 Phase error detection means 602, 612 Phase synchronization means 603 Frequency error detection means 604, 614 Frequency pull-in means 605, 615 Clock recovery means 606, 616 Frequency correction means

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Morie 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F term (reference) 5D044 BC01 BC02 CC04 GM12 GM14 GM15 5J106 AA03 BB03 CC20 CC26 CC33 CC41 CC46 DD08 DD33 DD38 EE08 EE15 FF02 KK03 KK05 KK08

Claims (11)

[Claims] 1. A clock recovery apparatus for reproducing a clock synchronized with an analog reproduction signal read from a recording medium by using a phase synchronization signal prerecorded on a recording medium, wherein the analog reproduction signal has a frequency equal to the reproduction clock. Frequency lock detecting means for determining whether or not the apparatus is in a locked state, and a digital signal processing circuit. When the frequency lock detecting means detects that the apparatus is not in the frequency locked state, the frequency is synchronized with the analog reproduction signal. A first oscillation control means for controlling an oscillating means so as to oscillate a reproduction clock; and a digital signal processing circuit, wherein when the frequency lock detection means detects that the frequency is locked, the analog reproduction signal is output. To oscillate the recovered clock phase-synchronized with the phase synchronization signal included in the A clock recovery device comprising: a second oscillation control means for controlling an oscillation means. 2. A clock recovery device for reproducing a clock synchronized with an analog reproduction signal read from the recording medium by using a phase synchronization signal prerecorded on a recording medium, wherein a clock between the analog reproduction signal and the clock is reproduced. Phase error detecting means for calculating a value proportional to the phase error and outputting the calculated value as a digital value; phase synchronizing means for oscillating the clock phase-synchronized with the analog reproduction signal based on the output of the phase error detecting means; Frequency error detection means for calculating an output of the detection means as input data, calculating a value proportional to a frequency error between the analog reproduction signal and the clock, and outputting the value as a digital value; and Frequency lock detecting means for detecting whether or not the frequency is in a locked state; Clock recovery apparatus characterized by comprising a frequency pull means performs frequency pull with the frequency error detected by the frequency error detecting means. 3. A clock recovery device for reproducing a clock synchronized with an analog reproduction signal read from the recording medium using a phase synchronization signal pre-recorded on a recording medium, wherein a clock between the analog reproduction signal and the clock is reproduced. A phase error detection means for calculating a value proportional to the phase error and outputting the value as a digital value; andusing the output of the phase error detection means as input data to calculate a value proportional to a frequency error between the analog reproduction signal and the clock. Frequency error detecting means for outputting as a digital value, frequency lock detecting means for detecting whether or not a frequency lock state is obtained by using an output of the frequency error detecting means as input data, and an output signal of the frequency lock detecting means as a control signal. Data holding means for holding output data of frequency error detecting means, and said frequency lock detecting means The phase a switch for ON / OFF the output signal of the error detecting means, and a digital loop filter which receives data output of the switch, the phase component output from the digital loop filter by the output signal,
A clock recovery device comprising: clock recovery means for recovering the clock by using a frequency component and an output of the data holding means as input data. 4. A clock recovery device for reproducing a clock synchronized with an analog reproduction signal read from the recording medium by using a phase synchronization signal prerecorded on a recording medium, wherein a clock between the analog reproduction signal and the clock is reproduced. A phase error detecting means for calculating a value proportional to the phase error and outputting the value as a digital value; an output of the phase error detecting means as input data to calculate a value proportional to a frequency error between the analog reproduction signal and the clock. A frequency error detection unit that outputs a digital value, a frequency lock detection unit that uses an output of the frequency error detection unit as input data and detects whether or not a frequency is locked, and an output signal of the frequency lock detection unit that is a control signal. Data holding means for holding output data of frequency error detecting means, and said frequency lock detecting means The phase a switch for ON / OFF the output signal of the error detecting means, and a digital loop filter which receives data output of the switch, the phase component output from the digital loop filter by the output signal,
Clock recovery means for recovering the clock using frequency components and the output of the data holding means as input data, and frequency correction means for correcting the oscillation frequency of the clock recovery means using the output of the data holding means as input data. A clock recovery device. 5. The clock recovery device according to claim 3, wherein said frequency error detecting means digitally calculates a difference value of a value proportional to a phase error in a certain time, and determines that an absolute value of said difference value is a predetermined value. A clock recovery device that performs a cumulative calculation and calculates a value proportional to the frequency error only when the value is smaller than 6. The clock recovery device according to claim 3, wherein said frequency error detection means digitally calculates a difference value of a value proportional to a phase error in a certain fixed time, and said difference value is a predetermined maximum value. A clock recovery apparatus for performing a cumulative calculation and calculating a value proportional to a frequency error only when the value is smaller and larger than a predetermined minimum value. 7. The clock recovery device according to claim 3, wherein the frequency error detection means digitally calculates a difference value of a value proportional to a phase error in a certain fixed time, and calculates the difference by a sign of the difference value. A predetermined correction corresponding to the characteristic of the phase error detection means is performed on the value, and cumulative calculation is performed only when the difference value selected by an external control signal or the absolute value of the corrected value is smaller than a predetermined value. A clock recovery device for calculating a value proportional to the frequency error. 8. The clock recovery device according to claim 4, wherein said frequency correction means is configured to output a clock signal when an absolute value of data proportional to a frequency error output from said frequency error detection means is larger than a predetermined value. A clock recovery device for correcting the oscillation frequency of the clock recovery means at the start of reproduction. 9. The clock recovery device according to claim 4, wherein said frequency correction means is configured to output data proportional to a frequency error output from said frequency error detection means when said data is larger than a predetermined maximum value or is smaller than a predetermined minimum value. A clock recovery device for correcting the oscillation frequency of the clock recovery means at the start of clock recovery when the clock recovery is small. 10. The clock recovery device according to claim 3, wherein the clock recovery unit adds a phase component output from the digital loop filter to an output of the data holding unit; A first D / A converter for converting an output of the adder into an analog signal; a second D / A converter for converting a frequency component output from the digital loop filter into an analog signal; Analog adding means for adding the output signal of the converting means and the output signal of the second D / A converting means; and clock generating means for generating the clock corresponding to the output of the analog adding means. A clock recovery device. 11. The clock recovery device according to claim 3, wherein the clock recovery unit includes a first digital addition unit that adds a phase component output from the digital loop filter and an output of the data holding unit. A second digital adding means for adding an output of the first digital adding means and a frequency component output from the digital loop filter; and a digital for generating the clock according to the output of the second digital adding means. A clock recovery device comprising: a clock generation unit.