JP2000200467A - Digital phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a diaital phase-locked loop circuit which has a capture range of wide range and can perform stably synchronized pull-in at high speed. SOLUTION: This circuit is provided with a band pass filter 4 eliminating a DC component from a digital data signal of multi-bits in which sampling is performed by an analog/digital converter 2 during reproduction of a single frequency data region of a data format recorded in a recording medium, a zero cross detector 5 detecting a position at which the output signal and the multi-bits digital data signal cross a zero level and which outputs a zero cross flag, a period counter 6 counting the zero cross flag as a start point, a phase error detector 7 for acquisition detecting a phase error with timing of the output signal, and a phase error detector 8 for tracking detecting a phase error of a multi-bits digital data signal. Phase error signals outputted from both phase error detectors 7, 8 are switched by a changeover switch 9 respectively and supplied to a digital/analog converter 11 from a loop filter 10. A reproducing clock is generated by an oscillator 12 based on the output as reference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase locked loop circuit, and more particularly to a digital phase locked loop used for reproducing a clock for reproducing digital data recorded on an optical disk medium, a magneto-optical disk medium, a magnetic medium or the like. It relates to a droop circuit.

[0002]

2. Description of the Related Art Generally, an optical disk device is well known as one of devices for recording and reproducing digital data.
2. Description of the Related Art When reproducing digital data in an optical disk device, a phase-locked loop (PLL) circuit has conventionally been used to synchronize the phase of a clock component of a reproduction signal with the phase of a reproduction clock. In particular, on a rewritable optical disk medium, there are a plurality of unit blocks called sectors, each of which is composed of a header portion in which address information and the like are written and a data portion for actually recording digital data. The phase-locked loop performs phase synchronization pull-in for each sector. To normally perform such intermittent reproduction, FIG.
As shown in (1), a synchronization pull-in pattern (hereinafter, referred to as a VFO pattern) 23a to 23d is formed in a header portion and a data portion of a sector by a single frequency.
Exists.

In this VFO pattern area, the response characteristic of the phase locked loop circuit is made faster to perform high-speed and stable phase lock-in, and before the end of the VFO pattern area, the response characteristic of the phase locked loop is made slower to reduce noise. By reducing the effects of the above, a synchronized state is maintained and data is reproduced. In FIG. 8, SM 24 is a sector mark indicating a start position of a sector, AM 25 is an address mark indicating a start position of address information, ID 26 is address information indicating an address of a corresponding sector, and PA 27 is a header portion and a data portion. Postamble indicating end point, DM28 is recorded data 2
9 is a data mark indicating the start position of No. 9.

FIG. 9 shows an example of a block configuration of a digital data reproducing circuit in an optical disk device. On the optical disk medium 30, digital data in which consecutive 0s or 1s are restricted to 3 or more and 14 or less, such as an 8-16 modulation method, is recorded. Since the amplitude of a waveform having a high-frequency component is attenuated by interference in accordance with the increase in the recording density in the linear direction of the recording data, the reproduction signal obtained by reproduction by the reproduction means 31 is provided with the waveform equalization means 1. The waveform equalizer 1 performs a correction to emphasize the high frequency components of the reproduced signal. The reproduced signal that has been emphasized in the high frequency range by the waveform equalizing means 1 is binarized by a binarizing means 32 at a predetermined slice level, and is converted into a binary digital signal.

[0005] The phase-locked loop circuit 33 obtains the phase of the reproduced clock which is the free-running frequency.
It is controlled so as to synchronize with the phase of the clock component of the digitized digital signal. That is, the phase locked loop circuit 33 compares the reproduced clock with the phase of the binarized signal by the phase comparator 34, and based on the phase error information output as a result, sets the loop so that the phase error is minimized. The phase of the reproduced clock is changed by a filter 35, an amplifier 36, and a VCO (voltage controlled oscillator) 37.
The response characteristic of the phase locked loop circuit 33 is switched by a loop gain switch 38. Then, the reproduced clock synchronized with the binary signal is supplied to the demodulation circuit 39.
To demodulate digital data.

[0006]

The VFO pattern areas 23a to 23d shown in FIG.
In some cases, the range that can be normally reproduced due to defects, servo processing, signal processing, or the like is limited. Even in such a case, in order to reliably perform phase lock-in, for example, a method of detecting a defect, a sector mark 24, an address mark 25, and a data mark 28 shown in FIG.
Measures have been taken to maximize the use of the FO pattern area.

The above digital data reproducing circuit is suitable for a method of discriminating a recording / reproducing signal into binarized data and demodulating digital data. However, the signal-to-noise ratio of the reproduced signal deteriorates as the density in the linear direction increases. When the remarks become remarkable, there is a problem that the quality of reproduced data is deteriorated. Therefore, as the recording density in the linear direction increases, a signal processing method called partial response maximum likelihood (hereinafter referred to as PRML), which is a signal processing method suitable for high-density recording and reproduction in the linear direction, is adopted. Tend to be adopted. The PRML signal processing method described above is intended to promote a waveform interference intentionally in a reproduced signal, equalize the reproduced signal to a band limited so as to suppress noise enhancement as much as possible, and then follow the known interference rule to determine the most reliable. In this method, data is demodulated by a maximum likelihood decoder that demodulates a likely sequence.

In the case of the above-described PRML signal processing system, data sampled in multiple bits must be generated by a reproduction clock synchronized with the phase of a clock component of the reproduction signal. However, since the conventional phase-locked loop circuit 33 is composed of analog elements, it is not suitable for integration because it is a system in which analog circuits and digital circuits are mixed in a complicated manner. In addition, analog circuits are subject to characteristic variations and aging due to the analog elements that make up them,
It is necessary to sufficiently consider quality control and compensation circuits. For this reason, there has been a problem that the cost of the digital data reproducing apparatus is increased.

On the other hand, if a digital circuit is used to realize a phase-locked loop circuit for clock recovery, the amount of delay in the loop increases as the transfer rate increases. There is a problem that the capture range indicating the size is reduced. This is because when obtaining phase error information from an analog signal, it is possible to handle a continuous time error amount, whereas when obtaining phase error information from digital data after being sampled, the vicinity of a zero cross This is because the phase error information must be inferred from the amplitude value of, and a sufficient continuous area of the phase error signal cannot be secured.

Furthermore, in the case of a rewritable disk having a short VFO pattern area, the possibility that the first half thereof deteriorates with the number of times of writing and the DC offset position is greatly shifted is also increased. Therefore, if the frequency of the reproduced clock and the frequency of the clock component of the reproduced signal are far apart, the phase synchronization pull-in is not completed only in the VFO pattern area, and burst errors during reproduction increase and data quality deteriorates. There was a problem of inviting.

An object of the present invention is to provide a digital phase locked loop circuit having a wide capture range and capable of quickly and stably synchronizing the phase of a reproduced clock and the phase of a clock component of a reproduced digital signal. It is to be.

Another object of the present invention is, in addition to the above object, for digital data in which a pattern signal composed of a single frequency does not exist in the data format of digital information recorded on a recording medium. To provide a digital phase locked loop circuit capable of pulling in synchronization.

Still another object of the present invention is to provide a digital phase locked loop circuit which is easy to integrate, has high reliability and is low in cost, in addition to the above objects.

[0014]

The invention according to claim 1 is
A digital phase locked loop circuit for reading out digital data recorded on a recording medium in a predetermined data format and generating a reproduction clock for obtaining a reproduction digital signal, comprising a single frequency in the data format Based on the acquisition phase error information detected from the single frequency data area and the tracking error phase information currently detected from the random signal data area composed of random signals in the digital data, the phase of the reproduction clock is It is characterized in that the phase of the clock component of the reproduced digital signal is synchronized.

As described above, by synchronizing the phase of the reproduced clock with the phase of the clock component of the reproduced digital signal based on the acquisition phase error information and the tracking phase error information, the continuous area of the phase error curve is changed. Be extended. As a result, the capture range is greatly expanded, and even when the frequency of the reproduced clock and the frequency of the clock component included in the reproduced signal are largely separated, high-speed
In addition, the phase synchronization can be stably performed.

According to a second aspect of the present invention, in the digital phase locked loop circuit according to the first aspect,
A gate generator that outputs a gate signal indicating whether or not the single-frequency data area is being reproduced, an analog-to-digital converter that samples the digital data into a multi-bit digital data signal using a reproduced clock, A band-pass filter that removes a DC component from the sampled multi-bit digital data signal during reproduction of the single-frequency data area; and an output signal of the band-pass filter and the multi-bit digital data signal. A zero-cross detector that detects a position crossing the zero level and outputs a zero-cross flag, a period counter that starts counting from the zero-cross flag as a starting point, and an output of the band-pass filter at a timing obtained from the period counter. An acquisition phase error detector for detecting a phase error from a signal, A tracking phase error detector for detecting a phase error of the multi-bit digital data signal based on the zero cross flag; and a phase error signal output from the acquisition phase error detector and the tracking phase error detector, respectively. A switching device that switches by a gate signal, a loop filter that filters an output signal of the switching device, a digital-to-analog converter that converts an output signal of the loop filter into an analog signal, and an analog output of the digital-to-analog converter. And an oscillator for generating the reproduction clock.

Even when a DC component exists in the sampled multi-bit digital data signal, the DC component is removed by the action of the band-pass filter. Thus, an accurate phase error can be detected in the single frequency data area, and the single frequency data area can be effectively used. In addition, clock reproduction suitable for the PRML signal processing method can be performed.

Further, the invention according to claim 3 is a digital phase locked loop circuit which reads out digital data recorded in a predetermined data format on a recording medium and generates a reproduction clock for obtaining a reproduction digital signal. Based on the phase error information obtained from the prediction of the zero-cross position in the random signal area of the digital data and another phase error information detected from the random signal in the digital data, The phase of a clock component included in a signal is synchronized.

By using the phase error information obtained from the prediction of the zero-cross position in the random signal area of the digital data, the random signal area immediately after the burst error and the digital data in which no single-frequency signal exists in the data format can be used. Also, the continuous region of the phase error curve is extended. As a result, the capture range is greatly expanded, and the phase of the reproduced clock and the phase of the clock component of the reproduced digital signal can be phase-locked with high speed and stability.

Further, the invention according to claim 4 is the invention according to claim 3.
In the digital phase locked loop described in the above, a loop gain controller that outputs a loop gain control gate signal for increasing the phase pull-in capability for a predetermined period from the start of phase pull-in, and the digital data is multi-bit digital data by a reproduction clock An analog-to-digital converter that samples the signal, a zero-cross position estimator that estimates a zero-cross position of random data in the sampled multi-bit digital data signal, an output signal of the zero-cross position estimator and a multi-bit An acquisition phase error detector for detecting phase error information of the random data from the digital data signal, and detecting a position where the sampled multi-bit digital data signal crosses a zero level to output a zero cross flag; Zero cross detector A tracking phase error detector that detects a phase error of the multi-bit digital data signal based on the flag; and a phase gain signal output from the acquisition phase error detector and the tracking phase error detector, respectively. A switch for switching by a control gate signal, a loop filter for filtering an output signal of the switch, a digital-to-analog converter for converting an output signal of the loop filter into an analog signal, and a reference for an analog output of the digital-to-analog converter. And an oscillator for generating the reproduction clock.

By the operation of the zero cross position predictor,
The zero-cross position of random data in the sampled multi-bit digital data signal is predicted, and by using the phase error information obtained from the prediction of the zero-cross position, the random data region and the data format immediately after the burst error are included in the data format. The continuous region of the phase error curve is extended even for digital data in which one frequency signal does not exist.
As a result, the capture range is greatly expanded, and the phase of the reproduced clock and the phase of the clock component of the reproduced digital signal can be phase-locked with high speed and stability.

[0022]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows one embodiment in which a digital phase locked loop circuit according to the present invention is applied to an optical disk device. In FIG. 1, a waveform equalizing means 1 is constituted by, for example, a high-order equiripple filter or the like which can arbitrarily set a boost amount and a cutoff frequency, and emphasizes a high frequency range of an input optical disk reproduction signal. Correction. The output signal of the waveform equalizer 1 is supplied to an analog / digital converter 2. The analog / digital converter 2 includes an oscillator 12
The output signal of the waveform equalizing means 1, which is an analog signal, is sampled into a multi-bit digital signal using the reproduced clock generated by the above.

The multi-bit digital signal sampled by the analog / digital converter 2 is input to a low-frequency component suppression circuit 3 for suppressing low-frequency noise components. The low-frequency component suppression circuit 3 inputs, for example, amplitude information near the zero crossing of the reproduced signal to a low-pass filter, and subtracts the obtained low-frequency component from the input signal in accordance with the correlation of the data. A device having a configuration for suppressing band noise can be used.

The digital phase locked loop circuit shown in FIG. 1 has a gate generator 1 for generating a gate signal indicating whether or not a signal currently being reproduced has a VFO pattern.
3 is provided. The gate generator 13 starts counting from the beginning of the sector by using, for example, a counter using a reproduced clock as a reference signal, and outputs a gate signal for distinguishing a VFO pattern area from a data area at a predetermined location according to the count number. Things can be used. V above
The FO pattern is a pattern in which a 4T pattern (T is a minimum recording unit) is continuously repeated, such as a DVD-RAM (DVD random access memory).

The output signal of the gate generator 13 is
When the signal indicates that the VFO pattern is being reproduced, the output signal of the low-frequency component suppression circuit 3 is input to a BPF (band-pass filter) 4 that removes a DC (direct current) component. The BPF 4 is a digital filter that nullifies a DC component in accordance with the cycle of the VFO pattern. As the digital filter, for example, when the VFO pattern has a 4T continuous waveform, as shown in FIG.
Delay means 14 for delaying by a time corresponding to T
And a subtraction unit 15 for subtracting the output of the delay unit 14 from the current data can be used.

The output signal of the BPF 4 is input to the zero cross detector 5. The zero-cross detector 5 is a circuit for detecting a position where an input signal crosses a zero level. Therefore, when the output signal of the BPF 4 is input to the zero cross detector 5, the zero cross detector 5 outputs a zero cross flag indicating the zero cross position of the output signal of the BPF 4.

The zero-cross flag obtained by the zero-cross detector 5 is supplied to a period counter 6. The cycle counter 6 uses the zero-cross flag as a starting point,
Counting is continuously performed at an arbitrary cycle n proportional to the cycle of the FO pattern signal, and a timing for extracting a phase error signal is generated. Note that the zero-cross detector 5 shown in FIG.
If the VFO pattern has a continuous waveform of 4T, a phase error signal is generated from the signal amplitude in consideration of the fact that the direction crossing the zero level of the reproduced signal alternates between rising and falling every 4T. The polarity at the time of the output may be output at the same time.

The timing signal obtained from the period counter 6 and the output signal of the BPF 4 are input to an acquisition phase error detector 7, and the acquisition phase error detector 7 calculates the phase from data that should be at the zero cross position. Error signal is detected. Here, the above-described acquisition phase error detector 7 is, for example, as shown in FIG. 4A, in a VFO pattern composed of 4T continuous signals,
It has a function of generating a continuous phase error signal of ± 720 °. On the other hand, in the conventional phase error detector, as shown in FIG. 4B, only continuity of about ± 180 ° is guaranteed.

FIG. 5 shows a phase error signal output from the acquisition phase error detector 7 when the frequency of the reproduced clock is different from the frequency of the clock component of the reproduced digital data. From FIG. 5, it can be seen that the sampling data at the zero-cross position can be reliably tracked at the time of phase synchronization even when the frequency is different, so that the continuous region of the phase error signal is expanded.

On the other hand, when the output signal of the gate generator 13 indicates that data other than the VFO pattern is currently being reproduced, the output signal of the low-frequency component suppression circuit 3 is input to the zero-cross detector 5. Like that. As a result, the zero-cross detector 5 outputs a zero-cross flag indicating the zero-cross position. At this time, the obtained zero-cross flag and the output signal of the low-frequency component suppression circuit 3 are input to the tracking phase error detector 8, and the phase error signal is always detected from data near the zero cross.

The phase error signal output from the acquisition phase error detector 7 and the phase error signal output from the tracking phase error detector 8 are input to a switch 9 and correspond to an output signal of a gate generator 13. And is supplied to the loop filter 10. The loop filter 10 operates using these phase error signals as input signals so that the phase of the reproduced clock and the phase of the clock component of the reproduced digital signal are synchronized.

The output signal of the loop filter 10 is converted into an analog signal by a digital / analog converter 11, and the analog signal is supplied to an oscillator 12. The oscillator 12 generates a reproduction clock based on the analog signal. Here, the oscillator 12 may be, for example, a VCO (Voltage Controlled Oscillator) that controls the oscillation frequency with a voltage, or may be a digitally controlled oscillator.
Except for the analog converter, it may be constituted by digital elements.

In the digital phase locked loop circuit having such a configuration, an accurate phase error can be detected even when a DC component exists in the reproduced signal in the VFO pattern area, so that the VFO pattern area can be effectively used. In addition, since the continuous region of the phase error curve can be expanded, the capture range is greatly expanded. This gives
Even when the frequency of the reproduction clock and the frequency of the clock component of the reproduction signal are largely apart, the phase of the reproduction clock and the phase of the clock component of the reproduction digital data can be synchronized quickly and stably. Clock reproduction required for reproducing the recorded digital data becomes possible.

(Second Embodiment) In this embodiment, for example,
For data in which a VFO pattern does not exist in a pattern recorded on an optical disk medium such as a VD-ROM or a CD-ROM, a reproduced signal becomes a random signal. The capture range when synchronizing the phase of the clock component and the phase of the recovered clock is narrow, and if the two frequencies are far apart, it will not be possible to reliably pull in the phase synchronization, or when the phase synchronization is restored immediately after a burst error. This also solves the problem that phase synchronization pull-in using a VFO pattern cannot be performed. FIG. 6 shows the configuration of the present embodiment.

In FIG. 6, the waveform equalizing means 1, analog-to-digital converter 2, and low-frequency component suppressing circuit 3 are the same as those described in the first embodiment shown in FIG. That is, the waveform equalizing means 1 to which the optical disk reproduction signal is input is constituted by, for example, a high-order equal ripple filter or the like which can arbitrarily set the boost amount and the cutoff frequency. Is corrected to emphasize. The output signal of the waveform equalizer 1 is supplied to an analog / digital converter 2. The analog / digital converter 2 includes an oscillator 12
The output signal of the waveform equalizing means 1, which is an analog signal, is sampled into a multi-bit digital signal using the reproduced clock generated by the above.

The multi-bit digital signal sampled by the analog / digital converter 2 is input to a low-frequency component suppressing circuit 3 for suppressing low-frequency noise. The low-frequency component suppression circuit 3 inputs amplitude information near the zero crossing of the reproduced signal to a low-pass filter, as in the first embodiment, and matches the obtained low-frequency component with data correlation. A device having a configuration for suppressing low-frequency noise by subtracting from an input signal by using the above-described method can be used.

In this embodiment, a loop gain controller 16 is provided in any section from the start of the phase acquisition to obtain a strong phase acquisition capability. The loop gain controller 1
6 supplies a control gate signal of a loop gain. For example, the loop gain controller 16 starts counting from the beginning of a sector by a counter using a reproduction clock as a reference signal, and places importance on an acquisition area where a high-speed pull-in is emphasized at a predetermined place according to the count number and stability. A device that outputs a gain control signal for selecting a tracking area can be used. As the loop gain controller 16, a device having a function of performing self-detection of the approach of the frequency of the reproduced clock and the frequency of the clock component of the reproduced digital data and switching the gain can also be used.

In this embodiment, when the output signal of the loop gain controller 16 indicates that the current region is the acquisition region, the polarity of the output signal of the low-frequency component suppression circuit 3 is determined, and the polarity of the output signal at different times is determined. A zero-cross position estimator 17 that outputs a timing signal for predicting data at an original zero-cross position and determining a position for detecting a phase error signal based on multi-valued level information obtained as a result of adding the result of the polarity. Have. Then, the timing signal obtained from the zero-cross position estimator 17 and the low-frequency component suppression circuit 3
Is input to the acquisition phase error detector 7, and the phase error signal is detected from data that should be at the zero cross position.

Here, the zero-crossing position estimator 17 calculates, for example, four consecutive times as a + b * D + b * D ² + a * D ³ (D ⁿ is nT with respect to the reference time) as a PRML signal processing method. A PR (a, b, b, a) ML system having a transmission characteristic represented by the following equation is used. When there is no signal of 3T or less as a data format such as a DVD or a CD as the zero-cross position estimator 17, a device having a configuration as shown in FIG. 7 can be used, for example.

The zero-cross position predictor 17 shown in FIG.
A delay unit 18 for delaying the input signal by 1T, an addition unit 19 for adding the input signal and the delay unit 18, and an output signal of the addition unit 19, if the polarity is positive, 1
A conversion means 20 for outputting 0 if negative;
Delay means 21a, 21 for delaying the output signal of
b, 21c, conversion means 20, and delay means 21a, 21
and an adding means 22 for adding output signals of four consecutive times b and 21c. The zero-crossing position predictor 17 specifies, for example, a position at 2 as a zero-crossing position based on five levels of levels 0 to 4 having correlation with the input signal obtained from the adding means 22, and Output a signal.

When the output signal of the loop gain controller 16 indicates that the tracking area is currently being reproduced, the output signal of the low-frequency component suppression circuit 3 is input to the zero-cross detector 5, The zero cross flag, which is a signal indicating the zero cross position, is obtained. At this time,
The obtained zero-cross flag and the output signal of the low-frequency component suppression circuit 3 are input to the tracking phase error detector 8, and the phase error signal is always detected from data near the zero cross.

The phase error signal output from the acquisition phase error detector 7 and the phase error signal output from the tracking phase error detector 8 are input to the switch 9 and output from the loop gain controller 16. And is supplied to the loop filter 10. The loop filter 10 uses the phase error signal as an input signal,
The operation is performed so that the phase of the reproduced clock and the phase of the clock component of the reproduced digital signal are synchronized.

The output signal of the loop filter 10 is converted into an analog signal by a digital / analog converter 11, and the analog signal is supplied to an oscillator 12.
The transmitter 12 generates a reproduction clock based on the analog signal. Here, the oscillator 12 may be, for example, a VCO (Voltage Controlled Oscillator) that controls the oscillation frequency with a voltage, or a digital element excluding a digital-to-analog converter. You may.

According to the present embodiment, the continuous range of the phase error curve can be expanded even for digital data in which a pattern signal composed of a single frequency does not exist in the data format, so that the capture range is greatly expanded. Even when the frequency of the reproduced clock and the frequency of the clock component of the reproduced signal are largely separated from each other, the phase of the reproduced clock and the phase of the clock component of the reproduced digital data can be synchronized quickly and stably. The clock reproduction required for reproducing the digital data recorded in the. Further, it is possible to shorten the re-locking time when re-locking the phase due to a defect or the like, and it is possible to minimize the deterioration of the reproduction data quality due to a burst error or the like.

[0046]

According to the present invention, an accurate phase error can be detected even when a DC component exists in a reproduced signal in a pattern region constituted by a single frequency.
Not only can the pattern area be used effectively, the continuous area of the phase error curve can be expanded, the capture range can be greatly expanded, and even when the frequency of the reproduced clock and the frequency of the clock component of the reproduced signal are far apart, The phase of the reproduction clock and the phase of the clock component of the reproduction digital data can be synchronized at high speed and stably.

Further, according to the present invention, by using the zero-cross position predictor, the continuous area of the phase error curve can be extended even for digital data in which a single frequency signal does not exist in the data format. Not only makes it possible to synchronize the phase of the reproduced clock with the phase of the clock component of the reproduced digital data at high speed and stably, but also to re-lock the phase when re-locking the phase due to a defect or the like. Can be reduced, and deterioration of the reproduction data quality due to a burst error or the like can be minimized.

Further, by digitizing the phase-locked loop, it becomes easy to integrate it when it is realized as an IC.
Since clock reproduction suitable for the RML signal processing method can be performed, a system suitable for high-density recording and reproduction can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a digital phase locked loop circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of the BPF of FIG. 1;

FIG. 3 is an explanatory diagram showing a relationship between a count operation of a period counter of FIG. 1 and a phase error signal.

FIG. 4 is an explanatory diagram of a continuity of a phase error signal in the digital phase locked loop circuit according to the first embodiment of the present invention and a conventional phase locked loop.

FIG. 5 is an explanatory diagram of a phase error signal output from the acquisition phase error detector of FIG. 1 under different synchronization frequencies.

FIG. 6 is a block diagram showing a configuration of a digital phase locked loop circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration example of a zero-cross position predictor in FIG. 6;

FIG. 8 is an explanatory diagram of a data format inside a sector in an optical disk reproducing device (DVD-RAM).

FIG. 9 is a block diagram showing a configuration of a conventional optical disc reproducing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Waveform equalization means 2 Analog-digital converter 3 Low frequency component suppression circuit 4 Bandpass filter (BPF) 5 Zero cross detector 6 Period counter 7 Phase error detector for acquisition 8 Phase error detector for tracking 9 Switching device 10 Loop Filter 11 Digital / Analog Converter 12 Oscillator 13 Gate Generator 14 Delay Means 15 Subtraction Means 16 Loop Gain Controller 17 Zero Cross Position Predictor 18 Delay Means 19 Addition Means 20 Conversion Means 21a to 21c Delay Means 22 Addition Means 23a to 23d VFO Pattern Area 24 sector mark 25 address mark 26 address information area 27 postamble 28 data mark 29 recording data area 30 optical disk medium 31 reproducing means

Claims (4)

[Claims] 1. A digital phase locked loop circuit for reading digital data recorded on a recording medium in a predetermined data format and generating a reproduction clock for obtaining a reproduction digital signal, comprising: Based on the acquisition phase error information detected from the single-frequency data area constituted by the frequency and the now-tracking phase error information detected from the random signal data area constituted by the random signal in the digital data, A digital phase locked loop circuit wherein the phase of a reproduced clock is synchronized with the phase of a clock component of a reproduced digital signal. 2. A gate generator for outputting a gate signal indicating whether or not the single-frequency data area is being reproduced, and an analog / digital converter for sampling the digital data into a multi-bit digital data signal by a reproduction clock. A digital converter; a band-pass filter for removing a DC component from the sampled multi-bit digital data signal during reproduction of the single-frequency data area; an output signal of the band-pass filter and a multi-bit filter. A zero-crossing detector that detects a position where the digital data signal crosses a zero level and outputs a zero-crossing flag, respectively; a period counter that starts counting from the zero-crossing flag as a starting point; Acquisition stage for detecting phase error from output signal of pass-through filter An error detector, a tracking phase error detector that detects a phase error of the multi-bit digital data signal based on the zero cross flag, and an output from the acquisition phase error detector and a tracking phase error detector, respectively. A switch for switching a phase error signal by the gate signal, a loop filter for filtering an output signal of the switch, a digital-analog converter for converting an output signal of the loop filter into an analog signal, and a digital-analog converter. The digital phase-locked loop circuit according to claim 1, further comprising: an oscillator that generates the reproduction clock based on an analog output. 3. A digital phase locked loop circuit for reading digital data recorded in a predetermined data format on a recording medium and generating a reproduction clock for obtaining a reproduction digital signal, wherein a random signal area of the digital data is provided. Based on the phase error information obtained from the prediction of the zero-crossing position and another phase error information detected from the random signal in the digital data, the phase of the reproduced clock and the phase of the clock component of the reproduced digital signal are calculated. A digital phase locked loop circuit characterized in that synchronization is performed. 4. A loop gain controller for outputting a loop gain control gate signal for increasing a phase pull-in capability for a predetermined period from the start of phase pull-in, and sampling the digital data into a multi-bit digital data signal by a reproduction clock. An analog-to-digital converter, a zero-cross position estimator for estimating a zero-cross position of random data in the sampled multi-bit digital data signal, an output signal of the zero-cross position estimator and the multi-bit digital data signal And a phase error detector for acquisition for detecting phase error information of the random data, and a zero cross detection for detecting a position where the sampled multi-bit digital data signal crosses a zero level and outputting a zero cross flag. Multi-bit based on the zero cross flag A tracking phase error detector for detecting a phase error of the digital data signal; and a switch for switching the phase error signals respectively output from the acquisition phase error detector and the tracking phase error detector by the loop gain control gate signal. A loop filter for filtering an output signal of the switching device; a digital-to-analog converter for converting an output signal of the loop filter to an analog signal; and generating the reproduction clock based on an analog output of the digital-to-analog converter. The digital phase locked loop circuit according to claim 3, further comprising an oscillator.