JPH08315517A - Data reproduction system for data recorder/reproducer - Google Patents

Abstract

PURPOSE: To prevent the reproduction efficiency of a data having degraded S/N ratio from lowering, in a data reproduction system using a PRML system read channel, by stabilizing the initial phase pull-in operation for generating a read sync clock required for data reproduction, thereby realizing an intended phase pull-in time. CONSTITUTION: When read data reproduction is executed through a PRML system read channel, phase pull-in operation of a PLL circuit 90 is started. During the phase pull-in operation, a phase error detection circuit 10 executes phase error detecting operation within a phase comparison range of ±360 (deg) using a 4T pattern data according to PR equalization characteristics, i.e., expected data series, as phase comparison reference data. With such constitution, the phase pull-in operation is finished within the range of preamble data in PLL sink area even for a read data having degraded S/N characteristics and the phase lock can be completed within an intended range of phase pull-in time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing processing system of a disk recording / reproducing apparatus which is used for a magnetic disk apparatus and adopts a PRML system signal processing technique.

[0002]

2. Description of the Related Art In recent years, a PRML (Partial Response M) has been used as a data reproduction processing system for a disk recording / reproducing apparatus such as a hard disk apparatus (HDD).
A channel using a read channel of an Axium Likelihood system has been developed. The PRML type read channel is a PR equalization processing circuit (PR equalizer) that gives inter-code interference according to PR characteristics (PR4, EPR4, etc.) to a read signal read from a disk by a head, and ML (maximum likelihood) decoding. System Viterbi (vit
erbi) has a decoder.

As shown in FIG. 4, the PRML type read channel has an amplifier (VGA) having a gain adjusting function.
2, low-pass filter (LPF) 3, A / D converter 4, PR equalizer 5, Viterbi decoder 6, and PL
It has an L circuit 9.

The VGA 2 is gain-adjusted by a gain detection circuit 8 and an automatic gain controller (AGC) 7,
This is an amplifier for keeping the level of the read signal from the head amplifier 1 constant. The LPF 3 removes high frequency noise from the read signal. The A / D converter 4 is, for example, a flash type (parallel type) and converts an analog read signal into digital data.

The PR equalizer 5 is an A / D converter 4
PR (P
The digital filter has a digital filter for executing a waveform equalization process in accordance with the artificial response characteristic.
The Viterbi decoder 6 is a maximum likelihood (ML) estimation decoding circuit that detects a maximum likelihood data series (most probable series) from PR equalized digital data (code data string) based on the Viterbi algorithm. .

The data series DD detected by the Viterbi decoder 6 is decoded into recording data such as an NRZ code by a recording decoder (not shown) and sent to the disk controller (HDC).

The PLL circuit 9 has a phase locked loop A
It is a circuit for generating a read synchronization clock (sampling clock) TC for executing digital signal processing such as A / D conversion processing of the / D converter 4.

The mode switching circuit 13 has a switching signal R / N.
In response to R, the phase pull-in mode of the PLL circuit 9 (N
R) is turned on to the V / I converter 12 side, and is turned on to the charge pump 17 side in the data read mode (R).

That is, in the phase pull-in mode (NR),
Phase error detection circuit 10 which is a digital phase detection circuit
Detects the phase error of the digital data (Yn) from the PR equalizer 5 at the sampling time (n points shown in FIG. 5) based on the level determination value (Xn) from the PLL sync (sync) level determination circuit 18. To do.

The read data Yn is, as shown in FIG.
It is preamble data composed of a repetitive frequency pattern recorded in a PLL sync area provided at the head of each data sector on the disc. The PLL circuit 9 is
Using this preamble data, the synchronization clock TC
Phase acquisition (acquisitio) to generate
n) Perform the operation.

The preamble data has a PR characteristic (PR
For example, it is a 4T pattern (the level of the identification point data is 1, 1, -1, -1) according to 4). FIG. 5 shows sampling data SD at four points from which the phase error has been eliminated.

As described above, the read data (Yn) and the level judgment value (X
In n), if the phase error detection gradient is “τn”, the relational expression of τn = −Yn * X (n−1) + Y (n−1) * Xn (1) holds. However, when Yn ≧ 0, Xn = 1, and when Yn <0, Xn = −1.

As shown in FIG. 6, the phase error detection circuit 10 has the above relational expression (1) with respect to the phase error amount [deg].
The detection data corresponding to the detection gradient “τn” obtained by The phase error detection circuit 10 is ± 180 [d
Eg] has a phase comparison range for the phase error.

The phase error detection circuit 10 compares the read data phase based on the level judgment value from the data level detection circuit 20 by the level switching circuit 19 at the time of tracking T compared to the phase pull-in (A). Run. The level switching circuit 19 operates by the switching signal A / T controlled by the timer data set in the register provided inside the read channel.

The switching signal A is a control signal output from the HDC in synchronization with the turning on of the read gate.
When the phase pull-in operation of the PLL circuit 9 is completed, the PLL sync level determination circuit 18 is turned off and the data level detection circuit 20 is turned on.

In the data read mode (R), the phase comparison circuit 16 detects a phase error between the reference clock RC and the read synchronization clock TC from the VCO (voltage controlled oscillator) 14. The charge pump circuit 17 and the loop filter 15 are circuits for converting the output phase difference of the phase comparison circuit 16 into a current and converting the current into a voltage.
That is, the loop filter 15 includes the charge pump circuit 17
Alternatively, the current from the V / I converter 12 is converted into a voltage and output to the VCO 14.

On the other hand, in the phase pull-in mode (NR),
The V / I converter 12 converts the output voltage of the D / A converter 11 into a current and outputs the current to the loop filter 15.
The D / A converter 11 includes the phase error detection circuit 10 described above.
The output of is converted to analog (voltage).

[0018]

[Problems to be Solved by the Invention]
Since the read channel of the system is particularly suitable for data reproduction from a disc having a high recording density, there is a high possibility that a read signal with deteriorated S / N characteristics will be input. The PLL circuit 9 of the read channel executes the phase pull-in operation of the read data whose S / N characteristic is deteriorated. However, due to the deterioration of the waveform quality due to noise, the compared data is transferred from the target phase lock point to the above-mentioned phase lock point. The phase comparison range of ± 180 [deg] may be exceeded and the state of comparison with an adjacent clock may occur.

In order to pull the initial phase error from the state of phase comparison with the adjacent clock to the phase locked state within a target time, it is necessary to set the loop gain of the PLL circuit 9 high and pull back the overshoot amount at high speed. is there. However, in the PRML type read channel, the circuit delay from the sample point of the A / D converter 4 to the phase comparison point is large, and if the loop gain is too high, the oscillation state occurs, so it is not possible to simply set the loop gain high. Can not. Therefore, the phase comparison point is ± 18
When the phase comparison range of 0 [deg] is exceeded,
It takes a lot of time until the phase is locked, and there is a high possibility that the phase pull-in operation will not end within the range of the preamble data in the PLL sync area.

It is an object of the present invention to stabilize an initial phase pull-in operation for generating a read synchronization clock necessary for data reproduction processing in a data reproduction processing system using a PRML system read channel. The purpose is to realize the phase pull-in time and prevent a decrease in the efficiency of the reproduction process of the data whose S / N ratio has deteriorated as a result.

[0021]

SUMMARY OF THE INVENTION The present invention is a data reproducing processing system for a disk recording / reproducing apparatus using a PRML type read channel, wherein a time period for a phase pull-in operation of a PLL circuit provided in the read channel is provided. A system having means for completing within.

This means includes a signal pattern output means for outputting an expected value data series which is, for example, 4T pattern data according to the PR equalization characteristic used as the phase comparison reference data during the phase pull-in operation of the PLL, and the read data. The phase error detection means outputs phase error detection data for detecting a phase error with the 4T pattern data and performing a phase pull-in operation.

[0023]

According to the present invention, since the PRML type read channel executes the reproduction process of the read data, the phase pull-in operation of the PLL circuit is started. The phase pull-in operation is completed by detecting the phase error of the preamble data pre-recorded in the PLL sync area on the disc and phase-locked so that the phase error becomes zero. The phase error detecting means of the present invention uses the PR used as the phase comparison reference data.
An expected value data series that is, for example, 4T pattern data according to the equalization characteristic is used, and as a result, the phase error detection operation is executed in the phase comparison range of ± 360 [deg]. As a result, even when the phase pull-in operation of the read data with deteriorated S / N characteristics is executed, the phase pull-in operation ends within the range of the preamble data of the PLL sync area, and the phase lock is performed within the target phase pull-in time range. Can be completed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a PRML read channel according to this embodiment, and FIGS. 2 and 3 are characteristic diagrams for explaining the operation of this embodiment. (Structure of Read Channel of PRML System) In this embodiment, a read channel of the PRML system used in the HDD, for example, a channel for performing PR equalization processing according to the PR characteristics of PR4 (or EPR4) is assumed. There is.

The characteristics of the read channel of this embodiment are shown in FIG.
As shown in, the PLL circuit 90 has a PLL sync pattern output circuit 21, a zero cross comparator 22, and a zero phase start circuit 23.

That is, the zero-cross comparator 22 has L
The zero cross point of the analog read signal output from PF3 is detected, and as shown by the dotted line in FIG. 2, a detection pulse ZC that is a zero cross clock that inverts at the zero cross point is output.

Here, the LPF 3 removes high frequency noise from the read signal from the head amplifier 1 held at a constant level by the VGA 2 and outputs it. A / D converter 4
Converts the read signal from the LPF 3 into digital data in synchronization with the sampling clock TC that is the read synchronization clock output from the VCO 14 of the PLL circuit 90.

The PR equalizer 5 is an A / D converter 4
PR (P
The waveform equalization processing according to the artial response characteristic is executed. Furthermore, the Viterbi decoder 6 is
The maximum likelihood data series is detected from the PR equalized digital data (code data string) in synchronization with the sampling clock TC output from O14, and the detected data series DD is output to a recording decoder (not shown). To do.

In the PLL circuit 90, the zero-cross comparator 22 supplies the detection pulse Z to the zero-phase start circuit 23.
Output C. The zero phase start circuit 23 uses the detection pulse ZC as a zero phase start timing,
The start phase error of the PLL circuit 90 is forced to 0. The zero phase start circuit 23 includes a delay circuit that delays the edge of the detection pulse ZC by 1/2 cycle.

The zero-phase start circuit 23 temporarily stops the output of the VCO 14 at the start of the phase pull-in operation of the PLL circuit 90, and the phase error detection circuit which is substantially a digital phase detection circuit by the switching signal R / NR. The circuit 10 is turned off. Then, the output of the VCO 14 is restarted with the edge of the detection pulse ZC as the timing of zero phase start, and the phase pull-in mode (NR) is restarted by the switching signal R / NR.

On the other hand, the PLL sync pattern output circuit 21
Is turned on by the level switching circuit 19 during the phase pull-in (A), and the phase equalization characteristic (PR)
4T pattern (the level of the identification point data is 1, 1, -1, -1) which is an expected value data series according to 4) is output.

In the phase pull-in mode (NR), the phase error detection circuit 10 has the PLL sync pattern output circuit 21.
The phase error of the preamble data (Yn) which is the digital data from the PR equalizer 5 at the sampling time point (n points shown in FIG. 2) is detected based on the 4T pattern data (Xn).

The D / A converter 11 converts the output of the phase error detection circuit 10 into analog (voltage). The V / I converter 12 converts the output voltage of the D / A converter 11 into a current and outputs the current to the loop filter 15. VCO1
4 changes the oscillation frequency according to the output voltage from the loop filter 15 and executes a phase pull-in operation for generating the synchronous clock TC.

In the data read mode (R), the phase comparison circuit 16 detects a phase error between the reference clock RC and the read synchronization clock TC from the VCO (voltage controlled oscillator) 14. The charge pump circuit 17 and the loop filter 15 convert the output phase difference of the phase comparison circuit 16 into a current, convert the current into a voltage, and output it to the VCO 14. (Phase Pull-In Operation) In the present embodiment, in the phase pull-in mode, the preamble data Yn of the PLL sync area as the read data has the 4T pattern (1, 1, -1,
-1) is read in this order.

The detection pulse ZC from the zero-cross comparator 22 is, as shown in FIG.
Data SD corresponding to the first "1" of (1, -1, -1)
On the other hand, it is inverted and rises at a position preceding by 1/2 cycle. The zero phase start circuit 23 delays the edge of the detection pulse ZC by 1/2 cycle and uses it as a timing signal for zero phase start.

That is, the zero phase start circuit 23 is
At the start of the phase pull-in operation of the L circuit 90, the VCO 14
Output is temporarily stopped, and the phase pull-in mode (NR) is restarted in synchronization with the timing signal. Therefore, the mode switching circuit 13 is turned on to the V / I converter 12 side according to the switching signal R / NR to restart the phase pull-in mode (NR) of the PLL circuit 9.

In this embodiment, the phase error detection circuit 10 is
Instead of the conventional level determination value (Xn), a 4T pattern, which is an equalized signal pattern according to the PR equalization characteristic output from the PLL sync pattern output circuit 21, is used as reference data, and read from the PR equalizer 5. Data Y
Detect the phase error of n.

The preamble data which is the read data Yn is, so to speak, an expected value data series, and is always (1, 1,
-1, -1) are input in this order, so X (n-2), X
The values of (n-1), Xn, and X (n + 1) are (-1, -1,
Rewrite as 1, 1).

Here, if the above-mentioned relational expression (1) is compared once for every two samples, τn = (-Yn * (-1) + Y (n-1) * (+ 1)) + (Y (n The relational expression of -1) * (-1) + Y (n-2) * (-1) ... (2) is established.

That is, as shown in FIG. 3, the phase error detection circuit 10 detects the detection data corresponding to the phase error detection gradient "τn" obtained by the relational expression (2) with respect to the phase error amount [deg]. Output DE. That is, the phase error detection circuit 10 has a phase comparison range for a phase error of ± 360 [deg].

In FIG. 3, the detection data indicated by the dotted line is
It is a phase error detection result when the conventional level determination value (Xn) is used. Here, X (n-2) and X (n-
1) and Xn are +1 and X (n + 1) when Yn ≧ 0
= + 1, and when Yn <0, X (n + 1) =-1.

When the conventional level judgment value (Xn) is used, the phase comparison range of the phase error detection circuit 10 is ± 180 [deg] as described above (see FIG. 6). Therefore, when the read data Yn, which is the compared data, exceeds the phase comparison range of ± 180 [deg] from the target phase lock point or the level determination is reversed due to deterioration of the waveform quality due to noise. Is in a state of being compared with the adjacent clock. Therefore, although it is originally the clock to be pulled in to the first (+1) of the preamble pattern (1, 1, -1, -1),
Since it is pulled in to the adjacent clock, the phase pull-in operation is performed in the opposite direction.

If the loop gain of the PLL circuit is increased,
However, if the loop gain cannot be increased, the next phase comparison causes noise to enter the phase comparison range of the adjacent (original) clock again, and the phase is pulled in the opposite direction. Although the phase synchronization lock is completed by repeating this phase pull-in operation, the conventional method causes a state where the phase synchronization lock is not completed within the range of the preamble data.

On the other hand, in this embodiment, the phase comparison range for the phase error is ± 360 [deg] for the phase error detection gradient "τn". Therefore, even if a large noise influences the read data Yn during the initial phase pull-in operation, the phase comparison operation can be performed within the range of ± 360 [deg]. Therefore, the phase pull-in operation should always be continued in the same direction. You can As a result, the phase pull-in time until the completion of the phase lock can be suppressed within the target time, and the phase pull-in operation can be ended within the range of the preamble data in the PLL sync area.

[0045]

As described in detail above, according to the present invention, P
In the data reproduction processing system using the read channel of the RML system, the initial phase pull-in operation in the PLL circuit is stabilized without making the loop gain particularly high, thereby completing the phase synchronization lock within the target phase pull-in time range. can do. Therefore, even when the reproduction process of the read data whose S / N ratio is deteriorated is executed, it is possible to prevent the efficiency of the reproduction process from being lowered due to the delay of the phase pull-in time of the PLL circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a PRML read channel according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram of read data for explaining the operation of the present embodiment.

FIG. 3 is a characteristic diagram for explaining a phase error detection operation of the present embodiment.

FIG. 4 is a block diagram showing a main part of a read channel of a conventional PRML system.

FIG. 5 is a characteristic diagram of read data for explaining the operation of the conventional PLL circuit.

FIG. 6 is a characteristic diagram for explaining a phase error detection operation of a conventional PLL circuit.

[Explanation of symbols]

1 ... Head amplifier, 2 ... VGA, 3 ... Low pass filter (LPF), 4 ... A / D converter, 5 ... PR equalizer, 6 ... Viterbi decoder, 7 ... AGC, 8 ... Gain detection circuit, 9, 90 ... PLL circuit 10 ... Phase error detection circuit, 11 ... D / A converter, 12 ... V / I converter, 13 ... Mode switching circuit, 14 ... VCO, 15 ... Loop filter, 16 ... Phase comparison circuit, 17 ... Charge pump, 20 ... Data level detection circuit, 21 ... PLL sync pattern output circuit, 22 ... Zero cross comparator, 23 ... Zero phase start circuit.

Claims (4)

[Claims] 1. A data reproducing processing system of a disk recording / reproducing apparatus using a PRML read channel, wherein VCO means for outputting a read synchronizing clock necessary for data reproducing processing, and a PLL for generating the read synchronizing clock. Of the preamble data prerecorded in the PLL sync area of the disc during the phase pull-in operation of
Read data output means for outputting after performing waveform equalization processing according to the equalization characteristic, and an expected value data series according to the PR equalization characteristic used as phase comparison reference data during the phase pull-in operation of the PLL. And a phase error detection between the read data from the read data output means and the expected value data series.
And a phase error detection means for outputting phase error detection data for executing a phase pull-in operation. 2. A data reproduction processing system for a disk recording / reproducing apparatus, which uses a PRML read channel and has a PLL circuit provided in the read channel for generating a read synchronization clock required for data reproduction processing, The preamble data, which is provided in the PLL circuit and is pre-recorded in the PLL sync area of the disc, is output after performing the A / D conversion process and the waveform equalization process according to the PR equalization characteristic during the phase pull-in operation of the PLL. Read data output means for detecting the phase error of the read data during the phase pull-in operation of the PLL, which is ± 360 [deg].
And a phase error detecting means for executing a phase error detecting operation within the phase comparison range of 1. in the data reproduction processing system of the disk recording / reproducing apparatus. 3. A data reproducing processing system for a disk recording / reproducing apparatus using a PRML read channel, wherein VCO means for outputting a read synchronizing clock required for data reproducing processing, and a PLL for generating the read synchronizing clock. Of the preamble data prerecorded in the PLL sync area of the disc during the phase pull-in operation of
Read data output means for outputting after performing waveform equalization processing according to the equalization characteristic, and an expected value data series according to the PR equalization characteristic used as phase comparison reference data during the phase pull-in operation of the PLL. Signal pattern output means, zero phase start processing means for executing a zero phase start processing for determining the order of the expected value data series at the start of the phase pull-in operation of the PLL, and execution of the zero phase start processing. And a phase error detection means for outputting phase error detection data for the VCO means to execute a phase pull-in operation, after which phase error detection between the read data from the read data output means and the expected value data series is executed. A data reproduction processing system for a disk recording / reproducing apparatus, comprising: 4. A data reproducing processing system of a disk recording / reproducing apparatus using a read / write channel of PRML system, wherein VCO means for outputting a read synchronization clock necessary for data reproducing processing, and phase at the phase pull-in operation of said PLL. Signal pattern output means for outputting an expected value data series according to the PR equalization characteristic used as comparison reference data, and pre-recorded in the PLL sync area of the disc at the time of the phase pull-in operation of the PLL for generating the read synchronization clock. A / D conversion processing and PR of the selected preamble data
Read data output means for outputting after performing waveform equalization processing according to equalization characteristics, zero cross detection means for detecting zero cross points of the analog preamble data before the A / D conversion processing, and zero cross detection means A phase for detecting a phase error between the expected value data series and the read data from the read data output means in accordance with the output clock of the VCO means, and outputting the phase error detection data for the VCO means to execute the phase pull-in operation. A data reproducing processing system for a disk recording / reproducing apparatus, comprising: an error detecting means.