JP2001319427A - Information reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such problem that, formerly, since information of original information point can not be used, it is difficult to obtain digital data having high reliability. SOLUTION: This information reproducing device is provided with a zero level detector 7 detecting a zero level from a reproducing signal, a binarization circuit 8 binarizing the reproducing signal based on the zero level, a PLL circuit 9 generating such a bit synchronizing clock as to making a point whose phase is shifted by 180 degrees from the zero crossing timing of the reproduced signal a sampling point based on the binarizing signal, an A/D converter 2 sampling the reproduced signal with the bit synchronizing clock, a digital equalizer 3 equalizing the waveform of the output signal of the A/D converter 2, a prediction value generating circuit 5 generating a prediction value from the output signal of the digital equalizer 3 and a Viterbi decoder 6 performing the maximum likelihood decoding of the digital data of the digital equalizer 3 by using the prediction value. Then, the device can perform a decoding processing having an excellent S/N characteristic and can perform a satisfactory decoding even to the signal having a low S/N ratio of a reproduced RF signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus for reproducing digitally recorded information recorded on a CD, a DVD or the like.

[0002]

2. Description of the Related Art A conventional information reproducing apparatus will be described with reference to the drawings. FIG. 10 shows, for example, JP-A-11-20
FIG. 1 is a block diagram illustrating a configuration of a conventional information reproducing device disclosed in Japanese Patent No. 3795.

In FIG. 10, 11 is an AGC circuit (variable gain amplifier), 12 is a waveform equalizer, 13 is an A / D converter, 14 is a level adjusting circuit, 15 is a predicted value generating circuit,
6 is a Viterbi decoder, 17 is a zero level detector, 18 is 2
The value conversion circuit 19 is a PLL circuit.

In a conventional information reproducing apparatus, a reproduction RF
The signal is adjusted by the AGC circuit 11 so that the amplitude of the envelope is constant, the waveform distortion is corrected by the waveform equalizer 12, and the signal is converted into digital data by the A / D converter 13.

The level adjustment circuit 14 detects a maximum value and a minimum value from the output of the waveform equalizer 12 and generates a set value of the AGC circuit 11 for keeping the amplitude of the digital data envelope constant. .

From the digital data output from the A / D converter 13, a predicted value generating circuit 15 generates five predicted values, and a Viterbi decoder 16 converts the digital data based on the predicted values into Viterbi decoding. Thus, a reproduced code sequence is generated.

At this time, the bit synchronization clock used for conversion in the A / D converter 13 uses the output of the zero level detector 17 for detecting a slice level (zero level) as a reference, and the binary synchronization circuit 18 generates a waveform or the like. 2 output
Based on the binarized signal that has been binarized, it is generated in the PLL circuit 19 in synchronization with the zero-cross timing (rising and falling edges of the binarized signal).

FIG. 11 shows the relationship between the sampling timing in the A / D converter 13 and the eye pattern of the RF signal after waveform equalization.

As described above, in the conventional information reproducing apparatus, the sampling point is adjusted so as to synchronize with the zero cross point as shown in FIG. For this reason, the prediction values used for the branch metric calculation of the Viterbi decoder 16 also include three types of signals such as 0, +, and-,
An odd number of signals including a zero level has been used, such as five types of signals such as levels U, MU, 0, -ML, and -L as shown in FIG.

However, the original information point of the reproduced signal is not a zero cross point but a position shifted by 180 degrees from this point, and the information of the original information point cannot be used in Viterbi decoding in a conventional information reproducing apparatus. There was a problem.

FIG. 12 shows an actual DV under relatively good conditions.
In the RF signal obtained by reading D, the level distribution (a) of the sample point at the zero cross point and the 180
An example of a level distribution (b) at a sample point at a point shifted by a degree is shown.

In the case where a sample point at a point shifted from the zero cross by 180 degrees is used, as shown in FIG. 12B, six types of peaks are formed, and particularly, two peaks at the center have sharp peaks. On the other hand, when a sample point synchronized with the zero cross point is used, as shown in FIG.
Except for the peak at zero level, the peak is separated into two parts, and the distribution is spread around.

In Viterbi decoding, a branch metric is calculated based on a distance or a square error between a predicted value and an input value.
Since the foremost decoding is performed by sequentially selecting paths that minimize the accumulated path metric, this means that the S / N-BER characteristic when performing Viterbi decoding in a conventional information reproducing apparatus is reduced. It causes deterioration.

[0014]

In the conventional information reproducing apparatus as described above, the information of the original information point cannot be used. Has a problem that it is difficult to obtain highly reliable digital data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to perform a decoding process having an excellent S / N characteristic without increasing the size of the apparatus and significantly increasing the cost.
An object of the present invention is to provide an information reproducing apparatus capable of performing good decoding even for a signal having a low S / N ratio of an F signal.

[0016]

According to a first aspect of the present invention, there is provided an information reproducing apparatus comprising: an AGC circuit for constantly controlling an envelope of a reproduction signal obtained by reading digital recording information recorded on a recording medium; A zero level detector for detecting a zero level from a reproduced signal output from the AGC circuit, and a binary for binarizing the reproduced signal output from the AGC circuit based on the zero level detected by the zero level detector Bit synchronization such that a point shifted by 180 degrees from the zero-cross timing of the reproduction signal from which the DC component has been removed is used as a sampling point based on the binarized signal output from the binarization circuit. P that generates the clock
An LL circuit, and an A / A that samples a reproduced signal output from the AGC circuit at the falling edge of the bit synchronization clock.
A D converter, a digital equalizer for equalizing the waveform of the output signal of the A / D converter, a prediction value generation circuit for generating a prediction value used in Viterbi decoding from the output signal of the digital equalizer, A Viterbi decoder for performing a maximum decoding of digital data as an output signal of the digital equalizer using the predicted value.

According to a second aspect of the present invention, in the information reproducing apparatus, the predicted value generation circuit detects a maximum value and a minimum value for a predetermined period from a sequence of digital data output from the digital equalizer. Detector, a median detector that calculates the median of the maximum value and the minimum value, a maximum amplitude detector that detects a dynamic range that is a difference between the maximum value and the minimum value, and the median value and the dynamic range. And a prediction value calculation circuit for calculating a plurality of types of prediction values based on the prediction value.

An information reproducing apparatus according to a third aspect of the present invention is the information reproducing apparatus, wherein the predicted value generation circuit detects an average value of a predetermined number from a sequence of digital data output from the digital equalizer. , A standard deviation detector for calculating the predetermined number of standard deviations, and a predicted value calculating circuit for calculating a plurality of types of predicted values based on the average value and the standard deviation.

According to a fourth aspect of the present invention, in the information reproducing apparatus, the predicted value generation circuit calculates a plurality of types of predicted values based on a histogram of digital data output from the digital equalizer. .

According to a fifth aspect of the present invention, in the information reproducing apparatus, the prediction value generation circuit detects an average value of a predetermined number from a sequence of digital data output from the digital equalizer. A standard deviation detector that calculates the predetermined number of standard deviations, and a predicted value calculation circuit that calculates a plurality of types of predicted values based on the average value and the standard deviation,
A predicted value storage circuit for storing a predicted value set from outside, and a predicted value selection for selecting a set predicted value from the predicted value storage circuit or a calculated predicted value from the predicted value calculation circuit based on an external instruction And a circuit.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An information reproducing apparatus according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 shows a DV according to Embodiment 1 of the present invention.
It is a block diagram which shows the structure of the front end part of information reproduction apparatuses, such as D reproduction apparatus. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, reference numeral 1 denotes an AGC for adjusting the amplitude of the envelope of the reproduced RF signal to be constant.
A circuit (variable gain amplifier), 2 is an A / D converter for converting the level-adjusted reproduced RF signal into digital data, 3 is a digital equalizer for equalizing the waveform of the received RF signal, and 4 is this digital equalizer. This is a level adjustment circuit that receives the output of the digital equalizer 3 and gives a gain instruction to the AGC circuit 1 so that the amplitude of the envelope of the reproduced RF signal becomes constant.

In FIG. 2, reference numeral 5 denotes a prediction value generating circuit for receiving the output of the digital equalizer 3 and generating a prediction value for Viterbi decoding. , A Viterbi decoder for decoding the digital data at the maximum level, 7 is a zero-level detector that receives the level-adjusted reproduced RF signal and detects a zero level, and 8 is a level based on the output of the zero-level detector 7. A binarizing circuit 9 for binarizing the adjusted reproduction RF signal, based on the output of the binarizing circuit 8, A / A for determining a sampling point
This is a PLL circuit that sets the clock (bit synchronization clock) of the D converter 2 to a point shifted by 180 degrees from the rising and falling edges of the zero-cross timing binary signal.

FIG. 2 is a block diagram showing an internal configuration of the predicted value generation circuit of the information reproducing apparatus according to the first embodiment.

In FIG. 2, reference numeral 51 denotes a digital equalizer 3
, A peak detector for detecting a maximum value and a minimum value for a predetermined period from a digital data sequence output from the digital signal generator; 52, a median detector for calculating the median of the output maximum value and minimum value; maximum amplitude detector for detecting a dynamic range is the difference between the value and the minimum value, x ₊ a Viterbi decoder 6 receives these outputs _{54, x -, y +,} y - 4 kinds of prediction outputs the prediction value of It is a value calculation circuit.

FIG. 3 is a diagram showing the internal structure and operation of the PLL circuit of the information reproducing apparatus according to the first embodiment.

In FIG. 3, reference numeral 91 denotes a phase detector for detecting the rising edge of the output of the binarization circuit 8 and the phase of the bit synchronization clock; 92, a charge pump for injecting and drawing charge based on the output; Is a capacitor for storing charge, and 94 is a VCO for changing the oscillation frequency according to the voltage of the capacitor 93.

Next, the operation of the information reproducing apparatus according to the first embodiment will be described with reference to the drawings.

First, the reproduced RF signal sent from the pickup unit is adjusted to a constant amplitude by the AGC circuit 1 and converted to digital data by the A / D converter 2. Here, the sampling point is a position shifted by 180 degrees from the zero cross point as described later. FIG.
4 shows the relationship between the sampling timing in the A / D converter 2 and the eye pattern of the reproduced RF signal.

The digital data is compensated for the high-frequency component attenuated by the digital equalizer 3. The digital equalizer 3 is constituted by a digital filter, and an example of the filter coefficient is shown below.

Transfer function H = -0.17 + 1.34 * Z- ²
-0.17 * Z ^-4

In the predicted value generating circuit 5, upon receiving the output of the digital equalizer 3, a peak detector 51 detects a maximum value MAX and a minimum value MIN during a predetermined period, and outputs a median value detector 52 and a maximum amplitude. The detector 53 calculates a median value CENTER and a dynamic range P_P shown below.

Median value CENTER = (MAX + MIN) / 2 Amplitude P_P = MAX−MIN

The predicted value calculation circuit 54 calculates four types of predicted values used for Viterbi decoding. An example is shown below.

[0035] _{y + = CENTER + 0.3 * P_P} x + = CENTER + 0.1 * P_P x - = CENTER-0.1 * P_P y - = CENTER-0.3 * P_P

The Viterbi decoder 6 performs the maximum decoding for each digital data using these four types of predicted values,
The branch metric is calculated.

In the DVD device according to the first embodiment, after the code data is formed into a packet structure, an error correction code is added, and the data is recorded in the NRZI system after being subjected to 8-16 modulation. . In the 8-16 modulation, the run length RL is limited to 3T or more (T is a modulation interval), and the trellis diagram and the state transition diagram using the four predicted values are shown in FIGS. 5 (a) and 5 (b). It becomes like.

As shown in FIG. 5, the following conditions are used as the constraint conditions because the run length RL is 3 or more.

(1) At the time of zero crossing, the predicted value x ₊ ,
x _- through the state to use. Rising (0> 1): State 1 and State 2 Falling (1> 0): State 4 and State 5

(2) After passing through x ₊ , y ₊ must be used at least once.
, Transits to the zero level negative side, and after passing x ₋ , it always transits to the zero level positive side via y ₋ at least once. + Side: state 2> state 3 (at least once)> state 4> state 5-side: state 5> state 0 (at least once)> state 1> state 2

On the other hand, as the measure of the branch metric, the information of the coded data is added to the timing of the zero cross, and it is important whether the sample point is on the + side or the-side of the zero level. The input of the decoder 6 is i
When n, the branch metric corresponding to the predicted value y ₊ = 0 if in ≧ y ₊ = ｙ (in−y ₊ ) ² other The branch metric corresponding to the predicted value x ₊ = (in−x ₊ ) ² predicted value x _- the corresponding branch metric = (in-x _-) ² predicted value y _- a corresponding branch metric _{= 0 if in ≦ y - =} 1/2 (in-y -) using ² other.

Next, the operation of adjusting the sampling timing will be described.

In the PLL circuit 9, as shown in FIG. 3, the phase detector 91 compares the rising edge of the output of the binarizing circuit 8 with the phase of the bit synchronization clock, and the rising edge is ahead of the rising edge of the bit synchronization clock. In the case (when the width of the difference signal between the output of the binarization circuit and the signal sampled at the falling edge of the bit synchronization clock is larger than の of the bit synchronization clock period), the first output P has its delay time Is output, and the rising edge is later than the rising edge of the bit synchronization clock (the width of the difference signal between the output of the binarization circuit and the signal sampled at the falling edge of the bit synchronization clock is equal to the bit width). Smaller than 1/2 of the synchronous clock cycle),
A pulse having a width corresponding to the advance time is output to the second output N.

The two signals P and N are supplied to the charge pump 9
In the former case, charge is injected into the capacitor 93 during the pulse width, and as a result, the voltage rises by an amount proportional to the amount of advance of the output rise of the binarization circuit 8, and conversely, in the latter case, The charge of the capacitor 93 is extracted, and as a result, its voltage decreases by an amount proportional to the delay amount.

As a result, in the former case, the frequency of the bit synchronization clock oscillated by the VCO 94 rises very slightly, and the rising of the output of the binarization circuit 8 relatively changes. In the latter case, the frequency of the bit synchronization clock oscillated by the VCO 94 decreases very slightly, and changes relatively in the direction in which the rise of the output of the binarization circuit 8 proceeds.

With such a mechanism, the rising timing of the output of the binarizing circuit 8 can be matched with the rising timing of the bit synchronization clock.

On the other hand, the A / D converter 2 performs sampling at the falling edge of the bit synchronization clock, so that sampling is performed at a point shifted by 180 degrees from the zero cross point. .

The slice level (zero level) used for binarizing the reproduced RF signal whose level has been adjusted by the binarization circuit 8 is constituted by an analog LPF having a cutoff frequency sufficiently lower than the modulation frequency. By using the zero level detected by the zero level detector 7,
Accurate timing reproduction can be performed without being affected by an offset generated in the circuit configuration or temporary fluctuation of zero level.

As described above, the sampling of the reproduced RF signal is
Since the measurement is performed at the original information point and the measure of the branch metric in the Viterbi decoding is suppressed for a prediction value far away from the zero level, S / N
Decoding processing with excellent characteristics can be performed, and good decoding can be performed even on a signal having a low S / N ratio of a reproduced RF signal.

Further, since the zero level is detected from the reproduced RF signal, and the predicted value is also changed according to the maximum / minimum value and the median value of the reproduced RF signal, the dynamic level of the dynamic range can be temporarily reduced. In addition, decoding of digital data that is resistant to offset can be realized.

That is, the information reproducing apparatus according to the first embodiment uses a different measure in accordance with the predicted value in calculating the branch metric for Viterbi decoding. Further, in the branch metric calculation of Viterbi decoding, when the output signal level of the digital equalizer 3 is within a predetermined range, the error is reduced. further,
In the Viterbi decoder 6, the constraint is that the signal passes through a predetermined predicted value before and after the zero cross. That is, in the Viterbi decoder 6, x
₊ And x _- the predicted value y ₊ and in addition to the zero level + side of -
Predicted value of the side y _- has, through the y ₊ always more than once after passing through the x ₊ Zero level - a transition to the side, x _- via _- a y always more than once after passing through Then, the transition to the zero level + side is set as a constraint condition.

Embodiment 2 In the first embodiment,
An embodiment corresponding to the case where the dynamic range and the peak average value are used for generating the predicted value, but the dynamic range becomes apparently large due to the influence of noise or the like will be described.

An information reproducing apparatus according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 6 is a diagram showing a configuration of an information reproducing apparatus according to Embodiment 2 of the present invention.

In FIG. 6, 55 is an average detector, 56
Is a standard deviation detector, and 54 is a predicted value calculation circuit as in FIG.

In the second embodiment, the digital equalizer 3
The average value AVE of the predetermined number of signals of the output, the standard deviation sigma is calculated, four predicted _{values, y + = AVE + σ,} x + = AVE + 0.4 * σ, x - = AVE-0.4 * σ, y ₋ = AVE−σ. Other parts are the same as in the first embodiment.

Also in the second embodiment, similar to the first embodiment, decoding processing with excellent S / N characteristics can be performed.
Good decoding is possible even for a signal having a low S / N ratio of the reproduced RF signal.

Embodiment 3 As another embodiment, a form in which a predicted value is generated using a histogram of the output of the digital equalizer 3 is also possible.

In this case, a histogram as shown in FIG. 12B is generated from the output of the digital equalizer 3 which has been discretized, the level value of the first frequency above the zero level is x _+, and the second frequency is the level of the y _+, the level value of the first frequency below the zero level x _- and, the level of the second frequency y _-
By doing so, decoding processing with excellent S / N characteristics can be performed as described above, and good decoding can be performed even on a signal having a low S / N ratio of a reproduced RF signal.

Embodiment 4 FIG. In each of the above embodiments,
For the setting of the predicted value, a value sequentially calculated from the output of the digital equalizer created from the reproduced RF signal was used, but in order to stabilize the operation at the start of the operation of the device, the numerical value set from the control circuit was used. A method of using it is also conceivable.

An information reproducing apparatus according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a configuration of a predicted value generation circuit of an information reproducing apparatus according to Embodiment 4 of the present invention.

In FIG. 7, an average value detector 55, a standard deviation detector 56, and a predicted value calculation circuit 54 are the same as those in the second embodiment shown in FIG. A predicted value storage circuit 57 stores a set of predicted values set by a CPU (not shown) of a control unit for controlling the operation of the DVD reproducing apparatus.
Is the output of the predicted value storage circuit 57 and the predicted value calculation circuit 54
Is a predictive value selection circuit for selecting the output of.

In the fourth embodiment, the CPU
When the operation of reproducing the VD is started, first, a set of predetermined predicted values is set in the predicted value storage circuit 57, and at the same time, the output of the predicted value storage circuit 57 is selected by the predicted value selection circuit 58. To perform DVD playback.

When a certain degree of normal demodulation becomes possible, the CPU sets the predicted value calculating circuit 54 to the predicted value selecting circuit 58 in order to easily cope with a temporary signal level fluctuation or the like.
To select the output of

In the fourth embodiment, as in the above-described embodiments, a decoding process having excellent S / N characteristics can be performed.
Good decoding is possible even for a signal having a low S / N ratio of the reproduced RF signal, and more stable operation is possible at the start of DVD reproduction operation.

Embodiment 5 In the above embodiment, the calculation of the branch metric has a square error as the error measure. However, by using the difference between the absolute value and the predicted value, a device having a smaller circuit scale and the same effect as described above is used. Can be realized.

Embodiment 6 FIG. In the above embodiment, four sets of values are used as predicted values, but it goes without saying that six or eight sets of predicted values can be used. FIG. 8 shows a trellis diagram and a state transition diagram using six prediction values.
And FIG.

According to the sixth embodiment, it is possible to more accurately evaluate the transition in a state away from the zero crossing, to perform decoding processing with excellent S / N characteristics as described above, and to realize reproduction RF.
Good decoding is possible even for a signal having a low signal-to-noise ratio, and more stable operation at the start of DVD playback operation.

[0068]

As described above, the information reproducing apparatus according to the first aspect of the present invention comprises: an AGC circuit for constantly controlling the envelope of a reproduction signal obtained by reading digital recording information recorded on a recording medium; A zero level detector for detecting a zero level from the reproduced signal output from the AGC circuit, and binarizing the reproduced signal output from the AGC circuit based on the zero level detected by the zero level detector. A binarizing circuit, and a bit which is based on the binarized signal output from the binarizing circuit and which sets a point shifted by 180 degrees from the zero cross timing of the reproduction signal from which the DC component has been removed as a sampling point. A PLL circuit for generating a synchronous clock, and an A / D converter for sampling a reproduced signal output from the AGC circuit at a falling edge of the bit synchronous clock. A digital equalizer for equalizing the waveform of the output signal of the A / D converter, a predicted value generation circuit for generating a predicted value used in Viterbi decoding from the output signal of the digital equalizer, And a Viterbi decoder for decoding the digital data, which is the output signal of the digital equalizer, to a maximum extent, so that decoding with excellent S / N characteristics can be performed without increasing the size of the apparatus and significantly increasing the cost. In addition, there is an effect that good decoding can be performed even for a signal having a low S / N ratio of a reproduced RF signal.

In the information reproducing apparatus according to a second aspect of the present invention, as described above, the predicted value generation circuit determines the maximum value and the minimum value for a predetermined period from the sequence of digital data output from the digital equalizer. A peak detector, a median detector that calculates a median of the maximum value and the minimum value, a maximum amplitude detector that detects a dynamic range that is a difference between the maximum value and the minimum value, and the median value. And a prediction value calculation circuit for calculating a plurality of types of prediction values based on the dynamic range. Thus, decoding processing with excellent S / N characteristics can be performed without increasing the size of the apparatus and significantly increasing the cost. There is an effect that good decoding is possible even for a signal having a low S / N ratio.

In the information reproducing apparatus according to a third aspect of the present invention, as described above, the predicted value generation circuit detects a predetermined number of average values from a series of digital data output from the digital equalizer. An average value detector, a standard deviation detector for calculating the predetermined number of standard deviations, and a prediction value calculation circuit for calculating a plurality of types of prediction values based on the average value and the standard deviation; It is possible to perform decoding processing with excellent S / N characteristics without increasing the size and cost, and to achieve an effect of enabling good decoding of a reproduced RF signal having a low S / N ratio.

In the information reproducing apparatus according to a fourth aspect of the present invention, as described above, the prediction value generation circuit generates a plurality of types of prediction values based on a histogram of digital data output from the digital equalizer. Since the calculation is performed, decoding processing having excellent S / N characteristics can be performed without increasing the size of the apparatus and significantly increasing the cost, and good decoding can be performed even for a signal having a low S / N ratio of a reproduced RF signal. This has the effect.

In the information reproducing apparatus according to a fifth aspect of the present invention, as described above, the predicted value generation circuit detects a predetermined number of average values from a series of digital data output from the digital equalizer. An average value detector, a standard deviation detector for calculating the predetermined number of standard deviations, a prediction value calculation circuit for calculating a plurality of types of prediction values based on the average value and the standard deviation, and externally set values Since it has a predicted value storage circuit that stores predicted values, and a predicted value selection circuit that selects a set predicted value from the predicted value storage circuit or a calculated predicted value from the predicted value calculation circuit based on an external instruction, , Without increasing the size and cost of the equipment
The decoding process with excellent / N characteristics can be performed, and the S /
There is an effect that good decoding can be performed even for a signal having a low N ratio.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an information reproducing apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a configuration of a predicted value generation circuit of the information reproducing apparatus according to Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a configuration and an operation of a PLL circuit of the information reproducing apparatus according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between a sampling timing and an eye pattern of the information reproducing apparatus according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a trellis diagram and a state transition of the information reproducing apparatus according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a predicted value generation circuit of the information reproducing apparatus according to Embodiment 2 of the present invention.

FIG. 7 is a block diagram showing a configuration of a predicted value generation circuit of an information reproducing apparatus according to Embodiment 4 of the present invention.

FIG. 8 is a diagram showing a trellis diagram of an information reproducing apparatus according to Embodiment 6 of the present invention.

FIG. 9 is a diagram showing a state transition of the information reproducing apparatus according to Embodiment 6 of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional information reproducing apparatus.

FIG. 11 is a diagram showing a relationship between a sampling timing and an eye pattern of a conventional information reproducing apparatus.

FIG. 12 is a diagram showing a level distribution of a sample point at a zero crossing point of the conventional information reproducing apparatus and a level distribution at a sampling point at a point shifted by 180 degrees from the zero crossing of the information reproducing apparatus according to the present invention.

[Explanation of symbols]

Reference Signs List 1 AGC circuit, 2 A / D converter, 3 digital equalizer, 4 level adjustment circuit, 5 5A, 5B prediction value generation circuit, 6 Viterbi decoder, 7 zero level detector, 8
Binarization circuit, 9 PLL circuit, 51 peak detector,
52 median value detector, 53 maximum amplitude detector, 54 predicted value calculation circuit, 55 average value detector, 56 standard deviation detector, 57 predicted value storage circuit, 58 predicted value selection circuit,
91 phase detector, 92 charge pump, 93 capacitor, 94 VCO.

Claims (5)

[Claims] 1. An AGC circuit for constantly controlling the envelope of a reproduction signal obtained by reading digital recording information recorded on a recording medium, and a zero level detection for detecting a zero level from the reproduction signal output from the AGC circuit. A binarization circuit for binarizing a reproduction signal output from the AGC circuit based on the zero level detected by the zero level detector; and a binarization signal output from the binarization circuit. Based on D
A PLL circuit for generating a bit synchronization clock such that a point shifted by 180 degrees from the zero-cross timing of the reproduction signal from which the C component has been removed is used as a sampling point, and a reproduction signal output from the AGC circuit is subjected to the bit synchronization. An A / D converter that samples at the falling edge of the clock; a digital equalizer that equalizes the waveform of the output signal of the A / D converter; and a prediction used in Viterbi decoding based on the output signal of the digital equalizer An information reproducing apparatus, comprising: a predicted value generating circuit that generates a value; and a Viterbi decoder that uses the predicted value to digitally decode the digital data that is the output signal of the digital equalizer. 2. A peak detector for detecting a maximum value and a minimum value for a predetermined period from a sequence of digital data output from the digital equalizer, and a center of the maximum value and the minimum value. A median detector for calculating a value; a maximum amplitude detector for detecting a dynamic range that is a difference between the maximum value and the minimum value; and a prediction for calculating a plurality of types of predicted values based on the median and the dynamic range. 2. The information reproducing apparatus according to claim 1, further comprising a value calculation circuit. 3. An average value detector for detecting a predetermined number of average values from a series of digital data output from the digital equalizer, and a standard value for calculating the predetermined number of standard deviations. The information reproducing apparatus according to claim 1, further comprising: a deviation detector; and a predicted value calculation circuit that calculates a plurality of types of predicted values based on the average value and the standard deviation. 4. The information reproducing apparatus according to claim 1, wherein the prediction value generation circuit calculates a plurality of types of prediction values based on a histogram of digital data output from the digital equalizer. 5. An average value detector for detecting a predetermined number of average values from a sequence of digital data output from the digital equalizer, and a standard value for calculating the predetermined number of standard deviations. A deviation detector, a prediction value calculation circuit that calculates a plurality of types of prediction values based on the average value and the standard deviation, a prediction value storage circuit that stores a prediction value that is set from outside, 2. The information reproducing apparatus according to claim 1, further comprising: a predicted value selecting circuit that selects a set predicted value from the predicted value storage circuit or a calculated predicted value from the predicted value calculation circuit based on the predicted value.