GB2336074A

GB2336074A - Phase alignment of data in high speed parallel data buses using a multi-phase low frequency sampling clock

Info

Publication number: GB2336074A
Application number: GB9806747A
Authority: GB
Inventors: Con Cremin; Anne Geraldine O'connell; Una Quinlan; Eugene O'neill
Original assignee: 3Com Technologies Ltd
Current assignee: 3Com Technologies Ltd
Priority date: 1998-03-30
Filing date: 1998-03-30
Publication date: 1999-10-06
Anticipated expiration: 2018-03-30
Also published as: GB9806747D0; GB2336074B

Abstract

A receiver for data transmitted serially on each of a plurality of parallel lines at a particular data rate comprises means 20 for generating a multi-phase clock signal having a rate which is a sub-multiple of the data rate and a plurality of data recovery means 10-18, one for each of the data lines. Each data recovery means includes sampling means 30-37 coupled to receive the data stream and controlled by a respective phase of the sampling clock, and a plurality of bit phase adjustment means, arranged to compare the phase of the data stream with a selected phase of the sampling clock and arranged to delay the bit stream to provide phase alignment with the selected phase of the sampling clock. Training signals are used for both bit and byte alignment. A plurality of multiplexers determine which of the sampling means will provide bits to one of eight output lines on which bytes are transmitted in parallel form.

Description

2336074 METHOD AND APPARATUS FOR THE PHASE ALIGNMENT OF DATA IN HIGH-SPEED

PARALLEL DATA BUSES USING A MULTI-PHASE LOW FREQUENCY SAMPLING CLOCK.

The present invention relates to the phase alignment of data which is conveyed, for example from one network device to another over a link of substantial length, in parallel buses. The invention is particularly although not exclusively intended for use in systems where the data rate is very high, for example of the order of 800 megabits per second.

One problem that arises in these circumstances is phase shift between the parallel lines, so that the data received from the parallel lines of the bus cannot be accurately sampled by means of a single common clock. An additional problem is that a stream of data bits obtained for example by serialising parallel data bytes needs proper byte alignment for the reconstitution of the data in its original form. One example of a system in which these problems arise is one in which a multiple bit parallel data signal has its individual bytes serialised and transmitted over a respective line of a parallel bus to a receiver at which the original signal is to be reconstituted. The problems are particularly severe where there is no common clock for the data transmitter and receiver and it is not feasible or not convenient to employ signal redundancy to convey within the data sufficient information for the reconstitution of a clock signal.

One feature of the. present invention is the the use of a comparatively low frequency, multi-phase sampling clock of which a respective phase can be used to produce phase alignment of the bits in a respective channel or line. Preferably according to the invention the phase relationship between the bits in that line and the respective phase of the sampling clock is adjusted by rneans of selective 104788 1 delay of the respective bit stream.

Another feature of the present invention is the use of a training signal in each bit stream to achieve the proper phase alignment of the bit stream and the sampling clock.

A further feature of the invention is the use of a further training signal, at the frequency of the low frequency clock, to provide for correct framing. i.e byte synchronisation.

The system preferably employs in addition to a multiplicity of parallel data lines control line which may be phase aligned in the same way as the data lines. Such control line may be used during ordinary transmission of data to convey a framing signal or 'data valid' signal.

DETAILED DESCRIPTION

The drawing illustrates the receiver section of a network device that is arranged to receive data by way of a nine-line parallel bus, having eight data lines and a control line. A transmitter of data streams on such a bus may take the form described in our contemporary patent application which is entitled "Method and apparatus for phase alignment of data in high speed parallel buses using adjustable high frequency sampling clocks" and is filed on the same day as the present application.

More particularly, as described in that other application, 64-bit wide parallel data is received on a bus and a 'packet valid' signal on an associated control line. Each group of eight bits (i.e. each byte) is received by a respective serialiser which 104788 1 11 1 toge ther with a control bit transmitter are under common clock control by a phase-locked loop synthesiser. This synthesiser, which may be of known form, generates from a local, stable, comparatively low frequency clock signal a high frequency clock, such as at 800 Mhz, for enabling the serialisers to transmit a data bit at a corresponding frequency. i.e. in this example one every 1.25 ns. The serial streams are driven onto the lines of the parallel bus by way of differential drivers.

When the system is operating normally, data is sent over the eight data lines in serial manner and the ninth line is used as a data valid line.

The general problem which needs solving is the establishment of a correct phase relationship between the ninth or control line and the bits on the other lines. This relationship must be established and maintained to within a bit period to enable the detection of the bit order in a byte for each channel.

BRIEF DESCRIPTION OF THE DRAWING

Figure 1 illustrates one embodiment of a receiver according to the invention.

DETAILED DESCRIPTION

Each of the data lines and the control line is connected to a respective data recovery block. The data recovery block 10 for the "0" data stream will be -described in detail. The other blocks 11-18 for the other seven data streams and the control stream are shown in outline only in Figure 1.

All the data recovery blocks 10 to 18 are under common clock control. The clock is at a comparatively low frequency relative to the nominal clock frequency of the 104788 data streams and is sub-harmonically related to it. In particular, where the data streams are at 800 Mbits/sec, the local clock, which is generated from a basic stable crystal controlled circuit 19, may be at 100 MHz. The multi-phase clock is generated by a phase-locked loop synthesiser 20, which generates the clock in eight different phases 00 to 07 For the sake of simplicity only four phases are shown explicitly.

In each of the data recovery blocks, each of the eight phases of the multi-phase low frequency clock can be used to sample a bit of the incoming data stream. To ensure accurate sampling, the incoming data stream must be phase aligned so that each phase of the clock effects sampling in the middle of a bit.

In this embodiment of the invention, the respective data line is connected to one input of a phase detector 21 of which a second input is connected to receive one of the phases of the low frequency sampling clock. The various phases of the sampling clock are coupled to the clock inputs of eight D-type flip-flops 31 to 37 (of which only four are shown) which are all connected to the output of a multiplexer 38 which is controlled by the phase detector. The inputs to the multiplexer are various taps on a delay line 39 of which the input is connected to the respective one of the data lines or to the control line as the case may be.

The outputs of the flip-flops 31 to 37 are connected to a plurality of multiplexers 40 to 47, in this case eight, one for each bit in a byte. These are controlled as will be described to determine which of the flipflops will provide bits to a respective one of eight output lines on which bytes are transmitted in parallel form.

The first step in the establishment of correct alignment requires the adjustment of the relative phase relationship between the sampling clock and the incoming 104788 data bits. In this embodiment the phase adjustment is achieved by adjusting the phase of the incoming data bits. For this purpose the phase detector measures the relative phase relationship and controls the multiplexer to select the delay which will align the incoming data bits to the respective phase of the sampling clock.

To facilitate the production of this phase alignment, it is convenient to transmit a training signal, for example a repetitive bit pattern 1010101.. . Such a pattern may be transmitted by the transmitter automatically when the system is powered up. It would be usual to repeat the pattern at appropriate intervals to recalibrate the receiver to account for drift, as generally described in the contemporary application already mentioned.

The next step in achieving proper aligrument is to establish which of the flipflop circuits corresponds to a predetermined bit, usually the first bit, "bit V in a byte.

For this purpose the transmitter can transmit a second training pattern which delimits a byte, such as a 100 Mhz pattern formed by transmitting on each line the pattern 111100001111... Such a pattern can be received in an eight bit serializer (not shown) in one of eight patterns, since there are eight possible phase positions of the training signal. The particular phase position will identify which bit represents the 0 to 1 transition in the training clock signal. Thus if the received pattern is decoded as 11000011, the seventh flip-flop holds 'bit zero'.

It may not be necessary to provide a training signal for byte synchronisation on all the channels. In particular if the skew between channels is known to be or can safely be presumed to be less than half a bit time, it may be sufficient to provide byte alignment on a single channel.

104788

Claims

1. A receiver for data transmitted serially on each of a plurality of parallel lines at a particular data rate, comprising:

means for generating a multi-phase clock signal having a rate which is a submultiple of the data rate; a plurality of data recovery means, one for each of said lines, each data recovery means including a sampling means coupled to receive the data stream and controlled by a respective phase of the sampling clock; 1 a plurality of bit phase adjustment means, one for each line, arranged to compare the phase of the respective bit stream with a selected phase of the sampling clock and arranged to delay controllably the respective bit stream to provide phase alignment thereof with said selected phase of the sampling clock.

2. A receiver according to claim 1 wherein said sampling means each comprises a clock controlled flip-flop responsive to the respective data stream and to a respective phase of the sampling clock.

3. A receiver according to claim 1 or claim 2 wherein means are provided to respond to a training signal on at least one of said lines, said training signal having transitions delimiting frame or byte boundaries., to determine a frame or byte reference for the sampling means.

4. A receiver according to any foregoing claim wherein the lines include a control line for the conveyance of a framing signal for the aligned data signals.

104788

5. A method of operating a receiver according to any foregoing claim, wherein a training signal composed of an alternation of bits is transmitted on each line to enable phase adjustment of the bit streams.

6. A method of operating a receiver according to claim 4 and comprising transmitting on at least one line said training signal at a frequency corresponding to the frequency of the sampling clock.

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