GB2336075A

GB2336075A - Phase alignment of data in high speed parallel data buses using adjustable high frequency sampling clocks

Info

Publication number: GB2336075A
Application number: GB9806748A
Authority: GB
Inventors: Con Cremin; J Noel Butler; Anne Geraldine O'connell; Una Quinlan; Eugene O'neill; Tadhg Creedon
Original assignee: 3Com Technologies Ltd
Current assignee: 3Com Technologies Ltd
Priority date: 1998-03-30
Filing date: 1998-03-30
Publication date: 1999-10-06
Anticipated expiration: 2018-03-30
Also published as: GB9806748D0; GB2336075B

Abstract

A receiver 2 for data bit streams transmitted serially on each of a plurality of parallel data lines at a particular data rate, comprises means for generating a plurality of sampling clock signals each of the same frequency as a reference clock signal and having the same frequency as the data on each of the data lines. Each data line has a data recovery means 70-78 comprising a sampling means coupled to receive the data stream and controlled by a respective sampling clock, a clock phase adjustment means arranged to compare the phase of a predetermined training signal on the data line with a respective sampling clock and arranged to adjust the sampling clock to provide phase alignment with the bit stream and a deserialiser 82 controlled by the respective sampling clock to provide from a group of serially received bits a group of parallel bits. A means for decoding a second training signal transmitted over at least one of the data lines is provided for determining a correct order of precedence of bits in the group of parallel bits.

Description

1 2336075 METHOD AND APPARATUS FOR THE PHASE ALIGNMENT OF DATA IN

HIGHSPEED PARALLEL DATA BUSES USING ADJUSTABLE HIGH FREQUENCY SAMPLING CLOCKS.

The present invention relates to the phase aligrument of data which is conveyed, for example from one network device to another over a link of substantial length, in parallel buses. The invention is particularly although not exclusively intended for use in systems where the data rate is very high, for example of the order 800 megabits per second.

One problem that arises in these circumstances is phase shift between the parallel lines, so that the data received from the parallel lines of the bus cannot be accurately sampled by means of a single common clock. An additional problem is that a stream of data bits obtained for example by serialising parallel data bytes needs proper byte alignment for the reconstitution of the data in its original form. One example of a system in which these problems arise is one in which a multiple bit parallel data signal has its individual bytes serialised and transmitted over a respective line of a parallel bus to a receiver at which the original signal is to be reconstituted. The problems are particularly severe where there is no common clock for the data transmitter and receiver and it is not feasible or not convenient to employ signal redundancy to convey within the data sufficient information for the reconstitution of a clock signal.

One feature of the invention is the dgrivation, from a common reference clock in a receiver, of a respective sampling clock for each data channel or line and aligning the phase of the sampfing clock to the respective bit stream. Such alignment may be facilitated by transmitting at appropriate times on each line a training signal at the nominal sampling clock frequency and using a closed loop 104789 phase detecting loop.

Another feature of the invention is the use of a further training signal having a cycle corresponding to the length of a frame in the data stream, i.e. eight bits where the data is to be constituted into data bytes. The phase of this signal at the receiver may be used to indicate a correct bit position within the frame or byte.

The system preferably employs in addition to a multiplicity of parallel data lines control line which may be phase aligned in the same way as the data lines. Such control line may be used during ordinary transmission of data to convey a framing signal or 'data valid' signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates by way of example one embodiment of the invention.

Figure 2 illustrates a phase alignment process used in the embodiment illustrated in Figure 1.

DETAILED DESCRIPTION

The drawing illustrates a system comprising a first network device, preferably constituted by a first 'chip', and called herein a transmitter 1, which receives data in for example 64-bit wide parallel form and is arranged to convert each word or packet into a plurality (in this example eight) of bit streams which are transmitted over respective lines to a receiver 2.

The transmitter shown is not unique to the system described herein. In particular 104789 it may be used in conjunction with a receiver as described in our patent application which is filed on the same day as this patent application and is entitled "Method and apparatus for the phase alignment of data in high speed parallel data buses using a multi-phase low frequency sampling clock" In the system shown, 64-bit wide parallel data is received on a bus 3 and with a $packet valid' signal pktVal on an associated control line 4. Each group of eight bits (i.e. each byte) is received by a respective serialiser 50 to 57 (of which only four are shown) which together with a control bit transmitter 58 are under common clock control by a phase- locked loop synthesiser 59. This synthesiser, which may be of known form, generates from a local, stable, comparatively low frequency clock signal a high frequency dock, such as at 800 Mhz, for enabling the serialisers to transmit a data bit at a corresponding frequency. i.e. in this example one every 1.25 ns. The serial streams are driven onto the lines of the parallel bus by way of differential drivers 60 to 68 respectively.

The receiver is coupled to receive data from the lines 50 to 58 and basically comprises a corresponding number of data recovery blocks 70 to 78, one for each data line. These data recovery blocks are under the common clock control of a phase-locked loop synthesiser 79 which from a local stable low frequency clock generates a high frequency reference clock, in this example at 800 Mhz. It may be noted that if the receiver 2 includes a further transmitter section for onward transmission of data in the same manner as the transmitter 1, it would obviously be preferable to use the same clock and therefore the same synthesiser for the control of both receiving and transmitting.

The data recovery blocks are in similar for and only the data recovery block 70 need be described.

104789 The block 70 includes a differential buffer amplifier 80 which is coupled to the line 60 and drives both a clock recovery circuit 81 and a deserialiser 82. The clock recovery circuit 81 in clock controlled from the synthesiser 79 and shifts the phase of the clock to align it to the phase of the incoming bits. The phase shifted clock is fed to the deserialiser 82, which converts a group (in this example eight) of incoming bits into parallel form so as to provide a respective output on an eight -bit parallel bus 90. A deserialiser for this purpose is described in the aforementioned contemporary patent application. The deserialised data is fed to a byte aligner 83, the function of which is to select which of the deserialised bits is the first bit of a pattern so as to achieve byte alignment. The data recovery blocks 71 to 77 provide similarly formatted data on the output lines 91 to 97 and the parallel data is output along with a data valid signal on an output bus 100 and control line 101 respectively. The control data is recovered by means of a data recovery block 78 similar to the blocks 70 to 77.

The problem of correct data recovery has three parts. First one must ensure that each incoming bit is sampled in the middle of the bit. Second, the bytes (or in general the frames composed of a group of bits) must be correctly delineated on each incoming bit stream. Third, the receiver must align all the bytes or frames correctly and, in this example, indicate a start of frame (i.e start of packet) signal to provide packet delineation.

Phase alignment may be achieved by, for example, sending a training pattern on each line (including the control line) at a selected time, preferably but not exclusively on the powering up of the system. The training pattern may be subharmonically related to the reference clock and may in particular be composed of an alternation of ones and zeros, i,. e. 101010... to constitute thereby a 400 Mhz 104789 sign al. The sampling clock, Le the phase-controllable version of the reference clock is shown at 201 in Figure 2 whereas the training signal is shown at 202. The training pattern is intended to enable a bit phase aligner, i.e. a phase-correcting loop within the clock recovery block to detect that the transitions of the training signal are in relation to the transitions of the sampling clock and to compute, either explicitly or implicitly, the position of the middle of the bit. The result of the process is a phase-adjusted sampling clock 203 which will correctly sample the bits on the respective line.

It may be necessary to recalibrate the phase of the sampling clock to compensate for drift. If so, the training sequence may be reinvoked at intervals of so example several hundred milliseconds. Alternatively, one may indirectly determine, by counting transitions per unit time and comparing with a programmable level or range, determine whether recalibration is necessary.

It would be generally preferable, to minimise power consumption to arrange the bit phase aligners to operate in sequence so that for example only one is performing a bit alignment function at any given time.

Byte or frame alignment can be achieved by the transmission of a training signal on each of the lines. The training signal or training packet may be subharmonically related to the clock frequency and may be in the form 111100001111...etc. This can be received in one of eight phases at the receiver, i.e. 11110000, 01111000, 00111100 etc. These values can be decoded at the receiver and used to select which of the eight bits is 'bit zero. This bit should always correspond to the 0 to 1 transition. For example, if the pattern received is 00111100, it indicates that 'bit 2' sampled the leading edge transition of the lowfrequency training signal and should represent 'bit 0' in the received data. A 104789 1 multiplexer can be used to select the bits in the correct order, as described in the aforementioned contemporary patent application. This process assumes that the pattern can be out of phase by a maximum of three bit times. For extra margin, we assume that two bit times are allowable, corresponding to the allowed skew between chips.

Once the byte alignment process is complete for all the lines, the bits and bytes are aligned across the whole bus and the lines may be used for normal transmission of data and line as the control line.

If the bit phase aligners stay in phase, for example by means of routine or selective calibration there should be no need to recalibrate the byte alignment. If for any reason there was a need to recalibrate the byte alignment, one may employ an undersize packet, composed of 11110000 bytes such as would allow the byte calibration but would not be transmitted onwards because it is undersize.

It may also be feasible to achieve bit phase alignment and byte alignment using the same training pattern.

It will be apparent that once all the nine lines are correctly in phase and frame synchronisation (i.e. bit and byte alignment), a signal may be transmitted on the control line to indicate a start of a packet and will be guaranteed to be aligned to the data on the eight data lines.

104789

Claims

1. A receiver for data bit streams transmitted serially on each of a plurality of parallel data lines at a particular data rate, comprising:

means for generating a plurality of sampling clock signals each of the same frequency as a reference clock signal and having the same frequency as the data on each of the data lines; a plurality of data recovery means, one for each of said lines, each data recovery means including a sampling means coupled to receive the data stream and controlled by a respective sampling clock; a plurality of clock phase adjustment means, one for each line, arranged to compare the phase of a predetermined signal on said line with a respective sampling clock and arranged to adjust the sampling clock to provide phase alignment thereof with said bit stream; a deserialiser for each bit stream, controlled by the respective sampling clock to provide from a group of serially received bits a group of parallel bits and means for decoding a second predetermined signal transmitted over at least one of the lines for determining a correct order of precedence of bits in the group of parallel bits.

2. A method of operating a receiver according to claim 1, and comprising transmitting one each of said lines a predetermined signal in the form of an alternation of bits constituting a signal at half the frequency of the sampling 104789 signals.

3. A method according to claim 2 and including transmitting on at least one of said lines the second predetermined signal in the form of a signal having transitions separated by an interval corresponding to a group of bits in succession.

4. A method according to claim 3 wherein said group corresponds to a byte.

104789